├── .gitignore ├── 3d-bracket ├── gg-hdmi-3d-bracket.f3d ├── gg-hdmi-3d-bracket.stl └── gg-hdmi-bracket.step ├── README.md ├── fab ├── gg-hdmi-rev-2.1 │ ├── gg-hdmi-rev-2.1-bom.csv │ ├── gg-hdmi-rev-2.1-gerbers-drill.zip │ └── gg-hdmi-rev-2.1-schematic.pdf ├── gg-hdmi-rev-2.2 │ ├── gg-hdmi-rev-2.2-bom.csv │ ├── gg-hdmi-rev-2.2-gerbers-drill.zip │ ├── gg-hdmi-rev-2.2-schematic.pdf │ └── gg-hdmi-rev-2.2-top-pos.csv ├── gg-hdmi-rev-2.3 │ ├── gg-hdmi-rev-2.3-bom.csv │ ├── gg-hdmi-rev-2.3-gerbers-drill.zip │ ├── gg-hdmi-rev-2.3-schematic.pdf │ └── gg-hdmi-rev-2.3-top-pos.csv └── gg-hdmi-rev-2.4 │ ├── gg-hdmi-rev-2.4-bom.csv │ ├── gg-hdmi-rev-2.4-gerbers-drill.zip │ ├── gg-hdmi-rev-2.4-schematic.pdf │ └── gg-hdmi-rev-2.4-top-pos.csv ├── images ├── gg-hdmi-board-ports.jpg ├── gg-hdmi-board-prog-pin-back.jpg ├── gg-hdmi-board-prog-pin-front.jpg ├── gg-hdmi-board-side-bracket.jpg ├── gg-hdmi-board.jpg ├── gg-hdmi-cga-test.jpg ├── gg-hdmi-ft2232h-diagram.png ├── gg-hdmi-mda-display.jpg ├── gg-hdmi-prog-1.jpg ├── gg-hdmi-prog-2.jpg ├── gg-hdmi-prog-5v.jpg ├── gg-hdmi-prog-pin-connected.jpg ├── gg-hdmi-test-cga-comp-normal.jpg ├── gg-hdmi-test-cga-comp-thin.jpg ├── gg-hdmi-test-cga-normal.jpg ├── gg-hdmi-test-cga-thin.jpg ├── gg-hdmi-test-cga-vga-normal.jpg ├── gg-hdmi-test-cga-vga-thin.jpg ├── gg-hdmi-test-cga70-hdmi-big.jpg ├── gg-hdmi-test-cga70-hdmi-small.jpg ├── gg-hdmi-test-mda-hdmi-colours.jpg ├── gg-hdmi-test-mda-hdmi-green.jpg ├── gg-hdmi-test-mda-vga.jpg ├── gg-hdmi-top-both.jpg ├── gg-hdmi-with-mimas-a7.jpg ├── gg-hdmi-zadig0.png ├── gg-hdmi-zadig1.png └── gremlin.jpg ├── isa-video ├── .gitignore ├── ISAVideo.pretty │ ├── graphics_gremlin.kicad_mod │ └── gremlin.kicad_mod ├── RAM.kicad_sch ├── RAM.sch ├── bus_interface.kicad_sch ├── bus_interface.sch ├── fp-info-cache ├── fp-lib-table ├── hdmi.kicad_sch ├── hdmi.sch ├── isavideo-cache.lib ├── isavideo-rescue.dcm ├── isavideo-rescue.kicad_sym ├── isavideo-rescue.lib ├── isavideo.kicad_pcb ├── isavideo.kicad_prl ├── isavideo.kicad_pro ├── isavideo.kicad_sch ├── isavideo.sch ├── libraries │ ├── 10029449-111RLF.stp │ ├── 23117631.kicad_mod │ ├── 76PSB04ST.stp │ ├── BEADC1608X95N.kicad_mod │ ├── BLM18RK601SN1D.lib │ ├── BLM18RK601SN1D.step │ ├── HDMI_A_Amphenol_10029449-111.kicad_mod │ ├── PJRAN1X1U04X.lib │ ├── PJRAN1X1U04X.step │ ├── SWITCHCRAFT_PJRAN1X1U04X.kicad_mod │ ├── TFP410_ThermalVias.kicad_mod │ ├── c-2311763-1-b1-3d.stp │ └── hdmi_conn.lib ├── power.kicad_sch ├── power.sch ├── sym-lib-table ├── vga_dac.kicad_sch └── vga_dac.sch ├── original_README.md ├── verilog ├── .gitignore ├── Makefile ├── README.md ├── cga.hex ├── cga.v ├── cga70_top.v ├── cga_attrib.v ├── cga_composite.v ├── cga_hdmiport.v ├── cga_overscan_top.v ├── cga_pixel.v ├── cga_scandoubler.v ├── cga_sequencer.v ├── cga_top.v ├── cga_vgaport.v ├── cga_vram.v ├── crtc6845.v ├── gremlin.pcf ├── is61_tester.v ├── is61c5128_t.v ├── isavideo_t.v ├── mda.hex ├── mda.v ├── mda70_top.v ├── mda_attrib.v ├── mda_hdmiport.v ├── mda_pixel.v ├── mda_sequencer.v ├── mda_top.v ├── mda_vgaport.v ├── mda_vram.v └── release │ ├── isavideo-20240505-nosnow.binm │ └── isavideo-20241229-withsnow.binm └── vga_display_status ├── .gitignore ├── vga_display_status.srcs ├── constrs_1 │ └── new │ │ └── constraints.xdc ├── sources_1 │ └── new │ │ ├── HDMI_test.v │ │ ├── TMDS_encoder.v │ │ └── top.v └── utils_1 │ └── imports │ └── synth_1 │ └── top.dcp └── vga_display_status.xpr /.gitignore: -------------------------------------------------------------------------------- 1 | *.bak 2 | *.kicad_pcb-bak 3 | *.xml 4 | *.net 5 | *.gbr 6 | *.drl 7 | -------------------------------------------------------------------------------- /3d-bracket/gg-hdmi-3d-bracket.f3d: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/3d-bracket/gg-hdmi-3d-bracket.f3d -------------------------------------------------------------------------------- /3d-bracket/gg-hdmi-3d-bracket.stl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/3d-bracket/gg-hdmi-3d-bracket.stl -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Graphics Gremlin HDMI 2 | 3 | This is a modified version of the Graphics Gremlin ISA CGA/MDA graphics card to include a HDMI port. This is still based on the same Lattice ICE40HX4K FPGA. 4 | 5 | (A production run has been made for this board. You can contact explit[at]mailbox[dot]org if you wish to purchase a unit.) 6 | 7 | The latest revision now displays CGA colour 6 brown correctly. Since this project builds on the original project, it carries over some emulation inaccuracies in demos like 8088MPH and other applications. 8 | 9 | 10 | 11 | 12 | Top view of board including the metal bracket. 13 | 14 | 15 | 16 | Left is the original Graphics Gremlin, right is my modified design. 17 | 18 | # Demo videos 19 | 20 | * Bootup and CGA compatibility tester (Brown fixed): https://www.youtube.com/watch?v=Ap-goSkkSUI 21 | * Bootup and CGA compatibility tester (Deprecated): https://www.youtube.com/watch?v=xLy6on_o4YM 22 | * 8088MPH: https://www.youtube.com/watch?v=WLpNmEhdTe4 23 | * Area5150 (using CGA overscan): https://www.youtube.com/watch?v=9wYU6qMWlpE 24 | * My talk on this project: https://www.youtube.com/watch?v=r_GiEIe_oZk 25 | 26 | # Changes from original project 27 | 28 | * Hardware changes 29 | * Added HDMI port by removing the RGBI DE9 port. Port positions adjusted to ease trace routing. 30 | * Added [TI TFP410](https://www.ti.com/product/TFP410) DVI transmitter (HDMI is compatible with DVI). HDMI is independent of the VGA/Composite output. 31 | * Test points for inputs to DVI transmitter. 32 | * Replaced the 3.3VDC 1A linear regulator with 3A as TFP410 is power hungry at up to 1A. 33 | * Added pin headers for power. 34 | * Added LED power indicators for 5V and 3.3V. 35 | * 2-layer -> 4-layer board to ease routing. 36 | * HDL code changes 37 | * Selectable MDA colours (HDMI only) 38 | * Removed normal MDA bitstream as there is no more RGBI port. 39 | * Added CGA 70Hz mode. 40 | * Added CGA 60Hz overscan mode for demo and debug purposes. 41 | * Modified Scandoubler code to support Display Enable signal as required by DVI chip but not VGA. 42 | 43 | Readme of the original Graphics Gremlin project can be found [here](original_README.md). 44 | 45 | # How to replicate this board and use it? 46 | 47 | 1. [Fabrication guidelines](https://github.com/yeokm1/graphics-gremlin-hdmi/wiki/Fabrication-guidelines) 48 | 49 | 2. [Flashing FPGA bitstream](https://github.com/yeokm1/graphics-gremlin-hdmi/wiki/Flashing-bitstream) 50 | 51 | 3. [Testing the board](https://github.com/yeokm1/graphics-gremlin-hdmi/wiki/Testing-procedures) 52 | 53 | 4. Usage guide below: 54 | 55 | # Switches position 56 | 57 | ## Switches 1 and 2 for MDA 58 | 59 | These colours are applicable for the HDMI section only. 60 | 61 | | 1 | 2 | MDA colour | 62 | |--------|--------|------------| 63 | | open | open | Green | 64 | | open | closed | Yellow | 65 | | closed | open | White | 66 | | closed | closed | Red | 67 | 68 | 69 | 70 | Sample of the different colours when testing the card on my [486 PC](https://github.com/yeokm1/retro-configs/tree/master/desktops/generic-486-pc). 71 | 72 | ## Switches 1 and 2 for CGA 73 | 74 | | Switch | CGA | 75 | |--------|--------------------------------------| 76 | | 1 | closed=composite mode. open=VGA mode | 77 | | 2 | closed=thin font. open=normal font | 78 | 79 | **Note that VGA and Composite cannot be used simultaneously.** No change from original Graphics Gremlin. HDMI will work on all modes. 80 | 81 | ## Switches 3 and 4 82 | 83 | | 3 | 4 | Bitstream | Function | 84 | |--------|--------|-------------|------------------------| 85 | | open | open | Bitstream 0 | MDA 70Hz | 86 | | open | closed | Bitstream 1 | CGA 70Hz | 87 | | closed | open | Bitstream 2 | CGA 60Hz | 88 | | closed | closed | Bitstream 3 | CGA 60Hz with overscan | 89 | 90 | ### CGA 60 and 70Hz 91 | After internal scandoubling, the CGA 60Hz will produce a 640x400x60Hz output suitable for most VGA monitors. While this works for the HDMI LCD monitors I have tested, it is technically below the DVI specification of a minimum of 640x480x60Hz and 25.175Mhz pixel clock. 92 | 93 | To meet the specification in case some monitors insist, I have added another mode CGA 70Hz which will produce 640x400 at 70Hz. (Actually 71Hz due to precision limitations of clock multiplying) This 70Hz is however not compatible with composite displays including the one inside IBM5155. 94 | 95 | ### CGA 60Hz with overscan 96 | 97 | The CGA overscan bitstream will show the overscan sections beyond the usual display area just short of Hsync and Vsync. Overscan is used in some demos like Area 5150. However not all HDMI monitors can accept this signal and/or display this properly. 98 | 99 | I notice that while a monitor may initially accept this mode, tendency is it will randomly throw you display errors later. 100 | 101 | **The purpose of this mode is just for debug and demo purposes**. 102 | 103 | # Development info 104 | 105 | ## Directory structure 106 | 107 | ``` 108 | |-- fab: Gerbers, BOM and PDF schematic 109 | |-- images: Images used in this repo 110 | |-- isa-video: Kicad Design files 111 | |-- verilog: Updated Verilog code to support HDMI 112 | | -- release: Bitstreams 113 | |-- vga_display_status: Vivado project to process ICE40 FPGA output to DVI transmiter that runs on my Mimas A7 FPGA board. 114 | |-- 3d-bracket: Step and STL file for a 3D-printable bracket 115 | ``` 116 | 117 | ## Verilog Toolchain 118 | 119 | To compile the project, I used the following open source tool-chain on my Ubuntu running on WSL on Windows 11. 120 | 121 | ```bash 122 | sudo apt install libftdi-dev cmake 123 | 124 | sudo apt install build-essential libboost-system-dev libboost-thread-dev libboost-program-options-dev libboost-test-dev libboost-filesystem-dev libboost-iostreams-dev libeigen3-dev 125 | 126 | sudo apt install tclsh clang tcl-dev libreadline-dev bison flex 127 | 128 | # Icestorm 129 | git clone https://github.com/YosysHQ/icestorm.git icestorm 130 | cd icestorm 131 | make -j$(nproc) 132 | sudo make install 133 | cd .. 134 | 135 | # NextPNR 136 | git clone https://github.com/YosysHQ/nextpnr nextpnr 137 | cd nextpnr 138 | cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . 139 | make -j$(nproc) 140 | sudo make install 141 | cd .. 142 | 143 | # Yosys 144 | git clone https://github.com/YosysHQ/yosys.git yosys 145 | cd yosys 146 | git submodule update --init 147 | make -j$(nproc) 148 | sudo make install 149 | ``` 150 | 151 | To program the bitstream to the board, I used `iceprog -p` from OSS CAD Suite. Follow the [flash instructions](https://github.com/yeokm1/graphics-gremlin-hdmi/wiki/Flashing-bitstream). 152 | 153 | ## Code compilation 154 | 155 | In my Ubuntu WSL: 156 | 157 | ```bash 158 | cd verilog 159 | mkdir build 160 | 161 | # No CGA snow (default) 162 | make 163 | 164 | # With CGA snow 165 | make DEFINES="-DCGA_SNOW=1" 166 | ``` 167 | 168 | ```bash 169 | # Program without CGA snow bitstream 170 | iceprog -p release\isavideo-20240505-nosnow.binm 171 | 172 | # Program with CGA snow bitstream 173 | iceprog -p release\isavideo-20241229-withsnow.binm 174 | 175 | # To see verbose output 176 | iceprog -v -p isavideo.binm 177 | 178 | # To suppress all output 179 | iceprog -v -p isavideo.binm 2> nul 180 | ``` 181 | 182 | ## Special handling for brown colour 183 | 184 | The PCB and code treats the palette value "I:0 R:1 G:1 B:0" specially to produce a brown instead of dark yellow as per the CGA standard. 185 | 186 | ```verilog 187 | // video[1] is the original green value 188 | assign hdmi_grn = video[1] ^ (hdmi_red & video[1] & (hdmi_blu ^ 1) & (hdmi_int ^ 1)); 189 | assign hdmi_grn_int = hdmi_int ^ (hdmi_red & video[1] & (hdmi_blu ^ 1) & (hdmi_int ^ 1)); 190 | ``` 191 | 192 | This is done using the above boolean logic to lower the green value by using the dedicated hdmi_green_int pin. This logic is [provided by @spbnick](https://github.com/yeokm1/yeokm1.github.io/discussions/115#discussioncomment-7022872). 193 | 194 | 195 | 196 | My IBM 5155 running the [CGA Compatibility Tester](https://github.com/MobyGamer/CGACompatibilityTester) displaying the colour palatte. 197 | 198 | ## Testing with Mimas A7 (Xilinx Artix 7) 199 | 200 | As part of my testing, I also made a small FPGA test project using another FPGA board Mimas A7 based on the Xilinx Artix 7. 201 | 202 | 203 | 204 | The FPGA test board reads the raw RGBI, HS, VS, DE and CLK signals that are given to the DVI transmitter and displays the output using its own HDMI output. 205 | 206 | The code is heavily based on the [HDMI_FPGA](https://github.com/dominic-meads/HDMI_FPGA/) project by Dominic Meads and runs on Vivado 2023. 207 | 208 | ## Bitstream Releases 209 | * 20240505 - Disables CGA Snow (Recommended) 210 | * 20241229 - Has CGA Snow. PC/XT systems which are overclocked with tools like [PC Sprint](https://github.com/reeshub/pc-sprint) should use this bitstream. This is due to the higher text mode data being clocked in which will cause artifacts if snow is totally avoided. More info in this [issue #5](https://github.com/yeokm1/graphics-gremlin-hdmi/issues/5). 211 | 212 | ## Hardware Releases 213 | 214 | * 2.1 (9 Aug 2021): Initial release for GG (HDMI) 215 | * 2.2 (17 Sept 2023): Extra Green control line for TFP410 216 | * 2.3 (13 Oct 2023): Corrected VGA port footprint bug 217 | * 2.4 (4 Jan 2024): Kicad 7.10, cleaned up schematic errors, removed unused traces, update pcb symbols and 3D models, cleaned up BOM. (No functional difference with 2.3) 218 | 219 | ## License 220 | This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 221 | International License. See [https://creativecommons.org/licenses/by-sa/4.0/](https://creativecommons.org/licenses/by-sa/4.0/). 222 | -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.1/gg-hdmi-rev-2.1-bom.csv: -------------------------------------------------------------------------------- 1 | Item,Qty,Reference(s),Value,Footprint,Mouser 2 | 1,23,"C1, C7, C8, C9, C10, C11, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31",1u,Capacitor_SMD:C_0603_1608Metric,810-CGA3E1X7R1C105AC 3 | 2,2,"C2, C4",10uF 16V,Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder,81-ZRB18AR61C106ME1L 4 | 3,6,"C3, C5, C6, C12, C18, C19",4.7u,Capacitor_SMD:C_0603_1608Metric,187-CL10A475KP8NNNC 5 | 4,3,"C32, C33, C34",10uF 16V,Capacitor_SMD:C_0603_1608Metric,81-ZRB18AR61C106ME1L 6 | 5,9,"C35, C36, C37, C38, C39, C40, C41, C42, C43",0.1uF,Capacitor_SMD:C_0603_1608Metric,581-060316C104K 7 | 6,2,"D1, D2",Yellow,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMY1100 8 | 7,1,D3,Green,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMG1100 9 | 8,1,F1,1A,Resistor_SMD:R_1206_3216Metric,530-0ZCJ0050FF2G 10 | 9,3,"FID1, FID2, FID3",Fiducial,Fiducials:Fiducial_1mm_Dia_2mm_Outer, 11 | 10,3,"FL1, FL2, FL3",BLM18RK601SN1D,libraries:BEADC1608X95N,81-BLM18RK601SN1 12 | 11,1,J1,PROG,Connector_PinHeader_2.54mm:PinHeader_2x04_P2.54mm_Vertical, 13 | 12,1,J2,DB15_Female_HighDensity_MountingHoles,Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm,571-2311763-1 14 | 13,1,J3,PJRAN1X1U04X,libraries:SWITCHCRAFT_PJRAN1X1U04X,502-PJRAN1X1U04X 15 | 14,1,J4,10029449-111RLF,libraries:HDMI_A_Amphenol_10029449-111,649-10029449-111RLF 16 | 15,1,J5,Conn_ISA_8bit,Conn:BUS_PC_8BIT, 17 | 16,1,J6,RFMOD,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical, 18 | 17,1,J7,Conn_01x05,Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical, 19 | 18,1,J8,Conn_02x06_Odd_Even,Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical, 20 | 19,13,"R1, R2, R3, R4, R5, R8, R9, R14, R15, R20, R23, R24, R27",10K,Passive:RESC1608X55,603-RC0603FR-0710KL 21 | 20,5,"R6, R7, R10, R25, R26",10,Passive:RESC1608X55,603-RC0603FR-0710RL 22 | 21,1,R11,DNI,Passive:RESC1608X55, 23 | 22,1,R12,2200,Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder,603-RC0603FR-072K2L 24 | 23,1,R13,1K,Passive:RESC1608X55,603-RC0603FR-071KL 25 | 24,5,"R16, R17, R18, R19, R31",75,Passive:RESC1608X55,603-RC0603FR-0775RL 26 | 25,2,"R21, R22",100,Passive:RESC1608X55,603-RC0603FR-07100RL 27 | 26,3,"R28, R29, R30",237,Passive:RESC1608X55,603-RC0603FR-07237RL 28 | 27,2,"R32, R42",1200,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-101K2L 29 | 28,2,"R33, R54",0,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-070RL 30 | 29,7,"R34, R36, R37, R39, R46, R48, R53",DNI,Resistor_SMD:R_0603_1608Metric, 31 | 30,9,"R35, R38, R40, R41, R43, R44, R47, R49, R50",10k,Resistor_SMD:R_0603_1608Metric,RC0603JR-0710KL 32 | 31,1,R45,5k,Resistor_SMD:R_0603_1608Metric,603-RT0603BRE075KL 33 | 32,1,R51,510,Resistor_SMD:R_0603_1608Metric,603-RC0603JR-07510RL 34 | 33,1,R52,33k,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-1033KL 35 | 34,6,"RN1, RN2, RN3, RN4, RN5, RN6",604,Passive:RESCAV80P320X160X70-8,652-CAY16-6040F4LF 36 | 35,4,"RN7, RN8, RN9, RN10",300,Passive:RESCAV80P320X160X70-8,652-CAY16-3000F4LF 37 | 36,1,SW1,SW_DIP_x04,Switch:SW_DIP254P762X635-8,706-76PSB04ST 38 | 37,1,U1,ICE40HX4K-TQ144,Active:TSQFP50P2200X2200X160-144,842-ICE40HX4K-TQ144 39 | 38,1,U2,SST26VF080A-104I/SN,Active:SOP127P620X175-8,579-26VF080A-104I/SN 40 | 39,3,"U3, U4, U5",74ALVC164245,Active:TSSOP50P810X120-48,771-74ALVC164245 41 | 40,1,U6,ADA4891-3,Active:SOP127P620X175-14,584-ADA4891-3ARZ 42 | 41,1,U7,IS61WV5128BLL-10KLI,Active:SOJ127P1118X376-36,870-61WV5128B10KLI 43 | 42,1,U8,LD1085D2T33R,Package_TO_SOT_SMD:TO-263-2,511-LD1085D2T33-TR 44 | 43,1,U9,AP2114HA-1.2,Active:SOT230P700X170-3,621-AP2114HA-1.2TRG1 45 | 44,1,U10,APX803S00-29SA-7,Active:SOT95P230X117-3,621-APX803S00-29SA-7 46 | 45,1,U11,74HCT125,Active:TSOP65P640X110-14,771-74HCT125PW-T 47 | 46,1,U12,TFP410PAP,Package_QFP:HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm_Mask4.4x4.4mm_ThermalVias,595-TFP410PAP 48 | 47,1,X1,10MHz,Passive:XTAL320X250X120-4,520-ECS-2333-100-BNT 49 | 48,1,X2,14.318MHz,Passive:XTAL320X250X120-4,815-ASE-14.318MLCT 50 | -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.1/gg-hdmi-rev-2.1-gerbers-drill.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.1/gg-hdmi-rev-2.1-gerbers-drill.zip -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.1/gg-hdmi-rev-2.1-schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.1/gg-hdmi-rev-2.1-schematic.pdf -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.2/gg-hdmi-rev-2.2-bom.csv: -------------------------------------------------------------------------------- 1 | Item,Qty,Designator,Comment,Footprint,Mouser 2 | 1,23,"C1, C7, C8, C9, C10, C11, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31",1u,Capacitor_SMD:C_0603_1608Metric,810-CGA3E1X7R1C105AC 3 | 2,2,"C2, C4",10uF 16V,Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder,81-ZRB18AR61C106ME1L 4 | 3,6,"C3, C5, C6, C12, C18, C19",4.7u,Capacitor_SMD:C_0603_1608Metric,187-CL10A475KP8NNNC 5 | 4,3,"C32, C33, C34",10uF 16V,Capacitor_SMD:C_0603_1608Metric,81-ZRB18AR61C106ME1L 6 | 5,9,"C35, C36, C37, C38, C39, C40, C41, C42, C43",0.1uF,Capacitor_SMD:C_0603_1608Metric,581-060316C104K 7 | 6,2,"D1, D2",Yellow,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMY1100 8 | 7,1,D3,Green,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMG1100 9 | 8,1,F1,1A,Resistor_SMD:R_1206_3216Metric,530-0ZCJ0050FF2G 10 | 9,3,"FID1, FID2, FID3",Fiducial,Fiducials:Fiducial_1mm_Dia_2mm_Outer, 11 | 10,3,"FL1, FL2, FL3",BLM18RK601SN1D,libraries:BEADC1608X95N,81-BLM18RK601SN1 12 | 11,1,J1,PROG,Connector_PinHeader_2.54mm:PinHeader_2x04_P2.54mm_Vertical, 13 | 12,1,J2,DB15_Female_HighDensity_MountingHoles,Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm,571-2311763-1 14 | 13,1,J3,PJRAN1X1U04X,libraries:SWITCHCRAFT_PJRAN1X1U04X,502-PJRAN1X1U04X 15 | 14,1,J4,10029449-111RLF,libraries:HDMI_A_Amphenol_10029449-111,649-10029449-111RLF 16 | 15,1,J5,Conn_ISA_8bit,Conn:BUS_PC_8BIT, 17 | 16,1,J6,RFMOD,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical, 18 | 17,1,J7,Conn_01x05,Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical, 19 | 18,1,J8,Conn_02x06_Odd_Even,Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical, 20 | 19,13,"R1, R2, R3, R4, R5, R8, R9, R14, R15, R20, R23, R24, R27",10K,Passive:RESC1608X55,603-RC0603FR-0710KL 21 | 20,5,"R6, R7, R10, R25, R26",10,Passive:RESC1608X55,603-RC0603FR-0710RL 22 | 21,1,R11,DNI,Passive:RESC1608X55, 23 | 22,1,R12,2200,Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder,603-RC0603FR-072K2L 24 | 23,1,R13,1K,Passive:RESC1608X55,603-RC0603FR-071KL 25 | 24,5,"R16, R17, R18, R19, R31",75,Passive:RESC1608X55,603-RC0603FR-0775RL 26 | 25,2,"R21, R22",100,Passive:RESC1608X55,603-RC0603FR-07100RL 27 | 26,3,"R28, R29, R30",237,Passive:RESC1608X55,603-RC0603FR-07237RL 28 | 27,2,"R32, R42",1200,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-101K2L 29 | 28,2,R33,0,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-070RL 30 | 29,7,"R34, R36, R37, R39, R46, R48, R53",DNI,Resistor_SMD:R_0603_1608Metric, 31 | 30,9,"R35, R38, R40, R41, R43, R44, R47, R49, R50",10k,Resistor_SMD:R_0603_1608Metric,RC0603JR-0710KL 32 | 31,1,R45,5k,Resistor_SMD:R_0603_1608Metric,603-RT0603BRE075KL 33 | 32,1,R51,510,Resistor_SMD:R_0603_1608Metric,603-RC0603JR-07510RL 34 | 33,1,R52,33k,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-1033KL 35 | 34,6,"RN1, RN2, RN3, RN4, RN5, RN6",604,Passive:RESCAV80P320X160X70-8,652-CAY16-6040F4LF 36 | 35,4,"RN7, RN8, RN9, RN10",300,Passive:RESCAV80P320X160X70-8,652-CAY16-3000F4LF 37 | 36,1,SW1,SW_DIP_x04,Switch:SW_DIP254P762X635-8,706-76PSB04ST 38 | 37,1,U1,ICE40HX4K-TQ144,Active:TSQFP50P2200X2200X160-144,842-ICE40HX4K-TQ144 39 | 38,1,U2,SST26VF080A-104I/SN,Active:SOP127P620X175-8,579-26VF080A-104I/SN 40 | 39,3,"U3, U4, U5",74ALVC164245,Active:TSSOP50P810X120-48,771-74ALVC164245 41 | 40,1,U6,ADA4891-3,Active:SOP127P620X175-14,584-ADA4891-3ARZ 42 | 41,1,U7,IS61WV5128BLL-10KLI,Active:SOJ127P1118X376-36,870-61WV5128B10KLI 43 | 42,1,U8,LD1085D2T33R,Package_TO_SOT_SMD:TO-263-2,511-LD1085D2T33-TR 44 | 43,1,U9,AP2114HA-1.2,Active:SOT230P700X170-3,621-AP2114HA-1.2TRG1 45 | 44,1,U10,APX803S00-29SA-7,Active:SOT95P230X117-3,621-APX803S00-29SA-7 46 | 45,1,U11,74HCT125,Active:TSOP65P640X110-14,771-74HCT125PW-T 47 | 46,1,U12,TFP410PAP,Package_QFP:HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm_Mask4.4x4.4mm_ThermalVias,595-TFP410PAP 48 | 47,1,X1,10MHz,Passive:XTAL320X250X120-4,520-ECS-2333-100-BNT 49 | 48,1,X2,14.318MHz,Passive:XTAL320X250X120-4,815-ASE-14.318MLCT 50 | -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.2/gg-hdmi-rev-2.2-gerbers-drill.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.2/gg-hdmi-rev-2.2-gerbers-drill.zip -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.2/gg-hdmi-rev-2.2-schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.2/gg-hdmi-rev-2.2-schematic.pdf -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.3/gg-hdmi-rev-2.3-bom.csv: -------------------------------------------------------------------------------- 1 | Item,Qty,Designator,Comment,Footprint,Mouser 2 | 1,23,"C1, C7, C8, C9, C10, C11, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31",1u,Capacitor_SMD:C_0603_1608Metric,810-CGA3E1X7R1C105AC 3 | 2,2,"C2, C4",10uF 16V,Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder,81-ZRB18AR61C106ME1L 4 | 3,6,"C3, C5, C6, C12, C18, C19",4.7u,Capacitor_SMD:C_0603_1608Metric,187-CL10A475KP8NNNC 5 | 4,3,"C32, C33, C34",10uF 16V,Capacitor_SMD:C_0603_1608Metric,81-ZRB18AR61C106ME1L 6 | 5,9,"C35, C36, C37, C38, C39, C40, C41, C42, C43",0.1uF,Capacitor_SMD:C_0603_1608Metric,581-060316C104K 7 | 6,2,"D1, D2",Yellow,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMY1100 8 | 7,1,D3,Green,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMG1100 9 | 8,1,F1,1A,Resistor_SMD:R_1206_3216Metric,530-0ZCJ0050FF2G 10 | 9,3,"FID1, FID2, FID3",Fiducial,Fiducials:Fiducial_1mm_Dia_2mm_Outer, 11 | 10,3,"FL1, FL2, FL3",BLM18RK601SN1D,libraries:BEADC1608X95N,81-BLM18RK601SN1 12 | 11,1,J1,PROG,Connector_PinHeader_2.54mm:PinHeader_2x04_P2.54mm_Vertical, 13 | 12,1,J2,DB15_Female_HighDensity_MountingHoles,Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm,571-2311763-1 14 | 13,1,J3,PJRAN1X1U04X,libraries:SWITCHCRAFT_PJRAN1X1U04X,502-PJRAN1X1U04X 15 | 14,1,J4,10029449-111RLF,libraries:HDMI_A_Amphenol_10029449-111,649-10029449-111RLF 16 | 15,1,J5,Conn_ISA_8bit,Conn:BUS_PC_8BIT, 17 | 16,1,J6,RFMOD,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical, 18 | 17,1,J7,Conn_01x05,Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical, 19 | 18,1,J8,Conn_02x06_Odd_Even,Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical, 20 | 19,13,"R1, R2, R3, R4, R5, R8, R9, R14, R15, R20, R23, R24, R27",10K,Passive:RESC1608X55,603-RC0603FR-0710KL 21 | 20,5,"R6, R7, R10, R25, R26",10,Passive:RESC1608X55,603-RC0603FR-0710RL 22 | 21,1,R11,DNI,Passive:RESC1608X55, 23 | 22,1,R12,2200,Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder,603-RC0603FR-072K2L 24 | 23,1,R13,1K,Passive:RESC1608X55,603-RC0603FR-071KL 25 | 24,5,"R16, R17, R18, R19, R31",75,Passive:RESC1608X55,603-RC0603FR-0775RL 26 | 25,2,"R21, R22",100,Passive:RESC1608X55,603-RC0603FR-07100RL 27 | 26,3,"R28, R29, R30",237,Passive:RESC1608X55,603-RC0603FR-07237RL 28 | 27,2,"R32, R42",1200,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-101K2L 29 | 28,2,R33,0,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-070RL 30 | 29,7,"R34, R36, R37, R39, R46, R48, R53",DNI,Resistor_SMD:R_0603_1608Metric, 31 | 30,9,"R35, R38, R40, R41, R43, R44, R47, R49, R50",10k,Resistor_SMD:R_0603_1608Metric,RC0603JR-0710KL 32 | 31,1,R45,5k,Resistor_SMD:R_0603_1608Metric,603-RT0603BRE075KL 33 | 32,1,R51,510,Resistor_SMD:R_0603_1608Metric,603-RC0603JR-07510RL 34 | 33,1,R52,33k,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-1033KL 35 | 34,6,"RN1, RN2, RN3, RN4, RN5, RN6",604,Passive:RESCAV80P320X160X70-8,652-CAY16-6040F4LF 36 | 35,4,"RN7, RN8, RN9, RN10",300,Passive:RESCAV80P320X160X70-8,652-CAY16-3000F4LF 37 | 36,1,SW1,SW_DIP_x04,Switch:SW_DIP254P762X635-8,706-76PSB04ST 38 | 37,1,U1,ICE40HX4K-TQ144,Active:TSQFP50P2200X2200X160-144,842-ICE40HX4K-TQ144 39 | 38,1,U2,SST26VF080A-104I/SN,Active:SOP127P620X175-8,579-26VF080A-104I/SN 40 | 39,3,"U3, U4, U5",74ALVC164245,Active:TSSOP50P810X120-48,771-74ALVC164245 41 | 40,1,U6,ADA4891-3,Active:SOP127P620X175-14,584-ADA4891-3ARZ 42 | 41,1,U7,IS61WV5128BLL-10KLI,Active:SOJ127P1118X376-36,870-61WV5128B10KLI 43 | 42,1,U8,LD1085D2T33R,Package_TO_SOT_SMD:TO-263-2,511-LD1085D2T33-TR 44 | 43,1,U9,AP2114HA-1.2,Active:SOT230P700X170-3,621-AP2114HA-1.2TRG1 45 | 44,1,U10,APX803S00-29SA-7,Active:SOT95P230X117-3,621-APX803S00-29SA-7 46 | 45,1,U11,74HCT125,Active:TSOP65P640X110-14,771-74HCT125PW-T 47 | 46,1,U12,TFP410PAP,Package_QFP:HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm_Mask4.4x4.4mm_ThermalVias,595-TFP410PAP 48 | 47,1,X1,10MHz,Passive:XTAL320X250X120-4,520-ECS-2333-100-BNT 49 | 48,1,X2,14.318MHz,Passive:XTAL320X250X120-4,815-ASE-14.318MLCT 50 | -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.3/gg-hdmi-rev-2.3-gerbers-drill.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.3/gg-hdmi-rev-2.3-gerbers-drill.zip -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.3/gg-hdmi-rev-2.3-schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.3/gg-hdmi-rev-2.3-schematic.pdf -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.3/gg-hdmi-rev-2.3-top-pos.csv: -------------------------------------------------------------------------------- 1 | Ref,Val,Package,PosX,PosY,Rot,Side 2 | "C1","1u","C_0603_1608Metric",154.051000,-97.155000,180.000000,top 3 | "C2","10uF 16V","C_0603_1608Metric_Pad1.08x0.95mm_HandSolder",110.600000,-108.850000,90.000000,top 4 | "C3","4.7u","C_0603_1608Metric",105.791000,-105.410000,90.000000,top 5 | "C4","10uF 16V","C_0603_1608Metric_Pad1.08x0.95mm_HandSolder",92.800000,-120.637500,-90.000000,top 6 | "C5","4.7u","C_0603_1608Metric",105.791000,-101.600000,-90.000000,top 7 | "C6","4.7u","C_0603_1608Metric",145.980000,-89.150000,-90.000000,top 8 | "C7","1u","C_0603_1608Metric",123.800000,-103.000000,90.000000,top 9 | "C8","1u","C_0603_1608Metric",134.874000,-103.632000,-90.000000,top 10 | "C9","1u","C_0603_1608Metric",144.145000,-89.154000,-90.000000,top 11 | "C10","1u","C_0603_1608Metric",144.780000,-92.964000,0.000000,top 12 | "C11","1u","C_0603_1608Metric",144.780000,-95.885000,0.000000,top 13 | "C12","4.7u","C_0603_1608Metric",115.697000,-87.630000,-90.000000,top 14 | "C13","1u","C_0603_1608Metric",131.826000,-73.914000,90.000000,top 15 | "C14","1u","C_0603_1608Metric",129.794000,-73.914000,90.000000,top 16 | "C15","1u","C_0603_1608Metric",117.348000,-87.630000,-90.000000,top 17 | "C16","1u","C_0603_1608Metric",117.348000,-91.186000,-90.000000,top 18 | "C17","1u","C_0603_1608Metric",116.586000,-80.899000,180.000000,top 19 | "C18","4.7u","C_0603_1608Metric",124.968000,-74.676000,180.000000,top 20 | "C19","4.7u","C_0603_1608Metric",136.398000,-103.632000,-90.000000,top 21 | "C20","1u","C_0603_1608Metric",110.871000,-65.786000,0.000000,top 22 | "C21","1u","C_0603_1608Metric",172.466000,-108.966000,180.000000,top 23 | "C22","1u","C_0603_1608Metric",176.530000,-108.966000,0.000000,top 24 | "C23","1u","C_0603_1608Metric",141.351000,-114.300000,90.000000,top 25 | "C24","1u","C_0603_1608Metric",141.224000,-121.031000,-90.000000,top 26 | "C25","1u","C_0603_1608Metric",110.363000,-115.062000,90.000000,top 27 | "C26","1u","C_0603_1608Metric",110.363000,-120.904000,-90.000000,top 28 | "C27","1u","C_0603_1608Metric",161.925000,-68.580000,90.000000,top 29 | "C28","1u","C_0603_1608Metric",95.504000,-81.280000,90.000000,top 30 | "C29","1u","C_0603_1608Metric",110.490000,-85.598000,90.000000,top 31 | "C30","1u","C_0603_1608Metric",162.433000,-111.125000,-90.000000,top 32 | "C31","1u","C_0603_1608Metric",178.180000,-64.810000,0.000000,top 33 | "C32","10uF 16V","C_0603_1608Metric",184.600000,-78.300000,180.000000,top 34 | "C33","10uF 16V","C_0603_1608Metric",181.310000,-76.210000,180.000000,top 35 | "C34","10uF 16V","C_0603_1608Metric",185.790000,-101.620000,180.000000,top 36 | "C35","0.1uF","C_0603_1608Metric",185.850000,-94.950000,0.000000,top 37 | "C36","0.1uF","C_0603_1608Metric",181.290000,-77.870000,180.000000,top 38 | "C37","0.1uF","C_0603_1608Metric",185.820000,-96.520000,180.000000,top 39 | "C38","0.1uF","C_0603_1608Metric",186.500000,-81.300000,90.000000,top 40 | "C39","0.1uF","C_0603_1608Metric",179.390000,-100.390000,-90.000000,top 41 | "C40","0.1uF","C_0603_1608Metric",185.800000,-98.160000,180.000000,top 42 | "C41","0.1uF","C_0603_1608Metric",191.300000,-78.400000,0.000000,top 43 | "C42","0.1uF","C_0603_1608Metric",170.140000,-92.960000,180.000000,top 44 | "C43","0.1uF","C_0603_1608Metric",185.800000,-99.960000,180.000000,top 45 | "D1","Yellow","LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder",115.175000,-104.600000,180.000000,top 46 | "D2","Yellow","LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder",115.200000,-101.200000,180.000000,top 47 | "D3","Green","LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder",181.740000,-109.740000,-90.000000,top 48 | "F1","1A","R_1206_3216Metric",173.400000,-63.000000,180.000000,top 49 | "FL1","BLM18RK601SN1D","BEADC1608X95N",187.700000,-77.800000,90.000000,top 50 | "FL2","BLM18RK601SN1D","BEADC1608X95N",181.320000,-74.570000,180.000000,top 51 | "FL3","BLM18RK601SN1D","BEADC1608X95N",186.570000,-104.510000,-90.000000,top 52 | "G***","LOGO","gremlin",138.800000,-68.700000,0.000000,top 53 | "G***","LOGO","graphics_gremlin",123.952000,-59.944000,0.000000,top 54 | "J1","PROG","PinHeader_2x04_P2.54mm_Vertical",117.983000,-68.072000,90.000000,top 55 | "J2","DB15_Female_HighDensity_MountingHoles","23117631",185.000000,-56.000000,90.000000,top 56 | "J3","PJRAN1X1U04X","SWITCHCRAFT_PJRAN1X1U04X",193.900000,-107.300000,90.000000,top 57 | "J4","10029449-111RLF","HDMI_A_Amphenol_10029449-111",192.500000,-88.400000,90.000000,top 58 | "J5","Conn_ISA_8bit","BUS_PC_8BIT",134.620000,-132.080000,0.000000,top 59 | "J6","RFMOD","PinHeader_1x04_P2.54mm_Vertical",179.100000,-44.300000,0.000000,top 60 | "J7","Conn_01x05","PinHeader_1x05_P2.54mm_Vertical",93.980000,-96.520000,180.000000,top 61 | "J8","Conn_02x06_Odd_Even","PinHeader_2x06_P2.54mm_Vertical",162.900000,-81.800000,0.000000,top 62 | "MH1","MNT_KEYSTONE_9200","MNT_KEYSTONE_9200",175.260000,-128.270000,0.000000,top 63 | "R1","10K","RESC1608X55",98.425000,-65.913000,0.000000,top 64 | "R2","10K","RESC1608X55",110.871000,-67.183000,180.000000,top 65 | "R3","10K","RESC1608X55",98.425000,-68.453000,0.000000,top 66 | "R4","10K","RESC1608X55",192.040000,-129.990000,-90.000000,top 67 | "R5","10K","RESC1608X55",190.410000,-129.980000,-90.000000,top 68 | "R6","10","RESC1608X55",150.495000,-92.456000,90.000000,top 69 | "R7","10","RESC1608X55",157.480000,-97.155000,180.000000,top 70 | "R8","10K","RESC1608X55",110.871000,-68.580000,180.000000,top 71 | "R9","10K","RESC1608X55",157.607000,-94.107000,90.000000,top 72 | "R10","10","RESC1608X55",167.259000,-120.523000,180.000000,top 73 | "R11","DNI","RESC1608X55",167.259000,-119.126000,180.000000,top 74 | "R12","2200","R_0603_1608Metric_Pad0.98x0.95mm_HandSolder",111.287500,-104.600000,0.000000,top 75 | "R13","1K","RESC1608X55",158.242000,-121.793000,0.000000,top 76 | "R14","10K","RESC1608X55",178.500000,-72.100000,0.000000,top 77 | "R15","10K","RESC1608X55",181.500000,-64.800000,0.000000,top 78 | "R16","75","RESC1608X55",174.949000,-55.985000,180.000000,top 79 | "R17","75","RESC1608X55",174.949000,-58.398000,180.000000,top 80 | "R18","75","RESC1608X55",168.600000,-53.530000,-90.000000,top 81 | "R19","75","RESC1608X55",174.949000,-60.684000,180.000000,top 82 | "R20","10K","RESC1608X55",144.272000,-82.169000,-90.000000,top 83 | "R21","100","RESC1608X55",147.710000,-89.130000,90.000000,top 84 | "R22","100","RESC1608X55",114.046000,-87.630000,90.000000,top 85 | "R23","10K","RESC1608X55",188.810000,-129.980000,-90.000000,top 86 | "R24","10K","RESC1608X55",187.040000,-129.980000,-90.000000,top 87 | "R25","10","RESC1608X55",160.528000,-115.316000,-90.000000,top 88 | "R26","10","RESC1608X55",164.211000,-111.125000,90.000000,top 89 | "R27","10K","RESC1608X55",159.639000,-108.204000,180.000000,top 90 | "R28","237","RESC1608X55",162.814000,-60.198000,0.000000,top 91 | "R29","237","RESC1608X55",162.814000,-61.722000,0.000000,top 92 | "R30","237","RESC1608X55",164.320000,-75.070000,180.000000,top 93 | "R31","75","RESC1608X55",162.814000,-63.500000,180.000000,top 94 | "R32","1200","R_0603_1608Metric",111.187500,-101.200000,0.000000,top 95 | "R33","0","R_0603_1608Metric",191.800000,-99.800000,-90.000000,top 96 | "R34","DNI","R_0603_1608Metric",195.200000,-99.760000,90.000000,top 97 | "R35","10k","R_0603_1608Metric",167.600000,-102.000000,-90.000000,top 98 | "R36","DNI","R_0603_1608Metric",167.600000,-105.100000,-90.000000,top 99 | "R37","DNI","R_0603_1608Metric",169.800000,-102.000000,-90.000000,top 100 | "R38","10k","R_0603_1608Metric",169.800000,-105.100000,-90.000000,top 101 | "R39","DNI","R_0603_1608Metric",172.000000,-102.000000,-90.000000,top 102 | "R40","10k","R_0603_1608Metric",172.000000,-105.100000,-90.000000,top 103 | "R41","10k","R_0603_1608Metric",181.900000,-101.900000,-90.000000,top 104 | "R42","1200","R_0603_1608Metric",181.740000,-113.290000,90.000000,top 105 | "R43","10k","R_0603_1608Metric",181.190000,-96.390000,-90.000000,top 106 | "R44","10k","R_0603_1608Metric",163.850000,-98.920000,90.000000,top 107 | "R45","5k","R_0603_1608Metric",176.800000,-101.900000,-90.000000,top 108 | "R46","DNI","R_0603_1608Metric",176.800000,-105.000000,-90.000000,top 109 | "R47","10k","R_0603_1608Metric",174.200000,-78.400000,-90.000000,top 110 | "R48","DNI","R_0603_1608Metric",175.900000,-78.400000,90.000000,top 111 | "R49","10k","R_0603_1608Metric",174.900000,-101.900000,-90.000000,top 112 | "R50","10k","R_0603_1608Metric",181.900000,-105.600000,-90.000000,top 113 | "R51","510","R_0603_1608Metric",183.500000,-95.360000,90.000000,top 114 | "R52","33k","R_0603_1608Metric",172.500000,-97.040000,90.000000,top 115 | "R53","DNI","R_0603_1608Metric",174.170000,-97.040000,-90.000000,top 116 | "RN1","604","RESCAV80P320X160X70-8",155.194000,-61.849000,0.000000,top 117 | "RN2","604","RESCAV80P320X160X70-8",155.194000,-66.040000,0.000000,top 118 | "RN3","604","RESCAV80P320X160X70-8",155.194000,-70.231000,0.000000,top 119 | "RN4","604","RESCAV80P320X160X70-8",155.194000,-74.422000,0.000000,top 120 | "RN5","604","RESCAV80P320X160X70-8",155.194000,-78.613000,0.000000,top 121 | "RN6","604","RESCAV80P320X160X70-8",155.194000,-82.677000,0.000000,top 122 | "RN7","300","RESCAV80P320X160X70-8",159.258000,-61.849000,0.000000,top 123 | "RN8","300","RESCAV80P320X160X70-8",159.258000,-67.310000,0.000000,top 124 | "RN9","300","RESCAV80P320X160X70-8",159.258000,-72.898000,0.000000,top 125 | "RN10","300","RESCAV80P320X160X70-8",159.258000,-78.613000,0.000000,top 126 | "SW1","SW_DIP_x04","SW_DIP254P762X635-8",188.600000,-116.100000,0.000000,top 127 | "U1","ICE40HX4K-TQ144","TSQFP50P2200X2200X160-144",130.934000,-88.683999,90.000000,top 128 | "U2","SST26VF080A-104I/SN","SOP127P620X175-8",104.394000,-67.818000,0.000000,top 129 | "U3","74ALVC164245","TSSOP50P810X120-48",174.498000,-116.840000,180.000000,top 130 | "U4","74ALVC164245","TSSOP50P810X120-48",149.225000,-117.856000,90.000000,top 131 | "U5","74ALVC164245","TSSOP50P810X120-48",118.491000,-117.856000,90.000000,top 132 | "U6","ADA4891-3","SOP127P620X175-14",166.878000,-69.342000,0.000000,top 133 | "U7","IS61WV5128BLL-10KLI","SOJ127P1118X376-36",103.251000,-85.852000,0.000000,top 134 | "U8","LD1085D2T33R","TO-263-2",99.000000,-112.300000,180.000000,top 135 | "U9","AP2114HA-1.2","SOT230P700X170-3",99.060000,-102.870000,180.000000,top 136 | "U10","APX803S00-29SA-7","SOT95P230X117-3",146.685000,-82.296000,0.000000,top 137 | "U11","74HCT125","TSOP65P640X110-14",178.200000,-69.600000,0.000000,top 138 | "U12","TFP410PAP","TFP410_ThermalVias",178.500000,-87.100000,90.000000,top 139 | "X1","10MHz","XTAL320X250X120-4",154.051000,-94.107000,180.000000,top 140 | "X2","14.318MHz","XTAL320X250X120-4",159.639000,-111.215000,-90.000000,top 141 | -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.4/gg-hdmi-rev-2.4-bom.csv: -------------------------------------------------------------------------------- 1 | Item,Qty,Designator,Comment,Footprint,Mouser,Non-Mouser Part Number 2 | 1,23,"C1, C7, C8, C9, C10, C11, C13, C14, C15, C16, C17, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31",1u,Capacitor_SMD:C_0603_1608Metric,810-CGA3E1X7R1C105AC, 3 | 2,2,"C2, C4",10uF 16V,Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder,81-ZRB18AR61C106ME1L, 4 | 3,6,"C3, C5, C6, C12, C18, C19",4.7u,Capacitor_SMD:C_0603_1608Metric,187-CL10A475KP8NNNC, 5 | 4,3,"C32, C33, C34",10uF 16V,Capacitor_SMD:C_0603_1608Metric,81-ZRB18AR61C106ME1L, 6 | 5,9,"C35, C36, C37, C38, C39, C40, C41, C42, C43",0.1uF,Capacitor_SMD:C_0603_1608Metric,581-060316C104K, 7 | 6,2,"D1, D2",Yellow,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMY1100, 8 | 7,1,D3,Green,LED_SMD:LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder,78-TLMG1100, 9 | 8,1,F1,1A,Resistor_SMD:R_1206_3216Metric,530-0ZCJ0050FF2G, 10 | 9,3,"FID1, FID2, FID3",Fiducial,Fiducials:Fiducial_1mm_Dia_2mm_Outer,DNP, 11 | 10,3,"FL1, FL2, FL3",BLM18RK601SN1D,libraries:BEADC1608X95N,81-BLM18RK601SN1, 12 | 11,1,J1,PROG,Connector_PinHeader_2.54mm:PinHeader_2x04_P2.54mm_Vertical,,PZ254-2-04-Z-8.5 13 | 12,1,J2,DB15_Female_HighDensity_MountingHoles,Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset8.35mm_Housed_MountingHolesOffset10.89mm,156-3315-E, 14 | 13,1,J3,PJRAN1X1U04X,libraries:SWITCHCRAFT_PJRAN1X1U04X,502-PJRAN1X1U04X, 15 | 14,1,J4,10029449-111RLF,libraries:HDMI_A_Amphenol_10029449-111,649-10029449-111RLF, 16 | 15,1,J5,DNP,Conn:BUS_PC_8BIT,DNP, 17 | 16,1,J6,RFMOD,Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical,,PZ254-1-04-Z-8.5 18 | 17,1,J7,Conn_01x05,Connector_PinHeader_2.54mm:PinHeader_1x05_P2.54mm_Vertical,,PZ254-1-05-Z-8.5 19 | 18,1,J8,Conn_02x06_Odd_Even,Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Vertical,,PZ254-2-06-Z-8.5 20 | 19,13,"R1, R2, R3, R4, R5, R8, R9, R14, R15, R20, R23, R24, R27",10K,Passive:RESC1608X55,603-RC0603FR-0710KL, 21 | 20,5,"R6, R7, R10, R25, R26",10,Passive:RESC1608X55,603-RC0603FR-0710RL, 22 | 21,1,R11,DNP,Passive:RESC1608X55,DNP, 23 | 22,1,R12,2200,Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder,603-RC0603FR-072K2L, 24 | 23,1,R13,1K,Passive:RESC1608X55,603-RC0603FR-071KL, 25 | 24,5,"R16, R17, R18, R19, R31",75,Passive:RESC1608X55,603-RC0603FR-0775RL, 26 | 25,2,"R21, R22",100,Passive:RESC1608X55,603-RC0603FR-07100RL, 27 | 26,3,"R28, R29, R30",237,Passive:RESC1608X55,603-RC0603FR-07237RL, 28 | 27,2,"R32, R42",1200,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-101K2L, 29 | 28,1,R33,0,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-070RL, 30 | 29,7,"R34, R36, R37, R39, R46, R48, R53",DNP,Resistor_SMD:R_0603_1608Metric,DNP, 31 | 30,9,"R35, R38, R40, R41, R43, R44, R47, R49, R50",10k,Resistor_SMD:R_0603_1608Metric,RC0603JR-0710KL, 32 | 31,1,R45,5k,Resistor_SMD:R_0603_1608Metric,603-RT0603BRE075KL, 33 | 32,1,R51,510,Resistor_SMD:R_0603_1608Metric,603-RC0603JR-07510RL, 34 | 33,1,R52,33k,Resistor_SMD:R_0603_1608Metric,603-RC0603FR-1033KL, 35 | 34,6,"RN1, RN2, RN3, RN4, RN5, RN6",604,Passive:RESCAV80P320X160X70-8,652-CAY16-6040F4LF, 36 | 35,4,"RN7, RN8, RN9, RN10",300,Passive:RESCAV80P320X160X70-8,652-CAY16-3000F4LF, 37 | 36,1,SW1,SW_DIP_x04,Switch:SW_DIP254P762X635-8,706-76PSB04ST, 38 | 37,1,U1,ICE40HX4K-TQ144,Active:TSQFP50P2200X2200X160-144,842-ICE40HX4K-TQ144, 39 | 38,1,U2,SST26VF080A-104I/SN,Active:SOP127P620X175-8,579-26VF080A-104I/SN, 40 | 39,3,"U3, U4, U5",74ALVC164245,Active:TSSOP50P810X120-48,771-74ALVC164245, 41 | 40,1,U6,ADA4891-3,Active:SOP127P620X175-14,584-ADA4891-3ARZ, 42 | 41,1,U7,IS61WV5128BLL-10KLI,Active:SOJ127P1118X376-36,870-61WV5128B10KLI, 43 | 42,1,U8,LD1085D2T33R,Package_TO_SOT_SMD:TO-263-2,511-LD1085D2T33-TR, 44 | 43,1,U9,AP2114HA-1.2,Active:SOT230P700X170-3,621-AP2114HA-1.2TRG1, 45 | 44,1,U10,APX803S00-29SA-7,Active:SOT95P230X117-3,621-APX803S00-29SA-7, 46 | 45,1,U11,74HCT125,Active:TSOP65P640X110-14,771-74HCT125PW-T, 47 | 46,1,U12,TFP410PAP,Package_QFP:HTQFP-64-1EP_10x10mm_P0.5mm_EP8x8mm_Mask4.4x4.4mm_ThermalVias,595-TFP410PAP, 48 | 47,1,X1,10MHz,Passive:XTAL320X250X120-4,520-ECS-2333-100-BNT, 49 | 48,1,X2,14.318MHz,Passive:XTAL320X250X120-4,815-ASE-14.318MLCT, 50 | 49,2,-,Jack screw for VGA port,UNC 4#40,710-94511000, 51 | -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.4/gg-hdmi-rev-2.4-gerbers-drill.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.4/gg-hdmi-rev-2.4-gerbers-drill.zip -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.4/gg-hdmi-rev-2.4-schematic.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/fab/gg-hdmi-rev-2.4/gg-hdmi-rev-2.4-schematic.pdf -------------------------------------------------------------------------------- /fab/gg-hdmi-rev-2.4/gg-hdmi-rev-2.4-top-pos.csv: -------------------------------------------------------------------------------- 1 | Ref,Val,Package,PosX,PosY,Rot,Side 2 | "C1","1u","C_0603_1608Metric",154.051000,-97.155000,180.000000,top 3 | "C2","10uF 16V","C_0603_1608Metric_Pad1.08x0.95mm_HandSolder",110.600000,-108.850000,90.000000,top 4 | "C3","4.7u","C_0603_1608Metric",105.791000,-105.410000,90.000000,top 5 | "C4","10uF 16V","C_0603_1608Metric_Pad1.08x0.95mm_HandSolder",92.800000,-120.637500,-90.000000,top 6 | "C5","4.7u","C_0603_1608Metric",105.791000,-101.600000,-90.000000,top 7 | "C6","4.7u","C_0603_1608Metric",145.980000,-89.150000,-90.000000,top 8 | "C7","1u","C_0603_1608Metric",123.800000,-103.000000,90.000000,top 9 | "C8","1u","C_0603_1608Metric",134.874000,-103.632000,-90.000000,top 10 | "C9","1u","C_0603_1608Metric",144.145000,-89.154000,-90.000000,top 11 | "C10","1u","C_0603_1608Metric",144.780000,-92.964000,0.000000,top 12 | "C11","1u","C_0603_1608Metric",144.780000,-95.885000,0.000000,top 13 | "C12","4.7u","C_0603_1608Metric",115.697000,-87.630000,-90.000000,top 14 | "C13","1u","C_0603_1608Metric",131.826000,-73.914000,90.000000,top 15 | "C14","1u","C_0603_1608Metric",129.794000,-73.914000,90.000000,top 16 | "C15","1u","C_0603_1608Metric",117.348000,-87.630000,-90.000000,top 17 | "C16","1u","C_0603_1608Metric",117.348000,-91.186000,-90.000000,top 18 | "C17","1u","C_0603_1608Metric",116.586000,-80.899000,180.000000,top 19 | "C18","4.7u","C_0603_1608Metric",124.968000,-74.676000,180.000000,top 20 | "C19","4.7u","C_0603_1608Metric",136.398000,-103.632000,-90.000000,top 21 | "C20","1u","C_0603_1608Metric",110.871000,-65.786000,0.000000,top 22 | "C21","1u","C_0603_1608Metric",172.466000,-108.966000,180.000000,top 23 | "C22","1u","C_0603_1608Metric",176.530000,-108.966000,0.000000,top 24 | "C23","1u","C_0603_1608Metric",141.351000,-114.300000,90.000000,top 25 | "C24","1u","C_0603_1608Metric",141.224000,-121.031000,-90.000000,top 26 | "C25","1u","C_0603_1608Metric",110.363000,-115.062000,90.000000,top 27 | "C26","1u","C_0603_1608Metric",110.363000,-120.904000,-90.000000,top 28 | "C27","1u","C_0603_1608Metric",161.925000,-68.580000,90.000000,top 29 | "C28","1u","C_0603_1608Metric",95.504000,-81.280000,90.000000,top 30 | "C29","1u","C_0603_1608Metric",110.490000,-85.598000,90.000000,top 31 | "C30","1u","C_0603_1608Metric",162.433000,-111.125000,-90.000000,top 32 | "C31","1u","C_0603_1608Metric",178.180000,-64.810000,0.000000,top 33 | "C32","10uF 16V","C_0603_1608Metric",184.600000,-78.300000,180.000000,top 34 | "C33","10uF 16V","C_0603_1608Metric",181.310000,-76.210000,180.000000,top 35 | "C34","10uF 16V","C_0603_1608Metric",185.790000,-101.620000,180.000000,top 36 | "C35","0.1uF","C_0603_1608Metric",185.850000,-94.950000,0.000000,top 37 | "C36","0.1uF","C_0603_1608Metric",181.290000,-77.870000,180.000000,top 38 | "C37","0.1uF","C_0603_1608Metric",185.820000,-96.520000,180.000000,top 39 | "C38","0.1uF","C_0603_1608Metric",186.500000,-81.300000,90.000000,top 40 | "C39","0.1uF","C_0603_1608Metric",179.390000,-100.390000,-90.000000,top 41 | "C40","0.1uF","C_0603_1608Metric",185.800000,-98.160000,180.000000,top 42 | "C41","0.1uF","C_0603_1608Metric",191.300000,-78.400000,0.000000,top 43 | "C42","0.1uF","C_0603_1608Metric",170.140000,-92.960000,180.000000,top 44 | "C43","0.1uF","C_0603_1608Metric",185.800000,-99.960000,180.000000,top 45 | "D1","Yellow","LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder",115.175000,-104.600000,180.000000,top 46 | "D2","Yellow","LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder",115.200000,-101.200000,180.000000,top 47 | "D3","Green","LED_0603_1608Metric_Pad1.05x0.95mm_HandSolder",181.740000,-109.740000,-90.000000,top 48 | "F1","1A","R_1206_3216Metric",173.400000,-63.000000,180.000000,top 49 | "FL1","BLM18RK601SN1D","BEADC1608X95N",187.700000,-77.800000,90.000000,top 50 | "FL2","BLM18RK601SN1D","BEADC1608X95N",181.320000,-74.570000,180.000000,top 51 | "FL3","BLM18RK601SN1D","BEADC1608X95N",186.570000,-104.510000,-90.000000,top 52 | "G***","LOGO","gremlin",138.800000,-68.700000,0.000000,top 53 | "G***","LOGO","graphics_gremlin",123.952000,-59.944000,0.000000,top 54 | "J1","PROG","PinHeader_2x04_P2.54mm_Vertical",117.983000,-68.072000,90.000000,top 55 | "J2","DB15_Female_HighDensity_MountingHoles","23117631",185.000000,-56.000000,90.000000,top 56 | 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Part="1" 244 | AR Path="/603A03FF/614E7978" Ref="C28" Part="1" 245 | F 0 "C28" H 7292 3946 50 0000 L CNN 246 | F 1 "1u" H 7292 3855 50 0000 L CNN 247 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 7200 3900 50 0001 C CNN 248 | F 3 "~" H 7200 3900 50 0001 C CNN 249 | F 4 "810-CGA3E1X7R1C105AC" H 0 0 50 0001 C CNN "Mouser" 250 | 1 7200 3900 251 | 1 0 0 -1 252 | $EndComp 253 | $Comp 254 | L Device:C_Small C? 255 | U 1 1 614E797E 256 | P 7450 3900 257 | AR Path="/614E797E" Ref="C?" Part="1" 258 | AR Path="/6043556F/614E797E" Ref="C?" Part="1" 259 | AR Path="/603A03FF/614E797E" Ref="C29" Part="1" 260 | F 0 "C29" H 7542 3946 50 0000 L CNN 261 | F 1 "1u" H 7542 3855 50 0000 L CNN 262 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 7450 3900 50 0001 C CNN 263 | F 3 "~" H 7450 3900 50 0001 C CNN 264 | F 4 "810-CGA3E1X7R1C105AC" H 0 0 50 0001 C CNN "Mouser" 265 | 1 7450 3900 266 | 1 0 0 -1 267 | $EndComp 268 | Wire Wire Line 269 | 7200 4000 7200 4050 270 | Wire Wire Line 271 | 7450 4000 7450 4050 272 | Wire Wire Line 273 | 7200 3800 7200 3750 274 | Wire Wire Line 275 | 7200 3750 7450 3750 276 | Wire Wire Line 277 | 7450 3750 7450 3800 278 | Wire Wire Line 279 | 7450 3750 7450 3650 280 | Connection ~ 7450 3750 281 | Wire Wire Line 282 | 7200 4050 7450 4050 283 | Wire Wire Line 284 | 7450 4050 7450 4150 285 | Connection ~ 7450 4050 286 | $Comp 287 | L power:+3V3 #PWR? 288 | U 1 1 614EBB64 289 | P 7450 3650 290 | AR Path="/614EBB64" Ref="#PWR?" Part="1" 291 | AR Path="/603A03FF/614EBB64" Ref="#PWR074" Part="1" 292 | F 0 "#PWR074" H 7450 3500 50 0001 C CNN 293 | F 1 "+3V3" H 7465 3823 50 0000 C CNN 294 | F 2 "" H 7450 3650 50 0001 C CNN 295 | F 3 "" H 7450 3650 50 0001 C CNN 296 | 1 7450 3650 297 | 1 0 0 -1 298 | $EndComp 299 | $Comp 300 | L power:GND #PWR? 301 | U 1 1 614EC04E 302 | P 7450 4150 303 | AR Path="/614EC04E" Ref="#PWR?" Part="1" 304 | AR Path="/603A03FF/614EC04E" Ref="#PWR075" Part="1" 305 | F 0 "#PWR075" H 7450 3900 50 0001 C CNN 306 | F 1 "GND" H 7455 3977 50 0000 C CNN 307 | F 2 "" H 7450 4150 50 0001 C CNN 308 | F 3 "" H 7450 4150 50 0001 C CNN 309 | 1 7450 4150 310 | 1 0 0 -1 311 | $EndComp 312 | Wire Wire Line 313 | 5000 4600 5000 4700 314 | Connection ~ 5000 4700 315 | Wire Wire Line 316 | 5000 4700 5000 5100 317 | $Comp 318 | L power:GND #PWR? 319 | U 1 1 612B8100 320 | P 5000 5100 321 | AR Path="/612B8100" Ref="#PWR?" Part="1" 322 | AR Path="/603A03FF/612B8100" Ref="#PWR083" Part="1" 323 | F 0 "#PWR083" H 5000 4850 50 0001 C CNN 324 | F 1 "GND" H 5005 4927 50 0000 C CNN 325 | F 2 "" H 5000 5100 50 0001 C CNN 326 | F 3 "" H 5000 5100 50 0001 C CNN 327 | 1 5000 5100 328 | 1 0 0 -1 329 | $EndComp 330 | Text Notes 7100 6800 0 100 ~ 0 331 | GRAPHICS GREMLIN (with HDMI) 332 | Text Notes 7100 6950 0 50 ~ 0 333 | DESIGN BY @TubeTimeUS\nModified by @yeokm1 334 | Text Notes 550 7700 0 50 ~ 0 335 | This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 International License. \nTo view a copy of this license, visit http://creativecommons.org/licenses/by-sa/4.0/ or send\na letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. 336 | Wire Bus Line 337 | 6700 2300 6700 3200 338 | Wire Bus Line 339 | 4750 2300 4750 4300 340 | $EndSCHEMATC 341 | -------------------------------------------------------------------------------- /isa-video/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name ISAVideo)(type KiCad)(uri ${KIPRJMOD}/ISAVideo.pretty)(options "")(descr "")) 3 | (lib (name libraries)(type KiCad)(uri ${KIPRJMOD}/libraries)(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /isa-video/isavideo-rescue.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /isa-video/isavideo.kicad_prl: -------------------------------------------------------------------------------- 1 | { 2 | "board": { 3 | "active_layer": 0, 4 | "active_layer_preset": "", 5 | "auto_track_width": true, 6 | "hidden_netclasses": [], 7 | "hidden_nets": [], 8 | "high_contrast_mode": 0, 9 | "net_color_mode": 1, 10 | "opacity": { 11 | "images": 0.6, 12 | "pads": 1.0, 13 | "tracks": 1.0, 14 | "vias": 1.0, 15 | "zones": 0.6 16 | }, 17 | "selection_filter": { 18 | "dimensions": true, 19 | "footprints": true, 20 | "graphics": true, 21 | "keepouts": true, 22 | "lockedItems": false, 23 | "otherItems": true, 24 | "pads": true, 25 | "text": true, 26 | "tracks": true, 27 | "vias": true, 28 | "zones": true 29 | }, 30 | "visible_items": [ 31 | 0, 32 | 1, 33 | 2, 34 | 3, 35 | 4, 36 | 5, 37 | 6, 38 | 7, 39 | 8, 40 | 9, 41 | 10, 42 | 11, 43 | 12, 44 | 13, 45 | 14, 46 | 15, 47 | 16, 48 | 17, 49 | 18, 50 | 19, 51 | 20, 52 | 21, 53 | 22, 54 | 23, 55 | 24, 56 | 25, 57 | 26, 58 | 27, 59 | 28, 60 | 29, 61 | 30, 62 | 32, 63 | 33, 64 | 34, 65 | 35, 66 | 36, 67 | 39, 68 | 40 69 | ], 70 | "visible_layers": "003ffff_80000007", 71 | "zone_display_mode": 0 72 | }, 73 | "meta": { 74 | "filename": "isavideo.kicad_prl", 75 | "version": 3 76 | }, 77 | "project": { 78 | "files": [] 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /isa-video/libraries/23117631.kicad_mod: -------------------------------------------------------------------------------- 1 | (footprint "23117631" (version 20221018) (generator pcbnew) 2 | (layer "F.Cu") 3 | (descr "2311763-1-2") 4 | (tags "Connector") 5 | (attr through_hole) 6 | (fp_text reference "J**" (at -4.315 9.07) (layer "F.SilkS") 7 | (effects (font (size 1.27 1.27) (thickness 0.254))) 8 | (tstamp bc60d677-2f7a-47a7-89f6-6fbfae59c813) 9 | ) 10 | (fp_text value "23117631" (at -4.315 9.07) (layer "F.SilkS") hide 11 | (effects (font (size 1.27 1.27) (thickness 0.254))) 12 | (tstamp 34a2a1fd-eefd-4fc1-92db-28bdc90f9d29) 13 | ) 14 | (fp_text user "${REFERENCE}" (at -4.315 9.07) (layer "F.Fab") 15 | (effects (font (size 1.27 1.27) (thickness 0.254))) 16 | (tstamp b678131e-a0b2-4e83-8352-36f59932ab2f) 17 | ) 18 | (fp_line (start -19.715 -1.83) (end 11.085 -1.83) 19 | (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 01c12d6b-a5b1-4814-9124-f7dc6a130eca)) 20 | (fp_line (start -19.715 13.97) (end -19.715 -1.83) 21 | (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp bde1c32a-be96-4fee-ad94-50769350e91f)) 22 | (fp_line (start 11.085 -1.83) (end 11.085 13.97) 23 | (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 160330f8-cd67-44ee-84c0-e3d4746baf16)) 24 | (fp_line (start 11.085 13.97) (end -19.715 13.97) 25 | (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 600bff17-03e8-44ac-9aae-a724518667fb)) 26 | (fp_line (start -20.715 -2.83) (end 12.085 -2.83) 27 | (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp 14dc0d12-e6be-400d-ab51-8064e3fee9a1)) 28 | (fp_line (start -20.715 20.97) (end -20.715 -2.83) 29 | (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp 93bd86a1-7e84-4a51-b17f-a1ab3d905423)) 30 | (fp_line (start 12.085 -2.83) (end 12.085 20.97) 31 | (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp 0ea44abb-e8bd-4f6f-80ca-baddf4f262ba)) 32 | (fp_line (start 12.085 20.97) (end -20.715 20.97) 33 | (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp 69e7f7b8-fcc5-4e40-99de-c8d8acd12f44)) 34 | (fp_line (start -19.715 -1.83) (end 11.085 -1.83) 35 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 65cd2b5f-7819-4dc4-aca2-316f867a04ea)) 36 | (fp_line (start -19.715 13.97) (end -19.715 -1.83) 37 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp d99e04bb-3c2b-4a9c-8249-f1b4572d3c9c)) 38 | (fp_line (start -12.48 13.97) (end -12.48 19.97) 39 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 42725dd6-8455-4c39-a73e-6e2912352ffe)) 40 | (fp_line (start -12.48 19.97) (end 3.85 19.97) 41 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 1e9b1acf-f0b7-4811-a380-34762ef2d357)) 42 | (fp_line (start 3.85 19.97) (end 3.85 13.97) 43 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 069592a3-758c-4dfa-b467-2deee3ef6616)) 44 | (fp_line (start 11.085 -1.83) (end 11.085 13.97) 45 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 1f485730-abfe-40c4-8434-05fbc6a24fac)) 46 | (fp_line (start 11.085 13.97) (end -19.715 13.97) 47 | (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 227df9df-bc25-4de5-b7a2-d5e9687d6405)) 48 | (pad "1" thru_hole rect (at 0 0) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 75145a00-c548-4542-b6d2-8f285cf1d196)) 49 | (pad "2" thru_hole circle (at -2.29 0) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 05a1753c-1e3e-4889-b203-e68cf93dfdc7)) 50 | (pad "3" thru_hole circle (at -4.58 0) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp eff1b102-b89d-4564-9306-fb459d56b712)) 51 | (pad "4" thru_hole circle (at -6.87 0) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 8eb5fd91-63fa-4195-b3cb-c1a2ed8cf5f5)) 52 | (pad "5" thru_hole circle (at -9.16 0) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp a89d5c77-dba2-4c12-81e7-9885358ceceb)) 53 | (pad "6" thru_hole circle (at 1.145 2.54) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 2b90684d-85f7-402b-a210-a0dcf5d55776)) 54 | (pad "7" thru_hole circle (at -1.145 2.54) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 4142644e-c9e2-4fed-964f-9980a7393de5)) 55 | (pad "8" thru_hole circle (at -3.435 2.54) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 3478f3c7-683c-41cc-a6b2-efd3a2bc53d6)) 56 | (pad "9" thru_hole circle (at -5.725 2.54) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 67ed7d66-5f72-49e5-9939-a143639dc0a1)) 57 | (pad "10" thru_hole circle (at -8.015 2.54) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 832ea557-fc6e-4227-b8a1-fe3769ff0e93)) 58 | (pad "11" thru_hole circle (at 0 5.08) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp e0be2107-79e1-43ba-a6d3-91f2681aa7ef)) 59 | (pad "12" thru_hole circle (at -2.29 5.08) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp b325e175-db17-4ca8-a750-b25dce6d5abe)) 60 | (pad "13" thru_hole circle (at -4.58 5.08) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 60e05a85-3500-4ef3-a8e8-80c652995246)) 61 | (pad "14" thru_hole circle (at -6.87 5.08) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp be1c745a-cd65-412e-ac67-614715db0d86)) 62 | (pad "15" thru_hole circle (at -9.16 5.08) (size 1.785 1.785) (drill 1.19) (layers "*.Cu" "*.Mask") (tstamp 49b804ae-2eec-49ef-9783-6e982ab3d45c)) 63 | (pad "MH1" thru_hole circle (at 8.185 2.54) (size 4.77 4.77) (drill 3.18) (layers "*.Cu" "*.Mask") (tstamp 12c58c17-4f6b-4697-9ece-0c51335d4a9b)) 64 | (pad "MH2" thru_hole circle (at -16.815 2.54) (size 4.77 4.77) (drill 3.18) (layers "*.Cu" "*.Mask") (tstamp 0a08214c-caee-42b3-8d58-ac0e337d5ce7)) 65 | (model "${KIPRJMOD}/libraries/c-2311763-1-b1-3d.stp" 66 | (offset (xyz -4.3 -20 6.3)) 67 | (scale (xyz 1 1 1)) 68 | (rotate (xyz -90 0 0)) 69 | ) 70 | ) 71 | -------------------------------------------------------------------------------- /isa-video/libraries/BEADC1608X95N.kicad_mod: -------------------------------------------------------------------------------- 1 | (footprint "BEADC1608X95N" (version 20221018) (generator pcbnew) 2 | (layer "F.Cu") 3 | (attr through_hole) 4 | (fp_text reference "REF**" (at -0.24 -1.07) (layer "F.SilkS") 5 | (effects (font (size 0.393701 0.393701) (thickness 0.15))) 6 | (tstamp e29699a2-a11e-4333-ba84-5b7fa2b05d72) 7 | ) 8 | (fp_text value "BEADC1608X95N" (at 1.76 1.07) (layer "F.Fab") 9 | (effects (font (size 0.393701 0.393701) (thickness 0.15))) 10 | (tstamp b3801723-5235-46c8-b93f-9c1ecca348a7) 11 | ) 12 | (fp_line (start -1.485 -0.735) (end 1.485 -0.735) 13 | (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp bddfe1a4-e558-41f7-9572-cde3a9c35543)) 14 | (fp_line (start -1.485 0.735) (end -1.485 -0.735) 15 | (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 02285b43-343d-40e3-a45d-8f4a6ca01a23)) 16 | (fp_line (start -1.485 0.735) (end 1.485 0.735) 17 | (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 447be3bd-7903-4c67-9773-0eba26794ef7)) 18 | (fp_line (start 1.485 0.735) (end 1.485 -0.735) 19 | (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 7c65bf5d-2f2e-4b0a-9b84-0ea7819bc443)) 20 | (fp_line (start -0.88 0.48) (end -0.88 -0.48) 21 | (stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp 6c74790d-ecbf-4145-95dc-51338c340b01)) 22 | (fp_line (start 0.88 -0.48) (end -0.88 -0.48) 23 | (stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp c05641dd-b011-4340-8175-f886bbb0b2ee)) 24 | (fp_line (start 0.88 0.48) (end -0.88 0.48) 25 | (stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp a96a968d-f90d-4026-a5e4-5def0035fd8f)) 26 | (fp_line (start 0.88 0.48) (end 0.88 -0.48) 27 | (stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp 93b22610-b10c-4957-830f-b881a0c04b50)) 28 | (pad "1" smd rect (at -0.735 0) (size 1 0.97) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 90eb2ef9-d22c-432e-a390-3c38f5c62f0b)) 29 | (pad "2" smd rect (at 0.735 0) (size 1 0.97) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp cdab0922-96f4-45bf-a308-0a4a97761ac2)) 30 | (model "${KIPRJMOD}/libraries/BLM18RK601SN1D.step" 31 | (offset (xyz 0 -0.48 0)) 32 | (scale (xyz 1 1 1)) 33 | (rotate (xyz 0 0 0)) 34 | ) 35 | ) 36 | -------------------------------------------------------------------------------- /isa-video/libraries/BLM18RK601SN1D.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | #(c) SnapEDA 2016 (snapeda.com) 4 | #This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0 5 | # 6 | # BLM18RK601SN1D 7 | # 8 | DEF BLM18RK601SN1D FL 0 40 N N 1 L N 9 | F0 "FL" -500 200 50 H V L BNN 10 | F1 "BLM18RK601SN1D" -500 -200 50 H V L BNN 11 | F2 "BEADC1608X95N" 0 0 50 H I L BNN 12 | F3 "" 0 0 50 H I L BNN 13 | DRAW 14 | P 2 0 0 10 0 0 25 75 N 15 | P 2 0 0 10 25 75 75 -75 N 16 | P 2 0 0 10 75 -75 125 75 N 17 | P 2 0 0 10 125 75 175 -75 N 18 | P 2 0 0 10 175 -75 225 75 N 19 | P 2 0 0 10 225 75 275 -75 N 20 | P 2 0 0 10 275 -75 325 75 N 21 | P 2 0 0 10 325 75 375 -75 N 22 | P 2 0 0 10 375 -75 400 0 N 23 | A -450 0 50 -1 1800 0 0 10 N -500 0 -400 0 24 | A -350 0 50 -1 1800 0 0 10 N -400 0 -300 0 25 | A -250 0 50 -1 1800 0 0 10 N -300 0 -200 0 26 | A -150 0 50 -1 1800 0 0 10 N -200 0 -100 0 27 | P 2 0 0 10 0 0 -100 0 N 28 | X ~ 2 500 0 100 L 40 40 0 0 P 29 | X ~ 1 -600 0 100 R 40 40 0 0 P 30 | ENDDRAW 31 | ENDDEF 32 | # 33 | # End Library -------------------------------------------------------------------------------- /isa-video/libraries/HDMI_A_Amphenol_10029449-111.kicad_mod: -------------------------------------------------------------------------------- 1 | (module HDMI_A_Amphenol_10029449-111 (layer F.Cu) (tedit 5E1BB628) 2 | (descr "HDMI, Type A, 10029449-111RLF, https://www.amphenol-icc.com/hdmi-10029449111rlf.html") 3 | (tags "HDMI type a connector") 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -4.8) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value HDMI_A_Amphenol_10029449-111 (at 0 8.45) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -8.2 1.7) (end -8.2 -1.3) (layer F.SilkS) (width 0.12)) 12 | (fp_line (start -8.2 -3.4) (end -5 -3.4) (layer F.SilkS) (width 0.12)) 13 | (fp_line (start -8.2 4.2) (end -8.2 5.2) (layer F.SilkS) (width 0.12)) 14 | (fp_line (start 8.2 5.2) (end 8.2 4.2) (layer F.SilkS) (width 0.12)) 15 | (fp_line (start 8.2 -3.4) (end 8.2 -2.8) (layer F.SilkS) (width 0.12)) 16 | (fp_line (start 8.2 -3.4) (end 5.5 -3.4) (layer F.SilkS) (width 0.12)) 17 | (fp_line (start 5.5 -3.4) (end 5.5 -4.05) (layer F.SilkS) (width 0.12)) 18 | (fp_line (start 8.1 -3.3) (end 8.1 6.42) (layer F.Fab) (width 0.1)) 19 | (fp_line (start 8.1 6.42) (end -8.1 6.42) (layer F.Fab) (width 0.1)) 20 | (fp_line (start -8.1 6.42) (end -8.1 -3.3) (layer F.Fab) (width 0.1)) 21 | (fp_line (start -8.1 -3.3) (end 8.1 -3.3) (layer F.Fab) (width 0.1)) 22 | (fp_text user %R (at 0 1.45) (layer F.Fab) 23 | (effects (font (size 1 1) (thickness 0.15))) 24 | ) 25 | (fp_line (start -9 -4.4) (end 9 -4.4) (layer F.CrtYd) (width 0.05)) 26 | (fp_line (start 9 -4.4) (end 9 6.92) (layer F.CrtYd) (width 0.05)) 27 | (fp_line (start 9 6.92) (end -9 6.92) (layer F.CrtYd) (width 0.05)) 28 | (fp_line (start -9 6.92) (end -9 -4.4) (layer F.CrtYd) (width 0.05)) 29 | (fp_line (start 4.75 -1.8) (end 4.5 -1.3) (layer F.Fab) (width 0.1)) 30 | (fp_line (start 4.5 -1.3) (end 5 -1.3) (layer F.Fab) (width 0.1)) 31 | (fp_line (start 5 -1.3) (end 4.75 -1.8) (layer F.Fab) (width 0.1)) 32 | (fp_line (start -3 5.45) (end 3 5.45) (layer Dwgs.User) (width 0.1)) 33 | (fp_text user "PCB Edge" (at 0 4.7) (layer Dwgs.User) 34 | (effects (font (size 0.5 0.5) (thickness 0.1))) 35 | ) 36 | (fp_line (start -8.2 -3.4) (end -8.2 -2.8) (layer F.SilkS) (width 0.12)) 37 | (fp_line (start 8.2 1.7) (end 8.2 -1.3) (layer F.SilkS) (width 0.12)) 38 | (pad 1 smd rect (at 4.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 39 | (pad 2 smd rect (at 4.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 40 | (pad 3 smd rect (at 3.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 41 | (pad 4 smd rect (at 3.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 42 | (pad 5 smd rect (at 2.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 43 | (pad 6 smd rect (at 2.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 44 | (pad 7 smd rect (at 1.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 45 | (pad 8 smd rect (at 1.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 46 | (pad 9 smd rect (at 0.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 47 | (pad 10 smd rect (at 0.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 48 | (pad 11 smd rect (at -0.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 49 | (pad 12 smd rect (at -0.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 50 | (pad 13 smd rect (at -1.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 51 | (pad 14 smd rect (at -1.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 52 | (pad 15 smd rect (at -2.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 53 | (pad 16 smd rect (at -2.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 54 | (pad 17 smd rect (at -3.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 55 | (pad 18 smd rect (at -3.75 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 56 | (pad 19 smd rect (at -4.25 -2.95) (size 0.3 1.9) (layers F.Cu F.Paste F.Mask)) 57 | (pad SH thru_hole circle (at 7.25 -2.05) (size 2 2) (drill 1.3) (layers *.Cu *.Mask)) 58 | (pad SH thru_hole circle (at -7.25 -2.05) (size 2 2) (drill 1.3) (layers *.Cu *.Mask)) 59 | (pad SH thru_hole circle (at 7.85 2.9) (size 2 2) (drill 1.3) (layers *.Cu *.Mask)) 60 | (pad SH thru_hole circle (at -7.85 2.9) (size 2 2) (drill 1.3) (layers *.Cu *.Mask)) 61 | (model 10029449-111RLF.stp 62 | (offset (xyz 0 0.3 3.5)) 63 | (scale (xyz 1 1 1)) 64 | (rotate (xyz 180 0 0)) 65 | ) 66 | ) 67 | -------------------------------------------------------------------------------- /isa-video/libraries/PJRAN1X1U04X.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.3 2 | #encoding utf-8 3 | #(c) SnapEDA 2016 (snapeda.com) 4 | #This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0 5 | # 6 | # PJRAN1X1U04X 7 | # 8 | DEF PJRAN1X1U04X J 0 40 Y N 1 L N 9 | F0 "J" -200 200 50 H V L BNN 10 | F1 "PJRAN1X1U04X" -200 -250 50 H V L BNN 11 | F2 "SWITCHCRAFT_PJRAN1X1U04X" 0 0 50 H I L BNN 12 | F3 "" 0 0 50 H I L BNN 13 | F4 "Manufacturer recommendations" 0 0 50 H I L BNN "STANDARD" 14 | F5 "A" 0 0 50 H I L BNN "PARTREV" 15 | F6 "Switchcraft" 0 0 50 H I L BNN "MANUFACTURER" 16 | F7 "13.0mm" 0 0 50 H I L BNN "MAXIMUM_PACKAGE_HEIGHT" 17 | DRAW 18 | P 3 0 0 10 0 90 10 50 -10 50 f 19 | P 2 0 0 10 0 0 200 0 N 20 | P 2 0 0 10 0 0 0 100 N 21 | P 2 0 0 10 200 -100 -200 -100 N 22 | P 2 0 0 10 200 100 -50 100 N 23 | P 2 0 0 10 -200 -100 -200 -25 N 24 | P 2 0 0 10 -200 -25 -175 -25 N 25 | P 2 0 0 10 -175 -25 -175 150 N 26 | P 2 0 0 10 -175 150 -225 150 N 27 | P 2 0 0 10 -225 150 -225 -25 N 28 | P 2 0 0 10 -225 -25 -200 -25 N 29 | P 2 0 0 10 -50 100 -75 75 N 30 | P 2 0 0 10 -75 75 -100 100 N 31 | X ~ 2 300 100 100 L 40 40 0 0 P 32 | X ~ 1 300 -100 100 L 40 40 0 0 P 33 | X ~ 3 300 0 100 L 40 40 0 0 P 34 | ENDDRAW 35 | ENDDEF 36 | # 37 | # End Library -------------------------------------------------------------------------------- /isa-video/libraries/SWITCHCRAFT_PJRAN1X1U04X.kicad_mod: -------------------------------------------------------------------------------- 1 | 2 | (module SWITCHCRAFT_PJRAN1X1U04X (layer F.Cu) (tedit 610EA737) 3 | (descr "") 4 | (fp_text reference REF** (at -1.825 -8.635 0) (layer F.SilkS) 5 | (effects (font (size 1.0 1.0) (thickness 0.15))) 6 | ) 7 | (fp_text value SWITCHCRAFT_PJRAN1X1U04X (at 10.24 -7.135 0) (layer F.Fab) 8 | (effects (font (size 1.0 1.0) (thickness 0.15))) 9 | ) 10 | (fp_line (start 5.0 -6.0) (end -5.0 -6.0) (layer F.SilkS) (width 0.127)) 11 | (fp_line (start -5.0 -6.0) (end -5.0 4.0) (layer F.SilkS) (width 0.127)) 12 | (fp_line (start 5.0 4.0) (end 5.0 -6.0) (layer F.SilkS) (width 0.127)) 13 | (fp_line (start 5.25 -6.25) (end -5.25 -6.25) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -5.25 -6.25) (end -5.25 4.25) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -5.25 4.25) (end -4.4 4.25) (layer F.CrtYd) (width 0.05)) 16 | (fp_line (start -4.4 4.25) (end -4.4 13.75) (layer F.CrtYd) (width 0.05)) 17 | (fp_line (start -4.4 13.75) (end 4.4 13.75) (layer F.CrtYd) (width 0.05)) 18 | (fp_line (start 4.4 13.75) (end 4.4 4.25) (layer F.CrtYd) (width 0.05)) 19 | (fp_line (start 4.4 4.25) (end 5.25 4.25) (layer F.CrtYd) (width 0.05)) 20 | (fp_line (start 5.25 4.25) (end 5.25 -6.25) (layer F.CrtYd) (width 0.05)) 21 | (fp_line (start -5.0 -6.0) (end -5.0 4.0) (layer F.Fab) (width 0.127)) 22 | (fp_line (start 5.0 4.0) (end 5.0 -6.0) (layer F.Fab) (width 0.127)) 23 | (fp_line (start 5.0 -6.0) (end -5.0 -6.0) (layer F.Fab) (width 0.127)) 24 | (fp_line (start -4.15 13.5) (end 4.15 13.5) (layer F.Fab) (width 0.127)) 25 | (fp_line (start -5.0 4.0) (end -4.15 4.0) (layer F.Fab) (width 0.127)) 26 | (fp_circle (center -5.75 0.0) (end -5.65 0.0) (layer F.SilkS) (width 0.2)) 27 | (fp_circle (center -5.75 0.0) (end -5.65 0.0) (layer F.Fab) (width 0.2)) 28 | (fp_line (start -4.15 4.0) (end 4.15 4.0) (layer F.Fab) (width 0.127)) 29 | (fp_line (start 4.15 4.0) (end 5.0 4.0) (layer F.Fab) (width 0.127)) 30 | (fp_line (start -4.15 4.0) (end -4.15 13.5) (layer F.Fab) (width 0.127)) 31 | (fp_line (start 4.15 13.5) (end 4.15 4.0) (layer F.Fab) (width 0.127)) 32 | (fp_line (start -5.0 4.0) (end 5.0 4.0) (layer F.SilkS) (width 0.127)) 33 | (fp_text user PCB-EDGE (at -3.0 3.75) (layer F.Fab) 34 | (effects (font (size 0.64 0.64) (thickness 0.15))) 35 | ) 36 | (pad 2 thru_hole oval (at -3.75 -3.7) (size 1.8 3.6) (drill oval 1.0 2.5) (layers *.Cu *.Mask)) 37 | (pad 1 thru_hole oval (at 0.0 0.0) (size 4.2 2.1) (drill oval 2.25 1.3) (layers *.Cu *.Mask)) 38 | (pad 3 thru_hole oval (at 3.75 -3.7) (size 1.8 3.6) (drill oval 1.0 2.5) (layers *.Cu *.Mask)) 39 | ) -------------------------------------------------------------------------------- /isa-video/libraries/hdmi_conn.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # Connector_HDMI_A_1.4 5 | # 6 | DEF Connector_HDMI_A_1.4 J 0 20 Y Y 1 F N 7 | F0 "J" -250 1050 50 H V C CNN 8 | F1 "Connector_HDMI_A_1.4" 400 1050 50 H V C CNN 9 | F2 "" 25 0 50 H I C CNN 10 | F3 "" 25 0 50 H I C CNN 11 | $FPLIST 12 | HDMI*A* 13 | $ENDFPLIST 14 | DRAW 15 | S -300 1000 400 -1000 0 1 10 f 16 | P 2 0 0 25 320 650 320 710 N 17 | P 6 0 0 25 0 650 0 710 0 680 75 680 75 710 75 650 N 18 | P 7 0 0 25 105 710 170 710 180 700 180 660 170 650 105 650 105 680 N 19 | P 7 0 1 0 100 350 150 350 200 250 200 -225 150 -325 100 -325 100 350 F 20 | P 8 0 1 25 210 650 210 710 250 710 250 650 250 710 280 710 290 700 290 650 N 21 | P 9 0 1 25 0 500 0 -500 150 -500 200 -400 300 -350 300 350 200 400 150 500 0 500 N 22 | X D2+ 1 -400 800 100 R 50 50 1 1 P 23 | X CK+ 10 -400 200 100 R 50 50 1 1 P 24 | X CKS 11 100 -1100 100 U 50 50 1 1 W 25 | X CK- 12 -400 100 100 R 50 50 1 1 P 26 | X CEC 13 -400 -100 100 R 50 50 1 1 B 27 | X UTILITY/HEAC+ 14 -400 -600 100 R 50 50 1 1 P 28 | X SCL 15 -400 -300 100 R 50 50 1 1 P 29 | X SDA 16 -400 -400 100 R 50 50 1 1 B 30 | X GND 17 200 -1100 100 U 50 50 1 1 W 31 | X +5V 18 0 1100 100 D 50 50 1 1 W 32 | X HPD/HEAC- 19 -400 -700 100 R 50 50 1 1 P 33 | X D2S 2 -200 -1100 100 U 50 50 1 1 W 34 | X D2- 3 -400 700 100 R 50 50 1 1 P 35 | X D1+ 4 -400 600 100 R 50 50 1 1 P 36 | X D1S 5 -100 -1100 100 U 50 50 1 1 W 37 | X D1- 6 -400 500 100 R 50 50 1 1 P 38 | X D0+ 7 -400 400 100 R 50 50 1 1 P 39 | X D0S 8 0 -1100 100 U 50 50 1 1 W 40 | X D0- 9 -400 300 100 R 50 50 1 1 P 41 | X SH SH 300 -1100 100 U 50 50 1 1 P 42 | ENDDRAW 43 | ENDDEF 44 | # 45 | #End Library 46 | -------------------------------------------------------------------------------- /isa-video/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (version 7) 3 | (lib (name "isavideo-rescue")(type "KiCad")(uri "${KIPRJMOD}/isavideo-rescue.kicad_sym")(options "")(descr "")) 4 | (lib (name "BLM18RK601SN1D")(type "Legacy")(uri "${KIPRJMOD}/libraries/BLM18RK601SN1D.lib")(options "")(descr "")) 5 | (lib (name "PJRAN1X1U04X")(type "Legacy")(uri "${KIPRJMOD}/libraries/PJRAN1X1U04X.lib")(options "")(descr "")) 6 | ) 7 | -------------------------------------------------------------------------------- /verilog/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | *.d -------------------------------------------------------------------------------- /verilog/Makefile: -------------------------------------------------------------------------------- 1 | # Graphics Gremlin 2 | # 3 | # Copyright (c) 2021 Eric Schlaepfer 4 | # This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | # International License. To view a copy of this license, visit 6 | # http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | # Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | # 9 | 10 | PROJ = isavideo 11 | IMAGES = mda70_top cga70_top cga_top cga_overscan_top 12 | SOURCES = mda70_top.v mda_top.v mda.v crtc6845.v mda_vgaport.v mda_vram.v mda_attrib.v mda_sequencer.v mda_pixel.v mda_hdmiport.v cga_top.v cga.v cga_vgaport.v cga_sequencer.v cga_pixel.v cga_attrib.v cga_vram.v cga_composite.v cga_scandoubler.v cga_hdmiport.v cga70_top.v cga_overscan_top.v 13 | PIN_DEF = gremlin.pcf 14 | DEVICE = hx8k 15 | ODIR = build 16 | DEPS = $(addprefix $(ODIR)/,$(addsuffix .d,$(IMAGES))) 17 | DEFINES ?= 18 | 19 | # Want to build report and main bin file 20 | all: $(addprefix $(ODIR)/,$(addsuffix .rpt,$(IMAGES))) $(ODIR)/$(PROJ).binm 21 | 22 | # removed %.v 23 | $(ODIR)/%.json: $(SOURCES) 24 | yosys -p 'synth_ice40 -top $(basename $(notdir $@)) -json $@' $(SOURCES) -E $(basename $(notdir $@)).d $(DEFINES) 25 | # yosys -p 'synth_ice40 -top mda_top -json $@' $(SOURCES) -E $(DEPS) 26 | # @echo yosys -p 'synth_ice40 -top isavideo -json $@' $^ -E $(DEPS) 27 | echo $@ 28 | 29 | $(ODIR)/%.asc: $(ODIR)/%.json $(PIN_DEF) 30 | # add -q to quiet lots of messages 31 | nextpnr-ice40 -q --$(DEVICE) --pcf $(PIN_DEF) --json $< --asc $@ --package tq144:4k 32 | # @echo nextpnr $< $@ 33 | 34 | $(ODIR)/%.bin: $(ODIR)/%.asc 35 | icepack $< $@ 36 | # @echo icepack $< $@ 37 | 38 | # Combined multiboot image 39 | $(ODIR)/%.binm: $(addprefix $(ODIR)/,$(addsuffix .bin, $(IMAGES))) 40 | icemulti -c -o $@ $^ 41 | 42 | $(ODIR)/%.rpt: $(ODIR)/%.asc 43 | icetime -d $(DEVICE) -mtr $@ $< 44 | # @echo icetime -d $(DEVICE) -mtr $@ $< 45 | 46 | sim: $(ODIR)/$(PROJ)_t.vcd 47 | 48 | $(ODIR)/$(PROJ)_t.vcd: $(PROJ)_t.v $(SOURCES) is61c5128_t.v 49 | 50 | prog: $(ODIR)/$(PROJ).binm 51 | # iCEburn -e -v -w $< 52 | iceprog -p $< 53 | 54 | sudo-prog: $(ODIR)/$(PROJ).bin 55 | @echo 'Executing prog as root!!!' 56 | iCEburn -e -v -w $< 57 | 58 | clean: 59 | rm -f $(ODIR)/$(PROJ).blif $(ODIR)/$(PROJ).asc $(ODIR)/$(PROJ).bin $(ODIR)/$(PROJ).json $(ODIR)/$(PROJ).d $(ODIR)/*.bin $(ODIR)/*.binm $(ODIR)/*.rpt 60 | 61 | reset: 62 | iceprog -t 63 | 64 | %.vcd: 65 | iverilog $^ -o $(@:.vcd=.out) 66 | vvp $(@:.vcd=.out) 67 | 68 | # Don't delete individual images 69 | PRECIOUS: $(addsuffix .bin, $(addprefix $(ODIR)/,$(IMAGES))) 70 | 71 | .PHONY: all prog clean reset 72 | 73 | # Depsfile 74 | -include $(DEPS) 75 | -------------------------------------------------------------------------------- /verilog/README.md: -------------------------------------------------------------------------------- 1 | # The Graphics Gremlin - FPGA code 2 | 3 | (Click here for the [main README](https://github.com/schlae/graphics-gremlin/blob/main/README.md)) 4 | 5 | The FPGA code is divided into two major sets of files, those for CGA graphics and those for MDA graphics. At some point I'll tidy up and make a nice organized directory tree, but for now they're all in the same place. 6 | 7 | * mda\_top.v: The top level file instantiating the MDA graphics logic (Not used as no more RGBI port) 8 | * mda70\_top.v: An alternative top level file for VGA compatible MDA graphics 9 | * mda.v: Implements MDA ISA interface, IO registers and instantiates the CRTC, SRAM interface, sequencer, and pixel engine 10 | * crtc6845.v: This is my mostly-accurate recreation of the old Motorola 6845 CRT controller chip. It generates all the sync timings as well as the character and row addresses. There are probably slight differences between it and the real thing. 11 | * mda\_sequencer.v: Controls timing across the entire card, deciding when to fetch SRAM data, look up character bits from the character ROM, and allow ISA bus access to the SRAM 12 | * mda\_vram.v: Implements the state machine to arbitrate ISA bus and pixel engine access to the video ram (external SRAM) 13 | * mda\_pixel.v: This is the pixel engine. It takes data coming from the SRAM, looks up the pixels in the character ROM, and shifts the data out one pixel at a time. 14 | * mda\_attrib.v: The attribute generator applies video attributes to the raw pixel data, including brightness, underline, inverse video, blinking. It also applies the blinking cursor. 15 | * mda\_vgaport.v: This module turns the digital MDA video signals into numbers to drive the resistor ladder DAC connected to the VGA port. If you (gasp) dislike amber monochrome monitors, then you can hack this code to make it green or white. 16 | * mda\_hdmiport.v: This module turns the digital MDA video signals to drive the DVI transmitter. Will also adjust the colour based on switch selection. 17 | 18 | CGA graphics logic is similar to MDA and shares the same crtc6845.v logic, but the cards are different enough that I couldn't share more. 19 | * cga\_top.v: Instantiates top level CGA logic with 60 Hz refresh rate. 20 | * cga70\_top.v: Instantiates top level CGA logic with 70Hz refresh rate if higher pixel clock is required. (Composite displays are unlikely to work in this mode) 21 | * cga\_overscan\_top.v: Instantiates top level CGA logic with 60Hz refresh rate and show overscan area. (Not all HDMI monitors can accept this) 22 | * cga.v: Implements the ISA bus interface, CGA control registers, wait state generator, and most of the other CGA modules 23 | * cga\_sequencer.v: Generates most of the timing signals used on the card, including memory fetches and pixel engine timing. 24 | * cga\_vram.v: Implements a very basic address MUX for the SRAM interface. This actually causes too much CGA snow, and should be improved using the MDA VRAM interface as a model. 25 | * cga\_pixel.v: The CGA pixel engine takes data from the SRAM, does a character lookup (text mode only), and shifts the data out 1 or 2 bits at a time, depending on the video mode. 26 | * cga\_attrib.v: The attribute generator applies video attributes to the raw pixels data, including color, brightness, and blinking. 27 | * cga\_composite.v: Contains the flip flops used to generate NTSC composite color as well as new sync pulses. The output is a 7-bit signal passed off to the green DAC channel for the RCA jack on the card. 28 | * cga\_scandoubler.v: A very basic scan doubler to convert 15.7KHz CGA video to 31.4KHz VGA video. To save memory, this is done using 4-bit digital RGBI signals. 29 | * cga\_vgaport.v: This module takes RGBI digital video from the scan doubler and turns it into numbers that drive the resistor ladder DAC connected to the VGA port. It produces CGA brown instead of dark yellow. 30 | * cga\_hdmiport.v: This module takes RGBI digital video from the scan doubler to drive the DVI transmitter. It will produce Brown at CGA color #6 by controlling the dedicated Green intensity control pin. 31 | 32 | Other miscellaneous files include: 33 | * cga.hex and mda.hex: character ROM 34 | * gremlin.pcf: The pin constraints file that determines what signals are tied to what pins on the FPGA 35 | * isavideo\_t.v: A sloppy test bench that I used to validate and troubleshoot the rest of the logic. 36 | * is61c5128\_t.v: A behavorial Verilog model of the SRAM chip. 37 | * is61\_tester.v: A test bench I used to verify the SRAM chip behavioral model. 38 | 39 | ## Building 40 | 41 | To build the project, you will need to install the tools from [Project IceStorm](http://www.clifford.at/icestorm/) (full instructions are available at that link). The Graphics Gremlin uses NextPNR, so make sure you install that. 42 | 43 | Alternatively, you can install the [OSS Cad Suite](https://github.com/YosysHQ/oss-cad-suite-build) which is prebuilt and runs on a variety of platforms. 44 | 45 | Once the tools are installed, just navigate to the Graphics Gremlin Verilog directory and run 46 | ``` 47 | mkdir build 48 | make 49 | ``` 50 | If you have the FTDI programming cable hooked up to the card, you can also type `make prog`. As a convenience, `make reset` will not program the FPGA but will toggle its reset line which is useful if you change the red switch bank and don't want to cycle power on the host PC. 51 | 52 | If the `make prog` command can't find the FTDI programming cable, make sure you have the udev rules set up. 53 | 54 | 55 | -------------------------------------------------------------------------------- /verilog/cga70_top.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga70_top( 11 | // Clocks 12 | input clk_10m, 13 | input clk_14m318, 14 | input clk_bus, 15 | 16 | // Bus reset 17 | input busreset, 18 | 19 | // ISA bus 20 | input[19:0] bus_a, 21 | input bus_ior_l, 22 | input bus_iow_l, 23 | input bus_memr_l, 24 | input bus_memw_l, 25 | inout[7:0] bus_d, 26 | output bus_dir, 27 | output bus_rdy, 28 | output bus_0ws_l, 29 | input bus_aen, 30 | input bus_ale, 31 | 32 | // RAM 33 | output ram_we_l, 34 | output[18:0] ram_a, 35 | inout[7:0] ram_d, 36 | 37 | output hdmi_red, 38 | output hdmi_grn, 39 | output hdmi_blu, 40 | output hdmi_int, 41 | output hdmi_grn_int, 42 | 43 | output hdmi_vs, 44 | output hdmi_hs, 45 | 46 | output hdmi_clk, 47 | 48 | output hdmi_de, 49 | 50 | 51 | // Video outputs 52 | // output hsync, 53 | // output vsync, 54 | // output vid_en_l, 55 | // output d_r, 56 | // output d_g, 57 | // output d_b, 58 | // output d_r2, 59 | // output d_g2, 60 | // output d_b2, 61 | output vga_hsync, 62 | output vga_vsync, 63 | output[5:0] red, 64 | output[6:0] green, 65 | output[5:0] blue, 66 | 67 | // Config switches 68 | input switch2, 69 | input switch3 70 | ); 71 | 72 | wire hsync; 73 | wire vsync; 74 | wire d_r; 75 | wire d_g; 76 | wire d_b; 77 | wire d_r2; 78 | wire d_g2; 79 | wire d_b2; 80 | 81 | // Sets up the card to generate a video signal 82 | // that will work with a standard VGA monitor 83 | // connected to the VGA port. 84 | parameter MDA_70HZ = 0; 85 | 86 | wire clk_main; 87 | wire pll_lock; 88 | 89 | wire[7:0] bus_out; 90 | 91 | wire[3:0] video; 92 | wire[3:0] vga_video; 93 | 94 | wire composite_on; 95 | wire thin_font; 96 | wire display_enable; 97 | wire dbl_display_enable; 98 | 99 | wire[5:0] vga_red; 100 | wire[6:0] vga_green; 101 | wire[5:0] vga_blue; 102 | wire[6:0] comp_video; 103 | 104 | // Unused pins on video connector 105 | assign bus_0ws_l = 1'b1; 106 | //assign vid_en_l = 1'b0; 107 | 108 | // Composite mode switch 109 | assign composite_on = switch3; 110 | 111 | // Thin font switch 112 | assign thin_font = switch2; 113 | 114 | // Set up bus direction 115 | assign bus_d = (bus_dir) ? bus_out : 8'hzz; 116 | 117 | // CGA mode 118 | // Take our incoming 14.318MHz clock and generate the pixel clock 119 | // Expected 33.408 Mhz but closest is 33.578 Mhz: 0, 33, 4 120 | // Could also use an SB_PLL40_2_PAD to generate an additional 121 | // 14.318MHz clock without having to use a separate divider. 122 | wire int_clk; 123 | `ifdef SYNTHESIS 124 | SB_PLL40_PAD #( 125 | .FEEDBACK_PATH("SIMPLE"), 126 | .DIVR(0), 127 | .DIVF(37), 128 | .DIVQ(4), 129 | .FILTER_RANGE(1) 130 | ) cga_pll ( 131 | .LOCK(pll_lock), 132 | .RESETB(1'b1), 133 | .BYPASS(1'b0), 134 | .PACKAGEPIN(clk_14m318), 135 | .PLLOUTGLOBAL(clk_main) 136 | ); 137 | `else 138 | assign clk_main = clk_14m318; 139 | `endif 140 | 141 | // CGA digital to analog converter 142 | cga_vgaport vga ( 143 | .clk(clk_main), 144 | .video(vga_video), 145 | .red(vga_red), 146 | .green(vga_green), 147 | .blue(vga_blue) 148 | ); 149 | 150 | cga_hdmiport hdmi( 151 | .clk(clk_main), 152 | .video(vga_video), 153 | .display_enable(dbl_display_enable), 154 | .hsync(vga_hsync), 155 | .vsync(vsync), 156 | .hdmi_red(hdmi_red), 157 | .hdmi_grn(hdmi_grn), 158 | .hdmi_blu(hdmi_blu), 159 | .hdmi_grn_int(hdmi_grn_int), 160 | .hdmi_int(hdmi_int), 161 | .hdmi_hs(hdmi_hs), 162 | .hdmi_vs(hdmi_vs), 163 | .hdmi_clk(hdmi_clk), 164 | .hdmi_de(hdmi_de), 165 | ); 166 | 167 | // Analog output mux: Either RGB or composite 168 | assign red = composite_on ? 6'd0 : vga_red; 169 | assign green = composite_on ? comp_video : vga_green; 170 | assign blue = composite_on ? 6'd0 : vga_blue; 171 | 172 | assign vga_vsync = vsync; 173 | 174 | cga cga1 ( 175 | .clk(clk_main), 176 | .bus_a(bus_a), 177 | .bus_ior_l(bus_ior_l), 178 | .bus_iow_l(bus_iow_l), 179 | .bus_memr_l(bus_memr_l), 180 | .bus_memw_l(bus_memw_l), 181 | .bus_d(bus_d), 182 | .bus_out(bus_out), 183 | .bus_dir(bus_dir), 184 | .bus_aen(bus_aen), 185 | .bus_rdy(bus_rdy), 186 | .ram_we_l(ram_we_l), 187 | .ram_a(ram_a), 188 | .ram_d(ram_d), 189 | .hsync(hsync), 190 | .dbl_hsync(vga_hsync), 191 | .vsync(vsync), 192 | .video(video), 193 | .dbl_video(vga_video), 194 | .comp_video(comp_video), 195 | .thin_font(thin_font), 196 | .display_enable(display_enable), 197 | .dbl_display_enable(dbl_display_enable) 198 | ); 199 | 200 | defparam cga1.OVERSCAN = 0; 201 | 202 | `ifdef SYNTHESIS 203 | defparam cga1.BLINK_MAX = 24'd4772727; 204 | `else 205 | defparam cga1.BLINK_MAX = 24'd10; 206 | `endif 207 | 208 | endmodule 209 | -------------------------------------------------------------------------------- /verilog/cga_attrib.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_attrib( 11 | input clk, 12 | input[7:0] att_byte, 13 | input[4:0] row_addr, 14 | input[7:0] cga_color_reg, 15 | input grph_mode, 16 | input bw_mode, 17 | input mode_640, 18 | input tandy_16_mode, 19 | input display_enable, 20 | input blink_enabled, 21 | input blink, 22 | input cursor, 23 | input hsync, 24 | input vsync, 25 | input pix_in, 26 | input c0, 27 | input c1, 28 | input pix_640, 29 | input [3:0] pix_tandy, 30 | output reg[3:0] pix_out 31 | ); 32 | 33 | reg blinkdiv; 34 | reg[1:0] blink_old; 35 | wire att_blink; 36 | wire[3:0] att_fg; 37 | wire[3:0] att_bg; 38 | wire cursorblink; 39 | wire blink_area; 40 | wire alpha_dots; 41 | wire mux_a; 42 | wire mux_b; 43 | wire shutter; 44 | wire selblue; 45 | wire[3:0] rgbi; 46 | wire[3:0] active_area; 47 | 48 | // Extract attributes from the attribute byte 49 | assign att_fg = att_byte[3:0]; 50 | assign att_bg = blink_enabled ? {1'b0, att_byte[6:4]} : att_byte[7:4]; 51 | assign att_blink = att_byte[7]; 52 | 53 | // Character blink is half the rate of the cursor blink 54 | always @ (posedge clk) 55 | begin 56 | blink_old <= {blink_old[0], blink}; 57 | if (blink_old == 2'b01) begin 58 | blinkdiv <= ~blinkdiv; 59 | end 60 | end 61 | 62 | // Assemble all the signals to create the final video signal 63 | assign cursorblink = cursor & blink; 64 | assign blink_area = ~(blink_enabled & att_blink & ~cursor) | ~blinkdiv; 65 | assign alpha_dots = (pix_in & blink_area) | cursorblink; 66 | 67 | // Determine mux A and mux B inputs for selecting output colors. 68 | assign mux_a = ~display_enable | 69 | (grph_mode ? 70 | (tandy_16_mode ? 0 : (~(~mode_640 & (c0 | c1)))) : 71 | ~alpha_dots); 72 | assign mux_b = grph_mode | ~display_enable; 73 | 74 | // Shutter closes when video is blanked during sync 75 | assign shutter = (hsync | vsync) | (mode_640 ? ~(display_enable & pix_640) : 0); 76 | 77 | // Blue palette selection bit 78 | assign selblue = bw_mode ? c0 : cga_color_reg[5]; 79 | 80 | assign active_area = tandy_16_mode ? pix_tandy : {cga_color_reg[4], c1, c0, selblue}; 81 | 82 | always @ (*) 83 | begin 84 | if (shutter) begin 85 | pix_out <= 4'b0; 86 | end else begin 87 | case ({mux_b, mux_a}) 88 | 2'b00: pix_out <= att_fg; // Text foreground 89 | 2'b01: pix_out <= att_bg; // Text background 90 | 2'b10: pix_out <= active_area; // Graphics 91 | 2'b11: pix_out <= cga_color_reg[3:0]; // Overscan color 92 | endcase 93 | end 94 | end 95 | 96 | endmodule 97 | 98 | -------------------------------------------------------------------------------- /verilog/cga_composite.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_composite( 11 | // Clock 12 | input clk, 13 | 14 | input lclk, 15 | input hclk, 16 | 17 | input[3:0] video, // IRGB video in 18 | input hsync, 19 | input vsync_l, 20 | input bw_mode, 21 | 22 | output hsync_out, 23 | output vsync_out, 24 | output [6:0] comp_video 25 | ); 26 | 27 | reg[3:0] vid_del; 28 | reg hsync_dly = 1'b0; 29 | reg vsync_dly_l = 1'b0; 30 | reg[3:0] hsync_counter = 4'd0; 31 | reg[3:0] vsync_counter = 4'd0; 32 | reg vsync_trig = 1'b0; 33 | 34 | reg[2:0] count_358 = 3'd0; 35 | wire clk_3m58; 36 | wire clk_14m3; 37 | reg clk_old = 1'b0; 38 | 39 | wire burst; 40 | wire csync; 41 | 42 | reg[6:0] grey_level; 43 | 44 | // Color shifter 45 | reg yellow_burst; 46 | reg red; 47 | reg magenta; 48 | wire blue; 49 | wire cyan; 50 | wire green; 51 | 52 | reg color_out; 53 | wire color_out2; 54 | 55 | reg hclk_old; 56 | 57 | always @ (posedge clk) 58 | begin 59 | hclk_old <= hclk; 60 | end 61 | 62 | // Resync the video to the falling edge of 14.318MHz 63 | always @ (posedge clk) 64 | begin 65 | if (clk_14m3 && !clk_old) begin 66 | vid_del <= video; 67 | end 68 | end 69 | 70 | // Delay the sync pulses 71 | always @ (posedge clk) 72 | begin 73 | if (hclk && !hclk_old) begin 74 | hsync_dly <= hsync; 75 | vsync_dly_l <= vsync_l; 76 | end 77 | end 78 | 79 | // hsync counter 80 | always @ (posedge clk) 81 | begin 82 | if (lclk) begin 83 | if (hsync_dly) begin 84 | if (hsync_counter == 4'd11) begin 85 | hsync_counter <= 4'd0; 86 | end else begin 87 | hsync_counter <= hsync_counter + 4'd1; 88 | if ((hsync_counter + 4'd1) == 4'd2) begin 89 | vsync_trig <= 1'b1; 90 | end 91 | end 92 | end else begin 93 | hsync_counter <= 4'd0; 94 | end 95 | end else begin 96 | vsync_trig <= 1'b0; 97 | end 98 | end 99 | 100 | assign hsync_out = (hsync_counter > 4'd1) && (hsync_counter < 4'd6); 101 | assign burst = bw_mode ? 1'b0 : (~vsync_dly_l & 102 | ((hsync_counter == 4'd7) || 103 | (hsync_counter == 4'd8))); 104 | 105 | // vsync counter 106 | always @ (posedge clk) 107 | begin 108 | if (vsync_trig) begin 109 | if (!vsync_dly_l) begin 110 | vsync_counter <= 4'd0; 111 | end else begin 112 | vsync_counter <= {vsync_counter[2:0], 1'b1}; 113 | end 114 | end 115 | end 116 | 117 | // Positive going vsync pulse 118 | assign vsync_out = vsync_counter[0] & ~vsync_counter[3]; 119 | 120 | assign csync = ~(vsync_out ^ hsync_out); 121 | 122 | // Generate 3.58MHz from the 28MHz clock coming in 123 | always @ (posedge clk) 124 | begin 125 | count_358 <= count_358 + 3'd1; 126 | clk_old <= clk_14m3; 127 | end 128 | assign clk_3m58 = count_358[2]; 129 | wire clk_7m; 130 | assign clk_7m = count_358[1]; 131 | assign clk_14m3 = count_358[0]; 132 | 133 | // Create color phase clocks 134 | always @ (posedge clk) 135 | begin 136 | // Check for 14.318MHz rising edge 137 | if (!clk_14m3 && clk_old) begin 138 | yellow_burst <= clk_3m58; 139 | red <= yellow_burst; 140 | end 141 | // Check for 14.318MHz falling edge 142 | if (clk_14m3 && !clk_old) begin 143 | magenta <= red; 144 | end 145 | end 146 | assign blue = ~yellow_burst; 147 | assign cyan = ~red; 148 | assign green = ~magenta; 149 | 150 | // Color mux 151 | always @ (*) 152 | begin 153 | // R, G, B 154 | case ({vid_del[2] ^ burst, vid_del[1] ^ burst, vid_del[0]}) 155 | 3'd0: color_out <= 1'b0; 156 | 3'd1: color_out <= blue; 157 | 3'd2: color_out <= green; 158 | 3'd3: color_out <= cyan; 159 | 3'd4: color_out <= red; 160 | 3'd5: color_out <= magenta; 161 | 3'd6: color_out <= yellow_burst; 162 | 3'd7: color_out <= 1'b1; 163 | endcase 164 | end 165 | 166 | // Black and white mode? Color is disabled. 167 | assign color_out2 = bw_mode ? 168 | (vid_del[2:0] != 0) : 169 | (color_out); 170 | 171 | always @ (*) 172 | begin 173 | case (vid_del[2:0]) 174 | 3'd0: grey_level <= 7'd29; 175 | 3'd1: grey_level <= 7'd36; 176 | 3'd2: grey_level <= 7'd49; 177 | 3'd3: grey_level <= 7'd56; 178 | 3'd4: grey_level <= 7'd39; 179 | 3'd5: grey_level <= 7'd46; 180 | 3'd6: grey_level <= 7'd60; 181 | 3'd7: grey_level <= 7'd68; 182 | endcase 183 | end 184 | 185 | assign comp_video = ~csync ? 0 : (grey_level + (vid_del[3] ? 7'd31 : 7'd0) + 186 | (color_out2 ? 7'd28 : 7'd0)); 187 | 188 | endmodule 189 | -------------------------------------------------------------------------------- /verilog/cga_hdmiport.v: -------------------------------------------------------------------------------- 1 | module cga_hdmiport( 2 | input clk, 3 | input[3:0] video, 4 | input display_enable, 5 | 6 | input hsync, 7 | input vsync, 8 | 9 | output hdmi_red, 10 | output hdmi_grn, 11 | output hdmi_blu, 12 | output hdmi_int, 13 | output hdmi_grn_int, 14 | 15 | output hdmi_vs, 16 | output hdmi_hs, 17 | 18 | output hdmi_clk, 19 | 20 | output hdmi_de, 21 | 22 | ); 23 | 24 | reg[0:0] prev_de; 25 | reg[0:0] prev_de2; 26 | reg[0:0] current_hs; 27 | reg[0:0] current_vs; 28 | reg[0:0] current_red; 29 | reg[0:0] current_blue; 30 | reg[0:0] current_grn; 31 | reg[0:0] current_grn_int; 32 | reg[0:0] current_de; 33 | 34 | always @(posedge clk) 35 | begin 36 | // Offset bug in image being shifted 2 pixels to the right. 37 | current_de <= prev_de; 38 | prev_de <= prev_de2; 39 | prev_de2 <= display_enable; 40 | 41 | current_vs <= vsync; 42 | current_hs <= hsync; 43 | 44 | current_red <= video[2]; 45 | current_blu <= video[0]; 46 | current_int <= video[3]; 47 | 48 | // To generate brown value 49 | current_grn <= video[1] ^ (video[2] & video[1] & (video[0] ^ 1) & (video[3] ^ 1)); 50 | current_grn_int <= video[3]^ (video[2] & video[1] & (video[0] ^ 1) & (video[3]^ 1)); 51 | end 52 | 53 | 54 | assign hdmi_clk = clk; 55 | 56 | assign hdmi_de = current_de; 57 | 58 | assign hdmi_vs = current_vs; 59 | assign hdmi_hs = current_hs; 60 | 61 | assign hdmi_red = current_red; 62 | assign hdmi_blu = current_blu; 63 | assign hdmi_int = current_int; 64 | 65 | assign hdmi_grn = current_grn; 66 | assign hdmi_grn_int = current_grn_int; 67 | 68 | endmodule -------------------------------------------------------------------------------- /verilog/cga_overscan_top.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_overscan_top( 11 | // Clocks 12 | input clk_10m, 13 | input clk_14m318, 14 | input clk_bus, 15 | 16 | // Bus reset 17 | input busreset, 18 | 19 | // ISA bus 20 | input[19:0] bus_a, 21 | input bus_ior_l, 22 | input bus_iow_l, 23 | input bus_memr_l, 24 | input bus_memw_l, 25 | inout[7:0] bus_d, 26 | output bus_dir, 27 | output bus_rdy, 28 | output bus_0ws_l, 29 | input bus_aen, 30 | input bus_ale, 31 | 32 | // RAM 33 | output ram_we_l, 34 | output[18:0] ram_a, 35 | inout[7:0] ram_d, 36 | 37 | output hdmi_red, 38 | output hdmi_grn, 39 | output hdmi_blu, 40 | output hdmi_int, 41 | output hdmi_grn_int, 42 | 43 | output hdmi_vs, 44 | output hdmi_hs, 45 | 46 | output hdmi_clk, 47 | 48 | output hdmi_de, 49 | 50 | 51 | // Video outputs 52 | // output hsync, 53 | // output vsync, 54 | // output vid_en_l, 55 | // output d_r, 56 | // output d_g, 57 | // output d_b, 58 | // output d_r2, 59 | // output d_g2, 60 | // output d_b2, 61 | output vga_hsync, 62 | output vga_vsync, 63 | output[5:0] red, 64 | output[6:0] green, 65 | output[5:0] blue, 66 | 67 | // Config switches 68 | input switch2, 69 | input switch3 70 | ); 71 | 72 | wire hsync; 73 | wire vsync; 74 | wire d_r; 75 | wire d_g; 76 | wire d_b; 77 | wire d_r2; 78 | wire d_g2; 79 | wire d_b2; 80 | 81 | // Sets up the card to generate a video signal 82 | // that will work with a standard VGA monitor 83 | // connected to the VGA port. 84 | parameter MDA_70HZ = 0; 85 | 86 | wire clk_main; 87 | wire pll_lock; 88 | 89 | wire[7:0] bus_out; 90 | 91 | wire[3:0] video; 92 | wire[3:0] vga_video; 93 | 94 | wire composite_on; 95 | wire thin_font; 96 | wire display_enable; 97 | wire dbl_display_enable; 98 | 99 | wire[5:0] vga_red; 100 | wire[6:0] vga_green; 101 | wire[5:0] vga_blue; 102 | wire[6:0] comp_video; 103 | 104 | // Unused pins on video connector 105 | assign bus_0ws_l = 1'b1; 106 | //assign vid_en_l = 1'b0; 107 | 108 | // Composite mode switch 109 | assign composite_on = switch3; 110 | 111 | // Thin font switch 112 | assign thin_font = switch2; 113 | 114 | // Set up bus direction 115 | assign bus_d = (bus_dir) ? bus_out : 8'hzz; 116 | 117 | // CGA mode 118 | // Take our incoming 14.318MHz clock and generate the pixel clock 119 | // 28.636MHz: 0, 63, 5 120 | // Could also use an SB_PLL40_2_PAD to generate an additional 121 | // 14.318MHz clock without having to use a separate divider. 122 | wire int_clk; 123 | `ifdef SYNTHESIS 124 | SB_PLL40_PAD #( 125 | .FEEDBACK_PATH("SIMPLE"), 126 | .DIVR(0), 127 | .DIVF(63), 128 | .DIVQ(5), 129 | .FILTER_RANGE(1) 130 | ) cga_pll ( 131 | .LOCK(pll_lock), 132 | .RESETB(1'b1), 133 | .BYPASS(1'b0), 134 | .PACKAGEPIN(clk_14m318), 135 | .PLLOUTGLOBAL(clk_main) 136 | ); 137 | `else 138 | assign clk_main = clk_14m318; 139 | `endif 140 | 141 | // CGA digital to analog converter 142 | cga_vgaport vga ( 143 | .clk(clk_main), 144 | .video(vga_video), 145 | .red(vga_red), 146 | .green(vga_green), 147 | .blue(vga_blue) 148 | ); 149 | 150 | cga_hdmiport hdmi( 151 | .clk(clk_main), 152 | .video(vga_video), 153 | .display_enable(dbl_display_enable), 154 | .hsync(vga_hsync), 155 | .vsync(vsync), 156 | .hdmi_red(hdmi_red), 157 | .hdmi_grn(hdmi_grn), 158 | .hdmi_blu(hdmi_blu), 159 | .hdmi_grn_int(hdmi_grn_int), 160 | .hdmi_int(hdmi_int), 161 | .hdmi_hs(hdmi_hs), 162 | .hdmi_vs(hdmi_vs), 163 | .hdmi_clk(hdmi_clk), 164 | .hdmi_de(hdmi_de), 165 | ); 166 | 167 | // Analog output mux: Either RGB or composite 168 | assign red = composite_on ? 6'd0 : vga_red; 169 | assign green = composite_on ? comp_video : vga_green; 170 | assign blue = composite_on ? 6'd0 : vga_blue; 171 | 172 | assign vga_vsync = vsync; 173 | 174 | cga cga1 ( 175 | .clk(clk_main), 176 | .bus_a(bus_a), 177 | .bus_ior_l(bus_ior_l), 178 | .bus_iow_l(bus_iow_l), 179 | .bus_memr_l(bus_memr_l), 180 | .bus_memw_l(bus_memw_l), 181 | .bus_d(bus_d), 182 | .bus_out(bus_out), 183 | .bus_dir(bus_dir), 184 | .bus_aen(bus_aen), 185 | .bus_rdy(bus_rdy), 186 | .ram_we_l(ram_we_l), 187 | .ram_a(ram_a), 188 | .ram_d(ram_d), 189 | .hsync(hsync), 190 | .dbl_hsync(vga_hsync), 191 | .vsync(vsync), 192 | .video(video), 193 | .dbl_video(vga_video), 194 | .comp_video(comp_video), 195 | .thin_font(thin_font), 196 | .display_enable(display_enable), 197 | .dbl_display_enable(dbl_display_enable) 198 | ); 199 | 200 | defparam cga1.OVERSCAN = 1; 201 | 202 | `ifdef SYNTHESIS 203 | defparam cga1.BLINK_MAX = 24'd4772727; 204 | `else 205 | defparam cga1.BLINK_MAX = 24'd10; 206 | `endif 207 | 208 | endmodule 209 | -------------------------------------------------------------------------------- /verilog/cga_pixel.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_pixel( 11 | input clk, 12 | input[4:0] clk_seq, 13 | input hres_mode, 14 | input grph_mode, 15 | input bw_mode, 16 | input mode_640, 17 | input tandy_16_mode, 18 | input thin_font, 19 | input[7:0] vram_data, 20 | input vram_read_char, 21 | input vram_read_att, 22 | input disp_pipeline, 23 | input charrom_read, 24 | input display_enable, 25 | input cursor, 26 | input[4:0] row_addr, 27 | input blink_enabled, 28 | input blink, 29 | input hsync, 30 | input vsync, 31 | input video_enabled, 32 | input[7:0] cga_color_reg, 33 | output[3:0] video 34 | ); 35 | 36 | reg[7:0] attr_byte; 37 | reg[7:0] char_byte; 38 | reg[7:0] char_byte_old; 39 | reg[7:0] attr_byte_del; 40 | reg[7:0] charbits; 41 | reg[1:0] cursor_del; 42 | reg[1:0] display_enable_del; 43 | reg pix; 44 | reg pix_delay; 45 | reg[1:0] pix_bits; 46 | reg[1:0] pix_bits_old; 47 | reg[3:0] tandy_bits; 48 | wire pix_640; 49 | wire[10:0] rom_addr; 50 | wire load_shifter; 51 | wire[2:0] charpix_sel; 52 | 53 | // Character ROM 54 | reg[7:0] char_rom[0:4095]; 55 | initial $readmemh("cga.hex", char_rom, 0, 4095); 56 | 57 | // Latch character and attribute data from VRAM 58 | // at appropriate times 59 | always @ (posedge clk) 60 | begin 61 | if (vram_read_char) begin 62 | char_byte <= vram_data; 63 | char_byte_old <= char_byte; 64 | end 65 | if (vram_read_att) begin 66 | attr_byte <= vram_data; 67 | end 68 | end 69 | 70 | // Fetch pixel data for graphics modes 71 | wire [2:0]muxin; 72 | assign muxin = hres_mode ? (clk_seq[3:1] + 3'd6) : (clk_seq[4:2] + 3'd7); 73 | always @ (*) 74 | begin 75 | if (video_enabled) begin 76 | // Hi-res vs low-res needs different adjustments 77 | // Normal CGA is low res only in graphics mode 78 | // Tandy uses "high res" mode for both 320x200x16 79 | // and 640x200x4 color modes 80 | case (muxin) 81 | 3'd0: pix_bits <= char_byte[7:6]; 82 | 3'd1: pix_bits <= char_byte[5:4]; 83 | 3'd2: pix_bits <= char_byte[3:2]; 84 | 3'd3: pix_bits <= char_byte[1:0]; 85 | 3'd4: pix_bits <= attr_byte[7:6]; 86 | 3'd5: pix_bits <= attr_byte[5:4]; 87 | 3'd6: pix_bits <= attr_byte[3:2]; 88 | 3'd7: pix_bits <= attr_byte[1:0]; 89 | default: pix_bits <= 2'b0; 90 | endcase 91 | end else begin 92 | pix_bits <= 2'b0; 93 | end 94 | end 95 | 96 | // Add a pipeline delay to the attribute byte data, cursor, and display 97 | // enable so they line up with the displayed character 98 | always @ (posedge clk) 99 | begin 100 | if (disp_pipeline) begin 101 | attr_byte_del <= video_enabled ? attr_byte : 8'd0; 102 | display_enable_del <= {display_enable_del[0], display_enable}; 103 | cursor_del <= {cursor_del[0], cursor}; 104 | end 105 | end 106 | 107 | // Look up character byte in our character ROM table 108 | assign rom_addr = {char_byte, row_addr[2:0]}; 109 | always @ (posedge clk) 110 | begin 111 | // Only load character bits at this point 112 | if (charrom_read) begin 113 | charbits <= char_rom[{~thin_font, rom_addr}]; 114 | end 115 | end 116 | 117 | // This must be a mux. Using a shift register causes very weird 118 | // issues with the character ROM and Yosys turns it into a bunch 119 | // of flip-flops instead of a ROM. 120 | assign charpix_sel = hres_mode ? (clk_seq[3:1] + 3'd6) : (clk_seq[4:2] + 3'd7); 121 | always @ (*) 122 | begin 123 | if (video_enabled) begin 124 | // Hi-res vs low-res needs different adjustments 125 | case (charpix_sel) 126 | 5'd0: pix <= charbits[7]; 127 | 5'd1: pix <= charbits[6]; 128 | 5'd2: pix <= charbits[5]; 129 | 5'd3: pix <= charbits[4]; 130 | 5'd4: pix <= charbits[3]; 131 | 5'd5: pix <= charbits[2]; 132 | 5'd6: pix <= charbits[1]; 133 | 5'd7: pix <= charbits[0]; 134 | default: pix <= 0; 135 | endcase 136 | end else begin 137 | pix <= 0; 138 | end 139 | end 140 | 141 | // In 640x200 mode, alternate between the two bits from 142 | // the shift register outputs at specific times in the sequence 143 | wire[2:0] tmp_clk_seq; 144 | assign tmp_clk_seq = clk_seq + 3'd7; 145 | assign pix_640 = tmp_clk_seq[1] ? pix_bits[0] : pix_bits[1]; 146 | 147 | // In Tandy 320x200x16 mode, concatenate two adjacent pixels 148 | wire temp; 149 | assign temp = clk_seq[1:0] == 2'b00; 150 | always @ (posedge clk) 151 | begin 152 | if (clk_seq[0]) begin 153 | if (clk_seq[1]) begin 154 | tandy_bits <= {pix_bits_old, pix_bits}; 155 | end else begin 156 | pix_bits_old <= pix_bits; 157 | end 158 | end 159 | end 160 | 161 | // Add one clk cycle delay to match up pixel data with attribute byte 162 | // data. 163 | always @ (posedge clk) 164 | begin 165 | pix_delay <= pix; 166 | end 167 | 168 | // Applies video attributes, generates final video 169 | cga_attrib attrib ( 170 | .clk(clk), 171 | .att_byte(attr_byte_del), 172 | .row_addr(row_addr), 173 | .cga_color_reg(cga_color_reg), 174 | .grph_mode(grph_mode), 175 | .bw_mode(bw_mode), 176 | .mode_640(mode_640), 177 | .tandy_16_mode(tandy_16_mode), 178 | .display_enable(display_enable_del[0]), 179 | .blink_enabled(blink_enabled), 180 | .blink(blink), 181 | .cursor(cursor_del[0]), 182 | .hsync(hsync), 183 | .vsync(vsync), 184 | .pix_in(pix_delay), 185 | .c0(pix_bits[0]), 186 | .c1(pix_bits[1]), 187 | .pix_640(pix_640), 188 | .pix_tandy(tandy_bits), 189 | .pix_out(video) 190 | ); 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /verilog/cga_scandoubler.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_scandoubler( 11 | input clk, 12 | input line_reset, 13 | input display_enable, 14 | input[3:0] video, 15 | output reg dbl_hsync, 16 | output[3:0] dbl_video, 17 | output dbl_display_enable 18 | ); 19 | 20 | reg sclk = 1'b0; 21 | reg[9:0] hcount_slow; 22 | reg[9:0] hcount_fast; 23 | reg line_reset_old = 1'b0; 24 | 25 | wire[9:0] addr_a; 26 | wire[9:0] addr_b; 27 | 28 | reg[4:0] data_a; 29 | reg[4:0] data_b; 30 | 31 | reg[4:0] scan_ram_a [1023:0]; 32 | reg[4:0] scan_ram_b [1023:0]; 33 | 34 | reg select = 1'b0; 35 | 36 | // VGA 640x480@60Hz has pix clk of 25.175MHz. Ours is 28.6364MHz, 37 | // so it is not quite an exact match. 896 clocks per line gives us 38 | // an horizontal rate of 31.96KHz which is close to 31.78KHz (spec). 39 | 40 | // Vertical lines are doubled, so 262 * 2 = 524 which matches exactly. 41 | 42 | always @ (posedge clk) 43 | begin 44 | line_reset_old <= line_reset; 45 | end 46 | 47 | // Double scanned horizontal counter 48 | always @ (posedge clk) 49 | begin 50 | if (line_reset & ~line_reset_old) begin 51 | hcount_fast <= 11'd0; 52 | end else begin 53 | if (hcount_fast == 10'd911) begin 54 | hcount_fast <= 10'd0; 55 | end else begin 56 | hcount_fast <= hcount_fast + 11'd1; 57 | end 58 | 59 | // Fixed doubled hsync 60 | if (hcount_fast == 10'd720) begin 61 | dbl_hsync <= 1; 62 | end 63 | if (hcount_fast == (10'd720 + 10'd160)) begin 64 | dbl_hsync <= 0; 65 | end 66 | end 67 | end 68 | 69 | // Standard scan horizontal counter 70 | always @ (posedge clk) 71 | begin 72 | sclk <= ~sclk; 73 | if (line_reset & ~line_reset_old) begin 74 | hcount_slow <= 10'd0; 75 | end else if (sclk) begin 76 | hcount_slow <= hcount_slow + 10'd1; 77 | end 78 | end 79 | 80 | // Select latch lets us swap between line store RAMs A and B 81 | always @ (posedge clk) 82 | begin 83 | if (line_reset & ~line_reset_old) begin 84 | select = ~select; 85 | end 86 | end 87 | 88 | assign addr_a = select ? hcount_slow : hcount_fast; 89 | assign addr_b = select ? hcount_fast : hcount_slow; 90 | 91 | // RAM A 92 | always @ (posedge clk) 93 | begin 94 | if (select) begin 95 | scan_ram_a[(addr_a)][0] <= video[0]; 96 | scan_ram_a[(addr_a)][1] <= video[1]; 97 | scan_ram_a[(addr_a)][2] <= video[2]; 98 | scan_ram_a[(addr_a)][3] <= video[3]; 99 | scan_ram_a[(addr_a)][4] <= display_enable; 100 | end 101 | data_a <= scan_ram_a[addr_a]; 102 | end 103 | 104 | // RAM B 105 | always @ (posedge clk) 106 | begin 107 | if (!select) begin 108 | scan_ram_b[(addr_b)][0] <= video[0]; 109 | scan_ram_b[(addr_b)][1] <= video[1]; 110 | scan_ram_b[(addr_b)][2] <= video[2]; 111 | scan_ram_b[(addr_b)][3] <= video[3]; 112 | scan_ram_b[(addr_b)][4] <= display_enable; 113 | end 114 | data_b <= scan_ram_b[addr_b]; 115 | end 116 | 117 | assign dbl_video[0] = select ? data_b[0] : data_a[0]; 118 | assign dbl_video[1] = select ? data_b[1] : data_a[1]; 119 | assign dbl_video[2] = select ? data_b[2] : data_a[2]; 120 | assign dbl_video[3] = select ? data_b[3] : data_a[3]; 121 | assign dbl_display_enable = select ? data_b[4] : data_a[4]; 122 | 123 | endmodule 124 | -------------------------------------------------------------------------------- /verilog/cga_sequencer.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_sequencer( 11 | input clk, 12 | output[4:0] clk_seq, 13 | output vram_read, 14 | output vram_read_a0, 15 | output vram_read_char, 16 | output vram_read_att, 17 | input hres_mode, 18 | output crtc_clk, 19 | output charrom_read, 20 | output disp_pipeline, 21 | output isa_op_enable, 22 | output hclk, 23 | output lclk, 24 | input tandy_16_gfx 25 | ); 26 | 27 | wire crtc_clk_int; 28 | reg[4:0] clkdiv = 5'b0; 29 | 30 | // Sequencer: times internal operations 31 | always @ (posedge clk) 32 | begin 33 | if (clkdiv == 5'd31) begin 34 | clkdiv <= 5'd0; 35 | end else begin 36 | clkdiv <= clkdiv + 1; 37 | end 38 | end 39 | 40 | // For 80 column text, we do everything twice for a complete clkdiv cycle. 41 | // For 40 column text, we do everything once for a complete clkdiv cycle. 42 | assign lclk = (clkdiv == 5'd0); 43 | assign hclk = (clkdiv == 5'd0) || (clkdiv == 5'd16); 44 | 45 | assign crtc_clk_int = (clkdiv == 5'd0) || (hres_mode ? (clkdiv == 5'd16) : 0); 46 | 47 | // Control signals based on the sequencer state 48 | assign vram_read = (clkdiv == 5'd1) || (clkdiv == 5'd2) || (clkdiv == 5'd3) || 49 | (clkdiv == 5'd17) || (clkdiv == 5'd18) || (clkdiv == 5'd19); 50 | assign vram_read_a0 = (clkdiv == 5'd2) || (clkdiv == 5'd18); 51 | assign vram_read_char = (clkdiv == 5'd2) || (hres_mode ? (clkdiv == 5'd18) : 0); 52 | assign vram_read_att = (clkdiv == 5'd3) || (hres_mode ? (clkdiv == 5'd19) : 0); 53 | assign charrom_read = (clkdiv == 5'd3) || (hres_mode ? (clkdiv == 5'd19) : 0);// 3 and 19? 54 | assign disp_pipeline = (clkdiv == (tandy_16_gfx ? 5'd7 : 5'd4)) || (hres_mode ? (clkdiv == (tandy_16_gfx ? 5'd23 : 5'd20)) : 0); 55 | assign crtc_clk = crtc_clk_int; 56 | assign clk_seq = clkdiv; 57 | // Leave a gap of at least 2 cycles between the end of ISA operation and 58 | // vram_read. This is because an ISA operation takes 3 cycles. 59 | assign isa_op_enable = ((clkdiv > 5'd4) && (clkdiv < 5'd15)) || 60 | ((clkdiv > 5'd20) && (clkdiv < 5'd31)); 61 | 62 | endmodule 63 | 64 | -------------------------------------------------------------------------------- /verilog/cga_top.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module cga_top( 11 | // Clocks 12 | input clk_10m, 13 | input clk_14m318, 14 | input clk_bus, 15 | 16 | // Bus reset 17 | input busreset, 18 | 19 | // ISA bus 20 | input[19:0] bus_a, 21 | input bus_ior_l, 22 | input bus_iow_l, 23 | input bus_memr_l, 24 | input bus_memw_l, 25 | inout[7:0] bus_d, 26 | output bus_dir, 27 | output bus_rdy, 28 | output bus_0ws_l, 29 | input bus_aen, 30 | input bus_ale, 31 | 32 | // RAM 33 | output ram_we_l, 34 | output[18:0] ram_a, 35 | inout[7:0] ram_d, 36 | 37 | output hdmi_red, 38 | output hdmi_grn, 39 | output hdmi_blu, 40 | output hdmi_int, 41 | output hdmi_grn_int, 42 | 43 | output hdmi_vs, 44 | output hdmi_hs, 45 | 46 | output hdmi_clk, 47 | 48 | output hdmi_de, 49 | 50 | 51 | // Video outputs 52 | // output hsync, 53 | // output vsync, 54 | // output vid_en_l, 55 | // output d_r, 56 | // output d_g, 57 | // output d_b, 58 | // output d_r2, 59 | // output d_g2, 60 | // output d_b2, 61 | output vga_hsync, 62 | output vga_vsync, 63 | output[5:0] red, 64 | output[6:0] green, 65 | output[5:0] blue, 66 | 67 | // Config switches 68 | input switch2, 69 | input switch3 70 | ); 71 | 72 | wire hsync; 73 | wire vsync; 74 | wire d_r; 75 | wire d_g; 76 | wire d_b; 77 | wire d_r2; 78 | wire d_g2; 79 | wire d_b2; 80 | 81 | // Sets up the card to generate a video signal 82 | // that will work with a standard VGA monitor 83 | // connected to the VGA port. 84 | parameter MDA_70HZ = 0; 85 | 86 | wire clk_main; 87 | wire pll_lock; 88 | 89 | wire[7:0] bus_out; 90 | 91 | wire[3:0] video; 92 | wire[3:0] vga_video; 93 | 94 | wire composite_on; 95 | wire thin_font; 96 | wire display_enable; 97 | wire dbl_display_enable; 98 | 99 | wire[5:0] vga_red; 100 | wire[6:0] vga_green; 101 | wire[5:0] vga_blue; 102 | wire[6:0] comp_video; 103 | 104 | // Unused pins on video connector 105 | assign bus_0ws_l = 1'b1; 106 | //assign vid_en_l = 1'b0; 107 | 108 | // Composite mode switch 109 | assign composite_on = switch3; 110 | 111 | // Thin font switch 112 | assign thin_font = switch2; 113 | 114 | // Set up bus direction 115 | assign bus_d = (bus_dir) ? bus_out : 8'hzz; 116 | 117 | // CGA mode 118 | // Take our incoming 14.318MHz clock and generate the pixel clock 119 | // 28.636MHz: 0, 63, 5 120 | // Could also use an SB_PLL40_2_PAD to generate an additional 121 | // 14.318MHz clock without having to use a separate divider. 122 | wire int_clk; 123 | `ifdef SYNTHESIS 124 | SB_PLL40_PAD #( 125 | .FEEDBACK_PATH("SIMPLE"), 126 | .DIVR(0), 127 | .DIVF(63), 128 | .DIVQ(5), 129 | .FILTER_RANGE(1) 130 | ) cga_pll ( 131 | .LOCK(pll_lock), 132 | .RESETB(1'b1), 133 | .BYPASS(1'b0), 134 | .PACKAGEPIN(clk_14m318), 135 | .PLLOUTGLOBAL(clk_main) 136 | ); 137 | `else 138 | assign clk_main = clk_14m318; 139 | `endif 140 | 141 | // CGA digital to analog converter 142 | cga_vgaport vga ( 143 | .clk(clk_main), 144 | .video(vga_video), 145 | .red(vga_red), 146 | .green(vga_green), 147 | .blue(vga_blue) 148 | ); 149 | 150 | cga_hdmiport hdmi( 151 | .clk(clk_main), 152 | .video(vga_video), 153 | .display_enable(dbl_display_enable), 154 | .hsync(vga_hsync), 155 | .vsync(vsync), 156 | .hdmi_red(hdmi_red), 157 | .hdmi_grn(hdmi_grn), 158 | .hdmi_blu(hdmi_blu), 159 | .hdmi_grn_int(hdmi_grn_int), 160 | .hdmi_int(hdmi_int), 161 | .hdmi_hs(hdmi_hs), 162 | .hdmi_vs(hdmi_vs), 163 | .hdmi_clk(hdmi_clk), 164 | .hdmi_de(hdmi_de), 165 | ); 166 | 167 | // Analog output mux: Either RGB or composite 168 | assign red = composite_on ? 6'd0 : vga_red; 169 | assign green = composite_on ? comp_video : vga_green; 170 | assign blue = composite_on ? 6'd0 : vga_blue; 171 | 172 | assign vga_vsync = vsync; 173 | 174 | cga cga1 ( 175 | .clk(clk_main), 176 | .bus_a(bus_a), 177 | .bus_ior_l(bus_ior_l), 178 | .bus_iow_l(bus_iow_l), 179 | .bus_memr_l(bus_memr_l), 180 | .bus_memw_l(bus_memw_l), 181 | .bus_d(bus_d), 182 | .bus_out(bus_out), 183 | .bus_dir(bus_dir), 184 | .bus_aen(bus_aen), 185 | .bus_rdy(bus_rdy), 186 | .ram_we_l(ram_we_l), 187 | .ram_a(ram_a), 188 | .ram_d(ram_d), 189 | .hsync(hsync), 190 | .dbl_hsync(vga_hsync), 191 | .vsync(vsync), 192 | .video(video), 193 | .dbl_video(vga_video), 194 | .comp_video(comp_video), 195 | .thin_font(thin_font), 196 | .display_enable(display_enable), 197 | .dbl_display_enable(dbl_display_enable) 198 | ); 199 | 200 | defparam cga1.OVERSCAN = 0; 201 | 202 | `ifdef SYNTHESIS 203 | defparam cga1.BLINK_MAX = 24'd4772727; 204 | `else 205 | defparam cga1.BLINK_MAX = 24'd10; 206 | `endif 207 | 208 | endmodule 209 | -------------------------------------------------------------------------------- /verilog/cga_vgaport.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | module cga_vgaport( 10 | input clk, 11 | 12 | input[3:0] video, 13 | 14 | // Analog outputs 15 | output[5:0] red, 16 | output[6:0] green, 17 | output[5:0] blue 18 | ); 19 | 20 | reg[17:0] c; 21 | 22 | assign blue = c[5:0]; 23 | assign green = {c[11:6], 1'b1}; // FIXME: 1? 24 | assign red = c[17:12]; 25 | 26 | always @(posedge clk) 27 | begin 28 | case(video) 29 | 4'h0: c <= 18'b000000_000000_000000; 30 | 4'h1: c <= 18'b000000_000000_101010; 31 | 4'h2: c <= 18'b000000_101010_000000; 32 | 4'h3: c <= 18'b000000_101010_101010; 33 | 4'h4: c <= 18'b101010_000000_000000; 34 | 4'h5: c <= 18'b101010_000000_101010; 35 | 4'h6: c <= 18'b101010_010101_000000; // Brown! 36 | 4'h7: c <= 18'b101010_101010_101010; 37 | 4'h8: c <= 18'b010101_010101_010101; 38 | 4'h9: c <= 18'b010101_010101_111111; 39 | 4'hA: c <= 18'b010101_111111_010101; 40 | 4'hB: c <= 18'b010101_111111_111111; 41 | 4'hC: c <= 18'b111111_010101_010101; 42 | 4'hD: c <= 18'b111111_010101_111111; 43 | 4'hE: c <= 18'b111111_111111_010101; 44 | 4'hF: c <= 18'b111111_111111_111111; 45 | default: ; 46 | endcase 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /verilog/cga_vram.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | module cga_vram( 10 | // Clock 11 | input clk, 12 | 13 | // Lines from other logic 14 | // Port 0 is read/write 15 | input[18:0] isa_addr, 16 | input[7:0] isa_din, 17 | output[7:0] isa_dout, 18 | input isa_read, 19 | input isa_write, 20 | input isa_op_enable, 21 | 22 | // Port 1 is read only 23 | input[18:0] pixel_addr, 24 | output reg[7:0] pixel_data, 25 | input pixel_read, 26 | 27 | // Lines to RAM pins 28 | output reg[18:0] ram_a, 29 | inout[7:0] ram_d, 30 | output ram_ce_l, 31 | output ram_oe_l, 32 | output ram_we_l 33 | ); 34 | 35 | parameter MDA_70HZ = 0; 36 | 37 | reg[19:0] op_addr = 20'd0; 38 | reg[7:0] ram_write_data = 8'd0; 39 | reg isa_write_old = 1'b0; 40 | reg[2:0] write_del = 0; 41 | 42 | assign ram_ce_l = 0; 43 | assign ram_oe_l = 0; 44 | 45 | assign ram_we_l = ~(write_del == 3'd4); 46 | assign isa_dout = ram_d; 47 | 48 | // Gated by clock so that we give the SRAM chip 49 | // some time to tristate its data output after 50 | // we begin the write operation. (tHZWE) 51 | assign ram_d = (~ram_we_l & ~clk) ? ram_write_data : 8'hZZ; 52 | 53 | // RAM address pin mux 54 | always @ (*) 55 | begin 56 | if (isa_read) begin 57 | ram_a <= isa_addr; 58 | end else if ((write_del == 3'd3) || (write_del == 3'd4)) begin 59 | ram_a <= op_addr; 60 | end else begin 61 | ram_a <= pixel_addr; 62 | end 63 | end 64 | 65 | // For edge detection of ISA writes 66 | always @ (posedge clk) 67 | begin 68 | isa_write_old <= isa_write; 69 | end 70 | 71 | // Address is latched on initial edge of write 72 | always @ (posedge clk) 73 | begin 74 | if (isa_write && !isa_write_old) begin 75 | op_addr <= isa_addr; 76 | end 77 | end 78 | 79 | // Wait a few cycles before latching data from ISA 80 | // bus, since the data isn't valid right away. 81 | always @ (posedge clk) 82 | begin 83 | if (isa_write && !isa_write_old) begin 84 | write_del <= 3'd1; 85 | end else if (write_del != 3'd0) begin 86 | if (write_del == 3'd7) begin 87 | write_del <= 3'd0; 88 | end else begin 89 | write_del <= write_del + 1; 90 | end 91 | end 92 | end 93 | 94 | always @ (posedge clk) 95 | begin 96 | if (write_del == 3'd2) begin 97 | ram_write_data <= isa_din; 98 | end 99 | end 100 | 101 | // Pixel data output mux 102 | always @ (posedge clk) 103 | begin 104 | if (isa_read || (write_del == 3'd3) || (write_del == 3'd4)) begin 105 | // The cause of CGA snow! 106 | pixel_data <= 8'hff; 107 | end else begin 108 | pixel_data <= ram_d; 109 | end 110 | end 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /verilog/crtc6845.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module crtc6845( 11 | input clk, 12 | input divclk, 13 | 14 | // ISA bus 15 | input cs, 16 | input a0, 17 | input write, 18 | input read, 19 | input[7:0] bus, 20 | output[7:0] bus_out, 21 | 22 | input lock, 23 | 24 | // Video control signals 25 | output hsync, 26 | output vsync, 27 | output display_enable, 28 | output display_enable_mda, 29 | output display_enable_overscan, 30 | output cursor, 31 | output [13:0] mem_addr, 32 | output [4:0] row_addr, 33 | output line_reset); 34 | 35 | parameter H_TOTAL = 0; 36 | parameter H_DISP = 0; 37 | parameter H_SYNCPOS = 0; 38 | parameter H_SYNCWIDTH = 0; 39 | parameter V_TOTAL = 0; 40 | parameter V_TOTALADJ = 0; 41 | parameter V_DISP = 0; 42 | parameter V_SYNCPOS = 0; 43 | parameter V_MAXSCAN = 0; 44 | parameter C_START = 0; 45 | parameter C_END = 0; 46 | 47 | reg[4:0] cur_addr; 48 | reg[7:0] bus_out; 49 | 50 | // Address register 51 | always @ (posedge clk) begin 52 | if (~a0 & write & cs) begin 53 | cur_addr <= bus[4:0]; 54 | end 55 | end 56 | 57 | // Register file 58 | always @ (posedge clk) begin 59 | if (a0 & write & cs & (~lock | (cur_addr > 5'd9))) begin 60 | case (cur_addr) 61 | 5'd0: h_total <= bus; 62 | 5'd1: h_disp <= bus; 63 | 5'd2: h_syncpos <= bus; 64 | 5'd3: h_syncwidth <= bus[3:0]; 65 | 5'd4: v_total <= bus[6:0]; 66 | 5'd5: v_totaladj <= bus[4:0]; 67 | 5'd6: v_disp <= bus[6:0]; 68 | 5'd7: v_syncpos <= bus[6:0]; 69 | // Register 8 not implemented 70 | 5'd9: v_maxscan <= bus[4:0]; 71 | 5'd10: c_start <= bus[6:0]; 72 | 5'd11: c_end <= bus[4:0]; 73 | 5'd12: start_a[13:8] <= bus[5:0]; 74 | 5'd13: start_a[7:0] <= bus; 75 | 5'd14: cursor_a[13:8] <= bus[5:0]; 76 | 5'd15: cursor_a[7:0] <= bus; 77 | default: ; 78 | endcase 79 | end 80 | end 81 | // TODO: Add light pen register (optional) 82 | always @ (*) 83 | begin 84 | case (cur_addr) 85 | 5'd0: bus_out <= h_total; 86 | 5'd1: bus_out <= h_disp; 87 | 5'd2: bus_out <= h_syncpos; 88 | 5'd3: bus_out <= h_syncwidth; 89 | 5'd4: bus_out <= v_total; 90 | 5'd5: bus_out <= v_totaladj; 91 | 5'd6: bus_out <= v_disp; 92 | 5'd7: bus_out <= v_syncpos; 93 | 5'd8: bus_out <= 8'h00; 94 | 5'd9: bus_out <= v_maxscan; 95 | 5'd10: bus_out <= c_start; 96 | 5'd11: bus_out <= c_end; 97 | 5'd12: bus_out <= {2'b00, start_a[13:8]}; 98 | 5'd13: bus_out <= start_a[7:0]; 99 | 5'd14: bus_out <= {2'b00, cursor_a[13:8]}; 100 | 5'd15: bus_out <= cursor_a[7:0]; 101 | 5'd16: bus_out <= 8'h00; // Light pen regs 102 | 5'd17: bus_out <= 8'h00; 103 | default: bus_out <= 8'h00; 104 | endcase; 105 | end 106 | 107 | // TODO: parameterize these defaults 108 | reg [7:0] h_total = H_TOTAL; //R0 97 109 | reg [7:0] h_disp = H_DISP; //R1 80 110 | reg [7:0] h_syncpos = H_SYNCPOS; //R2 82 111 | reg [3:0] h_syncwidth = H_SYNCWIDTH; //R3 15 112 | 113 | reg [6:0] v_total = V_TOTAL; //R4 25 114 | reg [4:0] v_totaladj = V_TOTALADJ; //R5 6 115 | reg [6:0] v_disp = V_DISP; //R6 25 116 | reg [6:0] v_syncpos = V_SYNCPOS; //R7 25 117 | reg [4:0] v_maxscan = V_MAXSCAN; //R9 13 118 | 119 | reg [6:0] c_start = C_START; //R10 11 120 | reg [4:0] c_end = C_END; //R11 12 121 | 122 | reg [13:0] start_a = 14'd0; //R13/R14 123 | 124 | reg [13:0] cursor_a = 14'd92; //R14/R15 125 | 126 | // Counters 127 | reg [7:0] h_count = 8'd0; 128 | reg [3:0] h_synccount = 4'd1; // Must start at 1 129 | reg [4:0] v_scancount = 5'd0; 130 | reg [6:0] v_rowcount = 7'd0; 131 | reg [3:0] v_synccount = 4'd0; 132 | reg [4:0] cursor_counter = 5'd0; // Cursor blink 133 | 134 | 135 | wire [4:0] next_v_scancount; 136 | wire [13:0] ma = 14'd0; 137 | reg [13:0] ma_rst = 14'd0; // Column reset of memory address 138 | 139 | reg vs = 1'b0; 140 | reg hs = 1'b0; 141 | reg hdisp = 1'b1; 142 | reg hdisp_mda = 1'b1; 143 | reg vdisp = 1'b1; 144 | 145 | reg hdisp_overscan = 1'b1; 146 | reg vdisp_overscan = 1'b1; 147 | 148 | wire cur_on; 149 | wire blink; 150 | 151 | wire h_end; 152 | wire v_end; 153 | 154 | assign vsync = vs; 155 | assign hsync = hs; 156 | assign display_enable = hdisp & vdisp; 157 | assign display_enable_mda = hdisp_mda & vdisp; 158 | assign display_enable_overscan = hdisp_overscan & vdisp_overscan; 159 | 160 | assign row_addr = v_scancount; 161 | 162 | assign h_end = (h_count == h_total); 163 | 164 | assign line_reset = h_end; 165 | 166 | // Horizontal counter 167 | always @ (posedge clk) 168 | begin 169 | if (divclk) begin 170 | 171 | if (h_count == h_total) begin 172 | h_count <= 8'd0; 173 | hdisp <= 1'b1; 174 | hdisp_overscan <= 1'b1; 175 | end else begin 176 | h_count <= h_count + 1; 177 | 178 | //hdisp_mda is used to generate another display_enable_mda as the existing display_enable on MDA has an issue of the screen being shifted to the right by one character 179 | if (h_count == 0) begin 180 | hdisp_mda <= 1'b1; 181 | end 182 | 183 | // Blanking 184 | if (h_count + 1 == h_disp) begin 185 | hdisp <= 1'b0; 186 | end 187 | 188 | if (h_count == h_disp) begin 189 | hdisp_mda <= 1'b0; 190 | end 191 | 192 | // Overscan DE up to just before Hsync 193 | if (h_count + 2 == h_syncpos) begin 194 | hdisp_overscan <= 1'b0; 195 | end 196 | 197 | // Sync output 198 | if (h_count + 1 == h_syncpos) begin 199 | hs <= 1'b1; 200 | end 201 | end 202 | end 203 | 204 | // Horizontal sync timer 205 | if (divclk & hs) begin 206 | if (h_synccount == h_syncwidth) begin 207 | h_synccount <= 4'b1; 208 | hs <= 1'b0; 209 | end else begin 210 | h_synccount <= h_synccount + 4'b1; 211 | end 212 | end 213 | end 214 | 215 | 216 | assign v_end = (v_rowcount == v_total) & 217 | (v_scancount == v_maxscan + v_totaladj); 218 | // Vertical counter 219 | always @ (posedge clk) 220 | begin 221 | if (divclk & (h_count == h_total)) begin // was h_syncpos 222 | 223 | if (v_rowcount != v_total) begin 224 | // Vertical count event 225 | if (v_scancount != v_maxscan) begin 226 | v_scancount <= v_scancount + 1; 227 | end else begin 228 | v_scancount <= 0; 229 | v_rowcount <= v_rowcount + 1; 230 | 231 | // Handle vertical pulse 232 | if (v_rowcount + 1 == v_syncpos) begin 233 | vs <= 1'b1; 234 | end 235 | 236 | // Overscan DE up to just before Vsync 237 | if (v_rowcount + 3 == v_syncpos) begin 238 | vdisp_overscan <= 1'b0; 239 | end 240 | 241 | // Handle blanking 242 | if (v_rowcount + 1 == v_disp) begin 243 | vdisp <= 1'b0; 244 | end 245 | end 246 | end else begin 247 | // Pad with vertical adjust 248 | if (v_scancount != v_maxscan + v_totaladj) begin 249 | v_scancount <= v_scancount + 1; 250 | end else begin 251 | v_scancount <= 0; 252 | v_rowcount <= 0; 253 | vdisp <= 1'b1; 254 | vdisp_overscan <= 1'b1; 255 | cursor_counter <= cursor_counter + 1; 256 | end 257 | end 258 | 259 | // Vertical sync pulse is fixed at 16 scan line times 260 | // Vsync pulse turns off after 16 lines 261 | if (vs) begin 262 | if (v_synccount == 4'd15) begin 263 | v_synccount <= 4'd0; 264 | vs <= 0; 265 | end else begin 266 | v_synccount <= v_synccount + 1; 267 | end 268 | end 269 | end 270 | end 271 | 272 | // Cursor 273 | assign cur_on = (v_scancount >= c_start[4:0]) & 274 | (v_scancount <= c_end[4:0]); 275 | assign blink = (c_start[6:5] == 2'b00) | 276 | (c_start[5] ? cursor_counter[4] : cursor_counter[3]); 277 | assign cursor = (cursor_a == mem_addr) & cur_on & 278 | blink & (c_start[6:5] != 2'b01) & display_enable; 279 | 280 | // Memory address generator 281 | assign mem_addr = start_a + ma_rst + {6'b000000, h_count}; 282 | always @ (posedge clk) 283 | begin 284 | if (divclk & (v_end | h_end)) begin 285 | if (v_end) begin 286 | ma_rst <= 14'd0; 287 | end else begin 288 | if (v_scancount == v_maxscan) begin 289 | ma_rst <= ma_rst + {6'b000000, h_disp}; 290 | end 291 | end 292 | end 293 | end 294 | endmodule 295 | -------------------------------------------------------------------------------- /verilog/gremlin.pcf: -------------------------------------------------------------------------------- 1 | ### Graphics Gremlin 2 | 3 | ### Copyright (c) 2021 Eric Schlaepfer 4 | ### This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | ### International License. To view a copy of this license, visit 6 | ### http://creativecommons.org/license/by-sa/4.0/ or send a letter to Creative 7 | ### Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | 9 | ### Clocks 10 | set_io clk_14m318 129 11 | set_io clk_10m 49 12 | set_io clk_bus 128 13 | 14 | ### Bus reset 15 | set_io busreset 52 16 | 17 | ### ISA bus 18 | set_io bus_a[0] 1 19 | set_io bus_a[1] 2 20 | set_io bus_a[2] 3 21 | set_io bus_a[3] 4 22 | set_io bus_a[4] 7 23 | set_io bus_a[5] 8 24 | set_io bus_a[6] 9 25 | set_io bus_a[7] 10 26 | set_io bus_a[8] 11 27 | set_io bus_a[9] 12 28 | set_io bus_a[10] 15 29 | set_io bus_a[11] 16 30 | set_io bus_a[12] 17 31 | set_io bus_a[13] 18 32 | set_io bus_a[14] 19 33 | set_io bus_a[15] 20 34 | set_io bus_a[16] 21 35 | set_io bus_a[17] 22 36 | set_io bus_a[18] 23 37 | set_io bus_a[19] 24 38 | set_io bus_ior_l 25 39 | set_io bus_iow_l 26 40 | set_io bus_memr_l 28 41 | set_io bus_memw_l 29 42 | set_io bus_d[0] 31 43 | set_io bus_d[1] 32 44 | set_io bus_d[2] 33 45 | set_io bus_d[3] 34 46 | set_io bus_d[4] 37 47 | set_io bus_d[5] 38 48 | set_io bus_d[6] 39 49 | set_io bus_d[7] 41 50 | set_io bus_dir 42 51 | set_io bus_rdy 43 52 | set_io bus_0ws_l 44 53 | set_io bus_aen 45 54 | set_io bus_ale 47 55 | 56 | ### RAM 57 | set_io ram_we_l 130 58 | set_io ram_a[0] 105 59 | set_io ram_a[1] 106 60 | set_io ram_a[2] 110 61 | set_io ram_a[3] 113 62 | set_io ram_a[4] 115 63 | set_io ram_a[5] 135 64 | set_io ram_a[6] 137 65 | set_io ram_a[7] 139 66 | set_io ram_a[8] 142 67 | set_io ram_a[9] 144 68 | set_io ram_a[10] 143 69 | set_io ram_a[11] 141 70 | set_io ram_a[12] 138 71 | set_io ram_a[13] 136 72 | set_io ram_a[14] 134 73 | set_io ram_a[15] 116 74 | set_io ram_a[16] 114 75 | set_io ram_a[17] 112 76 | set_io ram_a[18] 107 77 | set_io ram_d[0] 117 78 | set_io ram_d[1] 119 79 | set_io ram_d[2] 121 80 | set_io ram_d[3] 124 81 | set_io ram_d[4] 125 82 | set_io ram_d[5] 122 83 | set_io ram_d[6] 120 84 | set_io ram_d[7] 118 85 | 86 | ### HDMI outputs 87 | set_io hdmi_blu 48 88 | set_io hdmi_vs 55 89 | set_io hdmi_grn 56 90 | set_io hdmi_hs 60 91 | set_io hdmi_red 61 92 | set_io hdmi_clk 62 93 | set_io hdmi_de 73 94 | set_io hdmi_int 74 95 | set_io hdmi_grn_int 75 96 | 97 | 98 | ### Video outputs 99 | #set_io hsync 60 100 | #set_io vsync 55 101 | #set_io d_r 61 102 | #set_io d_g 56 103 | #set_io d_b 48 104 | #set_io d_r2 73 105 | #set_io d_g2 74 106 | #set_io d_b2 62 107 | #set_io vid_en_l 75 108 | 109 | set_io vga_hsync 102 110 | set_io vga_vsync 104 111 | set_io red[0] 93 112 | set_io red[1] 94 113 | set_io red[2] 95 114 | set_io red[3] 96 115 | set_io red[4] 97 116 | set_io red[5] 98 117 | set_io green[0] 83 118 | set_io green[1] 84 119 | set_io green[2] 85 120 | set_io green[3] 87 121 | set_io green[4] 88 122 | set_io green[5] 90 123 | set_io green[6] 91 124 | set_io blue[0] 76 125 | set_io blue[1] 78 126 | set_io blue[2] 79 127 | set_io blue[3] 80 128 | set_io blue[4] 81 129 | set_io blue[5] 82 130 | 131 | # Config switch inputs 132 | set_io switch2 101 133 | set_io switch3 99 134 | -------------------------------------------------------------------------------- /verilog/is61_tester.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `timescale 1ns / 1ps 10 | module is61_tester; 11 | 12 | reg[18:0] address; 13 | wire[7:0] data; 14 | reg ce_l; 15 | reg oe_l; 16 | reg we_l; 17 | 18 | reg[7:0] data_out; 19 | reg data_dir; 20 | 21 | assign data = data_dir ? data_out : 8'hzz; 22 | 23 | is61c5128 dut( 24 | .address(address), 25 | .data(data), 26 | .ce_l(ce_l), 27 | .oe_l(oe_l), 28 | .we_l(we_l) 29 | ); 30 | 31 | initial begin 32 | $dumpfile("is61_tester.vcd"); 33 | $dumpvars(0,is61_tester); 34 | ce_l = 1; 35 | oe_l = 1; 36 | we_l = 1; 37 | address = 19'h00000; 38 | data_out = 8'h00; 39 | data_dir = 0; 40 | 41 | #500 42 | data_dir = 1; 43 | data_out = 8'hAA; 44 | ce_l = 0; 45 | oe_l = 0; 46 | we_l = 0; 47 | #10 48 | we_l = 1; 49 | data_dir = 0; 50 | #10 51 | address = 19'h1; 52 | data_dir = 1; 53 | data_out = 8'h55; 54 | we_l = 0; 55 | #10 56 | we_l = 1; 57 | data_dir = 0; 58 | #10 59 | address = 19'h0; 60 | 61 | 62 | #100 $finish; 63 | end 64 | endmodule 65 | -------------------------------------------------------------------------------- /verilog/is61c5128_t.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | 10 | // behavioral model of IS61C5128AL SRAM 11 | module is61c5128( 12 | input[18:0] address, 13 | inout[7:0] data, 14 | input ce_l, 15 | input oe_l, 16 | input we_l 17 | ); 18 | 19 | wire array_out; 20 | wire[7:0] data_out; 21 | wire[7:0] data_in_delay; 22 | wire[7:0] debug_data0; 23 | wire data_dir; 24 | 25 | wire ce_delay; 26 | wire oe_delay; 27 | wire we_delay; 28 | wire[18:0] addr_delay; 29 | integer i; 30 | // Truncated data array for simulation speed 31 | reg [7:0] data_array[0:1024]; 32 | 33 | initial begin 34 | for (i = 0; i < 1024; i++) begin 35 | data_array[i] = i & 8'hFF; 36 | end 37 | end 38 | 39 | assign debug_data0 = data_array[10'h00]; 40 | 41 | assign #10 addr_delay = address; 42 | assign #2 ce_delay = ~ce_l; // 2ns tLZCS 43 | assign oe_delay = ~oe_l; // 0ns min tLZOE 44 | assign #3 we_delay = ~we_l; // 3ns tLZWE 45 | assign #1 data_in_delay = data; // This makes the 0ns hold time work 46 | 47 | // Tristate buffer 48 | assign data_dir = ce_delay & oe_delay & ~we_delay; 49 | assign data = data_dir ? data_out : 8'hzz; 50 | 51 | assign data_out = data_array[addr_delay[10:0]]; 52 | 53 | always @ (posedge we_l) begin 54 | data_array[addr_delay[10:0]] <= data_in_delay; 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /verilog/isavideo_t.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `timescale 1ns / 1ps 10 | 11 | // Test bench for ISA Video 12 | 13 | module isavideo_t; 14 | reg clk; 15 | wire hsync; 16 | wire vsync; 17 | wire video; 18 | 19 | reg[19:0] bus_a; 20 | wire[7:0] bus_d; 21 | reg[7:0] bus_d_out; 22 | reg bus_d_write = 0; 23 | wire bus_rdy; 24 | 25 | assign bus_d = (bus_d_write) ? bus_d_out : 8'hZZ; 26 | 27 | reg bus_ior_l = 1; 28 | reg bus_iow_l = 1; 29 | reg bus_memr_l = 1; 30 | reg bus_memw_l = 1; 31 | reg bus_aen = 1; 32 | 33 | wire ram_we_l; 34 | wire[18:0] ram_a; 35 | wire[7:0] ram_d; 36 | // Use isavideo here for MDA, cga_top for CGA. 37 | cga_top dut ( 38 | // .clk_10m(clk), // for MDA 39 | .clk_14m318(clk), // for CGA 40 | 41 | .bus_a(bus_a), 42 | .bus_ior_l(bus_ior_l), 43 | .bus_iow_l(bus_iow_l), 44 | .bus_memr_l(bus_memr_l), 45 | .bus_memw_l(bus_memw_l), 46 | .bus_aen(bus_aen), 47 | .bus_d(bus_d), 48 | .bus_rdy(bus_rdy), 49 | 50 | .ram_we_l(ram_we_l), 51 | .ram_d(ram_d), 52 | .ram_a(ram_a), 53 | 54 | .hsync(hsync), 55 | .vsync(vsync), 56 | .d_b2(video), 57 | .switch3(1'b0), 58 | .switch2(1'b0) 59 | ); 60 | 61 | is61c5128 vram( 62 | .address(ram_a), 63 | .data(ram_d), 64 | .ce_l(0), 65 | .oe_l(0), 66 | .we_l(ram_we_l) 67 | ); 68 | 69 | // 15=33.3MHz 70 | // 8=62.5MHz 71 | // 17=29.4MHz 72 | always #17 clk = ~clk; 73 | 74 | task isa_op; 75 | input state; 76 | input read; 77 | input io; 78 | begin 79 | if (read) begin 80 | if (io) begin 81 | bus_ior_l = state; 82 | end else begin 83 | bus_memr_l = state; 84 | end 85 | end else begin 86 | if (io) begin 87 | bus_iow_l = state; 88 | end else begin 89 | bus_memw_l = state; 90 | end 91 | end 92 | end 93 | endtask 94 | 95 | task isa_cycle; 96 | input[19:0] addr; 97 | input[7:0] data; 98 | input read; 99 | input io; 100 | begin 101 | bus_a = addr; 102 | bus_d_write = !read; 103 | bus_d_out = data; 104 | #176 105 | isa_op(0, read, io); 106 | #420 107 | wait(bus_rdy); 108 | isa_op(1, read, io); 109 | #236 110 | bus_d_write = 0; 111 | end 112 | endtask 113 | 114 | task crtc_write; 115 | input[7:0] addr; 116 | input[7:0] data; 117 | begin 118 | isa_cycle(20'h3D4, addr, 0, 1); 119 | isa_cycle(20'h3D5, data, 0, 1); 120 | end 121 | endtask 122 | 123 | integer i; 124 | 125 | initial begin 126 | clk = 0; 127 | $dumpfile("isavideo_t.vcd"); 128 | $dumpvars(0,isavideo_t); 129 | 130 | bus_aen = 0; 131 | 132 | // Set up graphics mode for this test. 133 | isa_cycle(20'h3D8, 8'b0000_1011, 0, 1); // 0000_1010 134 | isa_cycle(20'h3D9, 8'b0000_0000, 0, 1); 135 | crtc_write(8'd0, 8'd56); 136 | crtc_write(8'd1, 8'd40); 137 | crtc_write(8'd2, 8'd45); 138 | crtc_write(8'd4, 8'd127); 139 | crtc_write(8'd6, 8'd100); 140 | crtc_write(8'd7, 8'd112); 141 | crtc_write(8'd9, 8'd1); 142 | 143 | 144 | 145 | 146 | bus_a = 20'hB8055; 147 | bus_d_out = 8'hAA; 148 | bus_d_write = 1; 149 | #430 150 | #120 bus_memw_l = 0; 151 | #200 bus_memw_l = 1; 152 | #10 bus_d_write = 0; 153 | #100 bus_memr_l = 0; 154 | #200 bus_memr_l = 1; 155 | 156 | for (i = 0; i < 20; i++) begin 157 | #12 158 | #400 159 | bus_a = 20'hB8000 | i; 160 | bus_d_out = 8'h11; //8'hA0 + i; 161 | bus_memw_l = 0; 162 | bus_d_write = 1; 163 | #600 164 | wait(bus_rdy); 165 | bus_memw_l = 1; // was 200 166 | #50 bus_d_write = 0; 167 | end 168 | #400 169 | for (i = 0; i < 20; i++) begin 170 | #12 171 | #400 172 | bus_a = 20'hB8000 | i; 173 | bus_memr_l = 0; 174 | bus_d_write = 0; 175 | #600 176 | wait(bus_rdy); 177 | bus_memr_l = 1; 178 | end 179 | #400 180 | for (i = 0; i < 20; i+=2) begin 181 | bus_a = 20'hB8000 | i; 182 | bus_d_write = 0; 183 | #176 184 | bus_memr_l = 0; 185 | #420 186 | wait(bus_rdy); 187 | bus_memr_l = 1; 188 | #236 189 | bus_a = 20'hB8000 | (i + 1); 190 | #174 191 | bus_memr_l = 0; 192 | #420 193 | wait(bus_rdy); 194 | bus_memr_l = 1; 195 | #886 196 | bus_a = 20'hB8000 | i; 197 | bus_d_out = 8'h00 + (2<<(i&7)); 198 | bus_d_write = 1; 199 | #164 200 | bus_memw_l = 0; 201 | #420 202 | wait(bus_rdy); 203 | bus_memw_l = 1; 204 | #224 205 | bus_a = 20'hB8000 | (i + 1); 206 | bus_d_out = 8'h00 + (2<<((i + 1)&7)); 207 | #196 208 | bus_memw_l = 0; 209 | #420 210 | wait(bus_rdy); 211 | bus_memw_l = 1; 212 | #1494 213 | bus_d_write = 0; 214 | end 215 | 216 | // Try to write to CRTC 217 | bus_a = 20'h3D4; 218 | bus_aen = 0; 219 | bus_iow_l = 0; 220 | bus_d_write = 1; 221 | bus_d_out = 8'd1; 222 | #600 bus_iow_l = 1; 223 | bus_aen = 1; 224 | #400 225 | bus_a = 20'h3D5; 226 | bus_aen = 0; 227 | bus_iow_l = 0; 228 | bus_d_write = 1; 229 | bus_d_out = 8'd5; 230 | #600 bus_iow_l = 1; 231 | bus_aen = 1; 232 | bus_d_write = 0; 233 | #400 234 | bus_aen = 0; 235 | bus_ior_l = 0; 236 | bus_d_write = 0; 237 | #600 bus_ior_l = 1; 238 | bus_aen = 0; 239 | #350000 $finish; 240 | #10000 $finish; 241 | end 242 | endmodule 243 | 244 | -------------------------------------------------------------------------------- /verilog/mda.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module mda( 11 | // Clocks 12 | input clk, 13 | 14 | // ISA bus 15 | input[19:0] bus_a, 16 | input bus_ior_l, 17 | input bus_iow_l, 18 | input bus_memr_l, 19 | input bus_memw_l, 20 | input[7:0] bus_d, 21 | output[7:0] bus_out, 22 | output bus_dir, 23 | input bus_aen, 24 | 25 | // RAM 26 | output ram_we_l, 27 | output[18:0] ram_a, 28 | inout[7:0] ram_d, 29 | 30 | // Video outputs 31 | output hsync, 32 | output vsync, 33 | output video, 34 | output intensity, 35 | output display_enable_mda 36 | ); 37 | 38 | parameter MDA_70HZ = 1; 39 | parameter BLINK_MAX = 0; 40 | 41 | wire crtc_cs; 42 | wire status_cs; 43 | wire control_cs; 44 | wire bus_mem_cs; 45 | 46 | reg[7:0] bus_int_out; 47 | wire[7:0] bus_out_crtc; 48 | wire[7:0] bus_out_mem; 49 | wire[7:0] mda_status_reg; 50 | reg[7:0] mda_control_reg = 8'b0010_1000; 51 | wire video_enabled; 52 | wire blink_enabled; 53 | 54 | wire hsync_int; 55 | wire vsync_l; 56 | wire cursor; 57 | wire video; 58 | wire display_enable; 59 | wire intensity; 60 | 61 | wire[13:0] crtc_addr; 62 | wire[4:0] row_addr; 63 | 64 | wire charrom_read; 65 | wire disp_pipeline; 66 | wire isa_op_enable; 67 | wire vram_read_char; 68 | wire vram_read_att; 69 | wire vram_read; 70 | wire vram_read_a0; 71 | wire[4:0] clkdiv; 72 | wire crtc_clk; 73 | wire[7:0] ram_1_d; 74 | 75 | reg[23:0] blink_counter; 76 | reg blink; 77 | 78 | reg bus_memw_synced_l; 79 | reg bus_memr_synced_l; 80 | reg bus_ior_synced_l; 81 | reg bus_iow_synced_l; 82 | 83 | // Synchronize ISA bus control lines to our clock 84 | always @ (posedge clk) 85 | begin 86 | bus_memw_synced_l <= bus_memw_l; 87 | bus_memr_synced_l <= bus_memr_l; 88 | bus_ior_synced_l <= bus_ior_l; 89 | bus_iow_synced_l <= bus_iow_l; 90 | end 91 | 92 | // Some modules need a non-inverted vsync trigger 93 | assign vsync = ~vsync_l; 94 | 95 | // Mapped IO 96 | assign crtc_cs = (bus_a[19:3] == 17'b1110110 ) & ~bus_aen; // 3B4/3B5 97 | assign status_cs = (bus_a == 20'h3BA) & ~bus_aen; 98 | assign control_cs = (bus_a == 20'h3B8) & ~bus_aen; 99 | 100 | // Memory-mapped from B0000 to B7FFF 101 | assign bus_mem_cs = (bus_a[19:15] == 5'b10110); 102 | 103 | // Mux ISA bus data from every possible internal source. 104 | always @ (*) 105 | begin 106 | if (bus_mem_cs & ~bus_memr_l) begin 107 | bus_int_out <= bus_out_mem; 108 | end else if (status_cs & ~bus_ior_l) begin 109 | bus_int_out <= mda_status_reg; 110 | end else if (crtc_cs & ~bus_ior_l & (bus_a[0] == 1)) begin 111 | bus_int_out <= bus_out_crtc; 112 | end else begin 113 | bus_int_out <= 8'h00; 114 | end 115 | end 116 | 117 | // Only for read operations does bus_dir go high. 118 | assign bus_dir = ((crtc_cs | status_cs) & ~bus_ior_l) | 119 | (bus_mem_cs & ~bus_memr_l); 120 | assign bus_out = bus_int_out; 121 | 122 | 123 | // MDA status register (read only at 3BA) 124 | assign mda_status_reg = {4'b1111, video, 2'b00, hsync_int}; 125 | 126 | // MDA mode control register (write only) 127 | assign blink_enabled = mda_control_reg[5]; 128 | assign video_enabled = mda_control_reg[3]; 129 | 130 | // Hsync only present when video is enabled 131 | assign hsync = video_enabled & hsync_int; 132 | 133 | // Update control register 134 | always @ (posedge clk) 135 | begin 136 | if (control_cs & ~bus_iow_synced_l) begin 137 | mda_control_reg <= bus_d; 138 | end 139 | end 140 | 141 | // CRT controller (MC6845 compatible) 142 | crtc6845 crtc ( 143 | .clk(clk), 144 | .divclk(crtc_clk), 145 | .cs(crtc_cs), 146 | .a0(bus_a[0]), 147 | .write(~bus_iow_synced_l), 148 | .read(~bus_ior_synced_l), 149 | .bus(bus_d), 150 | .bus_out(bus_out_crtc), 151 | .lock(MDA_70HZ == 1), 152 | .hsync(hsync_int), 153 | .vsync(vsync_l), 154 | .display_enable(display_enable), 155 | .display_enable_mda(display_enable_mda), 156 | .cursor(cursor), 157 | .mem_addr(crtc_addr), 158 | .row_addr(row_addr) 159 | ); 160 | 161 | if (MDA_70HZ) begin 162 | defparam crtc.H_TOTAL = 8'd99; 163 | defparam crtc.H_DISP = 8'd80; 164 | defparam crtc.H_SYNCPOS = 8'd82; 165 | defparam crtc.H_SYNCWIDTH = 4'd12; 166 | defparam crtc.V_TOTAL = 7'd31; 167 | defparam crtc.V_TOTALADJ = 5'd1; 168 | defparam crtc.V_DISP = 7'd25; 169 | defparam crtc.V_SYNCPOS = 7'd27; 170 | defparam crtc.V_MAXSCAN = 5'd13; 171 | defparam crtc.C_START = 7'd11; 172 | defparam crtc.C_END = 5'd12; 173 | end else begin 174 | defparam crtc.H_TOTAL = 8'd97; 175 | defparam crtc.H_DISP = 8'd80; 176 | defparam crtc.H_SYNCPOS = 8'd82; 177 | defparam crtc.H_SYNCWIDTH = 4'd15; 178 | defparam crtc.V_TOTAL = 7'd25; 179 | defparam crtc.V_TOTALADJ = 5'd6; 180 | defparam crtc.V_DISP = 7'd25; 181 | defparam crtc.V_SYNCPOS = 7'd25; 182 | defparam crtc.V_MAXSCAN = 5'd13; 183 | defparam crtc.C_START = 7'd11; 184 | defparam crtc.C_END = 5'd12; 185 | end 186 | 187 | // Interface to video SRAM chip 188 | mda_vram video_buffer ( 189 | .clk(clk), 190 | .isa_addr({3'b000, bus_a[15:0]}), 191 | .isa_din(bus_d), 192 | .isa_dout(bus_out_mem), 193 | .isa_read(bus_mem_cs & ~bus_memr_synced_l), 194 | .isa_write(bus_mem_cs & ~bus_memw_synced_l), 195 | .pixel_addr({7'h00, crtc_addr[10:0], vram_read_a0}), 196 | .pixel_data(ram_1_d), 197 | .pixel_read(vram_read), 198 | .ram_a(ram_a), 199 | .ram_d(ram_d), 200 | .ram_we_l(ram_we_l), 201 | .isa_op_enable(isa_op_enable) 202 | ); 203 | 204 | defparam video_buffer.MDA_70HZ = MDA_70HZ; 205 | 206 | // Sequencer state machine 207 | mda_sequencer sequencer ( 208 | .clk(clk), 209 | .clk_seq(clkdiv), 210 | .vram_read(vram_read), 211 | .vram_read_a0(vram_read_a0), 212 | .vram_read_char(vram_read_char), 213 | .vram_read_att(vram_read_att), 214 | .crtc_clk(crtc_clk), 215 | .charrom_read(charrom_read), 216 | .disp_pipeline(disp_pipeline), 217 | .isa_op_enable(isa_op_enable) 218 | ); 219 | 220 | defparam sequencer.MDA_70HZ = MDA_70HZ; 221 | 222 | // Pixel pusher 223 | mda_pixel pixel ( 224 | .clk(clk), 225 | .clk_seq(clkdiv), 226 | .vram_data(ram_1_d), 227 | .vram_read_char(vram_read_char), 228 | .vram_read_att(vram_read_att), 229 | .disp_pipeline(disp_pipeline), 230 | .charrom_read(charrom_read), 231 | .display_enable(display_enable), 232 | .cursor(cursor), 233 | .row_addr(row_addr), 234 | .blink_enabled(blink_enabled), 235 | .blink(blink), 236 | .video_enabled(video_enabled), 237 | .video(video), 238 | .intensity(intensity) 239 | ); 240 | 241 | // Generate blink signal for cursor and character 242 | always @ (posedge clk) 243 | begin 244 | if (blink_counter == BLINK_MAX) begin 245 | blink_counter <= 0; 246 | blink <= ~blink; 247 | end else begin 248 | blink_counter <= blink_counter + 1; 249 | end 250 | end 251 | 252 | endmodule 253 | -------------------------------------------------------------------------------- /verilog/mda70_top.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module mda70_top( 11 | // Clocks 12 | input clk_10m, 13 | input clk_14m318, 14 | input clk_bus, 15 | 16 | // Bus reset 17 | input busreset, 18 | 19 | // ISA bus 20 | input[19:0] bus_a, 21 | input bus_ior_l, 22 | input bus_iow_l, 23 | input bus_memr_l, 24 | input bus_memw_l, 25 | inout[7:0] bus_d, 26 | output bus_dir, 27 | output bus_rdy, 28 | output bus_0ws_l, 29 | input bus_aen, 30 | input bus_ale, 31 | 32 | // RAM 33 | output ram_we_l, 34 | output[18:0] ram_a, 35 | inout[7:0] ram_d, 36 | 37 | // Video outputs 38 | // output hsync, 39 | // output vsync, 40 | // output vid_en_l, 41 | // output d_r, 42 | // output d_g, 43 | // output d_b, 44 | // output d_r2, 45 | // output d_g2, 46 | // output d_b2, 47 | 48 | output hdmi_red, 49 | output hdmi_grn, 50 | output hdmi_blu, 51 | output hdmi_int, 52 | output hdmi_grn_int, 53 | 54 | output hdmi_vs, 55 | output hdmi_hs, 56 | 57 | output hdmi_clk, 58 | 59 | output hdmi_de, 60 | 61 | output vga_hsync, 62 | output vga_vsync, 63 | output[5:0] red, 64 | output[6:0] green, 65 | output[5:0] blue, 66 | 67 | // Config switches 68 | input switch2, 69 | input switch3 70 | ); 71 | 72 | // Sets up the card to generate a video signal 73 | // that will work with a standard VGA monitor 74 | // connected to the VGA port. 75 | 76 | wire clk_main; 77 | wire pll_lock; 78 | 79 | wire[7:0] bus_out; 80 | 81 | wire video; 82 | wire intensity; 83 | wire display_enable; 84 | wire display_enable_mda; 85 | 86 | // Unused pins on video connector 87 | // assign bus_rdy = 1'b1; 88 | // assign bus_0ws_l = 1'b1; 89 | // assign vid_en_l = 1'b0; 90 | // assign d_r = 1'b0; 91 | // assign d_g = 1'b0; 92 | // assign d_b = 1'b0; 93 | // assign d_r2 = 1'b0; 94 | 95 | // assign d_g2 = intensity; 96 | // assign d_b2 = video; 97 | 98 | assign vga_hsync = hdmi_hs; 99 | assign vga_vsync = hdmi_vs; 100 | 101 | // Set up bus direction 102 | assign bus_d = (bus_dir) ? bus_out : 8'hzz; 103 | 104 | 105 | // Take our incoming 10MHz clock and generate the pixel clock 106 | // 56.875MHz: 0, 90, 4 107 | `ifdef SYNTHESIS 108 | SB_PLL40_PAD #( 109 | .FEEDBACK_PATH("SIMPLE"), 110 | .DIVR(0), 111 | .DIVF(90), 112 | .DIVQ(4), 113 | .FILTER_RANGE(1) 114 | ) mda_pll ( 115 | .LOCK(pll_lock), 116 | .RESETB(1'b1), 117 | .BYPASS(1'b0), 118 | .PACKAGEPIN(clk_10m), 119 | .PLLOUTGLOBAL(clk_main) 120 | ); 121 | `else 122 | assign clk_main = clk_10m; 123 | `endif 124 | 125 | mda_vgaport vga ( 126 | .clk(clk_main), 127 | .video(video), 128 | .intensity(intensity), 129 | .red(red), 130 | .green(green), 131 | .blue(blue) 132 | ); 133 | 134 | mda_hdmiport hdmi( 135 | .clk(clk_main), 136 | .video(video), 137 | .intensity(intensity), 138 | .display_enable(display_enable_mda), 139 | .switch2(switch2), 140 | .switch3(switch3), 141 | .hdmi_red(hdmi_red), 142 | .hdmi_grn(hdmi_grn), 143 | .hdmi_blu(hdmi_blu), 144 | .hdmi_int(hdmi_int), 145 | .hdmi_grn_int(hdmi_grn_int), 146 | .hdmi_clk(hdmi_clk), 147 | .hdmi_de(hdmi_de), 148 | ); 149 | 150 | mda mda1 ( 151 | .clk(clk_main), 152 | .bus_a(bus_a), 153 | .bus_ior_l(bus_ior_l), 154 | .bus_iow_l(bus_iow_l), 155 | .bus_memr_l(bus_memr_l), 156 | .bus_memw_l(bus_memw_l), 157 | .bus_d(bus_d), 158 | .bus_out(bus_out), 159 | .bus_dir(bus_dir), 160 | .bus_aen(bus_aen), 161 | .ram_we_l(ram_we_l), 162 | .ram_a(ram_a), 163 | .ram_d(ram_d), 164 | .hsync(hdmi_hs), 165 | .vsync(hdmi_vs), 166 | .intensity(intensity), 167 | .video(video), 168 | .display_enable_mda(display_enable_mda) 169 | 170 | ); 171 | 172 | defparam mda1.MDA_70HZ = 1; 173 | // Adjust blink rate 174 | defparam mda1.BLINK_MAX = 24'd9100000; 175 | 176 | endmodule 177 | -------------------------------------------------------------------------------- /verilog/mda_attrib.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module mda_attrib( 11 | input clk, 12 | input[7:0] att_byte, 13 | input[4:0] row_addr, 14 | input display_enable, 15 | input blink_enabled, 16 | input blink, 17 | input cursor, 18 | input pix_in, 19 | output pix_out, 20 | output intensity_out 21 | ); 22 | 23 | reg blinkdiv; 24 | reg[1:0] blink_old; 25 | wire att_inverse; 26 | wire att_underline; 27 | wire att_blink; 28 | wire att_nodisp; 29 | wire[2:0] att_fg; 30 | wire[2:0] att_bg; 31 | wire cursorblink; 32 | wire blink_area; 33 | wire vid_underline; 34 | wire intensity_bg; 35 | wire intensity_fg; 36 | wire alpha_dots; 37 | 38 | // Extract attributes from the attribute byte 39 | assign att_fg = att_byte[2:0]; 40 | assign att_bg = att_byte[6:4]; 41 | assign att_underline = (att_fg == 3'b001) & (row_addr==5'd12); 42 | assign intensity_bg = att_byte[7] & ~blink_enabled; 43 | assign intensity_fg = att_byte[3]; 44 | assign att_inverse = (att_fg == 3'b000) & (att_bg == 3'b111); 45 | assign att_nodisp = (att_fg == 3'b000) & (att_bg == 3'b000); 46 | assign att_blink = att_byte[7]; 47 | 48 | // Character blink is half the rate of the cursor blink 49 | always @ (posedge clk) 50 | begin 51 | blink_old <= {blink_old[0], blink}; 52 | if (blink_old == 2'b01) begin 53 | blinkdiv <= ~blinkdiv; 54 | end 55 | end 56 | 57 | // Assemble all the signals to create the final video signal 58 | assign cursorblink = cursor & blink; 59 | assign blink_area = att_blink & blinkdiv & ~cursor & blink_enabled; 60 | assign vid_underline = (pix_in | att_underline); 61 | assign alpha_dots = (vid_underline & ~att_nodisp & ~blink_area) | cursorblink; 62 | assign pix_out = (alpha_dots ^ att_inverse) & display_enable; 63 | 64 | // Assign intensity signal 65 | assign intensity_out = (alpha_dots ? intensity_fg : intensity_bg) & display_enable; 66 | 67 | 68 | endmodule 69 | 70 | -------------------------------------------------------------------------------- /verilog/mda_hdmiport.v: -------------------------------------------------------------------------------- 1 | module mda_hdmiport( 2 | input clk, 3 | input video, 4 | input intensity, 5 | 6 | input hsync, 7 | input vsync, 8 | input display_enable, 9 | 10 | input switch2, 11 | input switch3, 12 | 13 | output hdmi_red, 14 | output hdmi_grn, 15 | output hdmi_blu, 16 | output hdmi_int, 17 | output hdmi_grn_int, 18 | 19 | output hdmi_vs, 20 | output hdmi_hs, 21 | 22 | output hdmi_clk, 23 | 24 | output hdmi_de, 25 | 26 | ); 27 | 28 | reg[0:0] prev_de; 29 | reg[0:0] prev_de2; 30 | reg[0:0] current_hs; 31 | reg[0:0] current_vs; 32 | reg[0:0] current_red; 33 | reg[0:0] current_blue; 34 | reg[0:0] current_grn; 35 | reg[0:0] current_grn_int; 36 | reg[0:0] current_de; 37 | 38 | always @(posedge clk) 39 | begin 40 | //Cut clock in half to display as 720x350 instead of 1440x350 41 | hdmi_clk <= ~hdmi_clk; 42 | 43 | // Offset bug in image being shifted 2 pixels to the right. 44 | current_de <= prev_de; 45 | prev_de <= prev_de2; 46 | prev_de2 <= display_enable; 47 | 48 | current_vs <= vsync; 49 | current_hs <= hsync; 50 | 51 | // Use external switch 1 and 2 (internally mapped as switch 2 and 3) to select display colour 52 | /* 53 | switch2 switch3 colour r g b 54 | 0 0 green 0 1 0 55 | 0 1 yellow 1 1 0 56 | 1 0 white 1 1 1 57 | 1 1 red 1 0 0 58 | */ 59 | 60 | current_red <= video && (switch2 || switch3); 61 | current_grn <= video && ~(switch2 && switch3); 62 | current_blu <= video && (switch2 && ~(switch2 && switch3)); 63 | 64 | current_int <= intensity; 65 | current_grn_int <= intensity; 66 | 67 | end 68 | 69 | assign hdmi_de = current_de; 70 | 71 | assign hdmi_vs = current_vs; 72 | assign hdmi_hs = current_hs; 73 | 74 | assign hdmi_red = current_red; 75 | assign hdmi_blu = current_blu; 76 | assign hdmi_int = current_int; 77 | 78 | assign hdmi_grn = current_grn; 79 | assign hdmi_grn_int = current_grn_int; 80 | 81 | endmodule -------------------------------------------------------------------------------- /verilog/mda_pixel.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module mda_pixel( 11 | input clk, 12 | input[4:0] clk_seq, 13 | input[7:0] vram_data, 14 | input vram_read_char, 15 | input vram_read_att, 16 | input disp_pipeline, 17 | input charrom_read, 18 | input display_enable, 19 | input cursor, 20 | input[4:0] row_addr, 21 | input blink_enabled, 22 | input blink, 23 | input video_enabled, 24 | output video, 25 | output intensity 26 | ); 27 | 28 | reg[7:0] attr_byte; 29 | reg[7:0] char_byte; 30 | reg[7:0] char_byte_old; 31 | reg[7:0] attr_byte_del; 32 | reg[7:0] charbits; 33 | reg[1:0] cursor_del; 34 | reg[1:0] display_enable_del; 35 | reg pix; 36 | reg pix_delay; 37 | reg ninth_column; 38 | wire[11:0] rom_addr; 39 | 40 | // Character ROM 41 | reg[7:0] char_rom[0:4095]; 42 | initial $readmemh("mda.hex", char_rom, 0, 4095); 43 | 44 | 45 | // Latch character and attribute data from VRAM 46 | // at appropriate times 47 | always @ (posedge clk) 48 | begin 49 | if (vram_read_char) begin 50 | char_byte <= vram_data; //ES testing 51 | char_byte_old <= char_byte; 52 | end 53 | if (vram_read_att) begin 54 | attr_byte <= vram_data; //ES testing 55 | end 56 | end 57 | 58 | // Add a pipeline delay to the attribute byte data, cursor, and display 59 | // enable so they line up with the displayed character 60 | always @ (posedge clk) 61 | begin 62 | if (disp_pipeline) begin 63 | attr_byte_del <= video_enabled ? attr_byte : 8'd0; 64 | display_enable_del <= {display_enable_del[0], display_enable}; 65 | cursor_del <= {cursor_del[0], cursor}; 66 | end 67 | end 68 | 69 | // Look up character byte in our character ROM table 70 | assign rom_addr = {row_addr[3], char_byte, row_addr[2:0]}; 71 | always @ (posedge clk) 72 | begin 73 | // Only load character bits at this point 74 | if (charrom_read) begin 75 | charbits <= char_rom[rom_addr]; 76 | end 77 | end 78 | 79 | // Pixel shifter 80 | always @ (*) 81 | begin 82 | case (clk_seq[4:1]) 83 | 5'd0: pix <= charbits[0]; 84 | 5'd1: pix <= ninth_column; 85 | 5'd2: pix <= charbits[7]; 86 | 5'd3: pix <= charbits[6]; 87 | 5'd4: pix <= charbits[5]; 88 | 5'd5: pix <= charbits[4]; 89 | 5'd6: pix <= charbits[3]; 90 | 5'd7: pix <= charbits[2]; 91 | 5'd8: pix <= charbits[1]; 92 | default: pix <= 0; 93 | endcase 94 | end 95 | 96 | // For some characters, duplicate the 8th column as the 9th column 97 | // (Mainly line drawing characters so they span the whole cell) 98 | always @ (posedge clk) 99 | begin 100 | if (charrom_read) begin 101 | ninth_column <= (char_byte_old[7:5] == 3'b110) ? charbits[0] : 0; 102 | end 103 | end 104 | 105 | // Add one clk cycle delay to match up pixel data with attribute byte 106 | // data. 107 | always @ (posedge clk) 108 | begin 109 | pix_delay <= pix; 110 | end 111 | 112 | // Applies video attributes, generates final video 113 | mda_attrib attrib ( 114 | .clk(clk), 115 | .att_byte(attr_byte_del), 116 | .row_addr(row_addr), 117 | .display_enable(display_enable_del[1]), 118 | .blink_enabled(blink_enabled), 119 | .blink(blink), 120 | .cursor(cursor_del[1]), 121 | .pix_in(pix_delay), 122 | .pix_out(video), 123 | .intensity_out(intensity) 124 | ); 125 | 126 | endmodule 127 | -------------------------------------------------------------------------------- /verilog/mda_sequencer.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module mda_sequencer( 11 | input clk, 12 | output[4:0] clk_seq, 13 | output vram_read, 14 | output vram_read_a0, 15 | output vram_read_char, 16 | output vram_read_att, 17 | output crtc_clk, 18 | output charrom_read, 19 | output disp_pipeline, 20 | output isa_op_enable 21 | ); 22 | 23 | parameter MDA_70HZ = 0; 24 | 25 | reg crtc_clk_int = 1'b0; 26 | reg[4:0] clkdiv = 5'b0; 27 | 28 | // Sequencer: times internal operations 29 | always @ (posedge clk) 30 | begin 31 | if (clkdiv == 5'd17) begin 32 | clkdiv <= 5'd0; 33 | crtc_clk_int <= 1'b1; 34 | end else begin 35 | clkdiv <= clkdiv + 1; 36 | crtc_clk_int <= 1'b0; 37 | end 38 | end 39 | 40 | // Control signals based on the sequencer state 41 | assign vram_read = ((clkdiv == 5'd1) || (clkdiv == 5'd2) || (clkdiv == 5'd3) 42 | || (clkdiv == 5'd4)); 43 | assign vram_read_a0 = (clkdiv == 5'd3); 44 | assign vram_read_char = (clkdiv == 5'd3); 45 | assign vram_read_att = (clkdiv == 5'd4); 46 | assign charrom_read = (clkdiv == 5'd1); 47 | assign disp_pipeline = (clkdiv == 5'd4); 48 | assign crtc_clk = crtc_clk_int; 49 | assign clk_seq = clkdiv; 50 | // Leave a gap of at least 2 cycles between the end of ISA operation and 51 | // vram_read. This is because an ISA operation takes 3 cycles. 52 | // Stupid hack: 70Hz needs an extra cycle. 50Hz can't tolerate 53 | // an extra cycle. 54 | if (MDA_70HZ) begin 55 | assign isa_op_enable = (clkdiv > 5'd6) && (clkdiv < 5'd16); 56 | end else begin 57 | assign isa_op_enable = (clkdiv > 5'd5) && (clkdiv < 5'd16); 58 | end 59 | 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /verilog/mda_top.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | `default_nettype none 10 | module mda_top( 11 | // Clocks 12 | input clk_10m, 13 | input clk_14m318, 14 | input clk_bus, 15 | 16 | // Bus reset 17 | input busreset, 18 | 19 | // ISA bus 20 | input[19:0] bus_a, 21 | input bus_ior_l, 22 | input bus_iow_l, 23 | input bus_memr_l, 24 | input bus_memw_l, 25 | inout[7:0] bus_d, 26 | output bus_dir, 27 | output bus_rdy, 28 | output bus_0ws_l, 29 | input bus_aen, 30 | input bus_ale, 31 | 32 | // RAM 33 | output ram_we_l, 34 | output[18:0] ram_a, 35 | inout[7:0] ram_d, 36 | 37 | // Video outputs 38 | output hsync, 39 | output vsync, 40 | output vid_en_l, 41 | output d_r, 42 | output d_g, 43 | output d_b, 44 | output d_r2, 45 | output d_g2, 46 | output d_b2, 47 | output vga_hsync, 48 | output vga_vsync, 49 | output[5:0] red, 50 | output[6:0] green, 51 | output[5:0] blue, 52 | 53 | // Config switches 54 | input switch2, 55 | input switch3 56 | ); 57 | 58 | wire clk_main; 59 | wire pll_lock; 60 | 61 | wire[7:0] bus_out; 62 | 63 | wire video; 64 | wire intensity; 65 | 66 | // Unused pins on video connector 67 | assign bus_rdy = 1'b1; 68 | assign bus_0ws_l = 1'b1; 69 | assign vid_en_l = 1'b0; 70 | assign d_r = 1'b0; 71 | assign d_g = 1'b0; 72 | assign d_b = 1'b0; 73 | assign d_r2 = 1'b0; 74 | 75 | assign d_g2 = intensity; 76 | assign d_b2 = video; 77 | 78 | assign vga_hsync = hsync; 79 | assign vga_vsync = vsync; 80 | 81 | // Set up bus direction 82 | assign bus_d = (bus_dir) ? bus_out : 8'hzz; 83 | 84 | 85 | // Take our incoming 10MHz clock and generate the pixel clock 86 | // 33MHz: 0, 105, 5 87 | `ifdef SYNTHESIS 88 | SB_PLL40_PAD #( 89 | .FEEDBACK_PATH("SIMPLE"), 90 | .DIVR(0), 91 | .DIVF(105), 92 | .DIVQ(5), 93 | .FILTER_RANGE(1) 94 | ) mda_pll ( 95 | .LOCK(pll_lock), 96 | .RESETB(1'b1), 97 | .BYPASS(1'b0), 98 | .PACKAGEPIN(clk_10m), 99 | .PLLOUTGLOBAL(clk_main) 100 | ); 101 | `else 102 | assign clk_main = clk_10m; 103 | `endif 104 | 105 | mda_vgaport vga ( 106 | .clk(clk_main), 107 | .video(video), 108 | .intensity(intensity), 109 | .red(red), 110 | .green(green), 111 | .blue(blue) 112 | ); 113 | 114 | mda mda1 ( 115 | .clk(clk_main), 116 | .bus_a(bus_a), 117 | .bus_ior_l(bus_ior_l), 118 | .bus_iow_l(bus_iow_l), 119 | .bus_memr_l(bus_memr_l), 120 | .bus_memw_l(bus_memw_l), 121 | .bus_d(bus_d), 122 | .bus_out(bus_out), 123 | .bus_dir(bus_dir), 124 | .bus_aen(bus_aen), 125 | .ram_we_l(ram_we_l), 126 | .ram_a(ram_a), 127 | .ram_d(ram_d), 128 | .hsync(hsync), 129 | .vsync(vsync), 130 | .intensity(intensity), 131 | .video(video) 132 | ); 133 | 134 | defparam mda1.MDA_70HZ = 0; 135 | defparam mda1.BLINK_MAX = 24'd5280000; 136 | 137 | endmodule 138 | -------------------------------------------------------------------------------- /verilog/mda_vgaport.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | module mda_vgaport( 10 | input clk, 11 | 12 | input video, 13 | input intensity, 14 | 15 | // Analog outputs 16 | output[5:0] red, 17 | output[6:0] green, 18 | output[5:0] blue 19 | ); 20 | 21 | reg[5:0] r; 22 | reg[5:0] g; 23 | 24 | assign red = r; 25 | assign green = {g, 1'b0}; 26 | assign blue = 6'd0; 27 | 28 | always @(posedge clk) 29 | begin 30 | case({video, intensity}) 31 | 2'd0: begin 32 | r <= 6'd0; 33 | g <= 6'd0; 34 | end 35 | 2'd1: begin 36 | r <= 6'd16; 37 | g <= 6'd12; 38 | end 39 | 2'd2: begin 40 | r <= 6'd48; 41 | g <= 6'd21; 42 | end 43 | 2'd3: begin 44 | r <= 6'd63; 45 | g <= 6'd27; 46 | end 47 | default: ; 48 | endcase 49 | end 50 | endmodule 51 | -------------------------------------------------------------------------------- /verilog/mda_vram.v: -------------------------------------------------------------------------------- 1 | // Graphics Gremlin 2 | // 3 | // Copyright (c) 2021 Eric Schlaepfer 4 | // This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 5 | // International License. To view a copy of this license, visit 6 | // http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to Creative 7 | // Commons, PO Box 1866, Mountain View, CA 94042, USA. 8 | // 9 | module mda_vram( 10 | // Clock 11 | input clk, 12 | 13 | // Lines from other logic 14 | // Port 0 is read/write 15 | input[18:0] isa_addr, 16 | input[7:0] isa_din, 17 | output[7:0] isa_dout, 18 | input isa_read, 19 | input isa_write, 20 | input isa_op_enable, 21 | 22 | // Port 1 is read only 23 | input[18:0] pixel_addr, 24 | output[7:0] pixel_data, 25 | input pixel_read, 26 | 27 | // Lines to RAM pins 28 | output reg[18:0] ram_a, 29 | inout[7:0] ram_d, 30 | output ram_ce_l, 31 | output ram_oe_l, 32 | output ram_we_l 33 | ); 34 | 35 | parameter MDA_70HZ = 1; 36 | 37 | wire ram_write; 38 | reg[2:0] isa_phase = 3'd0; 39 | reg isa_write_old = 0; 40 | reg isa_read_old = 0; 41 | reg[19:0] op_addr = 20'd0; 42 | reg[7:0] op_data = 8'd0; 43 | reg op_write_queued = 0; 44 | reg op_read_queued = 0; 45 | reg[7:0] read_data_isa = 8'h0; 46 | reg[7:0] read_data_pixel = 8'h0; 47 | reg[7:0] ram_data_out = 8'h00; 48 | reg[2:0] write_del = 0; 49 | 50 | assign ram_ce_l = 0; 51 | assign ram_oe_l = 0; 52 | 53 | assign ram_write = (isa_phase == 3'd2) || (isa_phase == 3'd4); 54 | assign ram_we_l = ~(ram_write & ~pixel_read); 55 | assign isa_dout = read_data_isa; 56 | assign pixel_data = read_data_pixel; 57 | 58 | // Gated by clock so that we give the SRAM chip 59 | // some time to tristate its data output after 60 | // we begin the write operation. (tHZWE) 61 | assign ram_d = (~ram_we_l & (~clk | (isa_phase == 3'd4))) ? ram_data_out : 8'hZZ; 62 | 63 | // RAM address pin mux 64 | always @ (*) 65 | begin 66 | if (pixel_read) begin 67 | ram_a <= pixel_addr; 68 | end else if ((isa_phase == 3'd2) || (isa_phase == 3'd4)) begin 69 | ram_a <= op_addr; 70 | end else if (isa_read && isa_op_enable) begin 71 | ram_a <= isa_addr; 72 | end else begin 73 | ram_a <= 19'h0; 74 | end 75 | end 76 | 77 | // For edge detector 78 | always @ (posedge clk) 79 | begin 80 | isa_write_old <= isa_write; 81 | isa_read_old <= isa_read; 82 | end 83 | 84 | // Address is latched on initial edge of read or write signal 85 | always @ (posedge clk) 86 | begin 87 | if ((isa_write && ~isa_write_old) || (isa_read && ~isa_read_old)) begin 88 | op_addr <= isa_addr; 89 | end 90 | end 91 | 92 | // Wait a few cycles before latching data from ISA 93 | // bus, since the data isn't valid right away. 94 | always @ (posedge clk) 95 | begin 96 | if (isa_write && !isa_write_old) begin 97 | write_del <= 3'd1; 98 | end else if (write_del != 3'd0) begin 99 | if (write_del == 3'd7) begin 100 | write_del <= 3'd0; 101 | end else begin 102 | write_del <= write_del + 1; 103 | end 104 | end 105 | end 106 | 107 | // Write data (from host PC) is latched on final edge of write signal 108 | // We cheat and latch it after the initial edge plus a delay 109 | always @ (posedge clk) 110 | begin 111 | if (write_del == 3'd2) begin 112 | op_data <= isa_din; 113 | op_write_queued <= 1; 114 | end else if ((isa_phase == 3'd4)) begin 115 | op_write_queued <= 0; 116 | end 117 | end 118 | 119 | // Read operation triggered on initial edge of read signal 120 | always @ (posedge clk) 121 | begin 122 | if (isa_read && !isa_read_old) begin 123 | op_read_queued <= 1; 124 | end else if ((isa_phase == 3'd5)) begin 125 | op_read_queued <= 0; 126 | end 127 | end 128 | 129 | // ISA bus access state machine 130 | // State 0: idle, waiting for read or write to trip. 131 | // reads data for slower clocks 132 | // State 1: read addr phase (only for faster clocks) 133 | // State 2: write addr phase 134 | // State 4: write completion phase 135 | // State 5: read completion phase 136 | 137 | always @ (posedge clk) 138 | begin 139 | if (!isa_op_enable) begin 140 | isa_phase <= 3'd0; 141 | end else begin 142 | case (isa_phase) 143 | 3'd0: begin 144 | // Read signal is active, so start read phase 145 | if (op_read_queued) begin 146 | if (MDA_70HZ == 1) begin 147 | // At faster PLL clock, delay SRAM 148 | // read by 1 cycle to allow for more 149 | // address setup time. 150 | isa_phase <= 3'd1; 151 | end else begin 152 | // At slower PLL clock, shorten SRAM 153 | // read cycle so we don't run out 154 | // of ISA bus cycle time. 155 | read_data_isa <= ram_d; 156 | isa_phase <= 3'd5; // was 1 157 | end 158 | // A write is queued, so start write phase 159 | end else if (op_write_queued) begin 160 | isa_phase <= 3'd2; 161 | ram_data_out <= op_data; 162 | end 163 | end 164 | 3'd1: begin // Extra read cycle for fast PLL clocks 165 | read_data_isa <= ram_d; 166 | isa_phase <= 3'd5; 167 | end 168 | 3'd2: begin // Write phase 169 | isa_phase <= 3'd4; 170 | end 171 | 3'd4: isa_phase <= 3'd0; 172 | 3'd5: isa_phase <= 3'd0; 173 | default: isa_phase <= 3'd0; 174 | endcase 175 | end 176 | end 177 | 178 | // Pixel read port is much simpler. 179 | always @ (posedge clk) 180 | begin 181 | if (pixel_read) begin 182 | read_data_pixel <= ram_d; 183 | end 184 | end 185 | 186 | endmodule 187 | -------------------------------------------------------------------------------- /verilog/release/isavideo-20240505-nosnow.binm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/verilog/release/isavideo-20240505-nosnow.binm -------------------------------------------------------------------------------- /verilog/release/isavideo-20241229-withsnow.binm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/verilog/release/isavideo-20241229-withsnow.binm -------------------------------------------------------------------------------- /vga_display_status/.gitignore: -------------------------------------------------------------------------------- 1 | /vga_display_status.sim 2 | /vga_display_status.cache 3 | /vga_display_status.hw 4 | /vga_display_status.ioplanning 5 | /vga_display_status.ip_user_files 6 | /vga_display_status.runs 7 | -------------------------------------------------------------------------------- /vga_display_status/vga_display_status.srcs/constrs_1/new/constraints.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 2 | set_property PACKAGE_PIN H4 [get_ports clk] 3 | 4 | 5 | set_property IOSTANDARD TMDS_33 [get_ports {TMDSp[2]}] 6 | set_property IOSTANDARD TMDS_33 [get_ports {TMDSp[1]}] 7 | set_property IOSTANDARD TMDS_33 [get_ports {TMDSp[0]}] 8 | set_property IOSTANDARD TMDS_33 [get_ports TMDSp_clock] 9 | set_property IOSTANDARD TMDS_33 [get_ports {TMDSn[2]}] 10 | set_property IOSTANDARD TMDS_33 [get_ports {TMDSn[1]}] 11 | set_property IOSTANDARD TMDS_33 [get_ports {TMDSn[0]}] 12 | set_property IOSTANDARD TMDS_33 [get_ports TMDSn_clock] 13 | 14 | set_property PACKAGE_PIN L3 [get_ports TMDSp_clock] 15 | set_property PACKAGE_PIN K3 [get_ports TMDSn_clock] 16 | set_property PACKAGE_PIN B1 [get_ports {TMDSp[0]}] 17 | set_property PACKAGE_PIN A1 [get_ports {TMDSn[0]}] 18 | set_property PACKAGE_PIN E1 [get_ports {TMDSp[1]}] 19 | set_property PACKAGE_PIN D1 [get_ports {TMDSn[1]}] 20 | set_property PACKAGE_PIN G1 [get_ports {TMDSp[2]}] 21 | set_property PACKAGE_PIN F1 [get_ports {TMDSn[2]}] 22 | 23 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_red] 24 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_grn] 25 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_blu] 26 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_int] 27 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_vs] 28 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_hs] 29 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_clk] 30 | set_property IOSTANDARD LVCMOS33 [get_ports hdmi_de] 31 | 32 | 33 | set_property PACKAGE_PIN B20 [get_ports {hdmi_red}] 34 | set_property PACKAGE_PIN E19 [get_ports {hdmi_grn}] 35 | set_property PACKAGE_PIN D20 [get_ports {hdmi_blu}] 36 | set_property PACKAGE_PIN C18 [get_ports {hdmi_int}] 37 | set_property PACKAGE_PIN C22 [get_ports {hdmi_vs}] 38 | set_property PACKAGE_PIN F18 [get_ports {hdmi_hs}] 39 | set_property PACKAGE_PIN D17 [get_ports {hdmi_clk}] 40 | set_property PACKAGE_PIN F19 [get_ports {hdmi_de}] 41 | 42 | 43 | 44 | #create_clock -period 8.000 -name clk_in -waveform {0.000 4.000} [get_ports clk] 45 | -------------------------------------------------------------------------------- /vga_display_status/vga_display_status.srcs/sources_1/new/TMDS_encoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // (c) fpga4fun.com & KNJN LLC 2013 3 | 4 | //////////////////////////////////////////////////////////////////////// 5 | module TMDS_encoder( 6 | input clk, 7 | input [7:0] VD, // video data (red, green or blue) 8 | input [1:0] CD, // control data 9 | input VDE, // video data enable, to choose between CD (when VDE=0) and VD (when VDE=1) 10 | output reg [9:0] TMDS = 0 11 | ); 12 | 13 | wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7]; 14 | wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0); 15 | wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]}; 16 | 17 | reg [3:0] balance_acc = 0; 18 | wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4; 19 | wire balance_sign_eq = (balance[3] == balance_acc[3]); 20 | wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq; 21 | wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0)); 22 | wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc; 23 | wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}}; 24 | wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100); 25 | 26 | always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code; 27 | always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0; 28 | endmodule 29 | 30 | 31 | //////////////////////////////////////////////////////////////////////// -------------------------------------------------------------------------------- /vga_display_status/vga_display_status.srcs/sources_1/new/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 01.09.2023 10:54:51 7 | // Design Name: 8 | // Module Name: top 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module top( 24 | input clk, 25 | 26 | input hdmi_red, 27 | input hdmi_grn, 28 | input hdmi_blu, 29 | input hdmi_int, 30 | input hdmi_vs, 31 | input hdmi_hs, 32 | input hdmi_clk, 33 | input hdmi_de, 34 | 35 | output [2:0] TMDSp, TMDSn, 36 | output TMDSp_clock, TMDSn_clock 37 | ); 38 | 39 | 40 | 41 | HDMI_test(clk, hdmi_red, hdmi_grn, hdmi_blu, hdmi_int, hdmi_vs, hdmi_hs, hdmi_clk, hdmi_de, TMDSp, TMDSn, TMDSp_clock, TMDSn_clock); 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /vga_display_status/vga_display_status.srcs/utils_1/imports/synth_1/top.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yeokm1/graphics-gremlin-hdmi/034639d2a979d8896c8f2dc1cc4d00fbbf65c267/vga_display_status/vga_display_status.srcs/utils_1/imports/synth_1/top.dcp --------------------------------------------------------------------------------