├── .gitattributes ├── LICENSE ├── README.md ├── docs ├── 1GbSDRAM.png ├── ReadOperation.png ├── SDRAMCommands.png ├── SDRAMRTLBlockDiagram.png ├── WriteOperation.png ├── behavsim.png └── tcl.png └── rtl ├── sdram_controller.v ├── sdram_model.v └── sdram_top.v /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/.gitattributes -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/LICENSE -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/README.md -------------------------------------------------------------------------------- /docs/1GbSDRAM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/1GbSDRAM.png -------------------------------------------------------------------------------- /docs/ReadOperation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/ReadOperation.png -------------------------------------------------------------------------------- /docs/SDRAMCommands.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/SDRAMCommands.png -------------------------------------------------------------------------------- /docs/SDRAMRTLBlockDiagram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/SDRAMRTLBlockDiagram.png -------------------------------------------------------------------------------- /docs/WriteOperation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/WriteOperation.png -------------------------------------------------------------------------------- /docs/behavsim.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/behavsim.png -------------------------------------------------------------------------------- /docs/tcl.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/docs/tcl.png -------------------------------------------------------------------------------- /rtl/sdram_controller.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/rtl/sdram_controller.v -------------------------------------------------------------------------------- /rtl/sdram_model.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/rtl/sdram_model.v -------------------------------------------------------------------------------- /rtl/sdram_top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yigitbektasgursoy/SDRAM_Verilog/HEAD/rtl/sdram_top.v --------------------------------------------------------------------------------