├── .github ├── dependabot.yml └── workflows │ └── rust.yml ├── .gitignore ├── Cargo.toml ├── LICENSE ├── README.md ├── TODO.md ├── examples ├── decode.rs ├── exhaustive.rs ├── pattern-match.rs ├── rand.rs └── shitty-objdump.rs ├── res └── id ├── src ├── arrspec.rs ├── condition.rs ├── flageffect.rs ├── lib.rs ├── op.rs ├── operand.rs ├── reg.rs ├── shift.rs └── sysreg.rs └── tests ├── dis.rs ├── test_cases.txt └── testcases.rs /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | # To get started with Dependabot version updates, you'll need to specify which 2 | # package ecosystems to update and where the package manifests are located. 3 | # Please see the documentation for all configuration options: 4 | # https://help.github.com/github/administering-a-repository/configuration-options-for-dependency-updates 5 | 6 | version: 2 7 | updates: 8 | - package-ecosystem: "cargo" # See documentation for possible values 9 | directory: "/" # Location of package manifests 10 | schedule: 11 | interval: "daily" 12 | -------------------------------------------------------------------------------- /.github/workflows/rust.yml: -------------------------------------------------------------------------------- 1 | name: test 2 | on: [push, pull_request] 3 | 4 | env: 5 | CARGO_TERM_COLOR: always 6 | 7 | jobs: 8 | test: 9 | name: cargo test 10 | runs-on: ubuntu-latest 11 | steps: 12 | - uses: actions/checkout@v4 13 | - uses: dtolnay/rust-toolchain@stable 14 | - run: cargo test --verbose -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /target 2 | Cargo.lock 3 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "bad64" 3 | version = "0.10.0" 4 | authors = ["yrp "] 5 | edition = "2024" 6 | description = "Rust bindings for Binja's arm64 disassembler" 7 | license = "Apache-2.0" 8 | repository = "https://github.com/yrp604/bad64" 9 | categories = ["api-bindings", "encoding", "no-std"] 10 | keywords = ["disassembler", "armv8", "arm64", "aarch64", "binja"] 11 | 12 | 13 | [dependencies] 14 | bad64-sys = "0.8" 15 | cstr_core = "0.2" 16 | num-traits = "0.2" 17 | num-derive = "0.4" 18 | static_assertions = "1" 19 | 20 | [dev-dependencies] 21 | rand = "0.9" 22 | xmas-elf = "0.10" 23 | 24 | [features] 25 | std = [] 26 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Binja Arm64 Disassembler 2 | 3 | [![Build Status]][actions] [![Latest Version]][crates.io] [![Latest Docs]][docs.rs] 4 | 5 | [Build Status]: https://img.shields.io/github/actions/workflow/status/yrp604/bad64/rust.yml?branch=main 6 | [actions]: https://github.com/yrp604/bad64/actions?query=branch%3Amain 7 | [Latest Version]: https://img.shields.io/crates/v/bad64.svg 8 | [crates.io]: https://crates.io/crates/bad64 9 | [Latest Docs]: https://docs.rs/bad64/badge.svg 10 | [docs.rs]: https://docs.rs/bad64 11 | 12 | These are bindings to the [Binary Ninja](https://binary.ninja) arm64 13 | [architecture/disassembler plugin]([https://github.com/Vector35/arch-arm64](https://github.com/Vector35/binaryninja-api/tree/dev/arch/arm64)). 14 | 15 | Note that while Binary Ninja is an (excellent) commercial product, the 16 | disassembler is entirely Apache 2 licensed and may be used without a license. 17 | To install, just add bad64 as a normal dependency in Cargo.toml. 18 | 19 | For more information on how this disassembler was created, see [this blogpost][blogpost] 20 | by [Andrew Lamoureux][andrew]. 21 | 22 | [blogpost]: https://binary.ninja/2021/04/05/groundup-aarch64.html 23 | [andrew]: https://github.com/lwerdna 24 | 25 | For docs and usage, please see [docs.rs](http://docs.rs/bad64) and the 26 | [examples](examples). 27 | 28 | ``` 29 | $ cargo run --example decode 0x91010420 30 | Instruction { 31 | address: 0x1000, 32 | opcode: 0x91010420, 33 | op: ADD, 34 | num_operands: 0x3, 35 | operands: [ 36 | Reg { 37 | reg: X0, 38 | arrspec: None, 39 | }, 40 | Reg { 41 | reg: X1, 42 | arrspec: None, 43 | }, 44 | Imm64 { 45 | imm: Unsigned( 46 | 0x41, 47 | ), 48 | shift: None, 49 | }, 50 | ], 51 | flags_set: None, 52 | } 53 | add x0, x1, #0x41 54 | ``` 55 | -------------------------------------------------------------------------------- /TODO.md: -------------------------------------------------------------------------------- 1 | # TODO 2 | - [x] Make `no_std` compat 3 | - [-] Benchmarks 4 | - [x] Tests 5 | - [x] Docs 6 | - [ ] Figure out uarch system register support 7 | - [x] Arrspec 8 | - [x] Formatter -------------------------------------------------------------------------------- /examples/decode.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::process; 3 | 4 | fn main() { 5 | let args: Vec = env::args().collect(); 6 | 7 | if args.len() < 2 { 8 | eprintln!("Usage: {} ", args[0]); 9 | process::exit(1); 10 | } 11 | 12 | let op = u32::from_str_radix(args[1].trim_start_matches("0x"), 16) 13 | .expect(&format!("Could not parse {} as hex u32", args[1])); 14 | 15 | let base = match args.get(2) { 16 | Some(arg) => u64::from_str_radix(arg.trim_start_matches("0x"), 16) 17 | .expect(&format!("Could not parse {} as hex u64", arg)), 18 | None => 0x1000, 19 | }; 20 | 21 | let decoded = bad64::decode(op, base).expect(&format!("Could not decode {:#x}", op)); 22 | 23 | println!("{:#x?}", decoded); 24 | println!("{}", decoded); 25 | } 26 | -------------------------------------------------------------------------------- /examples/exhaustive.rs: -------------------------------------------------------------------------------- 1 | fn main() { 2 | let start = std::time::Instant::now(); 3 | let mut decoded = 0; 4 | 5 | for int in 0..=u32::MAX { 6 | let inst = bad64::decode(int, 0); 7 | 8 | if inst.is_ok() { 9 | decoded += 1; 10 | } 11 | 12 | if (int > 0) && (int & 0x07ff_ffff == 0) { 13 | let time = start.elapsed(); 14 | let p = (int as f64) / (u32::MAX as f64) * 100.0; 15 | let rate = (int as f64) / u64::max(1, time.as_secs()) as f64; 16 | println!( 17 | "checked {} words ({:.1}%) in {:.1?} ({:.0} words/sec)", 18 | int, p, time, rate 19 | ); 20 | } 21 | } 22 | 23 | let time = start.elapsed(); 24 | println!("decoded {} valid instructions in {:.1?}", decoded, time); 25 | } 26 | -------------------------------------------------------------------------------- /examples/pattern-match.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs; 3 | use std::process; 4 | 5 | use xmas_elf::ElfFile; 6 | 7 | use bad64::{disasm, Op, Operand, Reg}; 8 | 9 | fn main() { 10 | let argv: Vec = env::args().collect(); 11 | if argv.len() != 2 { 12 | eprintln!("Usage: {} ", argv[0]); 13 | process::exit(1); 14 | } 15 | 16 | let buf = fs::read(&argv[1]).unwrap(); 17 | 18 | let elf = ElfFile::new(&buf).unwrap(); 19 | 20 | let text_section = elf.find_section_by_name(".text").unwrap(); 21 | 22 | let base = text_section.address(); 23 | let size = text_section.size(); 24 | let bytes = text_section.raw_data(&elf); 25 | 26 | println!("disassembling {} bytes from .text @ {:#x}", size, base); 27 | 28 | // pattern match on operands 29 | for decoded in disasm(bytes, base).filter_map(Result::ok) { 30 | let ops = decoded.operands(); 31 | 32 | match ops { 33 | &[Operand::Reg { reg: Reg::XZR, .. }, ..] => println!( 34 | "64bit zero reg as first operand @ {:x} in {}", 35 | decoded.address(), 36 | decoded.op() 37 | ), 38 | _ => (), 39 | } 40 | } 41 | 42 | // pattern match on operation and operand 43 | for decoded in disasm(bytes, base).filter_map(Result::ok) { 44 | let op = decoded.op(); 45 | let ops = decoded.operands(); 46 | 47 | match (op, ops) { 48 | (Op::CMP, &[Operand::Reg { reg: Reg::XZR, .. }, ..]) 49 | | (Op::CMP, &[Operand::ShiftReg { reg: Reg::XZR, .. }, ..]) => println!( 50 | "64bit zero reg as first operand @ {:x} in {}", 51 | decoded.address(), 52 | decoded.op() 53 | ), 54 | _ => (), 55 | } 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /examples/rand.rs: -------------------------------------------------------------------------------- 1 | use rand::Rng; 2 | 3 | fn main() { 4 | loop { 5 | if let Ok(decoded) = bad64::decode(rand::rng().random::(), rand::rng().random::()) { 6 | println!("{:x}: {}", decoded.opcode(), decoded); 7 | } 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /examples/shitty-objdump.rs: -------------------------------------------------------------------------------- 1 | use std::env; 2 | use std::fs; 3 | use std::process; 4 | 5 | use xmas_elf::ElfFile; 6 | 7 | fn main() { 8 | let argv: Vec = env::args().collect(); 9 | if argv.len() != 2 { 10 | eprintln!("Usage: {} ", argv[0]); 11 | process::exit(1); 12 | } 13 | 14 | let buf = fs::read(&argv[1]).unwrap(); 15 | 16 | let elf = ElfFile::new(&buf).unwrap(); 17 | 18 | let text_section = elf.find_section_by_name(".text").unwrap(); 19 | 20 | let base = text_section.address(); 21 | let size = text_section.size(); 22 | let bytes = text_section.raw_data(&elf); 23 | 24 | println!("disassembling {} bytes from .text @ {:#x}", size, base); 25 | 26 | for maybe_decoded in bad64::disasm(bytes, base) { 27 | match maybe_decoded { 28 | Ok(decoded) => println!("{:04x}: {}", decoded.address(), decoded), 29 | Err(e) => println!("{:04x}: (bad)", e.address()), 30 | } 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /res/id: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yrp604/bad64/c394575d66d623b6cf7630828dc230051a1f6894/res/id -------------------------------------------------------------------------------- /src/arrspec.rs: -------------------------------------------------------------------------------- 1 | use core::convert::TryFrom; 2 | 3 | use bad64_sys::*; 4 | 5 | use crate::Reg; 6 | 7 | /// An arrangement specifier 8 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)] 9 | pub enum ArrSpec { 10 | Full(Option), 11 | TwoDoubles(Option), 12 | FourSingles(Option), 13 | EightHalves(Option), 14 | SixteenBytes(Option), 15 | OneDouble(Option), 16 | TwoSingles(Option), 17 | FourHalves(Option), 18 | EightBytes(Option), 19 | OneSingle(Option), 20 | TwoHalves(Option), 21 | FourBytes(Option), 22 | OneHalf(Option), 23 | OneByte(Option), 24 | } 25 | 26 | #[allow(non_upper_case_globals)] 27 | #[doc(hidden)] 28 | impl TryFrom<&bad64_sys::InstructionOperand> for ArrSpec { 29 | type Error = (); 30 | 31 | fn try_from(oo: &bad64_sys::InstructionOperand) -> Result { 32 | let lane = match oo.laneUsed { 33 | true => Some(oo.lane), 34 | false => None, 35 | }; 36 | 37 | match oo.arrSpec { 38 | ArrangementSpec::ARRSPEC_FULL => Ok(ArrSpec::Full(lane)), 39 | ArrangementSpec::ARRSPEC_2DOUBLES => Ok(ArrSpec::TwoDoubles(lane)), 40 | ArrangementSpec::ARRSPEC_4SINGLES => Ok(ArrSpec::FourSingles(lane)), 41 | ArrangementSpec::ARRSPEC_8HALVES => Ok(ArrSpec::EightHalves(lane)), 42 | ArrangementSpec::ARRSPEC_16BYTES => Ok(ArrSpec::SixteenBytes(lane)), 43 | ArrangementSpec::ARRSPEC_1DOUBLE => Ok(ArrSpec::OneDouble(lane)), 44 | ArrangementSpec::ARRSPEC_2SINGLES => Ok(ArrSpec::TwoSingles(lane)), 45 | ArrangementSpec::ARRSPEC_4HALVES => Ok(ArrSpec::FourHalves(lane)), 46 | ArrangementSpec::ARRSPEC_8BYTES => Ok(ArrSpec::EightBytes(lane)), 47 | ArrangementSpec::ARRSPEC_1SINGLE => Ok(ArrSpec::OneSingle(lane)), 48 | ArrangementSpec::ARRSPEC_2HALVES => Ok(ArrSpec::TwoHalves(lane)), 49 | ArrangementSpec::ARRSPEC_4BYTES => Ok(ArrSpec::FourBytes(lane)), 50 | ArrangementSpec::ARRSPEC_1HALF => Ok(ArrSpec::OneHalf(lane)), 51 | ArrangementSpec::ARRSPEC_1BYTE => Ok(ArrSpec::OneByte(lane)), 52 | ArrangementSpec::ARRSPEC_NONE => Err(()), 53 | } 54 | } 55 | } 56 | 57 | impl ArrSpec { 58 | pub fn lane(&self) -> Option { 59 | match *self { 60 | Self::Full(lane) 61 | | Self::TwoDoubles(lane) 62 | | Self::OneDouble(lane) 63 | | Self::FourSingles(lane) 64 | | Self::TwoSingles(lane) 65 | | Self::OneSingle(lane) 66 | | Self::EightHalves(lane) 67 | | Self::FourHalves(lane) 68 | | Self::TwoHalves(lane) 69 | | Self::OneHalf(lane) 70 | | Self::SixteenBytes(lane) 71 | | Self::EightBytes(lane) 72 | | Self::FourBytes(lane) 73 | | Self::OneByte(lane) => lane, 74 | } 75 | } 76 | 77 | pub fn suffix_truncated(&self) -> &'static str { 78 | match *self { 79 | Self::Full(_) => ".q", 80 | Self::TwoDoubles(_) | Self::OneDouble(_) => ".d", 81 | Self::FourSingles(_) | Self::TwoSingles(_) | Self::OneSingle(_) => ".s", 82 | Self::EightHalves(_) | Self::FourHalves(_) | Self::TwoHalves(_) | Self::OneHalf(_) => { 83 | ".h" 84 | } 85 | Self::SixteenBytes(_) | Self::EightBytes(_) | Self::FourBytes(_) | Self::OneByte(_) => { 86 | ".b" 87 | } 88 | } 89 | } 90 | 91 | pub fn suffix_full(&self) -> &'static str { 92 | match *self { 93 | Self::Full(_) => ".1q", 94 | Self::TwoDoubles(_) => ".2d", 95 | Self::OneDouble(_) => ".1d", 96 | Self::FourSingles(_) => ".4s", 97 | Self::TwoSingles(_) => ".2s", 98 | Self::OneSingle(_) => ".1s", 99 | Self::EightHalves(_) => ".8h", 100 | Self::FourHalves(_) => ".4h", 101 | Self::TwoHalves(_) => ".2h", 102 | Self::OneHalf(_) => ".1h", 103 | Self::SixteenBytes(_) => ".16b", 104 | Self::EightBytes(_) => ".8b", 105 | Self::FourBytes(_) => ".4b", 106 | Self::OneByte(_) => ".1b", 107 | } 108 | } 109 | 110 | pub fn suffix(&self, reg: Reg) -> &'static str { 111 | let is_sve = reg.is_sve(); 112 | let is_pred = reg.is_pred(); 113 | 114 | if !reg.is_simd() && !is_sve && !is_pred { 115 | return ""; 116 | } 117 | 118 | if self.lane().is_some() || is_sve || is_pred { 119 | return self.suffix_truncated(); 120 | } 121 | 122 | return self.suffix_full(); 123 | } 124 | } 125 | -------------------------------------------------------------------------------- /src/condition.rs: -------------------------------------------------------------------------------- 1 | use bad64_sys::*; 2 | 3 | use core::fmt; 4 | 5 | /// A condition 6 | #[derive(Clone, Copy, Debug, Hash, Eq, PartialEq, FromPrimitive, ToPrimitive)] 7 | #[repr(u32)] 8 | #[allow(non_camel_case_types)] 9 | pub enum Condition { 10 | EQ = Condition_COND_EQ as u32, 11 | NE = Condition_COND_NE as u32, 12 | CS = Condition_COND_CS as u32, 13 | CC = Condition_COND_CC as u32, 14 | MI = Condition_COND_MI as u32, 15 | PL = Condition_COND_PL as u32, 16 | VS = Condition_COND_VS as u32, 17 | VC = Condition_COND_VC as u32, 18 | HI = Condition_COND_HI as u32, 19 | LS = Condition_COND_LS as u32, 20 | GE = Condition_COND_GE as u32, 21 | LT = Condition_COND_LT as u32, 22 | GT = Condition_COND_GT as u32, 23 | LE = Condition_COND_LE as u32, 24 | AL = Condition_COND_AL as u32, 25 | NV = Condition_COND_NV as u32, 26 | } 27 | 28 | impl fmt::Display for Condition { 29 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 30 | match *self { 31 | Self::EQ => write!(f, "eq"), 32 | Self::NE => write!(f, "ne"), 33 | Self::CS => write!(f, "cs"), 34 | Self::CC => write!(f, "cc"), 35 | Self::MI => write!(f, "mi"), 36 | Self::PL => write!(f, "pl"), 37 | Self::VS => write!(f, "vs"), 38 | Self::VC => write!(f, "vc"), 39 | Self::HI => write!(f, "hi"), 40 | Self::LS => write!(f, "ls"), 41 | Self::GE => write!(f, "ge"), 42 | Self::LT => write!(f, "lt"), 43 | Self::GT => write!(f, "gt"), 44 | Self::LE => write!(f, "le"), 45 | Self::AL => write!(f, "al"), 46 | Self::NV => write!(f, "nv"), 47 | } 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /src/flageffect.rs: -------------------------------------------------------------------------------- 1 | /// The semantic meaning of the flag setting 2 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)] 3 | pub enum FlagEffect { 4 | Sets, 5 | Integer, 6 | Float, 7 | } 8 | 9 | #[doc(hidden)] 10 | #[allow(non_upper_case_globals)] 11 | impl TryFrom<&bad64_sys::Instruction> for FlagEffect { 12 | type Error = (); 13 | 14 | fn try_from(ii: &bad64_sys::Instruction) -> Result { 15 | match ii.setflags { 16 | bad64_sys::FlagEffect::FLAGEFFECT_SETS => Ok(FlagEffect::Sets), 17 | bad64_sys::FlagEffect::FLAGEFFECT_SETS_NORMAL => Ok(FlagEffect::Integer), 18 | bad64_sys::FlagEffect::FLAGEFFECT_SETS_FLOAT => Ok(FlagEffect::Float), 19 | bad64_sys::FlagEffect::FLAGEFFECT_NONE => Err(()), 20 | } 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /src/lib.rs: -------------------------------------------------------------------------------- 1 | //! # bad64 2 | //! 3 | //! bad64 is a set of Rust bindings to the Binja Arm64 Disassembler. 4 | //! 5 | //! For more information about the disassembler, please see the 6 | //! [upstream](https://github.com/Vector35/arch-arm64/tree/dev/disassembler) 7 | //! repo. 8 | //! 9 | //! There are two main entry points: 10 | //! 1. [`decode`] for decoding a single instruction. 11 | //! ``` 12 | //! use bad64::{decode, Op}; 13 | //! // nop - "\x1f\x20\x03\xd5" 14 | //! let decoded = decode(0xd503201f, 0x1000).unwrap(); 15 | //! 16 | //! assert_eq!(decoded.address(), 0x1000); 17 | //! assert_eq!(decoded.operands().len(), 0); 18 | //! assert_eq!(decoded.op(), Op::NOP); 19 | //! assert_eq!(decoded.op().mnem(), "nop"); 20 | //! ``` 21 | //! 22 | //! 2. [`disasm`] for disassembling a byte sequence. 23 | //! ``` 24 | //! use bad64::{disasm, Op, Operand, Reg, Imm}; 25 | //! 26 | //! // 1000: str x0, [sp, #-16]! ; "\xe0\x0f\x1f\xf8" 27 | //! // 1004: ldr x0, [sp], #16 ; "\xe0\x07\x41\xf8" 28 | //! let mut decoded_iter = disasm(b"\xe0\x0f\x1f\xf8\xe0\x07\x41\xf8", 0x1000); 29 | //! 30 | //! let push = decoded_iter.next().unwrap().unwrap(); 31 | //! 32 | //! // check out the push 33 | //! assert_eq!(push.address(), 0x1000); 34 | //! assert_eq!(push.operands().len(), 2); 35 | //! assert_eq!(push.op(), Op::STR); 36 | //! assert_eq!( 37 | //! push.operands()[0], 38 | //! Operand::Reg { reg: Reg::X0, arrspec: None } 39 | //! ); 40 | //! assert_eq!( 41 | //! push.operands()[1], 42 | //! Operand::MemPreIdx { reg: Reg::SP, imm: Imm::Signed(-16) } 43 | //! ); 44 | //! assert_eq!(push.operands().get(2), None); 45 | //! 46 | //! let pop = decoded_iter.next().unwrap().unwrap(); 47 | //! 48 | //! // check out the pop 49 | //! assert_eq!(pop.address(), 0x1004); 50 | //! assert_eq!(pop.operands().len(), 2); 51 | //! assert_eq!(pop.op(), Op::LDR); 52 | //! assert_eq!( 53 | //! pop.operands().get(0), 54 | //! Some(&Operand::Reg { reg: Reg::X0, arrspec: None }) 55 | //! ); 56 | //! assert_eq!( 57 | //! pop.operands().get(1), 58 | //! Some(&Operand::MemPostIdxImm { reg: Reg::SP, imm: Imm::Signed(16) }) 59 | //! ); 60 | //! assert_eq!(pop.operands().get(2), None); 61 | //! 62 | //! // make sure there's nothing left 63 | //! assert_eq!(decoded_iter.next(), None); 64 | //! ``` 65 | 66 | #![no_std] 67 | 68 | #[macro_use] 69 | extern crate num_derive; 70 | 71 | #[macro_use] 72 | extern crate static_assertions; 73 | 74 | #[cfg(feature = "std")] 75 | extern crate std; 76 | 77 | use core::convert::{TryFrom, TryInto}; 78 | use core::fmt; 79 | use core::hash::{Hash, Hasher}; 80 | 81 | use num_traits::FromPrimitive; 82 | 83 | use bad64_sys::*; 84 | 85 | mod arrspec; 86 | mod condition; 87 | mod flageffect; 88 | mod op; 89 | mod operand; 90 | mod reg; 91 | mod shift; 92 | mod sysreg; 93 | 94 | pub use arrspec::ArrSpec; 95 | pub use condition::Condition; 96 | pub use flageffect::FlagEffect; 97 | pub use op::Op; 98 | pub use operand::{Imm, Operand}; 99 | pub use reg::Reg; 100 | pub use shift::Shift; 101 | pub use sysreg::SysReg; 102 | 103 | /// A decoded instruction 104 | #[derive(Clone)] 105 | pub struct Instruction { 106 | address: u64, 107 | opcode: u32, 108 | op: Op, 109 | num_operands: usize, 110 | operands: [Operand; MAX_OPERANDS as usize], 111 | flags_set: Option, 112 | } 113 | 114 | // Needed because MaybeUninit doesn't allow derives 115 | impl PartialEq for Instruction { 116 | fn eq(&self, other: &Self) -> bool { 117 | self.address() == other.address() 118 | && self.op() == other.op() 119 | && self.opcode() == other.opcode() 120 | && self.num_operands == other.num_operands 121 | && self.flags_set == other.flags_set 122 | && self 123 | .operands() 124 | .iter() 125 | .zip(other.operands().iter()) 126 | .all(|(a, b)| a == b) 127 | } 128 | } 129 | 130 | impl Eq for Instruction {} 131 | 132 | impl Hash for Instruction { 133 | fn hash(&self, state: &mut H) { 134 | self.address.hash(state); 135 | self.opcode.hash(state); 136 | self.op.hash(state); 137 | self.num_operands.hash(state); 138 | self.flags_set.hash(state); 139 | 140 | for o in self.operands() { 141 | o.hash(state); 142 | } 143 | } 144 | } 145 | 146 | impl fmt::Display for Instruction { 147 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 148 | write!(f, "{}", self.op())?; 149 | 150 | let mut ops = self.operands().iter(); 151 | 152 | if let Some(op) = ops.next() { 153 | write!(f, " {}", op)?; 154 | 155 | for op in ops { 156 | write!(f, ", {}", op)?; 157 | } 158 | } 159 | 160 | Ok(()) 161 | } 162 | } 163 | 164 | impl fmt::Debug for Instruction { 165 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 166 | f.debug_struct("Instruction") 167 | .field("address", &self.address) 168 | .field("opcode", &self.opcode) 169 | .field("op", &self.op) 170 | .field("num_operands", &self.num_operands) 171 | .field("operands", &self.operands()) 172 | .field("flags_set", &self.flags_set) 173 | .finish() 174 | } 175 | } 176 | 177 | impl Instruction { 178 | /// Returns the instruction address 179 | /// 180 | /// # Example 181 | /// ``` 182 | /// use bad64::decode; 183 | /// // nop - "\x1f\x20\x03\xd5" 184 | /// let decoded = decode(0xd503201f, 0x1000).unwrap(); 185 | /// assert_eq!(decoded.address(), 0x1000); 186 | /// ``` 187 | pub fn address(&self) -> u64 { 188 | self.address 189 | } 190 | 191 | /// Returns the instruction opcode 192 | /// 193 | /// # Example 194 | /// ``` 195 | /// use bad64::decode; 196 | /// // nop - "\x1f\x20\x03\xd5" 197 | /// let decoded = decode(0xd503201f, 0x1000).unwrap(); 198 | /// assert_eq!(decoded.opcode(), 0xd503201f); 199 | /// ``` 200 | pub fn opcode(&self) -> u32 { 201 | self.opcode 202 | } 203 | 204 | /// Returns the instruction operation 205 | /// 206 | /// # Example 207 | /// ``` 208 | /// use bad64::{decode, Op}; 209 | /// // nop - "\x1f\x20\x03\xd5" 210 | /// let decoded = decode(0xd503201f, 0x1000).unwrap(); 211 | /// assert_eq!(decoded.op(), Op::NOP); 212 | // ``` 213 | pub fn op(&self) -> Op { 214 | self.op 215 | } 216 | 217 | /// Returns a slice of Operands 218 | /// 219 | /// # Example 220 | /// ``` 221 | /// use bad64::{decode, Operand, Reg}; 222 | /// 223 | /// // eor x0, x1, x2 - "\x20\x00\x02\xca" 224 | /// let decoded = decode(0xca020020, 0x1000).unwrap(); 225 | /// 226 | /// let mut ops = decoded.operands(); 227 | /// 228 | /// assert_eq!(ops.len(), 3); 229 | /// assert_eq!(ops[0], Operand::Reg { reg: Reg::X0, arrspec: None }); 230 | /// assert_eq!(ops[1], Operand::Reg { reg: Reg::X1, arrspec: None }); 231 | /// assert_eq!(ops[2], Operand::Reg { reg: Reg::X2, arrspec: None }); 232 | /// ``` 233 | pub fn operands(&self) -> &[Operand] { 234 | &self.operands[..self.num_operands] 235 | } 236 | 237 | /// Returns if the instruction updates the flags 238 | /// 239 | /// # Example 240 | /// ``` 241 | /// use bad64::{decode, FlagEffect}; 242 | /// 243 | /// // cmp x0, #0x41 - "\x1f\x04\x01\xf1" 244 | /// let decoded = decode(0xf101041f, 0x1000).unwrap(); 245 | /// assert_eq!(decoded.flags_set(), Some(FlagEffect::Sets)); 246 | /// 247 | /// // nop - "\x1f\x20\x03\xd5" 248 | /// let decoded = decode(0xd503201f, 0x1000).unwrap(); 249 | /// assert_eq!(decoded.flags_set(), None); 250 | /// ``` 251 | pub fn flags_set(&self) -> Option { 252 | self.flags_set 253 | } 254 | } 255 | /// Decoding errors types 256 | #[derive(Clone, Copy, Debug, Hash, Eq, PartialEq)] 257 | #[repr(i32)] 258 | pub enum DecodeError { 259 | Reserved(u64), 260 | Unmatched(u64), 261 | Unallocated(u64), 262 | Undefined(u64), 263 | EndOfInstruction(u64), 264 | Lost(u64), 265 | Unreachable(u64), 266 | Short(u64), 267 | ErrorOperands(u64), 268 | } 269 | 270 | impl DecodeError { 271 | fn new(code: i32, address: u64) -> Self { 272 | match code { 273 | DECODE_STATUS_RESERVED => Self::Reserved(address), 274 | DECODE_STATUS_UNMATCHED => Self::Unmatched(address), 275 | DECODE_STATUS_UNALLOCATED => Self::Unallocated(address), 276 | DECODE_STATUS_UNDEFINED => Self::Undefined(address), 277 | DECODE_STATUS_END_OF_INSTRUCTION => Self::EndOfInstruction(address), 278 | DECODE_STATUS_LOST => Self::Lost(address), 279 | DECODE_STATUS_UNREACHABLE => Self::Unreachable(address), 280 | DECODE_STATUS_ERROR_OPERANDS => Self::ErrorOperands(address), 281 | _ => panic!("unknown decode error code"), 282 | } 283 | } 284 | 285 | pub fn address(&self) -> u64 { 286 | match self { 287 | Self::Reserved(a) => *a, 288 | Self::Unmatched(a) => *a, 289 | Self::Unallocated(a) => *a, 290 | Self::Undefined(a) => *a, 291 | Self::EndOfInstruction(a) => *a, 292 | Self::Lost(a) => *a, 293 | Self::Unreachable(a) => *a, 294 | Self::Short(a) => *a, 295 | Self::ErrorOperands(a) => *a, 296 | } 297 | } 298 | } 299 | 300 | impl fmt::Display for DecodeError { 301 | fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { 302 | match self { 303 | DecodeError::Reserved(x) => write!(f, "Reserved: {:#x}", x), 304 | DecodeError::Unmatched(x) => write!(f, "Unmatched: {:#x}", x), 305 | DecodeError::Unallocated(x) => write!(f, "Unallocated: {:#x}", x), 306 | DecodeError::Undefined(x) => write!(f, "Undefined: {:#x}", x), 307 | DecodeError::EndOfInstruction(x) => write!(f, "EndOfInstruction: {:#x}", x), 308 | DecodeError::Lost(x) => write!(f, "Lost: {:#x}", x), 309 | DecodeError::Unreachable(x) => write!(f, "Unreachable: {:#x}", x), 310 | DecodeError::Short(x) => write!(f, "Short: {:#x}", x), 311 | DecodeError::ErrorOperands(x) => write!(f, "ErrorOperands: {:#x}", x), 312 | } 313 | } 314 | } 315 | 316 | #[cfg(feature = "std")] 317 | impl std::error::Error for DecodeError {} 318 | 319 | /// Decode a single instruction 320 | /// 321 | /// # Arguments 322 | /// 323 | /// * `ins` - A little endian u32 of code to be decoded 324 | /// * `address` - Location of code in memory 325 | /// 326 | /// # Examples 327 | /// ``` 328 | /// use bad64::{decode, Op}; 329 | /// 330 | /// // NOTE: little endian 331 | /// let decoded = decode(0xd503201f, 0x1000).unwrap(); 332 | /// 333 | /// assert_eq!(decoded.operands().len(), 0); 334 | /// assert_eq!(decoded.operands(), &[]); 335 | /// assert_eq!(decoded.op(), Op::NOP); 336 | /// assert_eq!(decoded.op().mnem(), "nop"); 337 | /// assert_eq!(decoded.address(), 0x1000); 338 | /// ``` 339 | pub fn decode(ins: u32, address: u64) -> Result { 340 | let (r, decoded) = unsafe { 341 | let mut decoded: bad64_sys::Instruction = core::mem::zeroed(); 342 | let r = aarch64_decompose(ins, &mut decoded, address); 343 | (r, decoded) 344 | }; 345 | 346 | match r { 347 | 0 => { 348 | let op = Op::from_u32(decoded.operation as u32).unwrap(); 349 | let mut operands: [Operand; MAX_OPERANDS as usize] = 350 | [Operand::Label(Imm::Unsigned(0)); MAX_OPERANDS as usize]; 351 | let mut num_operands = 0; 352 | 353 | for (n, operand) in decoded.operands.iter().enumerate() { 354 | match Operand::try_from(operand) { 355 | Ok(o) => { 356 | operands[n] = o; 357 | num_operands += 1; 358 | } 359 | Err(_) => break, 360 | } 361 | } 362 | 363 | let flags_set = FlagEffect::try_from(&decoded).ok(); 364 | 365 | Ok(Instruction { 366 | address, 367 | opcode: decoded.insword, 368 | op, 369 | num_operands, 370 | operands, 371 | flags_set, 372 | }) 373 | } 374 | _ => Err(DecodeError::new(r, address)), 375 | } 376 | } 377 | 378 | /// Disassemble byte slice 379 | /// 380 | /// # Arguments 381 | /// 382 | /// * `code` - u8 slice to zero or more instructions 383 | /// * `address` - Location of code in memory 384 | /// 385 | /// # Examples 386 | /// ``` 387 | /// use bad64::{disasm, Op}; 388 | /// 389 | /// let mut decoded_iter = disasm(b"\x1f\x20\x03\xd5\x1f\x20\x03\xd5", 0x1000); 390 | /// 391 | /// let decoded1 = decoded_iter.next().unwrap().unwrap(); 392 | /// 393 | /// assert_eq!(decoded1.address(), 0x1000); 394 | /// assert_eq!(decoded1.operands().len(), 0); 395 | /// assert_eq!(decoded1.op(), Op::NOP); 396 | /// assert_eq!(decoded1.op().mnem(), "nop"); 397 | /// 398 | /// let decoded2 = decoded_iter.next().unwrap().unwrap(); 399 | /// 400 | /// assert_eq!(decoded2.address(), 0x1004); 401 | /// assert_eq!(decoded2.operands().len(), 0); 402 | /// assert_eq!(decoded2.op(), Op::NOP); 403 | /// assert_eq!(decoded2.op().mnem(), "nop"); 404 | /// 405 | /// assert_eq!(decoded_iter.next(), None); 406 | /// ``` 407 | pub fn disasm( 408 | code: &[u8], 409 | address: u64, 410 | ) -> impl Iterator> + '_ { 411 | (address..) 412 | .step_by(4) 413 | .zip(code.chunks(4)) 414 | .map(|(addr, bytes)| match bytes.try_into() { 415 | Ok(v) => { 416 | let vv = u32::from_le_bytes(v); 417 | 418 | decode(vv, addr) 419 | } 420 | Err(_) => Err(DecodeError::Short(addr)), 421 | }) 422 | } 423 | -------------------------------------------------------------------------------- /src/op.rs: -------------------------------------------------------------------------------- 1 | use core::fmt; 2 | 3 | use bad64_sys::*; 4 | 5 | use cstr_core::CStr; 6 | use num_traits::ToPrimitive; 7 | 8 | // %s/^pub const \(Operation_ARM64_\(\w\+\)\): Operation = \d\+;/ \2 = \1 as u32,/g 9 | 10 | /// An instruction operation 11 | #[derive(Clone, Copy, Debug, Hash, Eq, PartialEq, FromPrimitive, ToPrimitive)] 12 | #[repr(u32)] 13 | #[allow(non_camel_case_types)] 14 | pub enum Op { 15 | ABS = Operation_ARM64_ABS as u32, 16 | ADC = Operation_ARM64_ADC as u32, 17 | ADCLB = Operation_ARM64_ADCLB as u32, 18 | ADCLT = Operation_ARM64_ADCLT as u32, 19 | ADCS = Operation_ARM64_ADCS as u32, 20 | ADD = Operation_ARM64_ADD as u32, 21 | ADDG = Operation_ARM64_ADDG as u32, 22 | ADDHA = Operation_ARM64_ADDHA as u32, 23 | ADDHN = Operation_ARM64_ADDHN as u32, 24 | ADDHN2 = Operation_ARM64_ADDHN2 as u32, 25 | ADDHNB = Operation_ARM64_ADDHNB as u32, 26 | ADDHNT = Operation_ARM64_ADDHNT as u32, 27 | ADDP = Operation_ARM64_ADDP as u32, 28 | ADDPL = Operation_ARM64_ADDPL as u32, 29 | ADDS = Operation_ARM64_ADDS as u32, 30 | ADDV = Operation_ARM64_ADDV as u32, 31 | ADDVA = Operation_ARM64_ADDVA as u32, 32 | ADDVL = Operation_ARM64_ADDVL as u32, 33 | ADR = Operation_ARM64_ADR as u32, 34 | ADRP = Operation_ARM64_ADRP as u32, 35 | AESD = Operation_ARM64_AESD as u32, 36 | AESE = Operation_ARM64_AESE as u32, 37 | AESIMC = Operation_ARM64_AESIMC as u32, 38 | AESMC = Operation_ARM64_AESMC as u32, 39 | AND = Operation_ARM64_AND as u32, 40 | ANDS = Operation_ARM64_ANDS as u32, 41 | ANDV = Operation_ARM64_ANDV as u32, 42 | ASR = Operation_ARM64_ASR as u32, 43 | ASRD = Operation_ARM64_ASRD as u32, 44 | ASRR = Operation_ARM64_ASRR as u32, 45 | ASRV = Operation_ARM64_ASRV as u32, 46 | AT = Operation_ARM64_AT as u32, 47 | AUTDA = Operation_ARM64_AUTDA as u32, 48 | AUTDB = Operation_ARM64_AUTDB as u32, 49 | AUTDZA = Operation_ARM64_AUTDZA as u32, 50 | AUTDZB = Operation_ARM64_AUTDZB as u32, 51 | AUTIA = Operation_ARM64_AUTIA as u32, 52 | AUTIA1716 = Operation_ARM64_AUTIA1716 as u32, 53 | AUTIASP = Operation_ARM64_AUTIASP as u32, 54 | AUTIAZ = Operation_ARM64_AUTIAZ as u32, 55 | AUTIB = Operation_ARM64_AUTIB as u32, 56 | AUTIB1716 = Operation_ARM64_AUTIB1716 as u32, 57 | AUTIBSP = Operation_ARM64_AUTIBSP as u32, 58 | AUTIBZ = Operation_ARM64_AUTIBZ as u32, 59 | AUTIZA = Operation_ARM64_AUTIZA as u32, 60 | AUTIZB = Operation_ARM64_AUTIZB as u32, 61 | AXFLAG = Operation_ARM64_AXFLAG as u32, 62 | B = Operation_ARM64_B as u32, 63 | BCAX = Operation_ARM64_BCAX as u32, 64 | BDEP = Operation_ARM64_BDEP as u32, 65 | BEXT = Operation_ARM64_BEXT as u32, 66 | BFC = Operation_ARM64_BFC as u32, 67 | BFCVT = Operation_ARM64_BFCVT as u32, 68 | BFCVTN = Operation_ARM64_BFCVTN as u32, 69 | BFCVTN2 = Operation_ARM64_BFCVTN2 as u32, 70 | BFCVTNT = Operation_ARM64_BFCVTNT as u32, 71 | BFDOT = Operation_ARM64_BFDOT as u32, 72 | BFI = Operation_ARM64_BFI as u32, 73 | BFM = Operation_ARM64_BFM as u32, 74 | BFMLAL = Operation_ARM64_BFMLAL as u32, 75 | BFMLALB = Operation_ARM64_BFMLALB as u32, 76 | BFMLALT = Operation_ARM64_BFMLALT as u32, 77 | BFMMLA = Operation_ARM64_BFMMLA as u32, 78 | BFMOPA = Operation_ARM64_BFMOPA as u32, 79 | BFMOPS = Operation_ARM64_BFMOPS as u32, 80 | BFXIL = Operation_ARM64_BFXIL as u32, 81 | BGRP = Operation_ARM64_BGRP as u32, 82 | BIC = Operation_ARM64_BIC as u32, 83 | BICS = Operation_ARM64_BICS as u32, 84 | BIF = Operation_ARM64_BIF as u32, 85 | BIT = Operation_ARM64_BIT as u32, 86 | BL = Operation_ARM64_BL as u32, 87 | BLR = Operation_ARM64_BLR as u32, 88 | BLRAA = Operation_ARM64_BLRAA as u32, 89 | BLRAAZ = Operation_ARM64_BLRAAZ as u32, 90 | BLRAB = Operation_ARM64_BLRAB as u32, 91 | BLRABZ = Operation_ARM64_BLRABZ as u32, 92 | BR = Operation_ARM64_BR as u32, 93 | BRAA = Operation_ARM64_BRAA as u32, 94 | BRAAZ = Operation_ARM64_BRAAZ as u32, 95 | BRAB = Operation_ARM64_BRAB as u32, 96 | BRABZ = Operation_ARM64_BRABZ as u32, 97 | BRK = Operation_ARM64_BRK as u32, 98 | BRKA = Operation_ARM64_BRKA as u32, 99 | BRKAS = Operation_ARM64_BRKAS as u32, 100 | BRKB = Operation_ARM64_BRKB as u32, 101 | BRKBS = Operation_ARM64_BRKBS as u32, 102 | BRKN = Operation_ARM64_BRKN as u32, 103 | BRKNS = Operation_ARM64_BRKNS as u32, 104 | BRKPA = Operation_ARM64_BRKPA as u32, 105 | BRKPAS = Operation_ARM64_BRKPAS as u32, 106 | BRKPB = Operation_ARM64_BRKPB as u32, 107 | BRKPBS = Operation_ARM64_BRKPBS as u32, 108 | BSL = Operation_ARM64_BSL as u32, 109 | BSL1N = Operation_ARM64_BSL1N as u32, 110 | BSL2N = Operation_ARM64_BSL2N as u32, 111 | BTI = Operation_ARM64_BTI as u32, 112 | B_AL = Operation_ARM64_B_AL as u32, 113 | B_CC = Operation_ARM64_B_CC as u32, 114 | B_CS = Operation_ARM64_B_CS as u32, 115 | B_EQ = Operation_ARM64_B_EQ as u32, 116 | B_GE = Operation_ARM64_B_GE as u32, 117 | B_GT = Operation_ARM64_B_GT as u32, 118 | B_HI = Operation_ARM64_B_HI as u32, 119 | B_LE = Operation_ARM64_B_LE as u32, 120 | B_LS = Operation_ARM64_B_LS as u32, 121 | B_LT = Operation_ARM64_B_LT as u32, 122 | B_MI = Operation_ARM64_B_MI as u32, 123 | B_NE = Operation_ARM64_B_NE as u32, 124 | B_NV = Operation_ARM64_B_NV as u32, 125 | B_PL = Operation_ARM64_B_PL as u32, 126 | B_VC = Operation_ARM64_B_VC as u32, 127 | B_VS = Operation_ARM64_B_VS as u32, 128 | CADD = Operation_ARM64_CADD as u32, 129 | CAS = Operation_ARM64_CAS as u32, 130 | CASA = Operation_ARM64_CASA as u32, 131 | CASAB = Operation_ARM64_CASAB as u32, 132 | CASAH = Operation_ARM64_CASAH as u32, 133 | CASAL = Operation_ARM64_CASAL as u32, 134 | CASALB = Operation_ARM64_CASALB as u32, 135 | CASALH = Operation_ARM64_CASALH as u32, 136 | CASB = Operation_ARM64_CASB as u32, 137 | CASH = Operation_ARM64_CASH as u32, 138 | CASL = Operation_ARM64_CASL as u32, 139 | CASLB = Operation_ARM64_CASLB as u32, 140 | CASLH = Operation_ARM64_CASLH as u32, 141 | CASP = Operation_ARM64_CASP as u32, 142 | CASPA = Operation_ARM64_CASPA as u32, 143 | CASPAL = Operation_ARM64_CASPAL as u32, 144 | CASPL = Operation_ARM64_CASPL as u32, 145 | CBNZ = Operation_ARM64_CBNZ as u32, 146 | CBZ = Operation_ARM64_CBZ as u32, 147 | CCMN = Operation_ARM64_CCMN as u32, 148 | CCMP = Operation_ARM64_CCMP as u32, 149 | CDOT = Operation_ARM64_CDOT as u32, 150 | CFINV = Operation_ARM64_CFINV as u32, 151 | CFP = Operation_ARM64_CFP as u32, 152 | CINC = Operation_ARM64_CINC as u32, 153 | CINV = Operation_ARM64_CINV as u32, 154 | CLASTA = Operation_ARM64_CLASTA as u32, 155 | CLASTB = Operation_ARM64_CLASTB as u32, 156 | CLREX = Operation_ARM64_CLREX as u32, 157 | CLS = Operation_ARM64_CLS as u32, 158 | CLZ = Operation_ARM64_CLZ as u32, 159 | CMEQ = Operation_ARM64_CMEQ as u32, 160 | CMGE = Operation_ARM64_CMGE as u32, 161 | CMGT = Operation_ARM64_CMGT as u32, 162 | CMHI = Operation_ARM64_CMHI as u32, 163 | CMHS = Operation_ARM64_CMHS as u32, 164 | CMLA = Operation_ARM64_CMLA as u32, 165 | CMLE = Operation_ARM64_CMLE as u32, 166 | CMLT = Operation_ARM64_CMLT as u32, 167 | CMN = Operation_ARM64_CMN as u32, 168 | CMP = Operation_ARM64_CMP as u32, 169 | CMPEQ = Operation_ARM64_CMPEQ as u32, 170 | CMPGE = Operation_ARM64_CMPGE as u32, 171 | CMPGT = Operation_ARM64_CMPGT as u32, 172 | CMPHI = Operation_ARM64_CMPHI as u32, 173 | CMPHS = Operation_ARM64_CMPHS as u32, 174 | CMPLE = Operation_ARM64_CMPLE as u32, 175 | CMPLO = Operation_ARM64_CMPLO as u32, 176 | CMPLS = Operation_ARM64_CMPLS as u32, 177 | CMPLT = Operation_ARM64_CMPLT as u32, 178 | CMPNE = Operation_ARM64_CMPNE as u32, 179 | CMPP = Operation_ARM64_CMPP as u32, 180 | CMTST = Operation_ARM64_CMTST as u32, 181 | CNEG = Operation_ARM64_CNEG as u32, 182 | CNOT = Operation_ARM64_CNOT as u32, 183 | CNT = Operation_ARM64_CNT as u32, 184 | CNTB = Operation_ARM64_CNTB as u32, 185 | CNTD = Operation_ARM64_CNTD as u32, 186 | CNTH = Operation_ARM64_CNTH as u32, 187 | CNTP = Operation_ARM64_CNTP as u32, 188 | CNTW = Operation_ARM64_CNTW as u32, 189 | COMPACT = Operation_ARM64_COMPACT as u32, 190 | CPP = Operation_ARM64_CPP as u32, 191 | CPY = Operation_ARM64_CPY as u32, 192 | CRC32B = Operation_ARM64_CRC32B as u32, 193 | CRC32CB = Operation_ARM64_CRC32CB as u32, 194 | CRC32CH = Operation_ARM64_CRC32CH as u32, 195 | CRC32CW = Operation_ARM64_CRC32CW as u32, 196 | CRC32CX = Operation_ARM64_CRC32CX as u32, 197 | CRC32H = Operation_ARM64_CRC32H as u32, 198 | CRC32W = Operation_ARM64_CRC32W as u32, 199 | CRC32X = Operation_ARM64_CRC32X as u32, 200 | CSDB = Operation_ARM64_CSDB as u32, 201 | CSEL = Operation_ARM64_CSEL as u32, 202 | CSET = Operation_ARM64_CSET as u32, 203 | CSETM = Operation_ARM64_CSETM as u32, 204 | CSINC = Operation_ARM64_CSINC as u32, 205 | CSINV = Operation_ARM64_CSINV as u32, 206 | CSNEG = Operation_ARM64_CSNEG as u32, 207 | CTERMEQ = Operation_ARM64_CTERMEQ as u32, 208 | CTERMNE = Operation_ARM64_CTERMNE as u32, 209 | DC = Operation_ARM64_DC as u32, 210 | DCPS1 = Operation_ARM64_DCPS1 as u32, 211 | DCPS2 = Operation_ARM64_DCPS2 as u32, 212 | DCPS3 = Operation_ARM64_DCPS3 as u32, 213 | DECB = Operation_ARM64_DECB as u32, 214 | DECD = Operation_ARM64_DECD as u32, 215 | DECH = Operation_ARM64_DECH as u32, 216 | DECP = Operation_ARM64_DECP as u32, 217 | DECW = Operation_ARM64_DECW as u32, 218 | DGH = Operation_ARM64_DGH as u32, 219 | DMB = Operation_ARM64_DMB as u32, 220 | DRPS = Operation_ARM64_DRPS as u32, 221 | DSB = Operation_ARM64_DSB as u32, 222 | DUP = Operation_ARM64_DUP as u32, 223 | DUPM = Operation_ARM64_DUPM as u32, 224 | DVP = Operation_ARM64_DVP as u32, 225 | EON = Operation_ARM64_EON as u32, 226 | EOR = Operation_ARM64_EOR as u32, 227 | EOR3 = Operation_ARM64_EOR3 as u32, 228 | EORBT = Operation_ARM64_EORBT as u32, 229 | EORS = Operation_ARM64_EORS as u32, 230 | EORTB = Operation_ARM64_EORTB as u32, 231 | EORV = Operation_ARM64_EORV as u32, 232 | ERET = Operation_ARM64_ERET as u32, 233 | ERETAA = Operation_ARM64_ERETAA as u32, 234 | ERETAB = Operation_ARM64_ERETAB as u32, 235 | ESB = Operation_ARM64_ESB as u32, 236 | EXT = Operation_ARM64_EXT as u32, 237 | EXTR = Operation_ARM64_EXTR as u32, 238 | FABD = Operation_ARM64_FABD as u32, 239 | FABS = Operation_ARM64_FABS as u32, 240 | FACGE = Operation_ARM64_FACGE as u32, 241 | FACGT = Operation_ARM64_FACGT as u32, 242 | FACLE = Operation_ARM64_FACLE as u32, 243 | FACLT = Operation_ARM64_FACLT as u32, 244 | FADD = Operation_ARM64_FADD as u32, 245 | FADDA = Operation_ARM64_FADDA as u32, 246 | FADDP = Operation_ARM64_FADDP as u32, 247 | FADDV = Operation_ARM64_FADDV as u32, 248 | FCADD = Operation_ARM64_FCADD as u32, 249 | FCCMP = Operation_ARM64_FCCMP as u32, 250 | FCCMPE = Operation_ARM64_FCCMPE as u32, 251 | FCMEQ = Operation_ARM64_FCMEQ as u32, 252 | FCMGE = Operation_ARM64_FCMGE as u32, 253 | FCMGT = Operation_ARM64_FCMGT as u32, 254 | FCMLA = Operation_ARM64_FCMLA as u32, 255 | FCMLE = Operation_ARM64_FCMLE as u32, 256 | FCMLT = Operation_ARM64_FCMLT as u32, 257 | FCMNE = Operation_ARM64_FCMNE as u32, 258 | FCMP = Operation_ARM64_FCMP as u32, 259 | FCMPE = Operation_ARM64_FCMPE as u32, 260 | FCMUO = Operation_ARM64_FCMUO as u32, 261 | FCPY = Operation_ARM64_FCPY as u32, 262 | FCSEL = Operation_ARM64_FCSEL as u32, 263 | FCVT = Operation_ARM64_FCVT as u32, 264 | FCVTAS = Operation_ARM64_FCVTAS as u32, 265 | FCVTAU = Operation_ARM64_FCVTAU as u32, 266 | FCVTL = Operation_ARM64_FCVTL as u32, 267 | FCVTL2 = Operation_ARM64_FCVTL2 as u32, 268 | FCVTLT = Operation_ARM64_FCVTLT as u32, 269 | FCVTMS = Operation_ARM64_FCVTMS as u32, 270 | FCVTMU = Operation_ARM64_FCVTMU as u32, 271 | FCVTN = Operation_ARM64_FCVTN as u32, 272 | FCVTN2 = Operation_ARM64_FCVTN2 as u32, 273 | FCVTNS = Operation_ARM64_FCVTNS as u32, 274 | FCVTNT = Operation_ARM64_FCVTNT as u32, 275 | FCVTNU = Operation_ARM64_FCVTNU as u32, 276 | FCVTPS = Operation_ARM64_FCVTPS as u32, 277 | FCVTPU = Operation_ARM64_FCVTPU as u32, 278 | FCVTX = Operation_ARM64_FCVTX as u32, 279 | FCVTXN = Operation_ARM64_FCVTXN as u32, 280 | FCVTXN2 = Operation_ARM64_FCVTXN2 as u32, 281 | FCVTXNT = Operation_ARM64_FCVTXNT as u32, 282 | FCVTZS = Operation_ARM64_FCVTZS as u32, 283 | FCVTZU = Operation_ARM64_FCVTZU as u32, 284 | FDIV = Operation_ARM64_FDIV as u32, 285 | FDIVR = Operation_ARM64_FDIVR as u32, 286 | FDUP = Operation_ARM64_FDUP as u32, 287 | FEXPA = Operation_ARM64_FEXPA as u32, 288 | FJCVTZS = Operation_ARM64_FJCVTZS as u32, 289 | FLOGB = Operation_ARM64_FLOGB as u32, 290 | FMAD = Operation_ARM64_FMAD as u32, 291 | FMADD = Operation_ARM64_FMADD as u32, 292 | FMAX = Operation_ARM64_FMAX as u32, 293 | FMAXNM = Operation_ARM64_FMAXNM as u32, 294 | FMAXNMP = Operation_ARM64_FMAXNMP as u32, 295 | FMAXNMV = Operation_ARM64_FMAXNMV as u32, 296 | FMAXP = Operation_ARM64_FMAXP as u32, 297 | FMAXV = Operation_ARM64_FMAXV as u32, 298 | FMIN = Operation_ARM64_FMIN as u32, 299 | FMINNM = Operation_ARM64_FMINNM as u32, 300 | FMINNMP = Operation_ARM64_FMINNMP as u32, 301 | FMINNMV = Operation_ARM64_FMINNMV as u32, 302 | FMINP = Operation_ARM64_FMINP as u32, 303 | FMINV = Operation_ARM64_FMINV as u32, 304 | FMLA = Operation_ARM64_FMLA as u32, 305 | FMLAL = Operation_ARM64_FMLAL as u32, 306 | FMLAL2 = Operation_ARM64_FMLAL2 as u32, 307 | FMLALB = Operation_ARM64_FMLALB as u32, 308 | FMLALT = Operation_ARM64_FMLALT as u32, 309 | FMLS = Operation_ARM64_FMLS as u32, 310 | FMLSL = Operation_ARM64_FMLSL as u32, 311 | FMLSL2 = Operation_ARM64_FMLSL2 as u32, 312 | FMLSLB = Operation_ARM64_FMLSLB as u32, 313 | FMLSLT = Operation_ARM64_FMLSLT as u32, 314 | FMMLA = Operation_ARM64_FMMLA as u32, 315 | FMOPA = Operation_ARM64_FMOPA as u32, 316 | FMOPS = Operation_ARM64_FMOPS as u32, 317 | FMOV = Operation_ARM64_FMOV as u32, 318 | FMSB = Operation_ARM64_FMSB as u32, 319 | FMSUB = Operation_ARM64_FMSUB as u32, 320 | FMUL = Operation_ARM64_FMUL as u32, 321 | FMULX = Operation_ARM64_FMULX as u32, 322 | FNEG = Operation_ARM64_FNEG as u32, 323 | FNMAD = Operation_ARM64_FNMAD as u32, 324 | FNMADD = Operation_ARM64_FNMADD as u32, 325 | FNMLA = Operation_ARM64_FNMLA as u32, 326 | FNMLS = Operation_ARM64_FNMLS as u32, 327 | FNMSB = Operation_ARM64_FNMSB as u32, 328 | FNMSUB = Operation_ARM64_FNMSUB as u32, 329 | FNMUL = Operation_ARM64_FNMUL as u32, 330 | FRECPE = Operation_ARM64_FRECPE as u32, 331 | FRECPS = Operation_ARM64_FRECPS as u32, 332 | FRECPX = Operation_ARM64_FRECPX as u32, 333 | FRINT32X = Operation_ARM64_FRINT32X as u32, 334 | FRINT32Z = Operation_ARM64_FRINT32Z as u32, 335 | FRINT64X = Operation_ARM64_FRINT64X as u32, 336 | FRINT64Z = Operation_ARM64_FRINT64Z as u32, 337 | FRINTA = Operation_ARM64_FRINTA as u32, 338 | FRINTI = Operation_ARM64_FRINTI as u32, 339 | FRINTM = Operation_ARM64_FRINTM as u32, 340 | FRINTN = Operation_ARM64_FRINTN as u32, 341 | FRINTP = Operation_ARM64_FRINTP as u32, 342 | FRINTX = Operation_ARM64_FRINTX as u32, 343 | FRINTZ = Operation_ARM64_FRINTZ as u32, 344 | FRSQRTE = Operation_ARM64_FRSQRTE as u32, 345 | FRSQRTS = Operation_ARM64_FRSQRTS as u32, 346 | FSCALE = Operation_ARM64_FSCALE as u32, 347 | FSQRT = Operation_ARM64_FSQRT as u32, 348 | FSUB = Operation_ARM64_FSUB as u32, 349 | FSUBR = Operation_ARM64_FSUBR as u32, 350 | FTMAD = Operation_ARM64_FTMAD as u32, 351 | FTSMUL = Operation_ARM64_FTSMUL as u32, 352 | FTSSEL = Operation_ARM64_FTSSEL as u32, 353 | GMI = Operation_ARM64_GMI as u32, 354 | HINT = Operation_ARM64_HINT as u32, 355 | HISTCNT = Operation_ARM64_HISTCNT as u32, 356 | HISTSEG = Operation_ARM64_HISTSEG as u32, 357 | HLT = Operation_ARM64_HLT as u32, 358 | HVC = Operation_ARM64_HVC as u32, 359 | IC = Operation_ARM64_IC as u32, 360 | INCB = Operation_ARM64_INCB as u32, 361 | INCD = Operation_ARM64_INCD as u32, 362 | INCH = Operation_ARM64_INCH as u32, 363 | INCP = Operation_ARM64_INCP as u32, 364 | INCW = Operation_ARM64_INCW as u32, 365 | INDEX = Operation_ARM64_INDEX as u32, 366 | INS = Operation_ARM64_INS as u32, 367 | INSR = Operation_ARM64_INSR as u32, 368 | IRG = Operation_ARM64_IRG as u32, 369 | ISB = Operation_ARM64_ISB as u32, 370 | LASTA = Operation_ARM64_LASTA as u32, 371 | LASTB = Operation_ARM64_LASTB as u32, 372 | LD1 = Operation_ARM64_LD1 as u32, 373 | LD1B = Operation_ARM64_LD1B as u32, 374 | LD1D = Operation_ARM64_LD1D as u32, 375 | LD1H = Operation_ARM64_LD1H as u32, 376 | LD1Q = Operation_ARM64_LD1Q as u32, 377 | LD1R = Operation_ARM64_LD1R as u32, 378 | LD1RB = Operation_ARM64_LD1RB as u32, 379 | LD1RD = Operation_ARM64_LD1RD as u32, 380 | LD1RH = Operation_ARM64_LD1RH as u32, 381 | LD1ROB = Operation_ARM64_LD1ROB as u32, 382 | LD1ROD = Operation_ARM64_LD1ROD as u32, 383 | LD1ROH = Operation_ARM64_LD1ROH as u32, 384 | LD1ROW = Operation_ARM64_LD1ROW as u32, 385 | LD1RQB = Operation_ARM64_LD1RQB as u32, 386 | LD1RQD = Operation_ARM64_LD1RQD as u32, 387 | LD1RQH = Operation_ARM64_LD1RQH as u32, 388 | LD1RQW = Operation_ARM64_LD1RQW as u32, 389 | LD1RSB = Operation_ARM64_LD1RSB as u32, 390 | LD1RSH = Operation_ARM64_LD1RSH as u32, 391 | LD1RSW = Operation_ARM64_LD1RSW as u32, 392 | LD1RW = Operation_ARM64_LD1RW as u32, 393 | LD1SB = Operation_ARM64_LD1SB as u32, 394 | LD1SH = Operation_ARM64_LD1SH as u32, 395 | LD1SW = Operation_ARM64_LD1SW as u32, 396 | LD1W = Operation_ARM64_LD1W as u32, 397 | LD2 = Operation_ARM64_LD2 as u32, 398 | LD2B = Operation_ARM64_LD2B as u32, 399 | LD2D = Operation_ARM64_LD2D as u32, 400 | LD2H = Operation_ARM64_LD2H as u32, 401 | LD2R = Operation_ARM64_LD2R as u32, 402 | LD2W = Operation_ARM64_LD2W as u32, 403 | LD3 = Operation_ARM64_LD3 as u32, 404 | LD3B = Operation_ARM64_LD3B as u32, 405 | LD3D = Operation_ARM64_LD3D as u32, 406 | LD3H = Operation_ARM64_LD3H as u32, 407 | LD3R = Operation_ARM64_LD3R as u32, 408 | LD3W = Operation_ARM64_LD3W as u32, 409 | LD4 = Operation_ARM64_LD4 as u32, 410 | LD4B = Operation_ARM64_LD4B as u32, 411 | LD4D = Operation_ARM64_LD4D as u32, 412 | LD4H = Operation_ARM64_LD4H as u32, 413 | LD4R = Operation_ARM64_LD4R as u32, 414 | LD4W = Operation_ARM64_LD4W as u32, 415 | LD64B = Operation_ARM64_LD64B as u32, 416 | LDADD = Operation_ARM64_LDADD as u32, 417 | LDADDA = Operation_ARM64_LDADDA as u32, 418 | LDADDAB = Operation_ARM64_LDADDAB as u32, 419 | LDADDAH = Operation_ARM64_LDADDAH as u32, 420 | LDADDAL = Operation_ARM64_LDADDAL as u32, 421 | LDADDALB = Operation_ARM64_LDADDALB as u32, 422 | LDADDALH = Operation_ARM64_LDADDALH as u32, 423 | LDADDB = Operation_ARM64_LDADDB as u32, 424 | LDADDH = Operation_ARM64_LDADDH as u32, 425 | LDADDL = Operation_ARM64_LDADDL as u32, 426 | LDADDLB = Operation_ARM64_LDADDLB as u32, 427 | LDADDLH = Operation_ARM64_LDADDLH as u32, 428 | LDAPR = Operation_ARM64_LDAPR as u32, 429 | LDAPRB = Operation_ARM64_LDAPRB as u32, 430 | LDAPRH = Operation_ARM64_LDAPRH as u32, 431 | LDAPUR = Operation_ARM64_LDAPUR as u32, 432 | LDAPURB = Operation_ARM64_LDAPURB as u32, 433 | LDAPURH = Operation_ARM64_LDAPURH as u32, 434 | LDAPURSB = Operation_ARM64_LDAPURSB as u32, 435 | LDAPURSH = Operation_ARM64_LDAPURSH as u32, 436 | LDAPURSW = Operation_ARM64_LDAPURSW as u32, 437 | LDAR = Operation_ARM64_LDAR as u32, 438 | LDARB = Operation_ARM64_LDARB as u32, 439 | LDARH = Operation_ARM64_LDARH as u32, 440 | LDAXP = Operation_ARM64_LDAXP as u32, 441 | LDAXR = Operation_ARM64_LDAXR as u32, 442 | LDAXRB = Operation_ARM64_LDAXRB as u32, 443 | LDAXRH = Operation_ARM64_LDAXRH as u32, 444 | LDCLR = Operation_ARM64_LDCLR as u32, 445 | LDCLRA = Operation_ARM64_LDCLRA as u32, 446 | LDCLRAB = Operation_ARM64_LDCLRAB as u32, 447 | LDCLRAH = Operation_ARM64_LDCLRAH as u32, 448 | LDCLRAL = Operation_ARM64_LDCLRAL as u32, 449 | LDCLRALB = Operation_ARM64_LDCLRALB as u32, 450 | LDCLRALH = Operation_ARM64_LDCLRALH as u32, 451 | LDCLRB = Operation_ARM64_LDCLRB as u32, 452 | LDCLRH = Operation_ARM64_LDCLRH as u32, 453 | LDCLRL = Operation_ARM64_LDCLRL as u32, 454 | LDCLRLB = Operation_ARM64_LDCLRLB as u32, 455 | LDCLRLH = Operation_ARM64_LDCLRLH as u32, 456 | LDEOR = Operation_ARM64_LDEOR as u32, 457 | LDEORA = Operation_ARM64_LDEORA as u32, 458 | LDEORAB = Operation_ARM64_LDEORAB as u32, 459 | LDEORAH = Operation_ARM64_LDEORAH as u32, 460 | LDEORAL = Operation_ARM64_LDEORAL as u32, 461 | LDEORALB = Operation_ARM64_LDEORALB as u32, 462 | LDEORALH = Operation_ARM64_LDEORALH as u32, 463 | LDEORB = Operation_ARM64_LDEORB as u32, 464 | LDEORH = Operation_ARM64_LDEORH as u32, 465 | LDEORL = Operation_ARM64_LDEORL as u32, 466 | LDEORLB = Operation_ARM64_LDEORLB as u32, 467 | LDEORLH = Operation_ARM64_LDEORLH as u32, 468 | LDFF1B = Operation_ARM64_LDFF1B as u32, 469 | LDFF1D = Operation_ARM64_LDFF1D as u32, 470 | LDFF1H = Operation_ARM64_LDFF1H as u32, 471 | LDFF1SB = Operation_ARM64_LDFF1SB as u32, 472 | LDFF1SH = Operation_ARM64_LDFF1SH as u32, 473 | LDFF1SW = Operation_ARM64_LDFF1SW as u32, 474 | LDFF1W = Operation_ARM64_LDFF1W as u32, 475 | LDG = Operation_ARM64_LDG as u32, 476 | LDGM = Operation_ARM64_LDGM as u32, 477 | LDLAR = Operation_ARM64_LDLAR as u32, 478 | LDLARB = Operation_ARM64_LDLARB as u32, 479 | LDLARH = Operation_ARM64_LDLARH as u32, 480 | LDNF1B = Operation_ARM64_LDNF1B as u32, 481 | LDNF1D = Operation_ARM64_LDNF1D as u32, 482 | LDNF1H = Operation_ARM64_LDNF1H as u32, 483 | LDNF1SB = Operation_ARM64_LDNF1SB as u32, 484 | LDNF1SH = Operation_ARM64_LDNF1SH as u32, 485 | LDNF1SW = Operation_ARM64_LDNF1SW as u32, 486 | LDNF1W = Operation_ARM64_LDNF1W as u32, 487 | LDNP = Operation_ARM64_LDNP as u32, 488 | LDNT1B = Operation_ARM64_LDNT1B as u32, 489 | LDNT1D = Operation_ARM64_LDNT1D as u32, 490 | LDNT1H = Operation_ARM64_LDNT1H as u32, 491 | LDNT1SB = Operation_ARM64_LDNT1SB as u32, 492 | LDNT1SH = Operation_ARM64_LDNT1SH as u32, 493 | LDNT1SW = Operation_ARM64_LDNT1SW as u32, 494 | LDNT1W = Operation_ARM64_LDNT1W as u32, 495 | LDP = Operation_ARM64_LDP as u32, 496 | LDPSW = Operation_ARM64_LDPSW as u32, 497 | LDR = Operation_ARM64_LDR as u32, 498 | LDRAA = Operation_ARM64_LDRAA as u32, 499 | LDRAB = Operation_ARM64_LDRAB as u32, 500 | LDRB = Operation_ARM64_LDRB as u32, 501 | LDRH = Operation_ARM64_LDRH as u32, 502 | LDRSB = Operation_ARM64_LDRSB as u32, 503 | LDRSH = Operation_ARM64_LDRSH as u32, 504 | LDRSW = Operation_ARM64_LDRSW as u32, 505 | LDSET = Operation_ARM64_LDSET as u32, 506 | LDSETA = Operation_ARM64_LDSETA as u32, 507 | LDSETAB = Operation_ARM64_LDSETAB as u32, 508 | LDSETAH = Operation_ARM64_LDSETAH as u32, 509 | LDSETAL = Operation_ARM64_LDSETAL as u32, 510 | LDSETALB = Operation_ARM64_LDSETALB as u32, 511 | LDSETALH = Operation_ARM64_LDSETALH as u32, 512 | LDSETB = Operation_ARM64_LDSETB as u32, 513 | LDSETH = Operation_ARM64_LDSETH as u32, 514 | LDSETL = Operation_ARM64_LDSETL as u32, 515 | LDSETLB = Operation_ARM64_LDSETLB as u32, 516 | LDSETLH = Operation_ARM64_LDSETLH as u32, 517 | LDSMAX = Operation_ARM64_LDSMAX as u32, 518 | LDSMAXA = Operation_ARM64_LDSMAXA as u32, 519 | LDSMAXAB = Operation_ARM64_LDSMAXAB as u32, 520 | LDSMAXAH = Operation_ARM64_LDSMAXAH as u32, 521 | LDSMAXAL = Operation_ARM64_LDSMAXAL as u32, 522 | LDSMAXALB = Operation_ARM64_LDSMAXALB as u32, 523 | LDSMAXALH = Operation_ARM64_LDSMAXALH as u32, 524 | LDSMAXB = Operation_ARM64_LDSMAXB as u32, 525 | LDSMAXH = Operation_ARM64_LDSMAXH as u32, 526 | LDSMAXL = Operation_ARM64_LDSMAXL as u32, 527 | LDSMAXLB = Operation_ARM64_LDSMAXLB as u32, 528 | LDSMAXLH = Operation_ARM64_LDSMAXLH as u32, 529 | LDSMIN = Operation_ARM64_LDSMIN as u32, 530 | LDSMINA = Operation_ARM64_LDSMINA as u32, 531 | LDSMINAB = Operation_ARM64_LDSMINAB as u32, 532 | LDSMINAH = Operation_ARM64_LDSMINAH as u32, 533 | LDSMINAL = Operation_ARM64_LDSMINAL as u32, 534 | LDSMINALB = Operation_ARM64_LDSMINALB as u32, 535 | LDSMINALH = Operation_ARM64_LDSMINALH as u32, 536 | LDSMINB = Operation_ARM64_LDSMINB as u32, 537 | LDSMINH = Operation_ARM64_LDSMINH as u32, 538 | LDSMINL = Operation_ARM64_LDSMINL as u32, 539 | LDSMINLB = Operation_ARM64_LDSMINLB as u32, 540 | LDSMINLH = Operation_ARM64_LDSMINLH as u32, 541 | LDTR = Operation_ARM64_LDTR as u32, 542 | LDTRB = Operation_ARM64_LDTRB as u32, 543 | LDTRH = Operation_ARM64_LDTRH as u32, 544 | LDTRSB = Operation_ARM64_LDTRSB as u32, 545 | LDTRSH = Operation_ARM64_LDTRSH as u32, 546 | LDTRSW = Operation_ARM64_LDTRSW as u32, 547 | LDUMAX = Operation_ARM64_LDUMAX as u32, 548 | LDUMAXA = Operation_ARM64_LDUMAXA as u32, 549 | LDUMAXAB = Operation_ARM64_LDUMAXAB as u32, 550 | LDUMAXAH = Operation_ARM64_LDUMAXAH as u32, 551 | LDUMAXAL = Operation_ARM64_LDUMAXAL as u32, 552 | LDUMAXALB = Operation_ARM64_LDUMAXALB as u32, 553 | LDUMAXALH = Operation_ARM64_LDUMAXALH as u32, 554 | LDUMAXB = Operation_ARM64_LDUMAXB as u32, 555 | LDUMAXH = Operation_ARM64_LDUMAXH as u32, 556 | LDUMAXL = Operation_ARM64_LDUMAXL as u32, 557 | LDUMAXLB = Operation_ARM64_LDUMAXLB as u32, 558 | LDUMAXLH = Operation_ARM64_LDUMAXLH as u32, 559 | LDUMIN = Operation_ARM64_LDUMIN as u32, 560 | LDUMINA = Operation_ARM64_LDUMINA as u32, 561 | LDUMINAB = Operation_ARM64_LDUMINAB as u32, 562 | LDUMINAH = Operation_ARM64_LDUMINAH as u32, 563 | LDUMINAL = Operation_ARM64_LDUMINAL as u32, 564 | LDUMINALB = Operation_ARM64_LDUMINALB as u32, 565 | LDUMINALH = Operation_ARM64_LDUMINALH as u32, 566 | LDUMINB = Operation_ARM64_LDUMINB as u32, 567 | LDUMINH = Operation_ARM64_LDUMINH as u32, 568 | LDUMINL = Operation_ARM64_LDUMINL as u32, 569 | LDUMINLB = Operation_ARM64_LDUMINLB as u32, 570 | LDUMINLH = Operation_ARM64_LDUMINLH as u32, 571 | LDUR = Operation_ARM64_LDUR as u32, 572 | LDURB = Operation_ARM64_LDURB as u32, 573 | LDURH = Operation_ARM64_LDURH as u32, 574 | LDURSB = Operation_ARM64_LDURSB as u32, 575 | LDURSH = Operation_ARM64_LDURSH as u32, 576 | LDURSW = Operation_ARM64_LDURSW as u32, 577 | LDXP = Operation_ARM64_LDXP as u32, 578 | LDXR = Operation_ARM64_LDXR as u32, 579 | LDXRB = Operation_ARM64_LDXRB as u32, 580 | LDXRH = Operation_ARM64_LDXRH as u32, 581 | LSL = Operation_ARM64_LSL as u32, 582 | LSLR = Operation_ARM64_LSLR as u32, 583 | LSLV = Operation_ARM64_LSLV as u32, 584 | LSR = Operation_ARM64_LSR as u32, 585 | LSRR = Operation_ARM64_LSRR as u32, 586 | LSRV = Operation_ARM64_LSRV as u32, 587 | MAD = Operation_ARM64_MAD as u32, 588 | MADD = Operation_ARM64_MADD as u32, 589 | MATCH = Operation_ARM64_MATCH as u32, 590 | MLA = Operation_ARM64_MLA as u32, 591 | MLS = Operation_ARM64_MLS as u32, 592 | MNEG = Operation_ARM64_MNEG as u32, 593 | MOV = Operation_ARM64_MOV as u32, 594 | MOVA = Operation_ARM64_MOVA as u32, 595 | MOVI = Operation_ARM64_MOVI as u32, 596 | MOVK = Operation_ARM64_MOVK as u32, 597 | MOVN = Operation_ARM64_MOVN as u32, 598 | MOVPRFX = Operation_ARM64_MOVPRFX as u32, 599 | MOVS = Operation_ARM64_MOVS as u32, 600 | MOVZ = Operation_ARM64_MOVZ as u32, 601 | MRS = Operation_ARM64_MRS as u32, 602 | MSB = Operation_ARM64_MSB as u32, 603 | MSR = Operation_ARM64_MSR as u32, 604 | MSUB = Operation_ARM64_MSUB as u32, 605 | MUL = Operation_ARM64_MUL as u32, 606 | MVN = Operation_ARM64_MVN as u32, 607 | MVNI = Operation_ARM64_MVNI as u32, 608 | NAND = Operation_ARM64_NAND as u32, 609 | NANDS = Operation_ARM64_NANDS as u32, 610 | NBSL = Operation_ARM64_NBSL as u32, 611 | NEG = Operation_ARM64_NEG as u32, 612 | NEGS = Operation_ARM64_NEGS as u32, 613 | NGC = Operation_ARM64_NGC as u32, 614 | NGCS = Operation_ARM64_NGCS as u32, 615 | NMATCH = Operation_ARM64_NMATCH as u32, 616 | NOP = Operation_ARM64_NOP as u32, 617 | NOR = Operation_ARM64_NOR as u32, 618 | NORS = Operation_ARM64_NORS as u32, 619 | NOT = Operation_ARM64_NOT as u32, 620 | NOTS = Operation_ARM64_NOTS as u32, 621 | ORN = Operation_ARM64_ORN as u32, 622 | ORNS = Operation_ARM64_ORNS as u32, 623 | ORR = Operation_ARM64_ORR as u32, 624 | ORRS = Operation_ARM64_ORRS as u32, 625 | ORV = Operation_ARM64_ORV as u32, 626 | PACDA = Operation_ARM64_PACDA as u32, 627 | PACDB = Operation_ARM64_PACDB as u32, 628 | PACDZA = Operation_ARM64_PACDZA as u32, 629 | PACDZB = Operation_ARM64_PACDZB as u32, 630 | PACGA = Operation_ARM64_PACGA as u32, 631 | PACIA = Operation_ARM64_PACIA as u32, 632 | PACIA1716 = Operation_ARM64_PACIA1716 as u32, 633 | PACIASP = Operation_ARM64_PACIASP as u32, 634 | PACIAZ = Operation_ARM64_PACIAZ as u32, 635 | PACIB = Operation_ARM64_PACIB as u32, 636 | PACIB1716 = Operation_ARM64_PACIB1716 as u32, 637 | PACIBSP = Operation_ARM64_PACIBSP as u32, 638 | PACIBZ = Operation_ARM64_PACIBZ as u32, 639 | PACIZA = Operation_ARM64_PACIZA as u32, 640 | PACIZB = Operation_ARM64_PACIZB as u32, 641 | PFALSE = Operation_ARM64_PFALSE as u32, 642 | PFIRST = Operation_ARM64_PFIRST as u32, 643 | PMUL = Operation_ARM64_PMUL as u32, 644 | PMULL = Operation_ARM64_PMULL as u32, 645 | PMULL2 = Operation_ARM64_PMULL2 as u32, 646 | PMULLB = Operation_ARM64_PMULLB as u32, 647 | PMULLT = Operation_ARM64_PMULLT as u32, 648 | PNEXT = Operation_ARM64_PNEXT as u32, 649 | PRFB = Operation_ARM64_PRFB as u32, 650 | PRFD = Operation_ARM64_PRFD as u32, 651 | PRFH = Operation_ARM64_PRFH as u32, 652 | PRFM = Operation_ARM64_PRFM as u32, 653 | PRFUM = Operation_ARM64_PRFUM as u32, 654 | PRFW = Operation_ARM64_PRFW as u32, 655 | PSB = Operation_ARM64_PSB as u32, 656 | PSSBB = Operation_ARM64_PSSBB as u32, 657 | PTEST = Operation_ARM64_PTEST as u32, 658 | PTRUE = Operation_ARM64_PTRUE as u32, 659 | PTRUES = Operation_ARM64_PTRUES as u32, 660 | PUNPKHI = Operation_ARM64_PUNPKHI as u32, 661 | PUNPKLO = Operation_ARM64_PUNPKLO as u32, 662 | RADDHN = Operation_ARM64_RADDHN as u32, 663 | RADDHN2 = Operation_ARM64_RADDHN2 as u32, 664 | RADDHNB = Operation_ARM64_RADDHNB as u32, 665 | RADDHNT = Operation_ARM64_RADDHNT as u32, 666 | RAX1 = Operation_ARM64_RAX1 as u32, 667 | RBIT = Operation_ARM64_RBIT as u32, 668 | RDFFR = Operation_ARM64_RDFFR as u32, 669 | RDFFRS = Operation_ARM64_RDFFRS as u32, 670 | RDVL = Operation_ARM64_RDVL as u32, 671 | RET = Operation_ARM64_RET as u32, 672 | RETAA = Operation_ARM64_RETAA as u32, 673 | RETAB = Operation_ARM64_RETAB as u32, 674 | REV = Operation_ARM64_REV as u32, 675 | REV16 = Operation_ARM64_REV16 as u32, 676 | REV32 = Operation_ARM64_REV32 as u32, 677 | REV64 = Operation_ARM64_REV64 as u32, 678 | REVB = Operation_ARM64_REVB as u32, 679 | REVD = Operation_ARM64_REVD as u32, 680 | REVH = Operation_ARM64_REVH as u32, 681 | REVW = Operation_ARM64_REVW as u32, 682 | RMIF = Operation_ARM64_RMIF as u32, 683 | ROR = Operation_ARM64_ROR as u32, 684 | RORV = Operation_ARM64_RORV as u32, 685 | RSHRN = Operation_ARM64_RSHRN as u32, 686 | RSHRN2 = Operation_ARM64_RSHRN2 as u32, 687 | RSHRNB = Operation_ARM64_RSHRNB as u32, 688 | RSHRNT = Operation_ARM64_RSHRNT as u32, 689 | RSUBHN = Operation_ARM64_RSUBHN as u32, 690 | RSUBHN2 = Operation_ARM64_RSUBHN2 as u32, 691 | RSUBHNB = Operation_ARM64_RSUBHNB as u32, 692 | RSUBHNT = Operation_ARM64_RSUBHNT as u32, 693 | SABA = Operation_ARM64_SABA as u32, 694 | SABAL = Operation_ARM64_SABAL as u32, 695 | SABAL2 = Operation_ARM64_SABAL2 as u32, 696 | SABALB = Operation_ARM64_SABALB as u32, 697 | SABALT = Operation_ARM64_SABALT as u32, 698 | SABD = Operation_ARM64_SABD as u32, 699 | SABDL = Operation_ARM64_SABDL as u32, 700 | SABDL2 = Operation_ARM64_SABDL2 as u32, 701 | SABDLB = Operation_ARM64_SABDLB as u32, 702 | SABDLT = Operation_ARM64_SABDLT as u32, 703 | SADALP = Operation_ARM64_SADALP as u32, 704 | SADDL = Operation_ARM64_SADDL as u32, 705 | SADDL2 = Operation_ARM64_SADDL2 as u32, 706 | SADDLB = Operation_ARM64_SADDLB as u32, 707 | SADDLBT = Operation_ARM64_SADDLBT as u32, 708 | SADDLP = Operation_ARM64_SADDLP as u32, 709 | SADDLT = Operation_ARM64_SADDLT as u32, 710 | SADDLV = Operation_ARM64_SADDLV as u32, 711 | SADDV = Operation_ARM64_SADDV as u32, 712 | SADDW = Operation_ARM64_SADDW as u32, 713 | SADDW2 = Operation_ARM64_SADDW2 as u32, 714 | SADDWB = Operation_ARM64_SADDWB as u32, 715 | SADDWT = Operation_ARM64_SADDWT as u32, 716 | SB = Operation_ARM64_SB as u32, 717 | SBC = Operation_ARM64_SBC as u32, 718 | SBCLB = Operation_ARM64_SBCLB as u32, 719 | SBCLT = Operation_ARM64_SBCLT as u32, 720 | SBCS = Operation_ARM64_SBCS as u32, 721 | SBFIZ = Operation_ARM64_SBFIZ as u32, 722 | SBFM = Operation_ARM64_SBFM as u32, 723 | SBFX = Operation_ARM64_SBFX as u32, 724 | SCLAMP = Operation_ARM64_SCLAMP as u32, 725 | SCVTF = Operation_ARM64_SCVTF as u32, 726 | SDIV = Operation_ARM64_SDIV as u32, 727 | SDIVR = Operation_ARM64_SDIVR as u32, 728 | SDOT = Operation_ARM64_SDOT as u32, 729 | SEL = Operation_ARM64_SEL as u32, 730 | SETF16 = Operation_ARM64_SETF16 as u32, 731 | SETF8 = Operation_ARM64_SETF8 as u32, 732 | SETFFR = Operation_ARM64_SETFFR as u32, 733 | SEV = Operation_ARM64_SEV as u32, 734 | SEVL = Operation_ARM64_SEVL as u32, 735 | SHA1C = Operation_ARM64_SHA1C as u32, 736 | SHA1H = Operation_ARM64_SHA1H as u32, 737 | SHA1M = Operation_ARM64_SHA1M as u32, 738 | SHA1P = Operation_ARM64_SHA1P as u32, 739 | SHA1SU0 = Operation_ARM64_SHA1SU0 as u32, 740 | SHA1SU1 = Operation_ARM64_SHA1SU1 as u32, 741 | SHA256H = Operation_ARM64_SHA256H as u32, 742 | SHA256H2 = Operation_ARM64_SHA256H2 as u32, 743 | SHA256SU0 = Operation_ARM64_SHA256SU0 as u32, 744 | SHA256SU1 = Operation_ARM64_SHA256SU1 as u32, 745 | SHA512H = Operation_ARM64_SHA512H as u32, 746 | SHA512H2 = Operation_ARM64_SHA512H2 as u32, 747 | SHA512SU0 = Operation_ARM64_SHA512SU0 as u32, 748 | SHA512SU1 = Operation_ARM64_SHA512SU1 as u32, 749 | SHADD = Operation_ARM64_SHADD as u32, 750 | SHL = Operation_ARM64_SHL as u32, 751 | SHLL = Operation_ARM64_SHLL as u32, 752 | SHLL2 = Operation_ARM64_SHLL2 as u32, 753 | SHRN = Operation_ARM64_SHRN as u32, 754 | SHRN2 = Operation_ARM64_SHRN2 as u32, 755 | SHRNB = Operation_ARM64_SHRNB as u32, 756 | SHRNT = Operation_ARM64_SHRNT as u32, 757 | SHSUB = Operation_ARM64_SHSUB as u32, 758 | SHSUBR = Operation_ARM64_SHSUBR as u32, 759 | SLI = Operation_ARM64_SLI as u32, 760 | SM3PARTW1 = Operation_ARM64_SM3PARTW1 as u32, 761 | SM3PARTW2 = Operation_ARM64_SM3PARTW2 as u32, 762 | SM3SS1 = Operation_ARM64_SM3SS1 as u32, 763 | SM3TT1A = Operation_ARM64_SM3TT1A as u32, 764 | SM3TT1B = Operation_ARM64_SM3TT1B as u32, 765 | SM3TT2A = Operation_ARM64_SM3TT2A as u32, 766 | SM3TT2B = Operation_ARM64_SM3TT2B as u32, 767 | SM4E = Operation_ARM64_SM4E as u32, 768 | SM4EKEY = Operation_ARM64_SM4EKEY as u32, 769 | SMADDL = Operation_ARM64_SMADDL as u32, 770 | SMAX = Operation_ARM64_SMAX as u32, 771 | SMAXP = Operation_ARM64_SMAXP as u32, 772 | SMAXV = Operation_ARM64_SMAXV as u32, 773 | SMC = Operation_ARM64_SMC as u32, 774 | SMIN = Operation_ARM64_SMIN as u32, 775 | SMINP = Operation_ARM64_SMINP as u32, 776 | SMINV = Operation_ARM64_SMINV as u32, 777 | SMLAL = Operation_ARM64_SMLAL as u32, 778 | SMLAL2 = Operation_ARM64_SMLAL2 as u32, 779 | SMLALB = Operation_ARM64_SMLALB as u32, 780 | SMLALT = Operation_ARM64_SMLALT as u32, 781 | SMLSL = Operation_ARM64_SMLSL as u32, 782 | SMLSL2 = Operation_ARM64_SMLSL2 as u32, 783 | SMLSLB = Operation_ARM64_SMLSLB as u32, 784 | SMLSLT = Operation_ARM64_SMLSLT as u32, 785 | SMMLA = Operation_ARM64_SMMLA as u32, 786 | SMNEGL = Operation_ARM64_SMNEGL as u32, 787 | SMOPA = Operation_ARM64_SMOPA as u32, 788 | SMOPS = Operation_ARM64_SMOPS as u32, 789 | SMOV = Operation_ARM64_SMOV as u32, 790 | SMSTART = Operation_ARM64_SMSTART as u32, 791 | SMSTOP = Operation_ARM64_SMSTOP as u32, 792 | SMSUBL = Operation_ARM64_SMSUBL as u32, 793 | SMULH = Operation_ARM64_SMULH as u32, 794 | SMULL = Operation_ARM64_SMULL as u32, 795 | SMULL2 = Operation_ARM64_SMULL2 as u32, 796 | SMULLB = Operation_ARM64_SMULLB as u32, 797 | SMULLT = Operation_ARM64_SMULLT as u32, 798 | SPLICE = Operation_ARM64_SPLICE as u32, 799 | SQABS = Operation_ARM64_SQABS as u32, 800 | SQADD = Operation_ARM64_SQADD as u32, 801 | SQCADD = Operation_ARM64_SQCADD as u32, 802 | SQDECB = Operation_ARM64_SQDECB as u32, 803 | SQDECD = Operation_ARM64_SQDECD as u32, 804 | SQDECH = Operation_ARM64_SQDECH as u32, 805 | SQDECP = Operation_ARM64_SQDECP as u32, 806 | SQDECW = Operation_ARM64_SQDECW as u32, 807 | SQDMLAL = Operation_ARM64_SQDMLAL as u32, 808 | SQDMLAL2 = Operation_ARM64_SQDMLAL2 as u32, 809 | SQDMLALB = Operation_ARM64_SQDMLALB as u32, 810 | SQDMLALBT = Operation_ARM64_SQDMLALBT as u32, 811 | SQDMLALT = Operation_ARM64_SQDMLALT as u32, 812 | SQDMLSL = Operation_ARM64_SQDMLSL as u32, 813 | SQDMLSL2 = Operation_ARM64_SQDMLSL2 as u32, 814 | SQDMLSLB = Operation_ARM64_SQDMLSLB as u32, 815 | SQDMLSLBT = Operation_ARM64_SQDMLSLBT as u32, 816 | SQDMLSLT = Operation_ARM64_SQDMLSLT as u32, 817 | SQDMULH = Operation_ARM64_SQDMULH as u32, 818 | SQDMULL = Operation_ARM64_SQDMULL as u32, 819 | SQDMULL2 = Operation_ARM64_SQDMULL2 as u32, 820 | SQDMULLB = Operation_ARM64_SQDMULLB as u32, 821 | SQDMULLT = Operation_ARM64_SQDMULLT as u32, 822 | SQINCB = Operation_ARM64_SQINCB as u32, 823 | SQINCD = Operation_ARM64_SQINCD as u32, 824 | SQINCH = Operation_ARM64_SQINCH as u32, 825 | SQINCP = Operation_ARM64_SQINCP as u32, 826 | SQINCW = Operation_ARM64_SQINCW as u32, 827 | SQNEG = Operation_ARM64_SQNEG as u32, 828 | SQRDCMLAH = Operation_ARM64_SQRDCMLAH as u32, 829 | SQRDMLAH = Operation_ARM64_SQRDMLAH as u32, 830 | SQRDMLSH = Operation_ARM64_SQRDMLSH as u32, 831 | SQRDMULH = Operation_ARM64_SQRDMULH as u32, 832 | SQRSHL = Operation_ARM64_SQRSHL as u32, 833 | SQRSHLR = Operation_ARM64_SQRSHLR as u32, 834 | SQRSHRN = Operation_ARM64_SQRSHRN as u32, 835 | SQRSHRN2 = Operation_ARM64_SQRSHRN2 as u32, 836 | SQRSHRNB = Operation_ARM64_SQRSHRNB as u32, 837 | SQRSHRNT = Operation_ARM64_SQRSHRNT as u32, 838 | SQRSHRUN = Operation_ARM64_SQRSHRUN as u32, 839 | SQRSHRUN2 = Operation_ARM64_SQRSHRUN2 as u32, 840 | SQRSHRUNB = Operation_ARM64_SQRSHRUNB as u32, 841 | SQRSHRUNT = Operation_ARM64_SQRSHRUNT as u32, 842 | SQSHL = Operation_ARM64_SQSHL as u32, 843 | SQSHLR = Operation_ARM64_SQSHLR as u32, 844 | SQSHLU = Operation_ARM64_SQSHLU as u32, 845 | SQSHRN = Operation_ARM64_SQSHRN as u32, 846 | SQSHRN2 = Operation_ARM64_SQSHRN2 as u32, 847 | SQSHRNB = Operation_ARM64_SQSHRNB as u32, 848 | SQSHRNT = Operation_ARM64_SQSHRNT as u32, 849 | SQSHRUN = Operation_ARM64_SQSHRUN as u32, 850 | SQSHRUN2 = Operation_ARM64_SQSHRUN2 as u32, 851 | SQSHRUNB = Operation_ARM64_SQSHRUNB as u32, 852 | SQSHRUNT = Operation_ARM64_SQSHRUNT as u32, 853 | SQSUB = Operation_ARM64_SQSUB as u32, 854 | SQSUBR = Operation_ARM64_SQSUBR as u32, 855 | SQXTN = Operation_ARM64_SQXTN as u32, 856 | SQXTN2 = Operation_ARM64_SQXTN2 as u32, 857 | SQXTNB = Operation_ARM64_SQXTNB as u32, 858 | SQXTNT = Operation_ARM64_SQXTNT as u32, 859 | SQXTUN = Operation_ARM64_SQXTUN as u32, 860 | SQXTUN2 = Operation_ARM64_SQXTUN2 as u32, 861 | SQXTUNB = Operation_ARM64_SQXTUNB as u32, 862 | SQXTUNT = Operation_ARM64_SQXTUNT as u32, 863 | SRHADD = Operation_ARM64_SRHADD as u32, 864 | SRI = Operation_ARM64_SRI as u32, 865 | SRSHL = Operation_ARM64_SRSHL as u32, 866 | SRSHLR = Operation_ARM64_SRSHLR as u32, 867 | SRSHR = Operation_ARM64_SRSHR as u32, 868 | SRSRA = Operation_ARM64_SRSRA as u32, 869 | SSBB = Operation_ARM64_SSBB as u32, 870 | SSHL = Operation_ARM64_SSHL as u32, 871 | SSHLL = Operation_ARM64_SSHLL as u32, 872 | SSHLL2 = Operation_ARM64_SSHLL2 as u32, 873 | SSHLLB = Operation_ARM64_SSHLLB as u32, 874 | SSHLLT = Operation_ARM64_SSHLLT as u32, 875 | SSHR = Operation_ARM64_SSHR as u32, 876 | SSRA = Operation_ARM64_SSRA as u32, 877 | SSUBL = Operation_ARM64_SSUBL as u32, 878 | SSUBL2 = Operation_ARM64_SSUBL2 as u32, 879 | SSUBLB = Operation_ARM64_SSUBLB as u32, 880 | SSUBLBT = Operation_ARM64_SSUBLBT as u32, 881 | SSUBLT = Operation_ARM64_SSUBLT as u32, 882 | SSUBLTB = Operation_ARM64_SSUBLTB as u32, 883 | SSUBW = Operation_ARM64_SSUBW as u32, 884 | SSUBW2 = Operation_ARM64_SSUBW2 as u32, 885 | SSUBWB = Operation_ARM64_SSUBWB as u32, 886 | SSUBWT = Operation_ARM64_SSUBWT as u32, 887 | ST1 = Operation_ARM64_ST1 as u32, 888 | ST1B = Operation_ARM64_ST1B as u32, 889 | ST1D = Operation_ARM64_ST1D as u32, 890 | ST1H = Operation_ARM64_ST1H as u32, 891 | ST1Q = Operation_ARM64_ST1Q as u32, 892 | ST1W = Operation_ARM64_ST1W as u32, 893 | ST2 = Operation_ARM64_ST2 as u32, 894 | ST2B = Operation_ARM64_ST2B as u32, 895 | ST2D = Operation_ARM64_ST2D as u32, 896 | ST2G = Operation_ARM64_ST2G as u32, 897 | ST2H = Operation_ARM64_ST2H as u32, 898 | ST2W = Operation_ARM64_ST2W as u32, 899 | ST3 = Operation_ARM64_ST3 as u32, 900 | ST3B = Operation_ARM64_ST3B as u32, 901 | ST3D = Operation_ARM64_ST3D as u32, 902 | ST3H = Operation_ARM64_ST3H as u32, 903 | ST3W = Operation_ARM64_ST3W as u32, 904 | ST4 = Operation_ARM64_ST4 as u32, 905 | ST4B = Operation_ARM64_ST4B as u32, 906 | ST4D = Operation_ARM64_ST4D as u32, 907 | ST4H = Operation_ARM64_ST4H as u32, 908 | ST4W = Operation_ARM64_ST4W as u32, 909 | ST64B = Operation_ARM64_ST64B as u32, 910 | ST64BV = Operation_ARM64_ST64BV as u32, 911 | ST64BV0 = Operation_ARM64_ST64BV0 as u32, 912 | STADD = Operation_ARM64_STADD as u32, 913 | STADDB = Operation_ARM64_STADDB as u32, 914 | STADDH = Operation_ARM64_STADDH as u32, 915 | STADDL = Operation_ARM64_STADDL as u32, 916 | STADDLB = Operation_ARM64_STADDLB as u32, 917 | STADDLH = Operation_ARM64_STADDLH as u32, 918 | STCLR = Operation_ARM64_STCLR as u32, 919 | STCLRB = Operation_ARM64_STCLRB as u32, 920 | STCLRH = Operation_ARM64_STCLRH as u32, 921 | STCLRL = Operation_ARM64_STCLRL as u32, 922 | STCLRLB = Operation_ARM64_STCLRLB as u32, 923 | STCLRLH = Operation_ARM64_STCLRLH as u32, 924 | STEOR = Operation_ARM64_STEOR as u32, 925 | STEORB = Operation_ARM64_STEORB as u32, 926 | STEORH = Operation_ARM64_STEORH as u32, 927 | STEORL = Operation_ARM64_STEORL as u32, 928 | STEORLB = Operation_ARM64_STEORLB as u32, 929 | STEORLH = Operation_ARM64_STEORLH as u32, 930 | STG = Operation_ARM64_STG as u32, 931 | STGM = Operation_ARM64_STGM as u32, 932 | STGP = Operation_ARM64_STGP as u32, 933 | STLLR = Operation_ARM64_STLLR as u32, 934 | STLLRB = Operation_ARM64_STLLRB as u32, 935 | STLLRH = Operation_ARM64_STLLRH as u32, 936 | STLR = Operation_ARM64_STLR as u32, 937 | STLRB = Operation_ARM64_STLRB as u32, 938 | STLRH = Operation_ARM64_STLRH as u32, 939 | STLUR = Operation_ARM64_STLUR as u32, 940 | STLURB = Operation_ARM64_STLURB as u32, 941 | STLURH = Operation_ARM64_STLURH as u32, 942 | STLXP = Operation_ARM64_STLXP as u32, 943 | STLXR = Operation_ARM64_STLXR as u32, 944 | STLXRB = Operation_ARM64_STLXRB as u32, 945 | STLXRH = Operation_ARM64_STLXRH as u32, 946 | STNP = Operation_ARM64_STNP as u32, 947 | STNT1B = Operation_ARM64_STNT1B as u32, 948 | STNT1D = Operation_ARM64_STNT1D as u32, 949 | STNT1H = Operation_ARM64_STNT1H as u32, 950 | STNT1W = Operation_ARM64_STNT1W as u32, 951 | STP = Operation_ARM64_STP as u32, 952 | STR = Operation_ARM64_STR as u32, 953 | STRB = Operation_ARM64_STRB as u32, 954 | STRH = Operation_ARM64_STRH as u32, 955 | STSET = Operation_ARM64_STSET as u32, 956 | STSETB = Operation_ARM64_STSETB as u32, 957 | STSETH = Operation_ARM64_STSETH as u32, 958 | STSETL = Operation_ARM64_STSETL as u32, 959 | STSETLB = Operation_ARM64_STSETLB as u32, 960 | STSETLH = Operation_ARM64_STSETLH as u32, 961 | STSMAX = Operation_ARM64_STSMAX as u32, 962 | STSMAXB = Operation_ARM64_STSMAXB as u32, 963 | STSMAXH = Operation_ARM64_STSMAXH as u32, 964 | STSMAXL = Operation_ARM64_STSMAXL as u32, 965 | STSMAXLB = Operation_ARM64_STSMAXLB as u32, 966 | STSMAXLH = Operation_ARM64_STSMAXLH as u32, 967 | STSMIN = Operation_ARM64_STSMIN as u32, 968 | STSMINB = Operation_ARM64_STSMINB as u32, 969 | STSMINH = Operation_ARM64_STSMINH as u32, 970 | STSMINL = Operation_ARM64_STSMINL as u32, 971 | STSMINLB = Operation_ARM64_STSMINLB as u32, 972 | STSMINLH = Operation_ARM64_STSMINLH as u32, 973 | STTR = Operation_ARM64_STTR as u32, 974 | STTRB = Operation_ARM64_STTRB as u32, 975 | STTRH = Operation_ARM64_STTRH as u32, 976 | STUMAX = Operation_ARM64_STUMAX as u32, 977 | STUMAXB = Operation_ARM64_STUMAXB as u32, 978 | STUMAXH = Operation_ARM64_STUMAXH as u32, 979 | STUMAXL = Operation_ARM64_STUMAXL as u32, 980 | STUMAXLB = Operation_ARM64_STUMAXLB as u32, 981 | STUMAXLH = Operation_ARM64_STUMAXLH as u32, 982 | STUMIN = Operation_ARM64_STUMIN as u32, 983 | STUMINB = Operation_ARM64_STUMINB as u32, 984 | STUMINH = Operation_ARM64_STUMINH as u32, 985 | STUMINL = Operation_ARM64_STUMINL as u32, 986 | STUMINLB = Operation_ARM64_STUMINLB as u32, 987 | STUMINLH = Operation_ARM64_STUMINLH as u32, 988 | STUR = Operation_ARM64_STUR as u32, 989 | STURB = Operation_ARM64_STURB as u32, 990 | STURH = Operation_ARM64_STURH as u32, 991 | STXP = Operation_ARM64_STXP as u32, 992 | STXR = Operation_ARM64_STXR as u32, 993 | STXRB = Operation_ARM64_STXRB as u32, 994 | STXRH = Operation_ARM64_STXRH as u32, 995 | STZ2G = Operation_ARM64_STZ2G as u32, 996 | STZG = Operation_ARM64_STZG as u32, 997 | STZGM = Operation_ARM64_STZGM as u32, 998 | SUB = Operation_ARM64_SUB as u32, 999 | SUBG = Operation_ARM64_SUBG as u32, 1000 | SUBHN = Operation_ARM64_SUBHN as u32, 1001 | SUBHN2 = Operation_ARM64_SUBHN2 as u32, 1002 | SUBHNB = Operation_ARM64_SUBHNB as u32, 1003 | SUBHNT = Operation_ARM64_SUBHNT as u32, 1004 | SUBP = Operation_ARM64_SUBP as u32, 1005 | SUBPS = Operation_ARM64_SUBPS as u32, 1006 | SUBR = Operation_ARM64_SUBR as u32, 1007 | SUBS = Operation_ARM64_SUBS as u32, 1008 | SUDOT = Operation_ARM64_SUDOT as u32, 1009 | SUMOPA = Operation_ARM64_SUMOPA as u32, 1010 | SUMOPS = Operation_ARM64_SUMOPS as u32, 1011 | SUNPKHI = Operation_ARM64_SUNPKHI as u32, 1012 | SUNPKLO = Operation_ARM64_SUNPKLO as u32, 1013 | SUQADD = Operation_ARM64_SUQADD as u32, 1014 | SVC = Operation_ARM64_SVC as u32, 1015 | SWP = Operation_ARM64_SWP as u32, 1016 | SWPA = Operation_ARM64_SWPA as u32, 1017 | SWPAB = Operation_ARM64_SWPAB as u32, 1018 | SWPAH = Operation_ARM64_SWPAH as u32, 1019 | SWPAL = Operation_ARM64_SWPAL as u32, 1020 | SWPALB = Operation_ARM64_SWPALB as u32, 1021 | SWPALH = Operation_ARM64_SWPALH as u32, 1022 | SWPB = Operation_ARM64_SWPB as u32, 1023 | SWPH = Operation_ARM64_SWPH as u32, 1024 | SWPL = Operation_ARM64_SWPL as u32, 1025 | SWPLB = Operation_ARM64_SWPLB as u32, 1026 | SWPLH = Operation_ARM64_SWPLH as u32, 1027 | SXTB = Operation_ARM64_SXTB as u32, 1028 | SXTH = Operation_ARM64_SXTH as u32, 1029 | SXTL = Operation_ARM64_SXTL as u32, 1030 | SXTL2 = Operation_ARM64_SXTL2 as u32, 1031 | SXTW = Operation_ARM64_SXTW as u32, 1032 | SYS = Operation_ARM64_SYS as u32, 1033 | SYSL = Operation_ARM64_SYSL as u32, 1034 | TBL = Operation_ARM64_TBL as u32, 1035 | TBNZ = Operation_ARM64_TBNZ as u32, 1036 | TBX = Operation_ARM64_TBX as u32, 1037 | TBZ = Operation_ARM64_TBZ as u32, 1038 | TCANCEL = Operation_ARM64_TCANCEL as u32, 1039 | TCOMMIT = Operation_ARM64_TCOMMIT as u32, 1040 | TLBI = Operation_ARM64_TLBI as u32, 1041 | TRN1 = Operation_ARM64_TRN1 as u32, 1042 | TRN2 = Operation_ARM64_TRN2 as u32, 1043 | TSB = Operation_ARM64_TSB as u32, 1044 | TST = Operation_ARM64_TST as u32, 1045 | TSTART = Operation_ARM64_TSTART as u32, 1046 | TTEST = Operation_ARM64_TTEST as u32, 1047 | UABA = Operation_ARM64_UABA as u32, 1048 | UABAL = Operation_ARM64_UABAL as u32, 1049 | UABAL2 = Operation_ARM64_UABAL2 as u32, 1050 | UABALB = Operation_ARM64_UABALB as u32, 1051 | UABALT = Operation_ARM64_UABALT as u32, 1052 | UABD = Operation_ARM64_UABD as u32, 1053 | UABDL = Operation_ARM64_UABDL as u32, 1054 | UABDL2 = Operation_ARM64_UABDL2 as u32, 1055 | UABDLB = Operation_ARM64_UABDLB as u32, 1056 | UABDLT = Operation_ARM64_UABDLT as u32, 1057 | UADALP = Operation_ARM64_UADALP as u32, 1058 | UADDL = Operation_ARM64_UADDL as u32, 1059 | UADDL2 = Operation_ARM64_UADDL2 as u32, 1060 | UADDLB = Operation_ARM64_UADDLB as u32, 1061 | UADDLP = Operation_ARM64_UADDLP as u32, 1062 | UADDLT = Operation_ARM64_UADDLT as u32, 1063 | UADDLV = Operation_ARM64_UADDLV as u32, 1064 | UADDV = Operation_ARM64_UADDV as u32, 1065 | UADDW = Operation_ARM64_UADDW as u32, 1066 | UADDW2 = Operation_ARM64_UADDW2 as u32, 1067 | UADDWB = Operation_ARM64_UADDWB as u32, 1068 | UADDWT = Operation_ARM64_UADDWT as u32, 1069 | UBFIZ = Operation_ARM64_UBFIZ as u32, 1070 | UBFM = Operation_ARM64_UBFM as u32, 1071 | UBFX = Operation_ARM64_UBFX as u32, 1072 | UCLAMP = Operation_ARM64_UCLAMP as u32, 1073 | UCVTF = Operation_ARM64_UCVTF as u32, 1074 | UDF = Operation_ARM64_UDF as u32, 1075 | UDIV = Operation_ARM64_UDIV as u32, 1076 | UDIVR = Operation_ARM64_UDIVR as u32, 1077 | UDOT = Operation_ARM64_UDOT as u32, 1078 | UHADD = Operation_ARM64_UHADD as u32, 1079 | UHSUB = Operation_ARM64_UHSUB as u32, 1080 | UHSUBR = Operation_ARM64_UHSUBR as u32, 1081 | UMADDL = Operation_ARM64_UMADDL as u32, 1082 | UMAX = Operation_ARM64_UMAX as u32, 1083 | UMAXP = Operation_ARM64_UMAXP as u32, 1084 | UMAXV = Operation_ARM64_UMAXV as u32, 1085 | UMIN = Operation_ARM64_UMIN as u32, 1086 | UMINP = Operation_ARM64_UMINP as u32, 1087 | UMINV = Operation_ARM64_UMINV as u32, 1088 | UMLAL = Operation_ARM64_UMLAL as u32, 1089 | UMLAL2 = Operation_ARM64_UMLAL2 as u32, 1090 | UMLALB = Operation_ARM64_UMLALB as u32, 1091 | UMLALT = Operation_ARM64_UMLALT as u32, 1092 | UMLSL = Operation_ARM64_UMLSL as u32, 1093 | UMLSL2 = Operation_ARM64_UMLSL2 as u32, 1094 | UMLSLB = Operation_ARM64_UMLSLB as u32, 1095 | UMLSLT = Operation_ARM64_UMLSLT as u32, 1096 | UMMLA = Operation_ARM64_UMMLA as u32, 1097 | UMNEGL = Operation_ARM64_UMNEGL as u32, 1098 | UMOPA = Operation_ARM64_UMOPA as u32, 1099 | UMOPS = Operation_ARM64_UMOPS as u32, 1100 | UMOV = Operation_ARM64_UMOV as u32, 1101 | UMSUBL = Operation_ARM64_UMSUBL as u32, 1102 | UMULH = Operation_ARM64_UMULH as u32, 1103 | UMULL = Operation_ARM64_UMULL as u32, 1104 | UMULL2 = Operation_ARM64_UMULL2 as u32, 1105 | UMULLB = Operation_ARM64_UMULLB as u32, 1106 | UMULLT = Operation_ARM64_UMULLT as u32, 1107 | UQADD = Operation_ARM64_UQADD as u32, 1108 | UQDECB = Operation_ARM64_UQDECB as u32, 1109 | UQDECD = Operation_ARM64_UQDECD as u32, 1110 | UQDECH = Operation_ARM64_UQDECH as u32, 1111 | UQDECP = Operation_ARM64_UQDECP as u32, 1112 | UQDECW = Operation_ARM64_UQDECW as u32, 1113 | UQINCB = Operation_ARM64_UQINCB as u32, 1114 | UQINCD = Operation_ARM64_UQINCD as u32, 1115 | UQINCH = Operation_ARM64_UQINCH as u32, 1116 | UQINCP = Operation_ARM64_UQINCP as u32, 1117 | UQINCW = Operation_ARM64_UQINCW as u32, 1118 | UQRSHL = Operation_ARM64_UQRSHL as u32, 1119 | UQRSHLR = Operation_ARM64_UQRSHLR as u32, 1120 | UQRSHRN = Operation_ARM64_UQRSHRN as u32, 1121 | UQRSHRN2 = Operation_ARM64_UQRSHRN2 as u32, 1122 | UQRSHRNB = Operation_ARM64_UQRSHRNB as u32, 1123 | UQRSHRNT = Operation_ARM64_UQRSHRNT as u32, 1124 | UQSHL = Operation_ARM64_UQSHL as u32, 1125 | UQSHLR = Operation_ARM64_UQSHLR as u32, 1126 | UQSHRN = Operation_ARM64_UQSHRN as u32, 1127 | UQSHRN2 = Operation_ARM64_UQSHRN2 as u32, 1128 | UQSHRNB = Operation_ARM64_UQSHRNB as u32, 1129 | UQSHRNT = Operation_ARM64_UQSHRNT as u32, 1130 | UQSUB = Operation_ARM64_UQSUB as u32, 1131 | UQSUBR = Operation_ARM64_UQSUBR as u32, 1132 | UQXTN = Operation_ARM64_UQXTN as u32, 1133 | UQXTN2 = Operation_ARM64_UQXTN2 as u32, 1134 | UQXTNB = Operation_ARM64_UQXTNB as u32, 1135 | UQXTNT = Operation_ARM64_UQXTNT as u32, 1136 | URECPE = Operation_ARM64_URECPE as u32, 1137 | URHADD = Operation_ARM64_URHADD as u32, 1138 | URSHL = Operation_ARM64_URSHL as u32, 1139 | URSHLR = Operation_ARM64_URSHLR as u32, 1140 | URSHR = Operation_ARM64_URSHR as u32, 1141 | URSQRTE = Operation_ARM64_URSQRTE as u32, 1142 | URSRA = Operation_ARM64_URSRA as u32, 1143 | USDOT = Operation_ARM64_USDOT as u32, 1144 | USHL = Operation_ARM64_USHL as u32, 1145 | USHLL = Operation_ARM64_USHLL as u32, 1146 | USHLL2 = Operation_ARM64_USHLL2 as u32, 1147 | USHLLB = Operation_ARM64_USHLLB as u32, 1148 | USHLLT = Operation_ARM64_USHLLT as u32, 1149 | USHR = Operation_ARM64_USHR as u32, 1150 | USMMLA = Operation_ARM64_USMMLA as u32, 1151 | USMOPA = Operation_ARM64_USMOPA as u32, 1152 | USMOPS = Operation_ARM64_USMOPS as u32, 1153 | USQADD = Operation_ARM64_USQADD as u32, 1154 | USRA = Operation_ARM64_USRA as u32, 1155 | USUBL = Operation_ARM64_USUBL as u32, 1156 | USUBL2 = Operation_ARM64_USUBL2 as u32, 1157 | USUBLB = Operation_ARM64_USUBLB as u32, 1158 | USUBLT = Operation_ARM64_USUBLT as u32, 1159 | USUBW = Operation_ARM64_USUBW as u32, 1160 | USUBW2 = Operation_ARM64_USUBW2 as u32, 1161 | USUBWB = Operation_ARM64_USUBWB as u32, 1162 | USUBWT = Operation_ARM64_USUBWT as u32, 1163 | UUNPKHI = Operation_ARM64_UUNPKHI as u32, 1164 | UUNPKLO = Operation_ARM64_UUNPKLO as u32, 1165 | UXTB = Operation_ARM64_UXTB as u32, 1166 | UXTH = Operation_ARM64_UXTH as u32, 1167 | UXTL = Operation_ARM64_UXTL as u32, 1168 | UXTL2 = Operation_ARM64_UXTL2 as u32, 1169 | UXTW = Operation_ARM64_UXTW as u32, 1170 | UZP1 = Operation_ARM64_UZP1 as u32, 1171 | UZP2 = Operation_ARM64_UZP2 as u32, 1172 | WFE = Operation_ARM64_WFE as u32, 1173 | WFET = Operation_ARM64_WFET as u32, 1174 | WFI = Operation_ARM64_WFI as u32, 1175 | WFIT = Operation_ARM64_WFIT as u32, 1176 | WHILEGE = Operation_ARM64_WHILEGE as u32, 1177 | WHILEGT = Operation_ARM64_WHILEGT as u32, 1178 | WHILEHI = Operation_ARM64_WHILEHI as u32, 1179 | WHILEHS = Operation_ARM64_WHILEHS as u32, 1180 | WHILELE = Operation_ARM64_WHILELE as u32, 1181 | WHILELO = Operation_ARM64_WHILELO as u32, 1182 | WHILELS = Operation_ARM64_WHILELS as u32, 1183 | WHILELT = Operation_ARM64_WHILELT as u32, 1184 | WHILERW = Operation_ARM64_WHILERW as u32, 1185 | WHILEWR = Operation_ARM64_WHILEWR as u32, 1186 | WRFFR = Operation_ARM64_WRFFR as u32, 1187 | XAFLAG = Operation_ARM64_XAFLAG as u32, 1188 | XAR = Operation_ARM64_XAR as u32, 1189 | XPACD = Operation_ARM64_XPACD as u32, 1190 | XPACI = Operation_ARM64_XPACI as u32, 1191 | XPACLRI = Operation_ARM64_XPACLRI as u32, 1192 | XTN = Operation_ARM64_XTN as u32, 1193 | XTN2 = Operation_ARM64_XTN2 as u32, 1194 | YIELD = Operation_ARM64_YIELD as u32, 1195 | ZERO = Operation_ARM64_ZERO as u32, 1196 | ZIP1 = Operation_ARM64_ZIP1 as u32, 1197 | ZIP2 = Operation_ARM64_ZIP2 as u32, 1198 | } 1199 | 1200 | // this is a guard to try to detect if new instructions get added 1201 | const_assert_eq!(Operation_ARM64_ZIP2, 1183); 1202 | 1203 | impl Op { 1204 | /// Get the operation name 1205 | /// 1206 | /// This is an alias for the instruction mnemonic 1207 | /// 1208 | /// # Examples 1209 | /// ``` 1210 | /// use bad64::{decode, Op}; 1211 | /// 1212 | /// // nop 1213 | /// let decoded = decode(0xd503201f, 0x1000).unwrap(); 1214 | /// 1215 | /// assert_eq!(decoded.op(), Op::NOP); 1216 | /// assert_eq!(decoded.op().mnem(), "nop"); 1217 | /// ``` 1218 | pub fn mnem(&self) -> &'static str { 1219 | #[cfg(target_os = "windows")] 1220 | { 1221 | unsafe { CStr::from_ptr(operation_to_str(self.to_i32().unwrap()) as _) } 1222 | .to_str() 1223 | .unwrap() 1224 | } 1225 | #[cfg(not(target_os = "windows"))] 1226 | { 1227 | unsafe { CStr::from_ptr(operation_to_str(self.to_u32().unwrap()) as _) } 1228 | .to_str() 1229 | .unwrap() 1230 | } 1231 | } 1232 | } 1233 | 1234 | impl fmt::Display for Op { 1235 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 1236 | write!(f, "{}", self.mnem()) 1237 | } 1238 | } 1239 | -------------------------------------------------------------------------------- /src/operand.rs: -------------------------------------------------------------------------------- 1 | use core::convert::TryFrom; 2 | use core::fmt; 3 | 4 | use bad64_sys::*; 5 | use cstr_core::CStr; 6 | use num_traits::FromPrimitive; 7 | 8 | use crate::ArrSpec; 9 | use crate::Condition; 10 | use crate::Reg; 11 | use crate::Shift; 12 | use crate::SysReg; 13 | 14 | /// A slice indicator 15 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)] 16 | pub enum SliceIndicator { 17 | Horizontal, 18 | Vertical, 19 | } 20 | 21 | #[allow(non_upper_case_globals)] 22 | #[doc(hidden)] 23 | impl TryFrom<&bad64_sys::InstructionOperand> for SliceIndicator { 24 | type Error = (); 25 | 26 | fn try_from(oo: &bad64_sys::InstructionOperand) -> Result { 27 | match oo.slice { 28 | SliceIndicator_SLICE_NONE => Err(()), 29 | SliceIndicator_SLICE_HORIZONTAL => Ok(Self::Horizontal), 30 | SliceIndicator_SLICE_VERTICAL => Ok(Self::Vertical), 31 | _ => Err(()), 32 | } 33 | } 34 | } 35 | 36 | impl fmt::Display for SliceIndicator { 37 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 38 | match *self { 39 | Self::Horizontal => write!(f, "H"), 40 | Self::Vertical => write!(f, "V"), 41 | } 42 | } 43 | } 44 | 45 | /// An instruction immediate 46 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)] 47 | pub enum Imm { 48 | Signed(i64), 49 | Unsigned(u64), 50 | } 51 | 52 | impl fmt::Display for Imm { 53 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 54 | match *self { 55 | Self::Signed(imm) => write!(f, "{:#x}", imm), 56 | Self::Unsigned(imm) => write!(f, "{:#x}", imm), 57 | } 58 | } 59 | } 60 | 61 | impl From<&bad64_sys::InstructionOperand> for Imm { 62 | fn from(oo: &bad64_sys::InstructionOperand) -> Self { 63 | if oo.signedImm { 64 | Self::Signed(oo.immediate as i64) 65 | } else { 66 | Self::Unsigned(oo.immediate) 67 | } 68 | } 69 | } 70 | 71 | /// An instruction operand 72 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq)] 73 | pub enum Operand { 74 | Imm32 { 75 | imm: Imm, 76 | shift: Option, 77 | }, 78 | Imm64 { 79 | imm: Imm, 80 | shift: Option, 81 | }, 82 | FImm32(u32), 83 | ShiftReg { 84 | reg: Reg, 85 | shift: Shift, 86 | }, 87 | QualReg { 88 | reg: Reg, 89 | qual: char, 90 | }, 91 | Reg { 92 | reg: Reg, 93 | arrspec: Option, 94 | }, 95 | MultiReg { 96 | regs: [Option; MAX_REGISTERS as usize], 97 | arrspec: Option, 98 | }, 99 | SysReg(SysReg), 100 | MemReg(Reg), 101 | MemOffset { 102 | reg: Reg, 103 | offset: Imm, 104 | mul_vl: bool, 105 | arrspec: Option, 106 | }, 107 | MemPreIdx { 108 | reg: Reg, 109 | imm: Imm, 110 | }, 111 | MemPostIdxReg([Reg; 2]), 112 | MemPostIdxImm { 113 | reg: Reg, 114 | imm: Imm, 115 | }, 116 | MemExt { 117 | regs: [Reg; 2], 118 | shift: Option, 119 | arrspec: Option, 120 | }, 121 | SmeTile { 122 | tile: u16, 123 | slice: Option, 124 | arrspec: Option, 125 | reg: Option, 126 | imm: Imm, 127 | }, 128 | AccumArray { 129 | reg: Reg, 130 | imm: Imm, 131 | }, 132 | IndexedElement { 133 | regs: [Reg; 2], 134 | arrspec: Option, 135 | imm: Imm, 136 | }, 137 | Label(Imm), 138 | ImplSpec { 139 | o0: u8, 140 | o1: u8, 141 | cm: u8, 142 | cn: u8, 143 | o2: u8, 144 | }, 145 | Cond(Condition), 146 | Name([u8; MAX_NAME as usize]), 147 | StrImm { 148 | str: [u8; MAX_NAME as usize], 149 | imm: u64, 150 | }, 151 | } 152 | 153 | #[allow(non_upper_case_globals)] 154 | #[doc(hidden)] 155 | impl TryFrom<&bad64_sys::InstructionOperand> for Operand { 156 | type Error = (); 157 | 158 | fn try_from(oo: &bad64_sys::InstructionOperand) -> Result { 159 | match oo.operandClass { 160 | OperandClass::IMM32 => Ok(Self::Imm32 { 161 | imm: Imm::from(oo), 162 | shift: Shift::try_from(oo).ok(), 163 | }), 164 | OperandClass::IMM64 => Ok(Self::Imm64 { 165 | imm: Imm::from(oo), 166 | shift: Shift::try_from(oo).ok(), 167 | }), 168 | OperandClass::FIMM32 => Ok(Self::FImm32(oo.immediate as u32)), 169 | OperandClass::REG => { 170 | let reg = Reg::from_u32(oo.reg[0] as u32).unwrap(); 171 | 172 | if let Ok(shift) = Shift::try_from(oo) { 173 | return Ok(Self::ShiftReg { reg, shift }); 174 | } 175 | 176 | if oo.pred_qual != 0 { 177 | assert!(reg.is_pred()); 178 | return Ok(Self::QualReg { 179 | reg, 180 | qual: char::from_u32(oo.pred_qual as u32).unwrap(), 181 | }); 182 | } 183 | 184 | let arrspec = ArrSpec::try_from(oo).ok(); 185 | 186 | Ok(Self::Reg { reg, arrspec }) 187 | } 188 | OperandClass::MULTI_REG => { 189 | let mut regs = [None; MAX_REGISTERS as usize]; 190 | 191 | for (n, regno) in oo.reg.iter().enumerate() { 192 | regs[n] = Reg::from_u32(*regno as u32); 193 | } 194 | 195 | let arrspec = ArrSpec::try_from(oo).ok(); 196 | 197 | Ok(Self::MultiReg { regs, arrspec }) 198 | } 199 | OperandClass::SYS_REG => Ok(Self::SysReg(SysReg::from_u32(oo.sysreg as u32).unwrap())), 200 | OperandClass::MEM_REG => Ok(Self::MemReg(Reg::from_u32(oo.reg[0] as u32).unwrap())), 201 | OperandClass::STR_IMM => Ok(Self::StrImm { 202 | str: unsafe { core::mem::transmute(oo.name) }, 203 | imm: oo.immediate, 204 | }), 205 | OperandClass::MEM_OFFSET => Ok(Self::MemOffset { 206 | reg: Reg::from_u32(oo.reg[0] as u32).unwrap(), 207 | offset: Imm::from(oo), 208 | mul_vl: oo.mul_vl, 209 | arrspec: ArrSpec::try_from(oo).ok(), 210 | }), 211 | OperandClass::MEM_PRE_IDX => Ok(Self::MemPreIdx { 212 | reg: Reg::from_u32(oo.reg[0] as u32).unwrap(), 213 | imm: Imm::from(oo), 214 | }), 215 | OperandClass::MEM_POST_IDX => { 216 | let reg0 = Reg::from_u32(oo.reg[0] as u32).unwrap(); 217 | 218 | match Reg::from_u32(oo.reg[1] as u32) { 219 | Some(reg1) => Ok(Self::MemPostIdxReg([reg0, reg1])), 220 | None => Ok(Self::MemPostIdxImm { 221 | reg: reg0, 222 | imm: Imm::from(oo), 223 | }), 224 | } 225 | } 226 | OperandClass::MEM_EXTENDED => Ok(Self::MemExt { 227 | regs: [ 228 | Reg::from_u32(oo.reg[0] as u32).unwrap(), 229 | Reg::from_u32(oo.reg[1] as u32).unwrap(), 230 | ], 231 | shift: Shift::try_from(oo).ok(), 232 | arrspec: ArrSpec::try_from(oo).ok(), 233 | }), 234 | OperandClass::SME_TILE => Ok(Self::SmeTile { 235 | tile: oo.tile, 236 | slice: SliceIndicator::try_from(oo).ok(), 237 | arrspec: ArrSpec::try_from(oo).ok(), 238 | reg: Reg::from_u32(oo.reg[0] as u32), 239 | imm: Imm::from(oo), 240 | }), 241 | OperandClass::INDEXED_ELEMENT => Ok(Self::IndexedElement { 242 | regs: [ 243 | Reg::from_u32(oo.reg[0] as u32).unwrap(), 244 | Reg::from_u32(oo.reg[1] as u32).unwrap(), 245 | ], 246 | arrspec: ArrSpec::try_from(oo).ok(), 247 | imm: Imm::from(oo), 248 | }), 249 | OperandClass::ACCUM_ARRAY => Ok(Self::AccumArray { 250 | reg: Reg::from_u32(oo.reg[0] as u32).unwrap(), 251 | imm: Imm::from(oo), 252 | }), 253 | OperandClass::LABEL => Ok(Self::Label(Imm::from(oo))), 254 | OperandClass::IMPLEMENTATION_SPECIFIC => Ok(Self::ImplSpec { 255 | o0: oo.implspec[0], 256 | o1: oo.implspec[1], 257 | cm: oo.implspec[2], 258 | cn: oo.implspec[3], 259 | o2: oo.implspec[4], 260 | }), 261 | OperandClass::CONDITION => Ok(Self::Cond(Condition::from_u32(oo.cond as u32).unwrap())), 262 | OperandClass::NAME => Ok(Self::Name(unsafe { core::mem::transmute(oo.name) })), 263 | OperandClass::NONE => Err(()), 264 | } 265 | } 266 | } 267 | 268 | fn write_full_reg(f: &mut fmt::Formatter<'_>, reg: Reg, arrspec: Option) -> fmt::Result { 269 | match arrspec { 270 | Some(arsp) => write!(f, "{}{}", reg, arsp.suffix(reg)), 271 | None => write!(f, "{}", reg), 272 | } 273 | } 274 | 275 | fn write_full_reg_lane( 276 | f: &mut fmt::Formatter<'_>, 277 | reg: Reg, 278 | arrspec: Option, 279 | ) -> fmt::Result { 280 | match arrspec { 281 | Some(arsp) => match arsp.lane() { 282 | Some(lane) => write!(f, "{}{}[{}]", reg, arsp.suffix(reg), lane), 283 | None => write!(f, "{}{}", reg, arsp.suffix(reg)), 284 | }, 285 | None => write!(f, "{}", reg), 286 | } 287 | } 288 | 289 | impl fmt::Display for Operand { 290 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 291 | match *self { 292 | Self::Imm64 { imm, shift } | Self::Imm32 { imm, shift } => { 293 | write!(f, "#{}", imm)?; 294 | 295 | if let Some(s) = shift { 296 | write!(f, ", {}", s)?; 297 | } 298 | 299 | Ok(()) 300 | } 301 | Self::FImm32(ff) => write!(f, "#{}", f32::from_le_bytes(ff.to_le_bytes())), 302 | Self::ShiftReg { reg, shift } => write!(f, "{}, {}", reg, shift), 303 | Self::QualReg { reg, qual } => write!(f, "{}/{}", reg, qual), 304 | Self::Reg { reg, arrspec } => write_full_reg_lane(f, reg, arrspec), 305 | Self::MultiReg { regs, arrspec } => { 306 | write!(f, "{{")?; 307 | 308 | let mut regs_iter = regs.iter().filter_map(|x| x.as_ref()); 309 | 310 | if let Some(reg) = regs_iter.next() { 311 | write_full_reg(f, *reg, arrspec)?; 312 | 313 | for reg in regs_iter { 314 | write!(f, ", ")?; 315 | write_full_reg(f, *reg, arrspec)?; 316 | } 317 | } 318 | 319 | write!(f, "}}")?; 320 | 321 | if let Some(arsp) = arrspec { 322 | if let Some(lane) = arsp.lane() { 323 | write!(f, "[{}]", lane)?; 324 | } 325 | } 326 | 327 | Ok(()) 328 | } 329 | Self::SysReg(sr) => write!(f, "{}", sr), 330 | Self::MemReg(mr) => write!(f, "[{}]", mr), 331 | Self::MemPreIdx { reg, imm } => write!(f, "[{}, #{}]!", reg, imm), 332 | Self::MemPostIdxImm { reg, imm } => write!(f, "[{}], #{}", reg, imm), 333 | Self::MemExt { 334 | regs, 335 | shift, 336 | arrspec, 337 | } => { 338 | write!(f, "[")?; 339 | write_full_reg(f, regs[0], arrspec)?; 340 | write!(f, ", ")?; 341 | write_full_reg(f, regs[1], arrspec)?; 342 | 343 | match shift { 344 | Some(ss) => write!(f, ", {}]", ss), 345 | None => write!(f, "]"), 346 | } 347 | } 348 | Self::MemPostIdxReg(regs) => write!(f, "[{}], {}", regs[0], regs[1]), 349 | Self::MemOffset { 350 | reg, 351 | offset, 352 | arrspec, 353 | mul_vl, 354 | } => { 355 | write!(f, "[")?; 356 | write_full_reg(f, reg, arrspec)?; 357 | 358 | if !matches!(offset, Imm::Signed(0) | Imm::Unsigned(0)) { 359 | write!(f, ", #{}", offset)?; 360 | 361 | if mul_vl { 362 | write!(f, ", mul vl")?; 363 | } 364 | } 365 | write!(f, "]") 366 | } 367 | Self::SmeTile { 368 | tile, 369 | slice, 370 | arrspec, 371 | reg, 372 | imm, 373 | } => { 374 | write!(f, "Z{}", tile)?; 375 | 376 | if let Some(slice) = slice { 377 | write!(f, "{}", slice)?; 378 | } 379 | 380 | if let Some(arrspec) = arrspec { 381 | write!(f, "{}", arrspec.suffix_truncated())?; 382 | } 383 | 384 | match (reg, arrspec) { 385 | (Some(reg), Some(ArrSpec::Full(_))) => write!(f, "[{}]", reg), 386 | (Some(reg), _) => write!(f, "[{}, {}]", reg, imm), 387 | _ => write!(f, ""), 388 | } 389 | } 390 | Self::AccumArray { reg, imm } => write!(f, "ZA[{}, #{}]", reg, imm), 391 | Self::IndexedElement { regs, arrspec, imm } => { 392 | write_full_reg(f, regs[0], arrspec)?; 393 | write!(f, "[{}", regs[1])?; 394 | 395 | if !matches!(imm, Imm::Signed(0) | Imm::Unsigned(0)) { 396 | write!(f, ", #{}", imm)?; 397 | } 398 | write!(f, "]") 399 | } 400 | Self::Label(imm) => write!(f, "{}", imm), 401 | Self::ImplSpec { o0, o1, cm, cn, o2 } => { 402 | write!(f, "s{}_{}_c{}_c{}_{}", o0, o1, cm, cn, o2) 403 | } 404 | Self::Cond(c) => write!(f, "{}", c), 405 | Self::Name(str) => { 406 | let name = unsafe { CStr::from_ptr(str.as_ptr() as _) } 407 | .to_str() 408 | .unwrap(); 409 | 410 | write!(f, "{}", name) 411 | } 412 | Self::StrImm { str, imm } => { 413 | let name = unsafe { CStr::from_ptr(str.as_ptr() as _) } 414 | .to_str() 415 | .unwrap(); 416 | 417 | write!(f, "{} #{:#x}", name, imm) 418 | } 419 | } 420 | } 421 | } 422 | -------------------------------------------------------------------------------- /src/reg.rs: -------------------------------------------------------------------------------- 1 | use core::fmt; 2 | 3 | use cstr_core::CStr; 4 | use num_traits::ToPrimitive; 5 | 6 | use bad64_sys::*; 7 | 8 | /// A register 9 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq, FromPrimitive, ToPrimitive)] 10 | #[repr(u32)] 11 | #[allow(non_camel_case_types)] 12 | pub enum Reg { 13 | W0 = Register_REG_W0 as u32, 14 | W1 = Register_REG_W1 as u32, 15 | W2 = Register_REG_W2 as u32, 16 | W3 = Register_REG_W3 as u32, 17 | W4 = Register_REG_W4 as u32, 18 | W5 = Register_REG_W5 as u32, 19 | W6 = Register_REG_W6 as u32, 20 | W7 = Register_REG_W7 as u32, 21 | W8 = Register_REG_W8 as u32, 22 | W9 = Register_REG_W9 as u32, 23 | W10 = Register_REG_W10 as u32, 24 | W11 = Register_REG_W11 as u32, 25 | W12 = Register_REG_W12 as u32, 26 | W13 = Register_REG_W13 as u32, 27 | W14 = Register_REG_W14 as u32, 28 | W15 = Register_REG_W15 as u32, 29 | W16 = Register_REG_W16 as u32, 30 | W17 = Register_REG_W17 as u32, 31 | W18 = Register_REG_W18 as u32, 32 | W19 = Register_REG_W19 as u32, 33 | W20 = Register_REG_W20 as u32, 34 | W21 = Register_REG_W21 as u32, 35 | W22 = Register_REG_W22 as u32, 36 | W23 = Register_REG_W23 as u32, 37 | W24 = Register_REG_W24 as u32, 38 | W25 = Register_REG_W25 as u32, 39 | W26 = Register_REG_W26 as u32, 40 | W27 = Register_REG_W27 as u32, 41 | W28 = Register_REG_W28 as u32, 42 | W29 = Register_REG_W29 as u32, 43 | W30 = Register_REG_W30 as u32, 44 | WZR = Register_REG_WZR as u32, 45 | WSP = Register_REG_WSP as u32, 46 | X0 = Register_REG_X0 as u32, 47 | X1 = Register_REG_X1 as u32, 48 | X2 = Register_REG_X2 as u32, 49 | X3 = Register_REG_X3 as u32, 50 | X4 = Register_REG_X4 as u32, 51 | X5 = Register_REG_X5 as u32, 52 | X6 = Register_REG_X6 as u32, 53 | X7 = Register_REG_X7 as u32, 54 | X8 = Register_REG_X8 as u32, 55 | X9 = Register_REG_X9 as u32, 56 | X10 = Register_REG_X10 as u32, 57 | X11 = Register_REG_X11 as u32, 58 | X12 = Register_REG_X12 as u32, 59 | X13 = Register_REG_X13 as u32, 60 | X14 = Register_REG_X14 as u32, 61 | X15 = Register_REG_X15 as u32, 62 | X16 = Register_REG_X16 as u32, 63 | X17 = Register_REG_X17 as u32, 64 | X18 = Register_REG_X18 as u32, 65 | X19 = Register_REG_X19 as u32, 66 | X20 = Register_REG_X20 as u32, 67 | X21 = Register_REG_X21 as u32, 68 | X22 = Register_REG_X22 as u32, 69 | X23 = Register_REG_X23 as u32, 70 | X24 = Register_REG_X24 as u32, 71 | X25 = Register_REG_X25 as u32, 72 | X26 = Register_REG_X26 as u32, 73 | X27 = Register_REG_X27 as u32, 74 | X28 = Register_REG_X28 as u32, 75 | X29 = Register_REG_X29 as u32, 76 | X30 = Register_REG_X30 as u32, 77 | XZR = Register_REG_XZR as u32, 78 | SP = Register_REG_SP as u32, 79 | V0 = Register_REG_V0 as u32, 80 | V1 = Register_REG_V1 as u32, 81 | V2 = Register_REG_V2 as u32, 82 | V3 = Register_REG_V3 as u32, 83 | V4 = Register_REG_V4 as u32, 84 | V5 = Register_REG_V5 as u32, 85 | V6 = Register_REG_V6 as u32, 86 | V7 = Register_REG_V7 as u32, 87 | V8 = Register_REG_V8 as u32, 88 | V9 = Register_REG_V9 as u32, 89 | V10 = Register_REG_V10 as u32, 90 | V11 = Register_REG_V11 as u32, 91 | V12 = Register_REG_V12 as u32, 92 | V13 = Register_REG_V13 as u32, 93 | V14 = Register_REG_V14 as u32, 94 | V15 = Register_REG_V15 as u32, 95 | V16 = Register_REG_V16 as u32, 96 | V17 = Register_REG_V17 as u32, 97 | V18 = Register_REG_V18 as u32, 98 | V19 = Register_REG_V19 as u32, 99 | V20 = Register_REG_V20 as u32, 100 | V21 = Register_REG_V21 as u32, 101 | V22 = Register_REG_V22 as u32, 102 | V23 = Register_REG_V23 as u32, 103 | V24 = Register_REG_V24 as u32, 104 | V25 = Register_REG_V25 as u32, 105 | V26 = Register_REG_V26 as u32, 106 | V27 = Register_REG_V27 as u32, 107 | V28 = Register_REG_V28 as u32, 108 | V29 = Register_REG_V29 as u32, 109 | V30 = Register_REG_V30 as u32, 110 | V31 = Register_REG_V31 as u32, 111 | B0 = Register_REG_B0 as u32, 112 | B1 = Register_REG_B1 as u32, 113 | B2 = Register_REG_B2 as u32, 114 | B3 = Register_REG_B3 as u32, 115 | B4 = Register_REG_B4 as u32, 116 | B5 = Register_REG_B5 as u32, 117 | B6 = Register_REG_B6 as u32, 118 | B7 = Register_REG_B7 as u32, 119 | B8 = Register_REG_B8 as u32, 120 | B9 = Register_REG_B9 as u32, 121 | B10 = Register_REG_B10 as u32, 122 | B11 = Register_REG_B11 as u32, 123 | B12 = Register_REG_B12 as u32, 124 | B13 = Register_REG_B13 as u32, 125 | B14 = Register_REG_B14 as u32, 126 | B15 = Register_REG_B15 as u32, 127 | B16 = Register_REG_B16 as u32, 128 | B17 = Register_REG_B17 as u32, 129 | B18 = Register_REG_B18 as u32, 130 | B19 = Register_REG_B19 as u32, 131 | B20 = Register_REG_B20 as u32, 132 | B21 = Register_REG_B21 as u32, 133 | B22 = Register_REG_B22 as u32, 134 | B23 = Register_REG_B23 as u32, 135 | B24 = Register_REG_B24 as u32, 136 | B25 = Register_REG_B25 as u32, 137 | B26 = Register_REG_B26 as u32, 138 | B27 = Register_REG_B27 as u32, 139 | B28 = Register_REG_B28 as u32, 140 | B29 = Register_REG_B29 as u32, 141 | B30 = Register_REG_B30 as u32, 142 | B31 = Register_REG_B31 as u32, 143 | H0 = Register_REG_H0 as u32, 144 | H1 = Register_REG_H1 as u32, 145 | H2 = Register_REG_H2 as u32, 146 | H3 = Register_REG_H3 as u32, 147 | H4 = Register_REG_H4 as u32, 148 | H5 = Register_REG_H5 as u32, 149 | H6 = Register_REG_H6 as u32, 150 | H7 = Register_REG_H7 as u32, 151 | H8 = Register_REG_H8 as u32, 152 | H9 = Register_REG_H9 as u32, 153 | H10 = Register_REG_H10 as u32, 154 | H11 = Register_REG_H11 as u32, 155 | H12 = Register_REG_H12 as u32, 156 | H13 = Register_REG_H13 as u32, 157 | H14 = Register_REG_H14 as u32, 158 | H15 = Register_REG_H15 as u32, 159 | H16 = Register_REG_H16 as u32, 160 | H17 = Register_REG_H17 as u32, 161 | H18 = Register_REG_H18 as u32, 162 | H19 = Register_REG_H19 as u32, 163 | H20 = Register_REG_H20 as u32, 164 | H21 = Register_REG_H21 as u32, 165 | H22 = Register_REG_H22 as u32, 166 | H23 = Register_REG_H23 as u32, 167 | H24 = Register_REG_H24 as u32, 168 | H25 = Register_REG_H25 as u32, 169 | H26 = Register_REG_H26 as u32, 170 | H27 = Register_REG_H27 as u32, 171 | H28 = Register_REG_H28 as u32, 172 | H29 = Register_REG_H29 as u32, 173 | H30 = Register_REG_H30 as u32, 174 | H31 = Register_REG_H31 as u32, 175 | S0 = Register_REG_S0 as u32, 176 | S1 = Register_REG_S1 as u32, 177 | S2 = Register_REG_S2 as u32, 178 | S3 = Register_REG_S3 as u32, 179 | S4 = Register_REG_S4 as u32, 180 | S5 = Register_REG_S5 as u32, 181 | S6 = Register_REG_S6 as u32, 182 | S7 = Register_REG_S7 as u32, 183 | S8 = Register_REG_S8 as u32, 184 | S9 = Register_REG_S9 as u32, 185 | S10 = Register_REG_S10 as u32, 186 | S11 = Register_REG_S11 as u32, 187 | S12 = Register_REG_S12 as u32, 188 | S13 = Register_REG_S13 as u32, 189 | S14 = Register_REG_S14 as u32, 190 | S15 = Register_REG_S15 as u32, 191 | S16 = Register_REG_S16 as u32, 192 | S17 = Register_REG_S17 as u32, 193 | S18 = Register_REG_S18 as u32, 194 | S19 = Register_REG_S19 as u32, 195 | S20 = Register_REG_S20 as u32, 196 | S21 = Register_REG_S21 as u32, 197 | S22 = Register_REG_S22 as u32, 198 | S23 = Register_REG_S23 as u32, 199 | S24 = Register_REG_S24 as u32, 200 | S25 = Register_REG_S25 as u32, 201 | S26 = Register_REG_S26 as u32, 202 | S27 = Register_REG_S27 as u32, 203 | S28 = Register_REG_S28 as u32, 204 | S29 = Register_REG_S29 as u32, 205 | S30 = Register_REG_S30 as u32, 206 | S31 = Register_REG_S31 as u32, 207 | D0 = Register_REG_D0 as u32, 208 | D1 = Register_REG_D1 as u32, 209 | D2 = Register_REG_D2 as u32, 210 | D3 = Register_REG_D3 as u32, 211 | D4 = Register_REG_D4 as u32, 212 | D5 = Register_REG_D5 as u32, 213 | D6 = Register_REG_D6 as u32, 214 | D7 = Register_REG_D7 as u32, 215 | D8 = Register_REG_D8 as u32, 216 | D9 = Register_REG_D9 as u32, 217 | D10 = Register_REG_D10 as u32, 218 | D11 = Register_REG_D11 as u32, 219 | D12 = Register_REG_D12 as u32, 220 | D13 = Register_REG_D13 as u32, 221 | D14 = Register_REG_D14 as u32, 222 | D15 = Register_REG_D15 as u32, 223 | D16 = Register_REG_D16 as u32, 224 | D17 = Register_REG_D17 as u32, 225 | D18 = Register_REG_D18 as u32, 226 | D19 = Register_REG_D19 as u32, 227 | D20 = Register_REG_D20 as u32, 228 | D21 = Register_REG_D21 as u32, 229 | D22 = Register_REG_D22 as u32, 230 | D23 = Register_REG_D23 as u32, 231 | D24 = Register_REG_D24 as u32, 232 | D25 = Register_REG_D25 as u32, 233 | D26 = Register_REG_D26 as u32, 234 | D27 = Register_REG_D27 as u32, 235 | D28 = Register_REG_D28 as u32, 236 | D29 = Register_REG_D29 as u32, 237 | D30 = Register_REG_D30 as u32, 238 | D31 = Register_REG_D31 as u32, 239 | Q0 = Register_REG_Q0 as u32, 240 | Q1 = Register_REG_Q1 as u32, 241 | Q2 = Register_REG_Q2 as u32, 242 | Q3 = Register_REG_Q3 as u32, 243 | Q4 = Register_REG_Q4 as u32, 244 | Q5 = Register_REG_Q5 as u32, 245 | Q6 = Register_REG_Q6 as u32, 246 | Q7 = Register_REG_Q7 as u32, 247 | Q8 = Register_REG_Q8 as u32, 248 | Q9 = Register_REG_Q9 as u32, 249 | Q10 = Register_REG_Q10 as u32, 250 | Q11 = Register_REG_Q11 as u32, 251 | Q12 = Register_REG_Q12 as u32, 252 | Q13 = Register_REG_Q13 as u32, 253 | Q14 = Register_REG_Q14 as u32, 254 | Q15 = Register_REG_Q15 as u32, 255 | Q16 = Register_REG_Q16 as u32, 256 | Q17 = Register_REG_Q17 as u32, 257 | Q18 = Register_REG_Q18 as u32, 258 | Q19 = Register_REG_Q19 as u32, 259 | Q20 = Register_REG_Q20 as u32, 260 | Q21 = Register_REG_Q21 as u32, 261 | Q22 = Register_REG_Q22 as u32, 262 | Q23 = Register_REG_Q23 as u32, 263 | Q24 = Register_REG_Q24 as u32, 264 | Q25 = Register_REG_Q25 as u32, 265 | Q26 = Register_REG_Q26 as u32, 266 | Q27 = Register_REG_Q27 as u32, 267 | Q28 = Register_REG_Q28 as u32, 268 | Q29 = Register_REG_Q29 as u32, 269 | Q30 = Register_REG_Q30 as u32, 270 | Q31 = Register_REG_Q31 as u32, 271 | Z0 = Register_REG_Z0 as u32, 272 | Z1 = Register_REG_Z1 as u32, 273 | Z2 = Register_REG_Z2 as u32, 274 | Z3 = Register_REG_Z3 as u32, 275 | Z4 = Register_REG_Z4 as u32, 276 | Z5 = Register_REG_Z5 as u32, 277 | Z6 = Register_REG_Z6 as u32, 278 | Z7 = Register_REG_Z7 as u32, 279 | Z8 = Register_REG_Z8 as u32, 280 | Z9 = Register_REG_Z9 as u32, 281 | Z10 = Register_REG_Z10 as u32, 282 | Z11 = Register_REG_Z11 as u32, 283 | Z12 = Register_REG_Z12 as u32, 284 | Z13 = Register_REG_Z13 as u32, 285 | Z14 = Register_REG_Z14 as u32, 286 | Z15 = Register_REG_Z15 as u32, 287 | Z16 = Register_REG_Z16 as u32, 288 | Z17 = Register_REG_Z17 as u32, 289 | Z18 = Register_REG_Z18 as u32, 290 | Z19 = Register_REG_Z19 as u32, 291 | Z20 = Register_REG_Z20 as u32, 292 | Z21 = Register_REG_Z21 as u32, 293 | Z22 = Register_REG_Z22 as u32, 294 | Z23 = Register_REG_Z23 as u32, 295 | Z24 = Register_REG_Z24 as u32, 296 | Z25 = Register_REG_Z25 as u32, 297 | Z26 = Register_REG_Z26 as u32, 298 | Z27 = Register_REG_Z27 as u32, 299 | Z28 = Register_REG_Z28 as u32, 300 | Z29 = Register_REG_Z29 as u32, 301 | Z30 = Register_REG_Z30 as u32, 302 | Z31 = Register_REG_Z31 as u32, 303 | P0 = Register_REG_P0 as u32, 304 | P1 = Register_REG_P1 as u32, 305 | P2 = Register_REG_P2 as u32, 306 | P3 = Register_REG_P3 as u32, 307 | P4 = Register_REG_P4 as u32, 308 | P5 = Register_REG_P5 as u32, 309 | P6 = Register_REG_P6 as u32, 310 | P7 = Register_REG_P7 as u32, 311 | P8 = Register_REG_P8 as u32, 312 | P9 = Register_REG_P9 as u32, 313 | P10 = Register_REG_P10 as u32, 314 | P11 = Register_REG_P11 as u32, 315 | P12 = Register_REG_P12 as u32, 316 | P13 = Register_REG_P13 as u32, 317 | P14 = Register_REG_P14 as u32, 318 | P15 = Register_REG_P15 as u32, 319 | P16 = Register_REG_P16 as u32, 320 | P17 = Register_REG_P17 as u32, 321 | P18 = Register_REG_P18 as u32, 322 | P19 = Register_REG_P19 as u32, 323 | P20 = Register_REG_P20 as u32, 324 | P21 = Register_REG_P21 as u32, 325 | P22 = Register_REG_P22 as u32, 326 | P23 = Register_REG_P23 as u32, 327 | P24 = Register_REG_P24 as u32, 328 | P25 = Register_REG_P25 as u32, 329 | P26 = Register_REG_P26 as u32, 330 | P27 = Register_REG_P27 as u32, 331 | P28 = Register_REG_P28 as u32, 332 | P29 = Register_REG_P29 as u32, 333 | P30 = Register_REG_P30 as u32, 334 | P31 = Register_REG_P31 as u32, 335 | } 336 | 337 | const_assert_eq!(Register_REG_END, Register_REG_PF31 + 1); 338 | 339 | impl Reg { 340 | /// Returns the register name 341 | /// 342 | /// # Examples 343 | /// ``` 344 | /// use bad64::Reg; 345 | /// 346 | /// assert_eq!(Reg::X0.name(), "x0"); 347 | /// ``` 348 | pub fn name(&self) -> &'static str { 349 | #[cfg(target_os = "windows")] 350 | { 351 | unsafe { CStr::from_ptr(get_register_name(self.to_i32().unwrap()) as _) } 352 | .to_str() 353 | .unwrap() 354 | } 355 | #[cfg(not(target_os = "windows"))] 356 | { 357 | unsafe { CStr::from_ptr(get_register_name(self.to_u32().unwrap()) as _) } 358 | .to_str() 359 | .unwrap() 360 | } 361 | } 362 | 363 | /// Returns the register size 364 | /// 365 | /// # Examples 366 | /// ``` 367 | /// use bad64::Reg; 368 | /// 369 | /// assert_eq!(Reg::X0.size(), 8); 370 | /// assert_eq!(Reg::V0.size(), 16); 371 | /// ``` 372 | /// 373 | /// ``` 374 | /// use bad64::{decode, Operand, Reg}; 375 | /// 376 | /// // add x0, x1, #0x41 - "\x20\x04\x01\x91" 377 | /// let decoded = decode(0x91010420, 0x1000).unwrap(); 378 | /// 379 | /// let op = decoded.operands()[0]; 380 | /// 381 | /// assert_eq!(op, Operand::Reg { reg: Reg::X0, arrspec: None }); 382 | /// 383 | /// match op { 384 | /// Operand::Reg { reg: r, .. } => assert_eq!(r.size(), 8), 385 | /// _ => assert!(false), 386 | /// }; 387 | /// ``` 388 | pub fn size(&self) -> usize { 389 | #[cfg(target_os = "windows")] 390 | { 391 | unsafe { bad64_sys::get_register_size(self.to_i32().unwrap()) as usize } 392 | } 393 | #[cfg(not(target_os = "windows"))] 394 | { 395 | unsafe { bad64_sys::get_register_size(self.to_u32().unwrap()) as usize } 396 | } 397 | } 398 | 399 | /// Returns register's SIMD status 400 | /// 401 | /// # Example 402 | /// ``` 403 | /// use bad64::Reg; 404 | /// 405 | /// assert_eq!(Reg::V0.is_simd(), true); 406 | /// assert_eq!(Reg::D0.is_simd(), false); 407 | /// assert_eq!(Reg::X0.is_simd(), false); 408 | /// assert_eq!(Reg::Z0.is_simd(), false); 409 | /// assert_eq!(Reg::P0.is_simd(), false); 410 | /// ``` 411 | pub fn is_simd(&self) -> bool { 412 | self.to_u32().unwrap() >= Reg::V0.to_u32().unwrap() 413 | && self.to_u32().unwrap() <= Reg::V31.to_u32().unwrap() 414 | } 415 | 416 | /// Returns register's SVE status 417 | /// 418 | /// # Example 419 | /// ``` 420 | /// use bad64::Reg; 421 | /// 422 | /// assert_eq!(Reg::Z0.is_sve(), true); 423 | /// assert_eq!(Reg::V0.is_sve(), false); 424 | /// assert_eq!(Reg::D0.is_sve(), false); 425 | /// assert_eq!(Reg::X0.is_sve(), false); 426 | /// assert_eq!(Reg::P0.is_simd(), false); 427 | /// ``` 428 | pub fn is_sve(&self) -> bool { 429 | self.to_u32().unwrap() >= Reg::Z0.to_u32().unwrap() 430 | && self.to_u32().unwrap() <= Reg::Z31.to_u32().unwrap() 431 | } 432 | 433 | /// Returns register's predicate status 434 | /// 435 | /// # Example 436 | /// ``` 437 | /// use bad64::Reg; 438 | /// 439 | /// assert_eq!(Reg::P0.is_pred(), true); 440 | /// assert_eq!(Reg::V0.is_pred(), false); 441 | /// assert_eq!(Reg::D0.is_pred(), false); 442 | /// assert_eq!(Reg::X0.is_pred(), false); 443 | /// assert_eq!(Reg::Z0.is_pred(), false); 444 | /// ``` 445 | pub fn is_pred(&self) -> bool { 446 | self.to_u32().unwrap() >= Reg::P0.to_u32().unwrap() 447 | && self.to_u32().unwrap() <= Reg::P31.to_u32().unwrap() 448 | } 449 | } 450 | 451 | impl fmt::Display for Reg { 452 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 453 | write!(f, "{}", self.name()) 454 | } 455 | } 456 | -------------------------------------------------------------------------------- /src/shift.rs: -------------------------------------------------------------------------------- 1 | use core::convert::TryFrom; 2 | use core::fmt; 3 | 4 | use bad64_sys::*; 5 | 6 | /// A shift applied to a register or immediate 7 | #[derive(Clone, Copy, Debug, Hash, Eq, PartialEq)] 8 | #[allow(non_camel_case_types)] 9 | pub enum Shift { 10 | LSL(u32), 11 | LSR(u32), 12 | ASR(u32), 13 | ROR(u32), 14 | UXTW(u32), 15 | SXTW(u32), 16 | SXTX(u32), 17 | UXTX(u32), 18 | SXTB(u32), 19 | SXTH(u32), 20 | UXTH(u32), 21 | UXTB(u32), 22 | MSL(u32), 23 | } 24 | 25 | #[doc(hidden)] 26 | #[allow(non_upper_case_globals)] 27 | impl TryFrom<&bad64_sys::InstructionOperand> for Shift { 28 | type Error = (); 29 | 30 | fn try_from(oo: &bad64_sys::InstructionOperand) -> Result { 31 | match oo.shiftType { 32 | ShiftType::ShiftType_LSL => Ok(Shift::LSL(oo.shiftValue)), 33 | ShiftType::ShiftType_LSR => Ok(Shift::LSR(oo.shiftValue)), 34 | ShiftType::ShiftType_ASR => Ok(Shift::ASR(oo.shiftValue)), 35 | ShiftType::ShiftType_ROR => Ok(Shift::ROR(oo.shiftValue)), 36 | ShiftType::ShiftType_UXTW => Ok(Shift::UXTW(oo.shiftValue)), 37 | ShiftType::ShiftType_SXTW => Ok(Shift::SXTW(oo.shiftValue)), 38 | ShiftType::ShiftType_UXTX => Ok(Shift::UXTX(oo.shiftValue)), 39 | ShiftType::ShiftType_SXTX => Ok(Shift::SXTX(oo.shiftValue)), 40 | ShiftType::ShiftType_SXTB => Ok(Shift::SXTB(oo.shiftValue)), 41 | ShiftType::ShiftType_SXTH => Ok(Shift::SXTH(oo.shiftValue)), 42 | ShiftType::ShiftType_UXTH => Ok(Shift::UXTH(oo.shiftValue)), 43 | ShiftType::ShiftType_UXTB => Ok(Shift::UXTB(oo.shiftValue)), 44 | ShiftType::ShiftType_MSL => Ok(Shift::MSL(oo.shiftValue)), 45 | ShiftType::ShiftType_NONE | ShiftType::ShiftType_END => Err(()), 46 | } 47 | } 48 | } 49 | 50 | impl fmt::Display for Shift { 51 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 52 | match *self { 53 | Self::LSL(a) => write!(f, "lsl #{:#x}", a), 54 | Self::LSR(a) => write!(f, "lsr #{:#x}", a), 55 | Self::ASR(a) => write!(f, "asr #{:#x}", a), 56 | Self::ROR(a) => write!(f, "ror #{:#x}", a), 57 | Self::UXTW(a) => { 58 | write!(f, "uxtw")?; 59 | if a != 0 { 60 | write!(f, " #{:#x}", a)?; 61 | } 62 | Ok(()) 63 | } 64 | Self::SXTW(a) => { 65 | write!(f, "sxtw")?; 66 | if a != 0 { 67 | write!(f, " #{:#x}", a)?; 68 | } 69 | Ok(()) 70 | } 71 | Self::UXTX(a) => { 72 | write!(f, "uxtx")?; 73 | if a != 0 { 74 | write!(f, " #{:#x}", a)?; 75 | } 76 | Ok(()) 77 | } 78 | Self::SXTX(a) => { 79 | write!(f, "sxtx")?; 80 | if a != 0 { 81 | write!(f, " #{:#x}", a)?; 82 | } 83 | Ok(()) 84 | } 85 | Self::SXTB(a) => { 86 | write!(f, "sxtb")?; 87 | if a != 0 { 88 | write!(f, " #{:#x}", a)?; 89 | } 90 | Ok(()) 91 | } 92 | Self::SXTH(a) => { 93 | write!(f, "sxth")?; 94 | if a != 0 { 95 | write!(f, " #{:#x}", a)?; 96 | } 97 | Ok(()) 98 | } 99 | Self::UXTH(a) => { 100 | write!(f, "uxth")?; 101 | if a != 0 { 102 | write!(f, " #{:#x}", a)?; 103 | } 104 | Ok(()) 105 | } 106 | Self::UXTB(a) => { 107 | write!(f, "uxtb")?; 108 | if a != 0 { 109 | write!(f, " #{:#x}", a)?; 110 | } 111 | Ok(()) 112 | } 113 | Self::MSL(a) => write!(f, "msl #{:#x}", a), 114 | } 115 | } 116 | } 117 | -------------------------------------------------------------------------------- /src/sysreg.rs: -------------------------------------------------------------------------------- 1 | use core::fmt; 2 | 3 | use cstr_core::CStr; 4 | use num_traits::ToPrimitive; 5 | 6 | use bad64_sys::*; 7 | 8 | /// A system register 9 | #[derive(Clone, Copy, Debug, Eq, Hash, PartialEq, FromPrimitive, ToPrimitive)] 10 | #[repr(u32)] 11 | #[allow(non_camel_case_types)] 12 | pub enum SysReg { 13 | OSDTRRX_EL1 = SystemReg_REG_OSDTRRX_EL1 as u32, 14 | DBGBVR0_EL1 = SystemReg_REG_DBGBVR0_EL1 as u32, 15 | DBGBCR0_EL1 = SystemReg_REG_DBGBCR0_EL1 as u32, 16 | DBGWVR0_EL1 = SystemReg_REG_DBGWVR0_EL1 as u32, 17 | DBGWCR0_EL1 = SystemReg_REG_DBGWCR0_EL1 as u32, 18 | DBGBVR1_EL1 = SystemReg_REG_DBGBVR1_EL1 as u32, 19 | DBGBCR1_EL1 = SystemReg_REG_DBGBCR1_EL1 as u32, 20 | DBGWVR1_EL1 = SystemReg_REG_DBGWVR1_EL1 as u32, 21 | DBGWCR1_EL1 = SystemReg_REG_DBGWCR1_EL1 as u32, 22 | MDCCINT_EL1 = SystemReg_REG_MDCCINT_EL1 as u32, 23 | MDSCR_EL1 = SystemReg_REG_MDSCR_EL1 as u32, 24 | DBGBVR2_EL1 = SystemReg_REG_DBGBVR2_EL1 as u32, 25 | DBGBCR2_EL1 = SystemReg_REG_DBGBCR2_EL1 as u32, 26 | DBGWVR2_EL1 = SystemReg_REG_DBGWVR2_EL1 as u32, 27 | DBGWCR2_EL1 = SystemReg_REG_DBGWCR2_EL1 as u32, 28 | OSDTRTX_EL1 = SystemReg_REG_OSDTRTX_EL1 as u32, 29 | DBGBVR3_EL1 = SystemReg_REG_DBGBVR3_EL1 as u32, 30 | DBGBCR3_EL1 = SystemReg_REG_DBGBCR3_EL1 as u32, 31 | DBGWVR3_EL1 = SystemReg_REG_DBGWVR3_EL1 as u32, 32 | DBGWCR3_EL1 = SystemReg_REG_DBGWCR3_EL1 as u32, 33 | DBGBVR4_EL1 = SystemReg_REG_DBGBVR4_EL1 as u32, 34 | DBGBCR4_EL1 = SystemReg_REG_DBGBCR4_EL1 as u32, 35 | DBGWVR4_EL1 = SystemReg_REG_DBGWVR4_EL1 as u32, 36 | DBGWCR4_EL1 = SystemReg_REG_DBGWCR4_EL1 as u32, 37 | DBGBVR5_EL1 = SystemReg_REG_DBGBVR5_EL1 as u32, 38 | DBGBCR5_EL1 = SystemReg_REG_DBGBCR5_EL1 as u32, 39 | DBGWVR5_EL1 = SystemReg_REG_DBGWVR5_EL1 as u32, 40 | DBGWCR5_EL1 = SystemReg_REG_DBGWCR5_EL1 as u32, 41 | OSECCR_EL1 = SystemReg_REG_OSECCR_EL1 as u32, 42 | DBGBVR6_EL1 = SystemReg_REG_DBGBVR6_EL1 as u32, 43 | DBGBCR6_EL1 = SystemReg_REG_DBGBCR6_EL1 as u32, 44 | DBGWVR6_EL1 = SystemReg_REG_DBGWVR6_EL1 as u32, 45 | DBGWCR6_EL1 = SystemReg_REG_DBGWCR6_EL1 as u32, 46 | DBGBVR7_EL1 = SystemReg_REG_DBGBVR7_EL1 as u32, 47 | DBGBCR7_EL1 = SystemReg_REG_DBGBCR7_EL1 as u32, 48 | DBGWVR7_EL1 = SystemReg_REG_DBGWVR7_EL1 as u32, 49 | DBGWCR7_EL1 = SystemReg_REG_DBGWCR7_EL1 as u32, 50 | DBGBVR8_EL1 = SystemReg_REG_DBGBVR8_EL1 as u32, 51 | DBGBCR8_EL1 = SystemReg_REG_DBGBCR8_EL1 as u32, 52 | DBGWVR8_EL1 = SystemReg_REG_DBGWVR8_EL1 as u32, 53 | DBGWCR8_EL1 = SystemReg_REG_DBGWCR8_EL1 as u32, 54 | DBGBVR9_EL1 = SystemReg_REG_DBGBVR9_EL1 as u32, 55 | DBGBCR9_EL1 = SystemReg_REG_DBGBCR9_EL1 as u32, 56 | DBGWVR9_EL1 = SystemReg_REG_DBGWVR9_EL1 as u32, 57 | DBGWCR9_EL1 = SystemReg_REG_DBGWCR9_EL1 as u32, 58 | DBGBVR10_EL1 = SystemReg_REG_DBGBVR10_EL1 as u32, 59 | DBGBCR10_EL1 = SystemReg_REG_DBGBCR10_EL1 as u32, 60 | DBGWVR10_EL1 = SystemReg_REG_DBGWVR10_EL1 as u32, 61 | DBGWCR10_EL1 = SystemReg_REG_DBGWCR10_EL1 as u32, 62 | DBGBVR11_EL1 = SystemReg_REG_DBGBVR11_EL1 as u32, 63 | DBGBCR11_EL1 = SystemReg_REG_DBGBCR11_EL1 as u32, 64 | DBGWVR11_EL1 = SystemReg_REG_DBGWVR11_EL1 as u32, 65 | DBGWCR11_EL1 = SystemReg_REG_DBGWCR11_EL1 as u32, 66 | DBGBVR12_EL1 = SystemReg_REG_DBGBVR12_EL1 as u32, 67 | DBGBCR12_EL1 = SystemReg_REG_DBGBCR12_EL1 as u32, 68 | DBGWVR12_EL1 = SystemReg_REG_DBGWVR12_EL1 as u32, 69 | DBGWCR12_EL1 = SystemReg_REG_DBGWCR12_EL1 as u32, 70 | DBGBVR13_EL1 = SystemReg_REG_DBGBVR13_EL1 as u32, 71 | DBGBCR13_EL1 = SystemReg_REG_DBGBCR13_EL1 as u32, 72 | DBGWVR13_EL1 = SystemReg_REG_DBGWVR13_EL1 as u32, 73 | DBGWCR13_EL1 = SystemReg_REG_DBGWCR13_EL1 as u32, 74 | DBGBVR14_EL1 = SystemReg_REG_DBGBVR14_EL1 as u32, 75 | DBGBCR14_EL1 = SystemReg_REG_DBGBCR14_EL1 as u32, 76 | DBGWVR14_EL1 = SystemReg_REG_DBGWVR14_EL1 as u32, 77 | DBGWCR14_EL1 = SystemReg_REG_DBGWCR14_EL1 as u32, 78 | DBGBVR15_EL1 = SystemReg_REG_DBGBVR15_EL1 as u32, 79 | DBGBCR15_EL1 = SystemReg_REG_DBGBCR15_EL1 as u32, 80 | DBGWVR15_EL1 = SystemReg_REG_DBGWVR15_EL1 as u32, 81 | DBGWCR15_EL1 = SystemReg_REG_DBGWCR15_EL1 as u32, 82 | OSLAR_EL1 = SystemReg_REG_OSLAR_EL1 as u32, 83 | OSDLR_EL1 = SystemReg_REG_OSDLR_EL1 as u32, 84 | DBGPRCR_EL1 = SystemReg_REG_DBGPRCR_EL1 as u32, 85 | DBGCLAIMSET_EL1 = SystemReg_REG_DBGCLAIMSET_EL1 as u32, 86 | DBGCLAIMCLR_EL1 = SystemReg_REG_DBGCLAIMCLR_EL1 as u32, 87 | TRCTRACEIDR = SystemReg_REG_TRCTRACEIDR as u32, 88 | TRCVICTLR = SystemReg_REG_TRCVICTLR as u32, 89 | TRCSEQEVR0 = SystemReg_REG_TRCSEQEVR0 as u32, 90 | TRCCNTRLDVR0 = SystemReg_REG_TRCCNTRLDVR0 as u32, 91 | TRCIMSPEC0 = SystemReg_REG_TRCIMSPEC0 as u32, 92 | TRCPRGCTLR = SystemReg_REG_TRCPRGCTLR as u32, 93 | TRCQCTLR = SystemReg_REG_TRCQCTLR as u32, 94 | TRCVIIECTLR = SystemReg_REG_TRCVIIECTLR as u32, 95 | TRCSEQEVR1 = SystemReg_REG_TRCSEQEVR1 as u32, 96 | TRCCNTRLDVR1 = SystemReg_REG_TRCCNTRLDVR1 as u32, 97 | TRCIMSPEC1 = SystemReg_REG_TRCIMSPEC1 as u32, 98 | TRCPROCSELR = SystemReg_REG_TRCPROCSELR as u32, 99 | TRCVISSCTLR = SystemReg_REG_TRCVISSCTLR as u32, 100 | TRCSEQEVR2 = SystemReg_REG_TRCSEQEVR2 as u32, 101 | TRCCNTRLDVR2 = SystemReg_REG_TRCCNTRLDVR2 as u32, 102 | TRCIMSPEC2 = SystemReg_REG_TRCIMSPEC2 as u32, 103 | TRCVIPCSSCTLR = SystemReg_REG_TRCVIPCSSCTLR as u32, 104 | TRCCNTRLDVR3 = SystemReg_REG_TRCCNTRLDVR3 as u32, 105 | TRCIMSPEC3 = SystemReg_REG_TRCIMSPEC3 as u32, 106 | TRCCONFIGR = SystemReg_REG_TRCCONFIGR as u32, 107 | TRCCNTCTLR0 = SystemReg_REG_TRCCNTCTLR0 as u32, 108 | TRCIMSPEC4 = SystemReg_REG_TRCIMSPEC4 as u32, 109 | TRCCNTCTLR1 = SystemReg_REG_TRCCNTCTLR1 as u32, 110 | TRCIMSPEC5 = SystemReg_REG_TRCIMSPEC5 as u32, 111 | TRCAUXCTLR = SystemReg_REG_TRCAUXCTLR as u32, 112 | TRCSEQRSTEVR = SystemReg_REG_TRCSEQRSTEVR as u32, 113 | TRCCNTCTLR2 = SystemReg_REG_TRCCNTCTLR2 as u32, 114 | TRCIMSPEC6 = SystemReg_REG_TRCIMSPEC6 as u32, 115 | TRCSEQSTR = SystemReg_REG_TRCSEQSTR as u32, 116 | TRCCNTCTLR3 = SystemReg_REG_TRCCNTCTLR3 as u32, 117 | TRCIMSPEC7 = SystemReg_REG_TRCIMSPEC7 as u32, 118 | TRCEVENTCTL0R = SystemReg_REG_TRCEVENTCTL0R as u32, 119 | TRCVDCTLR = SystemReg_REG_TRCVDCTLR as u32, 120 | TRCEXTINSELR = SystemReg_REG_TRCEXTINSELR as u32, 121 | TRCCNTVR0 = SystemReg_REG_TRCCNTVR0 as u32, 122 | TRCEVENTCTL1R = SystemReg_REG_TRCEVENTCTL1R as u32, 123 | TRCVDSACCTLR = SystemReg_REG_TRCVDSACCTLR as u32, 124 | TRCEXTINSELR1 = SystemReg_REG_TRCEXTINSELR1 as u32, 125 | TRCCNTVR1 = SystemReg_REG_TRCCNTVR1 as u32, 126 | TRCRSR = SystemReg_REG_TRCRSR as u32, 127 | TRCVDARCCTLR = SystemReg_REG_TRCVDARCCTLR as u32, 128 | TRCEXTINSELR2 = SystemReg_REG_TRCEXTINSELR2 as u32, 129 | TRCCNTVR2 = SystemReg_REG_TRCCNTVR2 as u32, 130 | TRCSTALLCTLR = SystemReg_REG_TRCSTALLCTLR as u32, 131 | TRCEXTINSELR3 = SystemReg_REG_TRCEXTINSELR3 as u32, 132 | TRCCNTVR3 = SystemReg_REG_TRCCNTVR3 as u32, 133 | TRCTSCTLR = SystemReg_REG_TRCTSCTLR as u32, 134 | TRCSYNCPR = SystemReg_REG_TRCSYNCPR as u32, 135 | TRCCCCTLR = SystemReg_REG_TRCCCCTLR as u32, 136 | TRCBBCTLR = SystemReg_REG_TRCBBCTLR as u32, 137 | TRCRSCTLR16 = SystemReg_REG_TRCRSCTLR16 as u32, 138 | TRCSSCCR0 = SystemReg_REG_TRCSSCCR0 as u32, 139 | TRCSSPCICR0 = SystemReg_REG_TRCSSPCICR0 as u32, 140 | TRCOSLAR = SystemReg_REG_TRCOSLAR as u32, 141 | TRCRSCTLR17 = SystemReg_REG_TRCRSCTLR17 as u32, 142 | TRCSSCCR1 = SystemReg_REG_TRCSSCCR1 as u32, 143 | TRCSSPCICR1 = SystemReg_REG_TRCSSPCICR1 as u32, 144 | TRCRSCTLR2 = SystemReg_REG_TRCRSCTLR2 as u32, 145 | TRCRSCTLR18 = SystemReg_REG_TRCRSCTLR18 as u32, 146 | TRCSSCCR2 = SystemReg_REG_TRCSSCCR2 as u32, 147 | TRCSSPCICR2 = SystemReg_REG_TRCSSPCICR2 as u32, 148 | TRCRSCTLR3 = SystemReg_REG_TRCRSCTLR3 as u32, 149 | TRCRSCTLR19 = SystemReg_REG_TRCRSCTLR19 as u32, 150 | TRCSSCCR3 = SystemReg_REG_TRCSSCCR3 as u32, 151 | TRCSSPCICR3 = SystemReg_REG_TRCSSPCICR3 as u32, 152 | TRCRSCTLR4 = SystemReg_REG_TRCRSCTLR4 as u32, 153 | TRCRSCTLR20 = SystemReg_REG_TRCRSCTLR20 as u32, 154 | TRCSSCCR4 = SystemReg_REG_TRCSSCCR4 as u32, 155 | TRCSSPCICR4 = SystemReg_REG_TRCSSPCICR4 as u32, 156 | TRCPDCR = SystemReg_REG_TRCPDCR as u32, 157 | TRCRSCTLR5 = SystemReg_REG_TRCRSCTLR5 as u32, 158 | TRCRSCTLR21 = SystemReg_REG_TRCRSCTLR21 as u32, 159 | TRCSSCCR5 = SystemReg_REG_TRCSSCCR5 as u32, 160 | TRCSSPCICR5 = SystemReg_REG_TRCSSPCICR5 as u32, 161 | TRCRSCTLR6 = SystemReg_REG_TRCRSCTLR6 as u32, 162 | TRCRSCTLR22 = SystemReg_REG_TRCRSCTLR22 as u32, 163 | TRCSSCCR6 = SystemReg_REG_TRCSSCCR6 as u32, 164 | TRCSSPCICR6 = SystemReg_REG_TRCSSPCICR6 as u32, 165 | TRCRSCTLR7 = SystemReg_REG_TRCRSCTLR7 as u32, 166 | TRCRSCTLR23 = SystemReg_REG_TRCRSCTLR23 as u32, 167 | TRCSSCCR7 = SystemReg_REG_TRCSSCCR7 as u32, 168 | TRCSSPCICR7 = SystemReg_REG_TRCSSPCICR7 as u32, 169 | TRCRSCTLR8 = SystemReg_REG_TRCRSCTLR8 as u32, 170 | TRCRSCTLR24 = SystemReg_REG_TRCRSCTLR24 as u32, 171 | TRCSSCSR0 = SystemReg_REG_TRCSSCSR0 as u32, 172 | TRCRSCTLR9 = SystemReg_REG_TRCRSCTLR9 as u32, 173 | TRCRSCTLR25 = SystemReg_REG_TRCRSCTLR25 as u32, 174 | TRCSSCSR1 = SystemReg_REG_TRCSSCSR1 as u32, 175 | TRCRSCTLR10 = SystemReg_REG_TRCRSCTLR10 as u32, 176 | TRCRSCTLR26 = SystemReg_REG_TRCRSCTLR26 as u32, 177 | TRCSSCSR2 = SystemReg_REG_TRCSSCSR2 as u32, 178 | TRCRSCTLR11 = SystemReg_REG_TRCRSCTLR11 as u32, 179 | TRCRSCTLR27 = SystemReg_REG_TRCRSCTLR27 as u32, 180 | TRCSSCSR3 = SystemReg_REG_TRCSSCSR3 as u32, 181 | TRCRSCTLR12 = SystemReg_REG_TRCRSCTLR12 as u32, 182 | TRCRSCTLR28 = SystemReg_REG_TRCRSCTLR28 as u32, 183 | TRCSSCSR4 = SystemReg_REG_TRCSSCSR4 as u32, 184 | TRCRSCTLR13 = SystemReg_REG_TRCRSCTLR13 as u32, 185 | TRCRSCTLR29 = SystemReg_REG_TRCRSCTLR29 as u32, 186 | TRCSSCSR5 = SystemReg_REG_TRCSSCSR5 as u32, 187 | TRCRSCTLR14 = SystemReg_REG_TRCRSCTLR14 as u32, 188 | TRCRSCTLR30 = SystemReg_REG_TRCRSCTLR30 as u32, 189 | TRCSSCSR6 = SystemReg_REG_TRCSSCSR6 as u32, 190 | TRCRSCTLR15 = SystemReg_REG_TRCRSCTLR15 as u32, 191 | TRCRSCTLR31 = SystemReg_REG_TRCRSCTLR31 as u32, 192 | TRCSSCSR7 = SystemReg_REG_TRCSSCSR7 as u32, 193 | TRCACVR0 = SystemReg_REG_TRCACVR0 as u32, 194 | TRCACVR8 = SystemReg_REG_TRCACVR8 as u32, 195 | TRCACATR0 = SystemReg_REG_TRCACATR0 as u32, 196 | TRCACATR8 = SystemReg_REG_TRCACATR8 as u32, 197 | TRCDVCVR0 = SystemReg_REG_TRCDVCVR0 as u32, 198 | TRCDVCVR4 = SystemReg_REG_TRCDVCVR4 as u32, 199 | TRCDVCMR0 = SystemReg_REG_TRCDVCMR0 as u32, 200 | TRCDVCMR4 = SystemReg_REG_TRCDVCMR4 as u32, 201 | TRCACVR1 = SystemReg_REG_TRCACVR1 as u32, 202 | TRCACVR9 = SystemReg_REG_TRCACVR9 as u32, 203 | TRCACATR1 = SystemReg_REG_TRCACATR1 as u32, 204 | TRCACATR9 = SystemReg_REG_TRCACATR9 as u32, 205 | TRCACVR2 = SystemReg_REG_TRCACVR2 as u32, 206 | TRCACVR10 = SystemReg_REG_TRCACVR10 as u32, 207 | TRCACATR2 = SystemReg_REG_TRCACATR2 as u32, 208 | TRCACATR10 = SystemReg_REG_TRCACATR10 as u32, 209 | TRCDVCVR1 = SystemReg_REG_TRCDVCVR1 as u32, 210 | TRCDVCVR5 = SystemReg_REG_TRCDVCVR5 as u32, 211 | TRCDVCMR1 = SystemReg_REG_TRCDVCMR1 as u32, 212 | TRCDVCMR5 = SystemReg_REG_TRCDVCMR5 as u32, 213 | TRCACVR3 = SystemReg_REG_TRCACVR3 as u32, 214 | TRCACVR11 = SystemReg_REG_TRCACVR11 as u32, 215 | TRCACATR3 = SystemReg_REG_TRCACATR3 as u32, 216 | TRCACATR11 = SystemReg_REG_TRCACATR11 as u32, 217 | TRCACVR4 = SystemReg_REG_TRCACVR4 as u32, 218 | TRCACVR12 = SystemReg_REG_TRCACVR12 as u32, 219 | TRCACATR4 = SystemReg_REG_TRCACATR4 as u32, 220 | TRCACATR12 = SystemReg_REG_TRCACATR12 as u32, 221 | TRCDVCVR2 = SystemReg_REG_TRCDVCVR2 as u32, 222 | TRCDVCVR6 = SystemReg_REG_TRCDVCVR6 as u32, 223 | TRCDVCMR2 = SystemReg_REG_TRCDVCMR2 as u32, 224 | TRCDVCMR6 = SystemReg_REG_TRCDVCMR6 as u32, 225 | TRCACVR5 = SystemReg_REG_TRCACVR5 as u32, 226 | TRCACVR13 = SystemReg_REG_TRCACVR13 as u32, 227 | TRCACATR5 = SystemReg_REG_TRCACATR5 as u32, 228 | TRCACATR13 = SystemReg_REG_TRCACATR13 as u32, 229 | TRCACVR6 = SystemReg_REG_TRCACVR6 as u32, 230 | TRCACVR14 = SystemReg_REG_TRCACVR14 as u32, 231 | TRCACATR6 = SystemReg_REG_TRCACATR6 as u32, 232 | TRCACATR14 = SystemReg_REG_TRCACATR14 as u32, 233 | TRCDVCVR3 = SystemReg_REG_TRCDVCVR3 as u32, 234 | TRCDVCVR7 = SystemReg_REG_TRCDVCVR7 as u32, 235 | TRCDVCMR3 = SystemReg_REG_TRCDVCMR3 as u32, 236 | TRCDVCMR7 = SystemReg_REG_TRCDVCMR7 as u32, 237 | TRCACVR7 = SystemReg_REG_TRCACVR7 as u32, 238 | TRCACVR15 = SystemReg_REG_TRCACVR15 as u32, 239 | TRCACATR7 = SystemReg_REG_TRCACATR7 as u32, 240 | TRCACATR15 = SystemReg_REG_TRCACATR15 as u32, 241 | TRCCIDCVR0 = SystemReg_REG_TRCCIDCVR0 as u32, 242 | TRCVMIDCVR0 = SystemReg_REG_TRCVMIDCVR0 as u32, 243 | TRCCIDCCTLR0 = SystemReg_REG_TRCCIDCCTLR0 as u32, 244 | TRCCIDCCTLR1 = SystemReg_REG_TRCCIDCCTLR1 as u32, 245 | TRCCIDCVR1 = SystemReg_REG_TRCCIDCVR1 as u32, 246 | TRCVMIDCVR1 = SystemReg_REG_TRCVMIDCVR1 as u32, 247 | TRCVMIDCCTLR0 = SystemReg_REG_TRCVMIDCCTLR0 as u32, 248 | TRCVMIDCCTLR1 = SystemReg_REG_TRCVMIDCCTLR1 as u32, 249 | TRCCIDCVR2 = SystemReg_REG_TRCCIDCVR2 as u32, 250 | TRCVMIDCVR2 = SystemReg_REG_TRCVMIDCVR2 as u32, 251 | TRCCIDCVR3 = SystemReg_REG_TRCCIDCVR3 as u32, 252 | TRCVMIDCVR3 = SystemReg_REG_TRCVMIDCVR3 as u32, 253 | TRCCIDCVR4 = SystemReg_REG_TRCCIDCVR4 as u32, 254 | TRCVMIDCVR4 = SystemReg_REG_TRCVMIDCVR4 as u32, 255 | TRCCIDCVR5 = SystemReg_REG_TRCCIDCVR5 as u32, 256 | TRCVMIDCVR5 = SystemReg_REG_TRCVMIDCVR5 as u32, 257 | TRCCIDCVR6 = SystemReg_REG_TRCCIDCVR6 as u32, 258 | TRCVMIDCVR6 = SystemReg_REG_TRCVMIDCVR6 as u32, 259 | TRCCIDCVR7 = SystemReg_REG_TRCCIDCVR7 as u32, 260 | TRCVMIDCVR7 = SystemReg_REG_TRCVMIDCVR7 as u32, 261 | TRCITCTRL = SystemReg_REG_TRCITCTRL as u32, 262 | TRCCLAIMSET = SystemReg_REG_TRCCLAIMSET as u32, 263 | TRCCLAIMCLR = SystemReg_REG_TRCCLAIMCLR as u32, 264 | TRCLAR = SystemReg_REG_TRCLAR as u32, 265 | TEECR32_EL1 = SystemReg_REG_TEECR32_EL1 as u32, 266 | TEEHBR32_EL1 = SystemReg_REG_TEEHBR32_EL1 as u32, 267 | DBGDTR_EL0 = SystemReg_REG_DBGDTR_EL0 as u32, 268 | DBGDTRTX_EL0 = SystemReg_REG_DBGDTRTX_EL0 as u32, 269 | DBGVCR32_EL2 = SystemReg_REG_DBGVCR32_EL2 as u32, 270 | SCTLR_EL1 = SystemReg_REG_SCTLR_EL1 as u32, 271 | ACTLR_EL1 = SystemReg_REG_ACTLR_EL1 as u32, 272 | CPACR_EL1 = SystemReg_REG_CPACR_EL1 as u32, 273 | RGSR_EL1 = SystemReg_REG_RGSR_EL1 as u32, 274 | GCR_EL1 = SystemReg_REG_GCR_EL1 as u32, 275 | TRFCR_EL1 = SystemReg_REG_TRFCR_EL1 as u32, 276 | TTBR0_EL1 = SystemReg_REG_TTBR0_EL1 as u32, 277 | TTBR1_EL1 = SystemReg_REG_TTBR1_EL1 as u32, 278 | TCR_EL1 = SystemReg_REG_TCR_EL1 as u32, 279 | APIAKEYLO_EL1 = SystemReg_REG_APIAKEYLO_EL1 as u32, 280 | APIAKEYHI_EL1 = SystemReg_REG_APIAKEYHI_EL1 as u32, 281 | APIBKEYLO_EL1 = SystemReg_REG_APIBKEYLO_EL1 as u32, 282 | APIBKEYHI_EL1 = SystemReg_REG_APIBKEYHI_EL1 as u32, 283 | APDAKEYLO_EL1 = SystemReg_REG_APDAKEYLO_EL1 as u32, 284 | APDAKEYHI_EL1 = SystemReg_REG_APDAKEYHI_EL1 as u32, 285 | APDBKEYLO_EL1 = SystemReg_REG_APDBKEYLO_EL1 as u32, 286 | APDBKEYHI_EL1 = SystemReg_REG_APDBKEYHI_EL1 as u32, 287 | APGAKEYLO_EL1 = SystemReg_REG_APGAKEYLO_EL1 as u32, 288 | APGAKEYHI_EL1 = SystemReg_REG_APGAKEYHI_EL1 as u32, 289 | SPSR_EL1 = SystemReg_REG_SPSR_EL1 as u32, 290 | ELR_EL1 = SystemReg_REG_ELR_EL1 as u32, 291 | SP_EL0 = SystemReg_REG_SP_EL0 as u32, 292 | SPSEL = SystemReg_REG_SPSEL as u32, 293 | CURRENTEL = SystemReg_REG_CURRENTEL as u32, 294 | PAN = SystemReg_REG_PAN as u32, 295 | UAO = SystemReg_REG_UAO as u32, 296 | ICC_PMR_EL1 = SystemReg_REG_ICC_PMR_EL1 as u32, 297 | AFSR0_EL1 = SystemReg_REG_AFSR0_EL1 as u32, 298 | AFSR1_EL1 = SystemReg_REG_AFSR1_EL1 as u32, 299 | ESR_EL1 = SystemReg_REG_ESR_EL1 as u32, 300 | ERRSELR_EL1 = SystemReg_REG_ERRSELR_EL1 as u32, 301 | ERXCTLR_EL1 = SystemReg_REG_ERXCTLR_EL1 as u32, 302 | ERXSTATUS_EL1 = SystemReg_REG_ERXSTATUS_EL1 as u32, 303 | ERXADDR_EL1 = SystemReg_REG_ERXADDR_EL1 as u32, 304 | ERXPFGCTL_EL1 = SystemReg_REG_ERXPFGCTL_EL1 as u32, 305 | ERXPFGCDN_EL1 = SystemReg_REG_ERXPFGCDN_EL1 as u32, 306 | ERXMISC0_EL1 = SystemReg_REG_ERXMISC0_EL1 as u32, 307 | ERXMISC1_EL1 = SystemReg_REG_ERXMISC1_EL1 as u32, 308 | ERXMISC2_EL1 = SystemReg_REG_ERXMISC2_EL1 as u32, 309 | ERXMISC3_EL1 = SystemReg_REG_ERXMISC3_EL1 as u32, 310 | ERXTS_EL1 = SystemReg_REG_ERXTS_EL1 as u32, 311 | TFSR_EL1 = SystemReg_REG_TFSR_EL1 as u32, 312 | TFSRE0_EL1 = SystemReg_REG_TFSRE0_EL1 as u32, 313 | FAR_EL1 = SystemReg_REG_FAR_EL1 as u32, 314 | PAR_EL1 = SystemReg_REG_PAR_EL1 as u32, 315 | PMSCR_EL1 = SystemReg_REG_PMSCR_EL1 as u32, 316 | PMSICR_EL1 = SystemReg_REG_PMSICR_EL1 as u32, 317 | PMSIRR_EL1 = SystemReg_REG_PMSIRR_EL1 as u32, 318 | PMSFCR_EL1 = SystemReg_REG_PMSFCR_EL1 as u32, 319 | PMSEVFR_EL1 = SystemReg_REG_PMSEVFR_EL1 as u32, 320 | PMSLATFR_EL1 = SystemReg_REG_PMSLATFR_EL1 as u32, 321 | PMSIDR_EL1 = SystemReg_REG_PMSIDR_EL1 as u32, 322 | PMBLIMITR_EL1 = SystemReg_REG_PMBLIMITR_EL1 as u32, 323 | PMBPTR_EL1 = SystemReg_REG_PMBPTR_EL1 as u32, 324 | PMBSR_EL1 = SystemReg_REG_PMBSR_EL1 as u32, 325 | PMBIDR_EL1 = SystemReg_REG_PMBIDR_EL1 as u32, 326 | TRBLIMITR_EL1 = SystemReg_REG_TRBLIMITR_EL1 as u32, 327 | TRBPTR_EL1 = SystemReg_REG_TRBPTR_EL1 as u32, 328 | TRBBASER_EL1 = SystemReg_REG_TRBBASER_EL1 as u32, 329 | TRBSR_EL1 = SystemReg_REG_TRBSR_EL1 as u32, 330 | TRBMAR_EL1 = SystemReg_REG_TRBMAR_EL1 as u32, 331 | TRBTRG_EL1 = SystemReg_REG_TRBTRG_EL1 as u32, 332 | PMINTENSET_EL1 = SystemReg_REG_PMINTENSET_EL1 as u32, 333 | PMINTENCLR_EL1 = SystemReg_REG_PMINTENCLR_EL1 as u32, 334 | PMMIR_EL1 = SystemReg_REG_PMMIR_EL1 as u32, 335 | MAIR_EL1 = SystemReg_REG_MAIR_EL1 as u32, 336 | AMAIR_EL1 = SystemReg_REG_AMAIR_EL1 as u32, 337 | LORSA_EL1 = SystemReg_REG_LORSA_EL1 as u32, 338 | LOREA_EL1 = SystemReg_REG_LOREA_EL1 as u32, 339 | LORN_EL1 = SystemReg_REG_LORN_EL1 as u32, 340 | LORC_EL1 = SystemReg_REG_LORC_EL1 as u32, 341 | MPAM1_EL1 = SystemReg_REG_MPAM1_EL1 as u32, 342 | MPAM0_EL1 = SystemReg_REG_MPAM0_EL1 as u32, 343 | VBAR_EL1 = SystemReg_REG_VBAR_EL1 as u32, 344 | RMR_EL1 = SystemReg_REG_RMR_EL1 as u32, 345 | DISR_EL1 = SystemReg_REG_DISR_EL1 as u32, 346 | ICC_EOIR0_EL1 = SystemReg_REG_ICC_EOIR0_EL1 as u32, 347 | ICC_BPR0_EL1 = SystemReg_REG_ICC_BPR0_EL1 as u32, 348 | ICC_AP0R0_EL1 = SystemReg_REG_ICC_AP0R0_EL1 as u32, 349 | ICC_AP0R1_EL1 = SystemReg_REG_ICC_AP0R1_EL1 as u32, 350 | ICC_AP0R2_EL1 = SystemReg_REG_ICC_AP0R2_EL1 as u32, 351 | ICC_AP0R3_EL1 = SystemReg_REG_ICC_AP0R3_EL1 as u32, 352 | ICC_AP1R0_EL1 = SystemReg_REG_ICC_AP1R0_EL1 as u32, 353 | ICC_AP1R1_EL1 = SystemReg_REG_ICC_AP1R1_EL1 as u32, 354 | ICC_AP1R2_EL1 = SystemReg_REG_ICC_AP1R2_EL1 as u32, 355 | ICC_AP1R3_EL1 = SystemReg_REG_ICC_AP1R3_EL1 as u32, 356 | ICC_DIR_EL1 = SystemReg_REG_ICC_DIR_EL1 as u32, 357 | ICC_SGI1R_EL1 = SystemReg_REG_ICC_SGI1R_EL1 as u32, 358 | ICC_ASGI1R_EL1 = SystemReg_REG_ICC_ASGI1R_EL1 as u32, 359 | ICC_SGI0R_EL1 = SystemReg_REG_ICC_SGI0R_EL1 as u32, 360 | ICC_EOIR1_EL1 = SystemReg_REG_ICC_EOIR1_EL1 as u32, 361 | ICC_BPR1_EL1 = SystemReg_REG_ICC_BPR1_EL1 as u32, 362 | ICC_CTLR_EL1 = SystemReg_REG_ICC_CTLR_EL1 as u32, 363 | ICC_SRE_EL1 = SystemReg_REG_ICC_SRE_EL1 as u32, 364 | ICC_IGRPEN0_EL1 = SystemReg_REG_ICC_IGRPEN0_EL1 as u32, 365 | ICC_IGRPEN1_EL1 = SystemReg_REG_ICC_IGRPEN1_EL1 as u32, 366 | ICC_SEIEN_EL1 = SystemReg_REG_ICC_SEIEN_EL1 as u32, 367 | CONTEXTIDR_EL1 = SystemReg_REG_CONTEXTIDR_EL1 as u32, 368 | TPIDR_EL1 = SystemReg_REG_TPIDR_EL1 as u32, 369 | SCXTNUM_EL1 = SystemReg_REG_SCXTNUM_EL1 as u32, 370 | CNTKCTL_EL1 = SystemReg_REG_CNTKCTL_EL1 as u32, 371 | CSSELR_EL1 = SystemReg_REG_CSSELR_EL1 as u32, 372 | NZCV = SystemReg_REG_NZCV as u32, 373 | DAIFSET = SystemReg_REG_DAIFSET as u32, 374 | DIT = SystemReg_REG_DIT as u32, 375 | SSBS = SystemReg_REG_SSBS as u32, 376 | TCO = SystemReg_REG_TCO as u32, 377 | FPCR = SystemReg_REG_FPCR as u32, 378 | FPSR = SystemReg_REG_FPSR as u32, 379 | DSPSR_EL0 = SystemReg_REG_DSPSR_EL0 as u32, 380 | DLR_EL0 = SystemReg_REG_DLR_EL0 as u32, 381 | PMCR_EL0 = SystemReg_REG_PMCR_EL0 as u32, 382 | PMCNTENSET_EL0 = SystemReg_REG_PMCNTENSET_EL0 as u32, 383 | PMCNTENCLR_EL0 = SystemReg_REG_PMCNTENCLR_EL0 as u32, 384 | PMOVSCLR_EL0 = SystemReg_REG_PMOVSCLR_EL0 as u32, 385 | PMSWINC_EL0 = SystemReg_REG_PMSWINC_EL0 as u32, 386 | PMSELR_EL0 = SystemReg_REG_PMSELR_EL0 as u32, 387 | PMCCNTR_EL0 = SystemReg_REG_PMCCNTR_EL0 as u32, 388 | PMXEVTYPER_EL0 = SystemReg_REG_PMXEVTYPER_EL0 as u32, 389 | PMXEVCNTR_EL0 = SystemReg_REG_PMXEVCNTR_EL0 as u32, 390 | DAIFCLR = SystemReg_REG_DAIFCLR as u32, 391 | PMUSERENR_EL0 = SystemReg_REG_PMUSERENR_EL0 as u32, 392 | PMOVSSET_EL0 = SystemReg_REG_PMOVSSET_EL0 as u32, 393 | TPIDR_EL0 = SystemReg_REG_TPIDR_EL0 as u32, 394 | TPIDRRO_EL0 = SystemReg_REG_TPIDRRO_EL0 as u32, 395 | SCXTNUM_EL0 = SystemReg_REG_SCXTNUM_EL0 as u32, 396 | AMCR_EL0 = SystemReg_REG_AMCR_EL0 as u32, 397 | AMUSERENR_EL0 = SystemReg_REG_AMUSERENR_EL0 as u32, 398 | AMCNTENCLR0_EL0 = SystemReg_REG_AMCNTENCLR0_EL0 as u32, 399 | AMCNTENSET0_EL0 = SystemReg_REG_AMCNTENSET0_EL0 as u32, 400 | AMCNTENCLR1_EL0 = SystemReg_REG_AMCNTENCLR1_EL0 as u32, 401 | AMCNTENSET1_EL0 = SystemReg_REG_AMCNTENSET1_EL0 as u32, 402 | AMEVCNTR00_EL0 = SystemReg_REG_AMEVCNTR00_EL0 as u32, 403 | AMEVCNTR01_EL0 = SystemReg_REG_AMEVCNTR01_EL0 as u32, 404 | AMEVCNTR02_EL0 = SystemReg_REG_AMEVCNTR02_EL0 as u32, 405 | AMEVCNTR03_EL0 = SystemReg_REG_AMEVCNTR03_EL0 as u32, 406 | AMEVCNTR10_EL0 = SystemReg_REG_AMEVCNTR10_EL0 as u32, 407 | AMEVCNTR11_EL0 = SystemReg_REG_AMEVCNTR11_EL0 as u32, 408 | AMEVCNTR12_EL0 = SystemReg_REG_AMEVCNTR12_EL0 as u32, 409 | AMEVCNTR13_EL0 = SystemReg_REG_AMEVCNTR13_EL0 as u32, 410 | AMEVCNTR14_EL0 = SystemReg_REG_AMEVCNTR14_EL0 as u32, 411 | AMEVCNTR15_EL0 = SystemReg_REG_AMEVCNTR15_EL0 as u32, 412 | AMEVCNTR16_EL0 = SystemReg_REG_AMEVCNTR16_EL0 as u32, 413 | AMEVCNTR17_EL0 = SystemReg_REG_AMEVCNTR17_EL0 as u32, 414 | AMEVCNTR18_EL0 = SystemReg_REG_AMEVCNTR18_EL0 as u32, 415 | AMEVCNTR19_EL0 = SystemReg_REG_AMEVCNTR19_EL0 as u32, 416 | AMEVCNTR110_EL0 = SystemReg_REG_AMEVCNTR110_EL0 as u32, 417 | AMEVCNTR111_EL0 = SystemReg_REG_AMEVCNTR111_EL0 as u32, 418 | AMEVCNTR112_EL0 = SystemReg_REG_AMEVCNTR112_EL0 as u32, 419 | AMEVCNTR113_EL0 = SystemReg_REG_AMEVCNTR113_EL0 as u32, 420 | AMEVCNTR114_EL0 = SystemReg_REG_AMEVCNTR114_EL0 as u32, 421 | AMEVCNTR115_EL0 = SystemReg_REG_AMEVCNTR115_EL0 as u32, 422 | AMEVTYPER10_EL0 = SystemReg_REG_AMEVTYPER10_EL0 as u32, 423 | AMEVTYPER11_EL0 = SystemReg_REG_AMEVTYPER11_EL0 as u32, 424 | AMEVTYPER12_EL0 = SystemReg_REG_AMEVTYPER12_EL0 as u32, 425 | AMEVTYPER13_EL0 = SystemReg_REG_AMEVTYPER13_EL0 as u32, 426 | AMEVTYPER14_EL0 = SystemReg_REG_AMEVTYPER14_EL0 as u32, 427 | AMEVTYPER15_EL0 = SystemReg_REG_AMEVTYPER15_EL0 as u32, 428 | AMEVTYPER16_EL0 = SystemReg_REG_AMEVTYPER16_EL0 as u32, 429 | AMEVTYPER17_EL0 = SystemReg_REG_AMEVTYPER17_EL0 as u32, 430 | AMEVTYPER18_EL0 = SystemReg_REG_AMEVTYPER18_EL0 as u32, 431 | AMEVTYPER19_EL0 = SystemReg_REG_AMEVTYPER19_EL0 as u32, 432 | AMEVTYPER110_EL0 = SystemReg_REG_AMEVTYPER110_EL0 as u32, 433 | AMEVTYPER111_EL0 = SystemReg_REG_AMEVTYPER111_EL0 as u32, 434 | AMEVTYPER112_EL0 = SystemReg_REG_AMEVTYPER112_EL0 as u32, 435 | AMEVTYPER113_EL0 = SystemReg_REG_AMEVTYPER113_EL0 as u32, 436 | AMEVTYPER114_EL0 = SystemReg_REG_AMEVTYPER114_EL0 as u32, 437 | AMEVTYPER115_EL0 = SystemReg_REG_AMEVTYPER115_EL0 as u32, 438 | CNTFRQ_EL0 = SystemReg_REG_CNTFRQ_EL0 as u32, 439 | CNTP_TVAL_EL0 = SystemReg_REG_CNTP_TVAL_EL0 as u32, 440 | CNTP_CTL_EL0 = SystemReg_REG_CNTP_CTL_EL0 as u32, 441 | CNTP_CVAL_EL0 = SystemReg_REG_CNTP_CVAL_EL0 as u32, 442 | CNTV_TVAL_EL0 = SystemReg_REG_CNTV_TVAL_EL0 as u32, 443 | CNTV_CTL_EL0 = SystemReg_REG_CNTV_CTL_EL0 as u32, 444 | CNTV_CVAL_EL0 = SystemReg_REG_CNTV_CVAL_EL0 as u32, 445 | PMEVCNTR0_EL0 = SystemReg_REG_PMEVCNTR0_EL0 as u32, 446 | PMEVCNTR1_EL0 = SystemReg_REG_PMEVCNTR1_EL0 as u32, 447 | PMEVCNTR2_EL0 = SystemReg_REG_PMEVCNTR2_EL0 as u32, 448 | PMEVCNTR3_EL0 = SystemReg_REG_PMEVCNTR3_EL0 as u32, 449 | PMEVCNTR4_EL0 = SystemReg_REG_PMEVCNTR4_EL0 as u32, 450 | PMEVCNTR5_EL0 = SystemReg_REG_PMEVCNTR5_EL0 as u32, 451 | PMEVCNTR6_EL0 = SystemReg_REG_PMEVCNTR6_EL0 as u32, 452 | PMEVCNTR7_EL0 = SystemReg_REG_PMEVCNTR7_EL0 as u32, 453 | PMEVCNTR8_EL0 = SystemReg_REG_PMEVCNTR8_EL0 as u32, 454 | PMEVCNTR9_EL0 = SystemReg_REG_PMEVCNTR9_EL0 as u32, 455 | PMEVCNTR10_EL0 = SystemReg_REG_PMEVCNTR10_EL0 as u32, 456 | PMEVCNTR11_EL0 = SystemReg_REG_PMEVCNTR11_EL0 as u32, 457 | PMEVCNTR12_EL0 = SystemReg_REG_PMEVCNTR12_EL0 as u32, 458 | PMEVCNTR13_EL0 = SystemReg_REG_PMEVCNTR13_EL0 as u32, 459 | PMEVCNTR14_EL0 = SystemReg_REG_PMEVCNTR14_EL0 as u32, 460 | PMEVCNTR15_EL0 = SystemReg_REG_PMEVCNTR15_EL0 as u32, 461 | PMEVCNTR16_EL0 = SystemReg_REG_PMEVCNTR16_EL0 as u32, 462 | PMEVCNTR17_EL0 = SystemReg_REG_PMEVCNTR17_EL0 as u32, 463 | PMEVCNTR18_EL0 = SystemReg_REG_PMEVCNTR18_EL0 as u32, 464 | PMEVCNTR19_EL0 = SystemReg_REG_PMEVCNTR19_EL0 as u32, 465 | PMEVCNTR20_EL0 = SystemReg_REG_PMEVCNTR20_EL0 as u32, 466 | PMEVCNTR21_EL0 = SystemReg_REG_PMEVCNTR21_EL0 as u32, 467 | PMEVCNTR22_EL0 = SystemReg_REG_PMEVCNTR22_EL0 as u32, 468 | PMEVCNTR23_EL0 = SystemReg_REG_PMEVCNTR23_EL0 as u32, 469 | PMEVCNTR24_EL0 = SystemReg_REG_PMEVCNTR24_EL0 as u32, 470 | PMEVCNTR25_EL0 = SystemReg_REG_PMEVCNTR25_EL0 as u32, 471 | PMEVCNTR26_EL0 = SystemReg_REG_PMEVCNTR26_EL0 as u32, 472 | PMEVCNTR27_EL0 = SystemReg_REG_PMEVCNTR27_EL0 as u32, 473 | PMEVCNTR28_EL0 = SystemReg_REG_PMEVCNTR28_EL0 as u32, 474 | PMEVCNTR29_EL0 = SystemReg_REG_PMEVCNTR29_EL0 as u32, 475 | PMEVCNTR30_EL0 = SystemReg_REG_PMEVCNTR30_EL0 as u32, 476 | PMEVTYPER0_EL0 = SystemReg_REG_PMEVTYPER0_EL0 as u32, 477 | PMEVTYPER1_EL0 = SystemReg_REG_PMEVTYPER1_EL0 as u32, 478 | PMEVTYPER2_EL0 = SystemReg_REG_PMEVTYPER2_EL0 as u32, 479 | PMEVTYPER3_EL0 = SystemReg_REG_PMEVTYPER3_EL0 as u32, 480 | PMEVTYPER4_EL0 = SystemReg_REG_PMEVTYPER4_EL0 as u32, 481 | PMEVTYPER5_EL0 = SystemReg_REG_PMEVTYPER5_EL0 as u32, 482 | PMEVTYPER6_EL0 = SystemReg_REG_PMEVTYPER6_EL0 as u32, 483 | PMEVTYPER7_EL0 = SystemReg_REG_PMEVTYPER7_EL0 as u32, 484 | PMEVTYPER8_EL0 = SystemReg_REG_PMEVTYPER8_EL0 as u32, 485 | PMEVTYPER9_EL0 = SystemReg_REG_PMEVTYPER9_EL0 as u32, 486 | PMEVTYPER10_EL0 = SystemReg_REG_PMEVTYPER10_EL0 as u32, 487 | PMEVTYPER11_EL0 = SystemReg_REG_PMEVTYPER11_EL0 as u32, 488 | PMEVTYPER12_EL0 = SystemReg_REG_PMEVTYPER12_EL0 as u32, 489 | PMEVTYPER13_EL0 = SystemReg_REG_PMEVTYPER13_EL0 as u32, 490 | PMEVTYPER14_EL0 = SystemReg_REG_PMEVTYPER14_EL0 as u32, 491 | PMEVTYPER15_EL0 = SystemReg_REG_PMEVTYPER15_EL0 as u32, 492 | PMEVTYPER16_EL0 = SystemReg_REG_PMEVTYPER16_EL0 as u32, 493 | PMEVTYPER17_EL0 = SystemReg_REG_PMEVTYPER17_EL0 as u32, 494 | PMEVTYPER18_EL0 = SystemReg_REG_PMEVTYPER18_EL0 as u32, 495 | PMEVTYPER19_EL0 = SystemReg_REG_PMEVTYPER19_EL0 as u32, 496 | PMEVTYPER20_EL0 = SystemReg_REG_PMEVTYPER20_EL0 as u32, 497 | PMEVTYPER21_EL0 = SystemReg_REG_PMEVTYPER21_EL0 as u32, 498 | PMEVTYPER22_EL0 = SystemReg_REG_PMEVTYPER22_EL0 as u32, 499 | PMEVTYPER23_EL0 = SystemReg_REG_PMEVTYPER23_EL0 as u32, 500 | PMEVTYPER24_EL0 = SystemReg_REG_PMEVTYPER24_EL0 as u32, 501 | PMEVTYPER25_EL0 = SystemReg_REG_PMEVTYPER25_EL0 as u32, 502 | PMEVTYPER26_EL0 = SystemReg_REG_PMEVTYPER26_EL0 as u32, 503 | PMEVTYPER27_EL0 = SystemReg_REG_PMEVTYPER27_EL0 as u32, 504 | PMEVTYPER28_EL0 = SystemReg_REG_PMEVTYPER28_EL0 as u32, 505 | PMEVTYPER29_EL0 = SystemReg_REG_PMEVTYPER29_EL0 as u32, 506 | PMEVTYPER30_EL0 = SystemReg_REG_PMEVTYPER30_EL0 as u32, 507 | PMCCFILTR_EL0 = SystemReg_REG_PMCCFILTR_EL0 as u32, 508 | VPIDR_EL2 = SystemReg_REG_VPIDR_EL2 as u32, 509 | VMPIDR_EL2 = SystemReg_REG_VMPIDR_EL2 as u32, 510 | SCTLR_EL2 = SystemReg_REG_SCTLR_EL2 as u32, 511 | ACTLR_EL2 = SystemReg_REG_ACTLR_EL2 as u32, 512 | HCR_EL2 = SystemReg_REG_HCR_EL2 as u32, 513 | MDCR_EL2 = SystemReg_REG_MDCR_EL2 as u32, 514 | CPTR_EL2 = SystemReg_REG_CPTR_EL2 as u32, 515 | HSTR_EL2 = SystemReg_REG_HSTR_EL2 as u32, 516 | HACR_EL2 = SystemReg_REG_HACR_EL2 as u32, 517 | TRFCR_EL2 = SystemReg_REG_TRFCR_EL2 as u32, 518 | SDER32_EL2 = SystemReg_REG_SDER32_EL2 as u32, 519 | TTBR0_EL2 = SystemReg_REG_TTBR0_EL2 as u32, 520 | TTBR1_EL2 = SystemReg_REG_TTBR1_EL2 as u32, 521 | TCR_EL2 = SystemReg_REG_TCR_EL2 as u32, 522 | VTTBR_EL2 = SystemReg_REG_VTTBR_EL2 as u32, 523 | VTCR_EL2 = SystemReg_REG_VTCR_EL2 as u32, 524 | VNCR_EL2 = SystemReg_REG_VNCR_EL2 as u32, 525 | VSTTBR_EL2 = SystemReg_REG_VSTTBR_EL2 as u32, 526 | VSTCR_EL2 = SystemReg_REG_VSTCR_EL2 as u32, 527 | DACR32_EL2 = SystemReg_REG_DACR32_EL2 as u32, 528 | SPSR_EL2 = SystemReg_REG_SPSR_EL2 as u32, 529 | ELR_EL2 = SystemReg_REG_ELR_EL2 as u32, 530 | SP_EL1 = SystemReg_REG_SP_EL1 as u32, 531 | SPSR_IRQ = SystemReg_REG_SPSR_IRQ as u32, 532 | SPSR_ABT = SystemReg_REG_SPSR_ABT as u32, 533 | SPSR_UND = SystemReg_REG_SPSR_UND as u32, 534 | SPSR_FIQ = SystemReg_REG_SPSR_FIQ as u32, 535 | IFSR32_EL2 = SystemReg_REG_IFSR32_EL2 as u32, 536 | AFSR0_EL2 = SystemReg_REG_AFSR0_EL2 as u32, 537 | AFSR1_EL2 = SystemReg_REG_AFSR1_EL2 as u32, 538 | ESR_EL2 = SystemReg_REG_ESR_EL2 as u32, 539 | VSESR_EL2 = SystemReg_REG_VSESR_EL2 as u32, 540 | FPEXC32_EL2 = SystemReg_REG_FPEXC32_EL2 as u32, 541 | TFSR_EL2 = SystemReg_REG_TFSR_EL2 as u32, 542 | FAR_EL2 = SystemReg_REG_FAR_EL2 as u32, 543 | HPFAR_EL2 = SystemReg_REG_HPFAR_EL2 as u32, 544 | PMSCR_EL2 = SystemReg_REG_PMSCR_EL2 as u32, 545 | MAIR_EL2 = SystemReg_REG_MAIR_EL2 as u32, 546 | AMAIR_EL2 = SystemReg_REG_AMAIR_EL2 as u32, 547 | MPAMHCR_EL2 = SystemReg_REG_MPAMHCR_EL2 as u32, 548 | MPAMVPMV_EL2 = SystemReg_REG_MPAMVPMV_EL2 as u32, 549 | MPAM2_EL2 = SystemReg_REG_MPAM2_EL2 as u32, 550 | MPAMVPM0_EL2 = SystemReg_REG_MPAMVPM0_EL2 as u32, 551 | MPAMVPM1_EL2 = SystemReg_REG_MPAMVPM1_EL2 as u32, 552 | MPAMVPM2_EL2 = SystemReg_REG_MPAMVPM2_EL2 as u32, 553 | MPAMVPM3_EL2 = SystemReg_REG_MPAMVPM3_EL2 as u32, 554 | MPAMVPM4_EL2 = SystemReg_REG_MPAMVPM4_EL2 as u32, 555 | MPAMVPM5_EL2 = SystemReg_REG_MPAMVPM5_EL2 as u32, 556 | MPAMVPM6_EL2 = SystemReg_REG_MPAMVPM6_EL2 as u32, 557 | MPAMVPM7_EL2 = SystemReg_REG_MPAMVPM7_EL2 as u32, 558 | VBAR_EL2 = SystemReg_REG_VBAR_EL2 as u32, 559 | RMR_EL2 = SystemReg_REG_RMR_EL2 as u32, 560 | VDISR_EL2 = SystemReg_REG_VDISR_EL2 as u32, 561 | ICH_AP0R0_EL2 = SystemReg_REG_ICH_AP0R0_EL2 as u32, 562 | ICH_AP0R1_EL2 = SystemReg_REG_ICH_AP0R1_EL2 as u32, 563 | ICH_AP0R2_EL2 = SystemReg_REG_ICH_AP0R2_EL2 as u32, 564 | ICH_AP0R3_EL2 = SystemReg_REG_ICH_AP0R3_EL2 as u32, 565 | ICH_AP1R0_EL2 = SystemReg_REG_ICH_AP1R0_EL2 as u32, 566 | ICH_AP1R1_EL2 = SystemReg_REG_ICH_AP1R1_EL2 as u32, 567 | ICH_AP1R2_EL2 = SystemReg_REG_ICH_AP1R2_EL2 as u32, 568 | ICH_AP1R3_EL2 = SystemReg_REG_ICH_AP1R3_EL2 as u32, 569 | ICH_VSEIR_EL2 = SystemReg_REG_ICH_VSEIR_EL2 as u32, 570 | ICC_SRE_EL2 = SystemReg_REG_ICC_SRE_EL2 as u32, 571 | ICH_HCR_EL2 = SystemReg_REG_ICH_HCR_EL2 as u32, 572 | ICH_MISR_EL2 = SystemReg_REG_ICH_MISR_EL2 as u32, 573 | ICH_VMCR_EL2 = SystemReg_REG_ICH_VMCR_EL2 as u32, 574 | ICH_LR0_EL2 = SystemReg_REG_ICH_LR0_EL2 as u32, 575 | ICH_LR1_EL2 = SystemReg_REG_ICH_LR1_EL2 as u32, 576 | ICH_LR2_EL2 = SystemReg_REG_ICH_LR2_EL2 as u32, 577 | ICH_LR3_EL2 = SystemReg_REG_ICH_LR3_EL2 as u32, 578 | ICH_LR4_EL2 = SystemReg_REG_ICH_LR4_EL2 as u32, 579 | ICH_LR5_EL2 = SystemReg_REG_ICH_LR5_EL2 as u32, 580 | ICH_LR6_EL2 = SystemReg_REG_ICH_LR6_EL2 as u32, 581 | ICH_LR7_EL2 = SystemReg_REG_ICH_LR7_EL2 as u32, 582 | ICH_LR8_EL2 = SystemReg_REG_ICH_LR8_EL2 as u32, 583 | ICH_LR9_EL2 = SystemReg_REG_ICH_LR9_EL2 as u32, 584 | ICH_LR10_EL2 = SystemReg_REG_ICH_LR10_EL2 as u32, 585 | ICH_LR11_EL2 = SystemReg_REG_ICH_LR11_EL2 as u32, 586 | ICH_LR12_EL2 = SystemReg_REG_ICH_LR12_EL2 as u32, 587 | ICH_LR13_EL2 = SystemReg_REG_ICH_LR13_EL2 as u32, 588 | ICH_LR14_EL2 = SystemReg_REG_ICH_LR14_EL2 as u32, 589 | ICH_LR15_EL2 = SystemReg_REG_ICH_LR15_EL2 as u32, 590 | CONTEXTIDR_EL2 = SystemReg_REG_CONTEXTIDR_EL2 as u32, 591 | TPIDR_EL2 = SystemReg_REG_TPIDR_EL2 as u32, 592 | SCXTNUM_EL2 = SystemReg_REG_SCXTNUM_EL2 as u32, 593 | CNTVOFF_EL2 = SystemReg_REG_CNTVOFF_EL2 as u32, 594 | CNTHCTL_EL2 = SystemReg_REG_CNTHCTL_EL2 as u32, 595 | CNTHP_TVAL_EL2 = SystemReg_REG_CNTHP_TVAL_EL2 as u32, 596 | CNTHP_CTL_EL2 = SystemReg_REG_CNTHP_CTL_EL2 as u32, 597 | CNTHP_CVAL_EL2 = SystemReg_REG_CNTHP_CVAL_EL2 as u32, 598 | CNTHV_TVAL_EL2 = SystemReg_REG_CNTHV_TVAL_EL2 as u32, 599 | CNTHV_CTL_EL2 = SystemReg_REG_CNTHV_CTL_EL2 as u32, 600 | CNTHV_CVAL_EL2 = SystemReg_REG_CNTHV_CVAL_EL2 as u32, 601 | CNTHVS_TVAL_EL2 = SystemReg_REG_CNTHVS_TVAL_EL2 as u32, 602 | CNTHVS_CTL_EL2 = SystemReg_REG_CNTHVS_CTL_EL2 as u32, 603 | CNTHVS_CVAL_EL2 = SystemReg_REG_CNTHVS_CVAL_EL2 as u32, 604 | CNTHPS_TVAL_EL2 = SystemReg_REG_CNTHPS_TVAL_EL2 as u32, 605 | CNTHPS_CTL_EL2 = SystemReg_REG_CNTHPS_CTL_EL2 as u32, 606 | CNTHPS_CVAL_EL2 = SystemReg_REG_CNTHPS_CVAL_EL2 as u32, 607 | SCTLR_EL12 = SystemReg_REG_SCTLR_EL12 as u32, 608 | CPACR_EL12 = SystemReg_REG_CPACR_EL12 as u32, 609 | TRFCR_EL12 = SystemReg_REG_TRFCR_EL12 as u32, 610 | TTBR0_EL12 = SystemReg_REG_TTBR0_EL12 as u32, 611 | TTBR1_EL12 = SystemReg_REG_TTBR1_EL12 as u32, 612 | TCR_EL12 = SystemReg_REG_TCR_EL12 as u32, 613 | SPSR_EL12 = SystemReg_REG_SPSR_EL12 as u32, 614 | ELR_EL12 = SystemReg_REG_ELR_EL12 as u32, 615 | AFSR0_EL12 = SystemReg_REG_AFSR0_EL12 as u32, 616 | AFSR1_EL12 = SystemReg_REG_AFSR1_EL12 as u32, 617 | ESR_EL12 = SystemReg_REG_ESR_EL12 as u32, 618 | TFSR_EL12 = SystemReg_REG_TFSR_EL12 as u32, 619 | FAR_EL12 = SystemReg_REG_FAR_EL12 as u32, 620 | PMSCR_EL12 = SystemReg_REG_PMSCR_EL12 as u32, 621 | MAIR_EL12 = SystemReg_REG_MAIR_EL12 as u32, 622 | AMAIR_EL12 = SystemReg_REG_AMAIR_EL12 as u32, 623 | MPAM1_EL12 = SystemReg_REG_MPAM1_EL12 as u32, 624 | VBAR_EL12 = SystemReg_REG_VBAR_EL12 as u32, 625 | CONTEXTIDR_EL12 = SystemReg_REG_CONTEXTIDR_EL12 as u32, 626 | SCXTNUM_EL12 = SystemReg_REG_SCXTNUM_EL12 as u32, 627 | CNTKCTL_EL12 = SystemReg_REG_CNTKCTL_EL12 as u32, 628 | CNTP_TVAL_EL02 = SystemReg_REG_CNTP_TVAL_EL02 as u32, 629 | CNTP_CTL_EL02 = SystemReg_REG_CNTP_CTL_EL02 as u32, 630 | CNTP_CVAL_EL02 = SystemReg_REG_CNTP_CVAL_EL02 as u32, 631 | CNTV_TVAL_EL02 = SystemReg_REG_CNTV_TVAL_EL02 as u32, 632 | CNTV_CTL_EL02 = SystemReg_REG_CNTV_CTL_EL02 as u32, 633 | CNTV_CVAL_EL02 = SystemReg_REG_CNTV_CVAL_EL02 as u32, 634 | SCTLR_EL3 = SystemReg_REG_SCTLR_EL3 as u32, 635 | ACTLR_EL3 = SystemReg_REG_ACTLR_EL3 as u32, 636 | SCR_EL3 = SystemReg_REG_SCR_EL3 as u32, 637 | SDER32_EL3 = SystemReg_REG_SDER32_EL3 as u32, 638 | CPTR_EL3 = SystemReg_REG_CPTR_EL3 as u32, 639 | MDCR_EL3 = SystemReg_REG_MDCR_EL3 as u32, 640 | TTBR0_EL3 = SystemReg_REG_TTBR0_EL3 as u32, 641 | TCR_EL3 = SystemReg_REG_TCR_EL3 as u32, 642 | SPSR_EL3 = SystemReg_REG_SPSR_EL3 as u32, 643 | ELR_EL3 = SystemReg_REG_ELR_EL3 as u32, 644 | SP_EL2 = SystemReg_REG_SP_EL2 as u32, 645 | AFSR0_EL3 = SystemReg_REG_AFSR0_EL3 as u32, 646 | AFSR1_EL3 = SystemReg_REG_AFSR1_EL3 as u32, 647 | ESR_EL3 = SystemReg_REG_ESR_EL3 as u32, 648 | TFSR_EL3 = SystemReg_REG_TFSR_EL3 as u32, 649 | FAR_EL3 = SystemReg_REG_FAR_EL3 as u32, 650 | MAIR_EL3 = SystemReg_REG_MAIR_EL3 as u32, 651 | AMAIR_EL3 = SystemReg_REG_AMAIR_EL3 as u32, 652 | MPAM3_EL3 = SystemReg_REG_MPAM3_EL3 as u32, 653 | VBAR_EL3 = SystemReg_REG_VBAR_EL3 as u32, 654 | RMR_EL3 = SystemReg_REG_RMR_EL3 as u32, 655 | ICC_CTLR_EL3 = SystemReg_REG_ICC_CTLR_EL3 as u32, 656 | ICC_SRE_EL3 = SystemReg_REG_ICC_SRE_EL3 as u32, 657 | ICC_IGRPEN1_EL3 = SystemReg_REG_ICC_IGRPEN1_EL3 as u32, 658 | TPIDR_EL3 = SystemReg_REG_TPIDR_EL3 as u32, 659 | SCXTNUM_EL3 = SystemReg_REG_SCXTNUM_EL3 as u32, 660 | CNTPS_TVAL_EL1 = SystemReg_REG_CNTPS_TVAL_EL1 as u32, 661 | CNTPS_CTL_EL1 = SystemReg_REG_CNTPS_CTL_EL1 as u32, 662 | CNTPS_CVAL_EL1 = SystemReg_REG_CNTPS_CVAL_EL1 as u32, 663 | PSTATE_SPSEL = SystemReg_REG_PSTATE_SPSEL as u32, 664 | } 665 | 666 | const_assert_eq!(SystemReg_SYSREG_END, 65300); 667 | 668 | impl SysReg { 669 | /// Get system register name 670 | /// 671 | /// # Examples 672 | /// ``` 673 | /// use bad64::SysReg; 674 | /// assert_eq!(SysReg::VBAR_EL3.name(), "vbar_el3"); 675 | /// ``` 676 | /// 677 | /// ``` 678 | /// use bad64::{decode, Operand, SysReg}; 679 | /// // msr vbar_el3, x0 680 | /// let decoded = decode(0xd51ec000, 0).unwrap(); 681 | /// 682 | /// let op = decoded.operands()[0]; 683 | /// 684 | /// assert_eq!(op, Operand::SysReg(SysReg::VBAR_EL3)); 685 | /// 686 | /// match op { 687 | /// Operand::SysReg(sr) => assert_eq!(sr.name(), "vbar_el3"), 688 | /// _ => assert!(false), 689 | /// }; 690 | /// ``` 691 | pub fn name(&self) -> &'static str { 692 | #[cfg(target_os = "windows")] 693 | { 694 | unsafe { 695 | CStr::from_ptr(bad64_sys::get_system_register_name(self.to_i32().unwrap()) as _) 696 | } 697 | .to_str() 698 | .unwrap() 699 | } 700 | #[cfg(not(target_os = "windows"))] 701 | { 702 | unsafe { 703 | CStr::from_ptr(bad64_sys::get_system_register_name(self.to_u32().unwrap()) as _) 704 | } 705 | .to_str() 706 | .unwrap() 707 | } 708 | } 709 | } 710 | 711 | impl fmt::Display for SysReg { 712 | fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { 713 | write!(f, "{}", self.name()) 714 | } 715 | } 716 | -------------------------------------------------------------------------------- /tests/dis.rs: -------------------------------------------------------------------------------- 1 | use bad64::*; 2 | 3 | #[test] 4 | fn decode_nop() { 5 | let ins = decode(0xd503201f, 0).unwrap(); 6 | 7 | assert_eq!(ins.op(), Op::NOP); 8 | assert_eq!(ins.op().mnem(), "nop"); 9 | assert_eq!(ins.operands().len(), 0); 10 | } 11 | 12 | #[test] 13 | fn decode_iter_nop() { 14 | let ins1 = decode(0xd503201f, 0).unwrap(); 15 | let mut ii = disasm(b"\x1f\x20\x03\xd5", 0); 16 | 17 | let ins2 = ii.next().unwrap().unwrap(); 18 | 19 | assert_eq!(0, ins2.address()); 20 | assert_eq!(ins1, ins2); 21 | 22 | assert_eq!(ii.next(), None); 23 | } 24 | 25 | #[test] 26 | fn decode_iter_err() { 27 | let mut ii = disasm(&[0x41_u8; 8], 0); 28 | 29 | assert_eq!(ii.next().unwrap(), Err(DecodeError::Unallocated(0))); 30 | assert_eq!(ii.next().unwrap(), Err(DecodeError::Unallocated(4))); 31 | assert_eq!(ii.next(), None); 32 | } 33 | 34 | #[test] 35 | fn decode_iter_short() { 36 | let mut ii = disasm(&[0x41_u8; 3], 0); 37 | 38 | assert_eq!(ii.next().unwrap(), Err(DecodeError::Short(0))); 39 | assert_eq!(ii.next(), None); 40 | } 41 | 42 | #[test] 43 | fn decode_add() { 44 | // add x0, x1, #0x41 45 | let ins = decode(0x91010420, 0).unwrap(); 46 | 47 | assert_eq!(ins.op(), Op::ADD); 48 | assert_eq!(ins.op().mnem(), "add"); 49 | assert_eq!(ins.operands().len(), 3); 50 | 51 | let o0 = ins.operands()[0]; 52 | let o1 = ins.operands()[1]; 53 | let o2 = ins.operands()[2]; 54 | assert_eq!(ins.operands().get(3), None); 55 | assert_eq!(ins.operands().get(5), None); 56 | 57 | assert_eq!( 58 | o0, 59 | Operand::Reg { 60 | reg: Reg::X0, 61 | arrspec: None, 62 | } 63 | ); 64 | assert_eq!( 65 | o1, 66 | Operand::Reg { 67 | reg: Reg::X1, 68 | arrspec: None, 69 | } 70 | ); 71 | assert_eq!( 72 | o2, 73 | Operand::Imm64 { 74 | imm: Imm::Unsigned(0x41), 75 | shift: None 76 | } 77 | ); 78 | } 79 | 80 | #[test] 81 | fn system_reg() { 82 | // msr vbar_el3, x0 83 | let ins = decode(0xd51ec000, 0).unwrap(); 84 | 85 | let o0 = ins.operands().get(0); 86 | assert_eq!(o0, Some(&Operand::SysReg(SysReg::VBAR_EL3))); 87 | } 88 | 89 | #[test] 90 | fn decode_failure() { 91 | assert_eq!(decode(0x41414141, 0), Err(DecodeError::Unallocated(0))); 92 | } 93 | -------------------------------------------------------------------------------- /tests/testcases.rs: -------------------------------------------------------------------------------- 1 | use std::fs; 2 | use std::num::ParseIntError; 3 | 4 | #[test] 5 | fn testcases() { 6 | fn fuzzy_eq(expected: &str, actual: &str) -> bool { 7 | fn fuzzy_token(a: &str, b: &str) -> bool { 8 | fn parse_num(n: &str) -> Result { 9 | let s = n 10 | .trim_start_matches("#") 11 | .trim_end_matches(",") 12 | .trim_end_matches(".0") 13 | .trim_end_matches("!") 14 | .trim_end_matches("]"); 15 | 16 | if s.starts_with("-") { 17 | return match s { 18 | _ if s.starts_with("-0x") => { 19 | Ok(-i64::from_str_radix(s.trim_start_matches("-0x"), 16)? as u64) 20 | } 21 | _ => Ok(i64::from_str_radix(s, 10)? as u64), 22 | }; 23 | } 24 | 25 | return match s { 26 | _ if s.starts_with("0x") => { 27 | Ok(u64::from_str_radix(s.trim_start_matches("0x"), 16)?) 28 | } 29 | _ => Ok(u64::from_str_radix(s, 10)?), 30 | }; 31 | } 32 | 33 | match (a, b) { 34 | ("cs", "hs") | ("hs", "cs") => true, 35 | ("lo", "cc") | ("cc", "lo") => true, 36 | _ if a.starts_with('#') || b.starts_with("#") => { 37 | match (parse_num(a), parse_num(b)) { 38 | (Ok(x), Ok(y)) => { 39 | println!("parsed {:#x} {:#x}", x, y); 40 | x == y || x & 0xffff_ffff == y & 0xffff_ffff || x & 0xff == y & 0xff 41 | } 42 | (Ok(_), Err(_)) => { 43 | println!("couldnt parse: {}", b); 44 | false 45 | } 46 | (Err(_), Ok(_)) => { 47 | println!("couldnt parse: {}", a); 48 | false 49 | } 50 | (Err(_), Err(_)) => { 51 | println!("couldnt parse: {} / {}", a, b); 52 | false 53 | } 54 | } 55 | } 56 | _ if a.to_lowercase() == b.to_lowercase() => true, 57 | _ => a == b, 58 | } 59 | } 60 | 61 | match actual { 62 | "axflag" if expected.starts_with("msr") => true, 63 | "xaflag" if expected.starts_with("msr") => true, 64 | "cfinv" if expected.starts_with("msr") => true, 65 | "dgh" if expected.starts_with("hint") => true, 66 | _ if actual.ends_with("sxtx]") && expected.ends_with("sxtx #0x0]") => true, 67 | _ if actual.ends_with("uxtw]") && expected.ends_with("uxtw #0x0]") => true, 68 | _ if actual.ends_with("sxtw]") && expected.ends_with("sxtw #0x0]") => true, 69 | _ if actual.starts_with("cmpp") && expected.starts_with("subps") => true, 70 | _ if actual.starts_with("mov") && expected.starts_with("dupm") => true, 71 | _ if actual.starts_with("msr pan") && expected.starts_with("msr s0_0") => true, 72 | _ if actual.starts_with("msr ssbs") && expected.starts_with("msr s0_3") => true, 73 | _ if actual.starts_with("sb") && expected.starts_with("msr s0_3") => true, 74 | _ if actual.starts_with("sdot") => true, 75 | _ if actual.starts_with("udot") => true, 76 | _ if actual == expected => true, 77 | _ if actual.to_lowercase() == expected.to_lowercase() => true, 78 | _ => expected 79 | .split(' ') 80 | .zip(actual.split(' ')) 81 | .all(|(a, b)| fuzzy_token(a, b)), 82 | } 83 | } 84 | 85 | let testcases = fs::read_to_string("tests/test_cases.txt").unwrap(); 86 | 87 | for (n, line) in testcases.lines().enumerate() { 88 | if line.starts_with("//") { 89 | println!("processing {}...", line); 90 | continue; 91 | } 92 | 93 | let chunks: Vec<&str> = line.trim_end().split_whitespace().collect(); 94 | 95 | let op = u32::from_str_radix(chunks[0], 16).unwrap(); 96 | let expected = chunks[1..].join(" "); 97 | 98 | let decoded = bad64::decode(op, 0x8000_0000_0000_0004).unwrap(); 99 | let actual = format!("{}", decoded); 100 | 101 | if !fuzzy_eq(&expected, &actual) { 102 | println!("opcode: {:x}", op); 103 | println!("expected: |{}|", expected); 104 | println!("actual: |{}|", actual); 105 | println!("debug: {:x?}", decoded); 106 | println!( 107 | "progress: {}/{}", 108 | n, 109 | testcases.lines().collect::>().len() 110 | ); 111 | assert!(false); 112 | } 113 | } 114 | } 115 | --------------------------------------------------------------------------------