├── u_top_z-top_z.v
├── top_zhiwen_yuyin.v
├── 百度LBS开放平台显示的HTML代码
├── 显示.png
└── html代码.txt
├── gps.v
├── chuli.v
├── smg2.v
├── top_gy_26.v
├── x7seg_msg.v
├── bps_set.v
├── bps_set_115200.v
├── bps_set_9600.v
├── bps_set_lora.v
├── bps_set_gy_26.v
├── bps_set_57600.v
├── zhiwen.v
├── top_lora_tx.v
├── top_zhiwen.v
├── Top_gy_25_tx.v
├── top_uart_rx.v
├── top_uart_rx_gy_26.v
├── top_hongwai.v
├── Top_uart_tx_zhiwen.v
├── top_gps.v
├── div_25HZ.v
├── uart_bps.v
├── uart_bps_1.v
├── uart_bps_9600.v
├── lora_rx.v
├── top_rx_surf.v
├── control.v
├── HC_SR04.v
├── hc_sr042.v
├── uart_tx_dzj.v
├── 盲人家中板子的FPGA代码
├── bps_set.v
├── bps_set_115200.v
├── Top_uart_tx.v
├── lora.v
├── Top_uart_tx_dzj_test.v
├── Top_uart_tx_test.v
├── fangdou.v
├── Top_uart_tx_dzj.v
├── lora_rx.v
├── uart_tx.v
├── lora_rx_chuli.v
├── uart_rx_dzj_lora.v
├── x7seg_msg.v
├── uart_rx.v
├── lora_rx_test.v
└── uart_tx_dzj.v
├── TOP_GY_25.v
├── select_addr.v
├── top_xinlv.v
├── uart_tx_lora.v
├── uart_tx.v
├── tb_top.v
├── tp_z.v
├── top_bizhng.v
├── top2.v
├── top_music.v
├── uart_sentdata_mess.v
├── uart_receive.v
├── uart_receive_1.v
├── uart_receive_9600.v
├── uart_receive_xinlv.v
├── uart_rx.v
├── uart_rx_dzj.v
├── time_.v
├── top_calling.v
├── judge_Red_Green.v
├── top.v
├── data_extract.v
├── top_duanxin.v
├── shumaguan.v
├── bcd2.v
├── bin_bcd.v
├── GY25_RX.v
├── VGA.v
├── zhuti.v
├── bizhang.v
├── xinlv_rx.v
├── top_surf_net.v
├── calling.v
├── hongwai_rx.v
├── gsm.v
├── VGA_square.v
├── gps_rx.v
├── Arudino代码
└── Tricycle_For_Arduino.ino
└── pick_up_rx.v
/u_top_z-top_z.v:
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1 | module u_top_z-top_z( );
2 |
3 |
4 |
5 | endmodule
6 |
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/top_zhiwen_yuyin.v:
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https://raw.githubusercontent.com/yuezhao1/ANLU_fpga/HEAD/top_zhiwen_yuyin.v
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/百度LBS开放平台显示的HTML代码/显示.png:
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https://raw.githubusercontent.com/yuezhao1/ANLU_fpga/HEAD/百度LBS开放平台显示的HTML代码/显示.png
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/gps.v:
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1 | module gps_yuyin(
2 | input key,
3 | input clk,
4 | input rst_n,
5 | output reg [17:0]shijian
6 | );
7 | always@(posedge clk or negedge rst_n)
8 | begin
9 | if(~rst_n)
10 | shijian<=1'b0;
11 | else if(key)
12 | shijian<=18'd102444;
13 | end
14 |
15 | endmodule
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/chuli.v:
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1 | module chuli(
2 | input clk,
3 | input rst_n,
4 | input [7:0]angle,
5 |
6 | output reg [1:0]led
7 | );
8 | always@(posedge clk or negedge rst_n)
9 | begin
10 | if(!rst_n)
11 | led<=2'b00;
12 | else if(angle>=6'd45) //大于45度盲人将要摔倒
13 | led<=2'b01;
14 | else led<=2'b10;
15 | end
16 |
17 |
18 | endmodule
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/smg2.v:
--------------------------------------------------------------------------------
1 | module smg2(input [9:0] x,
2 | input clk,
3 | input rst_n,
4 | //output reg [6:0] smg_duan,
5 | //output reg [3:0] smg_wei,
6 | //output reg dp,
7 | output reg led0,
8 | output [9:0]hz
9 | );
10 |
11 | assign hz = x[3:0]*1 + x[7:4]*10 + x[9:8]*100;
12 |
13 |
14 | always@(posedge clk or negedge rst_n)
15 | if(!rst_n)
16 | led0 <= 0;
17 | else if(hz <=40)
18 | led0 <= 1;
19 | else
20 | led0 <= 0;
21 |
22 |
23 | endmodule
24 |
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/top_gy_26.v:
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1 | module top_gy_26(
2 | input flag_gy26,
3 | input clk,
4 | input rst,
5 | input data_rx,
6 | output RX232,
7 | output [9:0]jiaodu
8 | );
9 | Top_uart_tx_gy_26 a (
10 | .flag_gy26(flag_gy26),
11 | .clk(clk),
12 | .rst(rst),
13 | .RX232(RX232),
14 | .over_all(over_all),
15 | .over_rx(over_rx)
16 | );
17 | top_uart_rx_gy_26 b (
18 | .clk(clk),
19 | .rst(rst),
20 | .data_rx(data_rx),
21 | .jiaodu(jiaodu)
22 | );
23 |
24 | endmodule
25 |
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/x7seg_msg.v:
--------------------------------------------------------------------------------
1 | module x7seg_msg(
2 | input [9:0] x,
3 | input clk,
4 | input rst_n,
5 | //output reg [6:0] smg_duan,
6 | //output reg [3:0] smg_wei,
7 | //output reg dp,
8 | output reg led1,
9 | output [9:0]hq
10 | );
11 |
12 |
13 | assign hq = x[3:0]*1 + x[7:4]*10 + x[9:8]*100;
14 |
15 |
16 | always@(posedge clk or negedge rst_n)
17 | if(rst_n==0)
18 | led1 <= 0;
19 | else if(hq <= 60)
20 | led1 <= 1;
21 | else
22 | led1 <= 0;
23 | endmodule
24 |
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/bps_set.v:
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1 | module bps_set(
2 | input clk,
3 | input rst_n,
4 | input bps_start,
5 | output bps_clk
6 | );
7 | reg[12:0]cnt_bps;
8 | parameter bps=13'd5208; //(50_000_000/9600)
9 | always@(posedge clk or negedge rst_n)
10 | begin
11 | if(!rst_n) cnt_bps<= 13'd0;
12 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
13 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
14 | else cnt_bps<= 1'b0;
15 | end
16 | assign bps_clk=(cnt_bps==13'd2604)?1'b1:1'b0;
17 | endmodule
18 |
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/bps_set_115200.v:
--------------------------------------------------------------------------------
1 | module bps_set_115200(
2 | input clk,
3 | input rst_n,
4 | input bps_start,
5 | output bps_clk
6 | );
7 | reg[12:0]cnt_bps;
8 | parameter bps=13'd434; //(50_000_000/115200)
9 | always@(posedge clk or negedge rst_n)
10 | begin
11 | if(!rst_n) cnt_bps<= 13'd0;
12 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
13 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
14 | else cnt_bps<= 1'b0;
15 | end
16 | assign bps_clk=(cnt_bps==13'd217)?1'b1:1'b0;
17 | endmodule
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/bps_set_9600.v:
--------------------------------------------------------------------------------
1 | module bps_set_9600(
2 | input clk,
3 | input rst_n,
4 | input bps_start,
5 | output bps_clk
6 | );
7 | reg[12:0]cnt_bps;
8 | parameter bps=13'd5208; //(50_000_000/9600)
9 | always@(posedge clk or negedge rst_n)
10 | begin
11 | if(!rst_n) cnt_bps<= 13'd0;
12 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
13 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
14 | else cnt_bps<= 1'b0;
15 | end
16 | assign bps_clk=(cnt_bps==13'd2604)?1'b1:1'b0;
17 | endmodule
18 |
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/bps_set_lora.v:
--------------------------------------------------------------------------------
1 | module bps_set_lora(
2 | input clk,
3 | input rst_n,
4 | input bps_start,
5 | output bps_clk
6 | );
7 | reg[12:0]cnt_bps;
8 | parameter bps=13'd434; //(50_000_000/9600)
9 | always@(posedge clk or negedge rst_n)
10 | begin
11 | if(!rst_n) cnt_bps<= 13'd0;
12 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
13 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
14 | else cnt_bps<= 1'b0;
15 | end
16 | assign bps_clk=(cnt_bps==13'd217)?1'b1:1'b0;
17 | endmodule
18 |
--------------------------------------------------------------------------------
/bps_set_gy_26.v:
--------------------------------------------------------------------------------
1 | module bps_set_gy_26(
2 | input clk,
3 | input rst,
4 | input bps_start,
5 | output bps_clk
6 | );
7 | reg[12:0]cnt_bps;
8 | parameter bps=13'd5208; //(50_000_000/9600)
9 | always@(posedge clk or negedge rst)
10 | begin
11 | if(!rst) cnt_bps<= 13'd0;
12 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
13 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
14 | else cnt_bps<= 1'b0;
15 | end
16 | assign bps_clk=(cnt_bps==13'd2604)?1'b1:1'b0;
17 |
18 |
19 | endmodule
20 |
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/bps_set_57600.v:
--------------------------------------------------------------------------------
1 | module bps_set_57600(
2 | input clk,
3 | input rst_n,
4 | input bps_start,
5 | output bps_clk
6 | );
7 | reg[12:0]cnt_bps;
8 | parameter bps=13'd868; //(50_000_000/57600)
9 | always@(posedge clk or negedge rst_n)
10 | begin
11 | if(!rst_n) cnt_bps<= 13'd0;
12 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
13 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
14 | else cnt_bps<= 1'b0;
15 | end
16 | assign bps_clk=(cnt_bps==13'd434)?1'b1:1'b0; //868/2=434
17 | endmodule
18 |
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/zhiwen.v:
--------------------------------------------------------------------------------
1 | module zhiwen(
2 | input chumo,
3 | input over_all,
4 | input zhongzhi,
5 | //input clk,
6 | //input rst_n,
7 |
8 | output reg tx_en
9 | );
10 | /*reg [25:0]cnt;
11 | always@(posedge clk or negedge rst_n) //这里需要有1s的延迟 再检测指纹
12 | begin
13 | if(!rst_n)
14 | cnt<=1'b0;
15 | else if(cnt==26'd49_999)
16 | cnt<=1'b0;
17 | else cnt<=cnt+1'b1;
18 | end*/
19 | always@(*)
20 | begin
21 | if(zhongzhi)
22 | tx_en=1'b1;
23 | else if(over_all)
24 | tx_en=1'b0;
25 | else if(chumo/*&cnt==26'd49_999*/)
26 | tx_en=1'b1;
27 | else tx_en=1'b0;
28 | end
29 | endmodule
30 |
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/top_lora_tx.v:
--------------------------------------------------------------------------------
1 | module top_lora_tx(
2 | input clk,
3 | input rst_n,
4 | input send_en,
5 | input [7:0] data_rx,
6 |
7 | output RX232,
8 | output over_rx
9 | );
10 |
11 | wire bps_start_1;
12 |
13 | bps_set_lora u_bps_set_lora(
14 | .clk(clk),
15 | .rst_n(rst_n),
16 | .bps_start(bps_start_1),
17 | .bps_clk(bps_clk)
18 | );
19 |
20 | uart_tx_lora u_uart_tx_lora(
21 | .clk(clk),
22 | .bps_clk(bps_clk),
23 | .send_en(send_en),
24 | .rst_n(rst_n),
25 | .data_rx(data_rx),
26 | .RX232(RX232),
27 | .over_rx(over_rx),
28 | .bps_start(bps_start_1)
29 | );
30 |
31 |
32 | endmodule
33 |
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/top_zhiwen.v:
--------------------------------------------------------------------------------
1 | module top_zhiwen(
2 | input clk,
3 | input rst_n,
4 | input chumo,
5 | input data_rx,
6 |
7 | output RX232,
8 | output [1:0]flag
9 |
10 | );
11 | Top_uart_tx_zhiwen a (
12 | .flag(tx_en),
13 | .clk(clk),
14 | .rst_n(rst_n),
15 | .RX232(RX232),
16 | .over_rx(over_rx),
17 | .over_all(over_all)
18 | );
19 | zhiwen ab (
20 | .zhongzhi(zhongzhi),
21 | .chumo(chumo),
22 | .over_all(over_all),
23 | .tx_en(tx_en)
24 | );
25 | top_uart_rx abc (
26 | .clk(clk),
27 | .rst_n(rst_n),
28 | .data_rx(data_rx),
29 | .flag(flag)
30 | );
31 | assign zhongzhi = flag[0];
32 |
33 |
34 |
35 | endmodule
36 |
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/Top_gy_25_tx.v:
--------------------------------------------------------------------------------
1 | module Top_gy_25_tx(
2 | input clk,
3 | input rst_n,
4 |
5 | output RX232,
6 | output over_rx,
7 | output over_all
8 | );
9 | wire [7:0]data_rx;
10 | uart_tx_dzj a (
11 | .clk(clk),
12 | .rst_n(rst_n),
13 | .over_tx(over_rx),
14 | .data_rx(data_rx),
15 | .send_en(send_en),
16 | .over_all(over_all)
17 | );
18 | uart_tx_GY25 abc (
19 | .clk(clk),
20 | .bps_clk(bps_clk),
21 | .send_en(send_en),
22 | .rst_n(rst_n),
23 | .data_rx(data_rx),
24 | .RX232(RX232),
25 | .over_rx(over_rx),
26 | .bps_start(bps_start)
27 | );
28 | bps_set_115200 abcd (
29 | .clk(clk),
30 | .rst_n(rst_n),
31 | .bps_start(bps_start),
32 | .bps_clk(bps_clk)
33 | );
34 |
35 |
36 | endmodule
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/top_uart_rx.v:
--------------------------------------------------------------------------------
1 | module top_uart_rx(
2 | input clk,
3 | input rst_n,
4 | input data_rx,
5 | //input over_all,
6 | output [1:0]flag,
7 | output over_rx
8 | );
9 | wire [7:0]data_tx;
10 | bps_set_57600 a (
11 | .clk(clk),
12 | .rst_n(rst_n),
13 | .bps_start(bps_start),
14 | .bps_clk(bps_clk)
15 | );
16 | uart_rx ab (
17 | .nedge(nedge),
18 | .clk(clk),
19 | .rst_n(rst_n),
20 | .bps_clk(bps_clk),
21 | .data_rx(data_rx),
22 | .data_tx(data_tx),
23 | .over_rx(over_rx),
24 | .bps_start(bps_start)
25 | );
26 | uart_rx_dzj_zhiwen abc (
27 | .clk(clk),
28 | //.over_all(over_all),
29 | .rst_n(rst_n),
30 | .data_tx(data_tx),
31 | .nedge(nedge),
32 | .over_rx(over_rx),
33 | .flag(flag)
34 | );
35 | endmodule
36 |
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/top_uart_rx_gy_26.v:
--------------------------------------------------------------------------------
1 | module top_uart_rx_gy_26(
2 | input clk,
3 | input rst,
4 | input data_rx,
5 |
6 | output [9:0] jiaodu,
7 | output over_rx
8 | );
9 |
10 | wire [7:0]data_tx;
11 |
12 | bps_set_gy_26 a (
13 | .clk(clk),
14 | .rst(rst),
15 | .bps_start(bps_start),
16 | .bps_clk(bps_clk)
17 | );
18 | uart_rx_gy_26 ab (
19 | .nedge(nedge),
20 | .clk(clk),
21 | .rst(rst),
22 | .bps_clk(bps_clk),
23 | .data_rx(data_rx),
24 | .data_tx(data_tx),
25 | .over_rx(over_rx),
26 | .bps_start(bps_start)
27 | );
28 | uart_rx_dzj_gy_26 abc (
29 | .clk(clk),
30 | .rst(rst),
31 | .data_tx(data_tx),
32 | .over_rx(over_rx),
33 | .nedge(nedge),
34 | .jiaodu(jiaodu)
35 | );
36 |
37 |
38 | endmodule
39 |
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/top_hongwai.v:
--------------------------------------------------------------------------------
1 | module top_hongwai(
2 | input clk,
3 | input rst_n,
4 | input data_rx,
5 |
6 | output [1:0] flag_tu_ao
7 | );
8 |
9 | wire [7:0] data_tx;
10 | wire rx_int;
11 |
12 | hongwai_rx u_hongwai_rx (
13 | .clk(clk),
14 | .rst_n(rst_n),
15 | .data_rx(data_tx),
16 | .rx_int(rx_int),
17 | .flag_tu_ao(flag_tu_ao)
18 | );
19 |
20 | uart_bps_9600 u_uart_bps_9600 (
21 | .clk(clk),
22 | .rst_n(rst_n),
23 | .cnt_start(bps_start),
24 | .bps_sig(clk_bps)
25 | );
26 |
27 | uart_receive u_uart_receive (
28 | .clk(clk),
29 | .rst_n(rst_n),
30 | .clk_bps(clk_bps),
31 | .data_rx(data_rx),
32 |
33 | .rx_int(rx_int),
34 | .data_tx(data_tx),
35 | .bps_start(bps_start)
36 | );
37 |
38 |
39 | endmodule
40 |
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/Top_uart_tx_zhiwen.v:
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1 | module Top_uart_tx_zhiwen(
2 | input flag,
3 | input clk,
4 | input rst_n,
5 |
6 | output RX232,
7 | output over_rx,
8 | output over_all
9 | );
10 | wire [7:0]data_rx;
11 | uart_tx_dzj_zhiwen a (
12 | .flag(flag),
13 | .clk(clk),
14 | .rst_n(rst_n),
15 | .over_tx(over_rx),
16 | .data_rx(data_rx),
17 | .send_en(send_en),
18 | .over_all(over_all)
19 | );
20 | uart_tx abc (
21 | .clk(clk),
22 | .bps_clk(bps_clk),
23 | .send_en(send_en),
24 | .rst_n(rst_n),
25 | .data_rx(data_rx),
26 | .RX232(RX232),
27 | .over_rx(over_rx),
28 | .bps_start(bps_start)
29 | );
30 | bps_set_57600 abcd (
31 | .clk(clk),
32 | .rst_n(rst_n),
33 | .bps_start(bps_start),
34 | .bps_clk(bps_clk)
35 | );
36 |
37 |
38 | endmodule
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/top_gps.v:
--------------------------------------------------------------------------------
1 | module top_gps(
2 | input clk,
3 | input rst_n,
4 | input data_rx,
5 |
6 | output [383:0] data_rx_end
7 | );
8 | wire [7:0]data_tx;
9 | gps_rx a (
10 | .clk(clk),
11 | .rst_n(rst_n),
12 | .data_rx(data_tx),
13 | .rx_int(rx_int),
14 |
15 | .data_rx_end(data_rx_end),
16 | .ymr_out(ymr_out),
17 | .time_out(time_out)
18 | );
19 |
20 | uart_bps_9600 u_uart_bps_9600 (
21 | .clk(clk),
22 | .rst_n(rst_n),
23 | .cnt_start(bps_start),
24 |
25 | .bps_sig(clk_bps)
26 | );
27 |
28 | uart_receive_9600 u_uart_receive_9600 (
29 | .clk(clk),
30 | .rst_n(rst_n),
31 | .clk_bps(clk_bps),
32 | .data_rx(data_rx),
33 |
34 | .rx_int(rx_int),
35 | .data_tx(data_tx),
36 | .bps_start(bps_start)
37 | );
38 |
39 | endmodule
40 |
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/div_25HZ.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:34:21 11/02/2019
7 | // Design Name:
8 | // Module Name: div_25HZ
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module div_25HZ(
22 | input clk,
23 | input rst_n,
24 |
25 | output reg VGA_clk
26 | );
27 |
28 | //2分频
29 | always @(posedge clk or negedge rst_n)begin
30 | if(!rst_n)
31 | VGA_clk <= 1'b0;
32 | else
33 | VGA_clk <= ~VGA_clk;
34 | end
35 | endmodule
36 |
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/uart_bps.v:
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1 | module uart_bps(clk,rst_n,cnt_start,bps_sig
2 | );
3 | input clk;
4 | input rst_n;
5 | input cnt_start;
6 | output bps_sig;
7 |
8 | reg [12:0]cnt_bps;
9 | wire bps_sig;
10 |
11 | parameter bps_t = 13'd433;//5207
12 |
13 | always@(posedge clk or negedge rst_n)
14 | begin
15 | if(!rst_n)
16 | begin
17 | cnt_bps <= 13'd0;
18 | end
19 | else if(cnt_bps == bps_t)
20 | begin
21 | cnt_bps <= 13'd0;
22 | end
23 | else if(cnt_start)
24 | begin
25 | cnt_bps <= cnt_bps + 1'b1;
26 | end
27 | else
28 | begin
29 | cnt_bps <= 1'b0;
30 | end
31 | end
32 |
33 | assign bps_sig = (cnt_bps == 13'd217) ? 1'b1 : 1'b0; //将采集数据的时刻放在波特率计数器每次循环计数的中间位置
34 |
35 | endmodule
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/uart_bps_1.v:
--------------------------------------------------------------------------------
1 | module uart_bps_1(clk,rst_n,cnt_start,bps_sig
2 | );
3 | input clk;
4 | input rst_n;
5 | input cnt_start;
6 | output bps_sig;
7 |
8 | reg [12:0]cnt_bps;
9 | wire bps_sig;
10 |
11 | parameter bps_t = 13'd5207;
12 |
13 | always@(posedge clk or negedge rst_n)
14 | begin
15 | if(!rst_n)
16 | begin
17 | cnt_bps <= 13'd0;
18 | end
19 | else if(cnt_bps == bps_t)
20 | begin
21 | cnt_bps <= 13'd0;
22 | end
23 | else if(cnt_start)
24 | begin
25 | cnt_bps <= cnt_bps + 1'b1;
26 | end
27 | else
28 | begin
29 | cnt_bps <= 1'b0;
30 | end
31 | end
32 |
33 | assign bps_sig = (cnt_bps == 13'd2604) ? 1'b1 : 1'b0; //将采集数据的时刻放在波特率计数器每次循环计数的中间位置
34 |
35 | endmodule
--------------------------------------------------------------------------------
/uart_bps_9600.v:
--------------------------------------------------------------------------------
1 | module uart_bps_9600(clk,rst_n,cnt_start,bps_sig
2 | );
3 | input clk;
4 | input rst_n;
5 | input cnt_start;
6 | output bps_sig;
7 |
8 | reg [12:0]cnt_bps;
9 | wire bps_sig;
10 |
11 | parameter bps_t = 13'd5207;
12 |
13 | always@(posedge clk or negedge rst_n)
14 | begin
15 | if(!rst_n)
16 | begin
17 | cnt_bps <= 13'd0;
18 | end
19 | else if(cnt_bps == bps_t)
20 | begin
21 | cnt_bps <= 13'd0;
22 | end
23 | else if(cnt_start)
24 | begin
25 | cnt_bps <= cnt_bps + 1'b1;
26 | end
27 | else
28 | begin
29 | cnt_bps <= 1'b0;
30 | end
31 | end
32 |
33 | assign bps_sig = (cnt_bps == 13'd2604) ? 1'b1 : 1'b0; //将采集数据的时刻放在波特率计数器每次循环计数的中间位置
34 |
35 | endmodule
--------------------------------------------------------------------------------
/lora_rx.v:
--------------------------------------------------------------------------------
1 | module lora_rx(
2 | input clk,
3 | input rst_n,
4 | input data_rx,
5 | input over_all,
6 |
7 | output [1:0] flag_lora,
8 | output over_rx
9 |
10 | );
11 | wire [7:0]data_tx;
12 |
13 | bps_set_115200 a (
14 | .clk(clk),
15 | .rst_n(rst_n),
16 | .bps_start(bps_start),
17 | .bps_clk(bps_clk)
18 | );
19 | uart_rx ab (
20 | .nedge(nedge),
21 | .clk(clk),
22 | .rst_n(rst_n),
23 | .bps_clk(bps_clk),
24 | .data_rx(data_rx),
25 | .data_tx(data_tx),
26 | .over_rx(over_rx),
27 | .bps_start(bps_start)
28 | );
29 | uart_rx_dzj_lora abc (
30 | .clk(clk),
31 | .over_all(over_all),
32 | .rst_n(rst_n),
33 | .data_tx(data_tx),
34 | .nedge(nedge),
35 | .over_rx(over_rx),
36 | .flag_lora(flag_lora)
37 | );
38 |
39 |
40 | endmodule
41 |
--------------------------------------------------------------------------------
/top_rx_surf.v:
--------------------------------------------------------------------------------
1 | module top_rx_surf(
2 | input clk,
3 | input rst_n,
4 | input data_rx,
5 |
6 | output flag_en_1,//存使能
7 | output [7:0] addr_daohang_data,
8 | output [92:0] data_rx_end_internet
9 | );
10 |
11 |
12 | wire [7:0] data_tx;
13 |
14 |
15 | surf_internet_rx u_surf_internet_rx (
16 | .clk(clk),
17 | .rst_n(rst_n),
18 | .data_rx(data_tx),
19 | .rx_int(rx_int),
20 | .flag_en_1(flag_en_1),
21 | .addr_daohang_data(addr_daohang_data),
22 | .data_rx_end_internet(data_rx_end_internet)
23 | );
24 |
25 | uart_bps_1 u_uart_bps_1 (
26 | .clk(clk),
27 | .rst_n(rst_n),
28 | .cnt_start(bps_start),
29 | .bps_sig(clk_bps)
30 | );
31 |
32 | uart_receive_1 u_uart_receive_1 (
33 | .clk(clk),
34 | .rst_n(rst_n),
35 | .clk_bps(clk_bps),
36 | .data_rx(data_rx),
37 |
38 | .rx_int(rx_int),
39 | .data_tx(data_tx),
40 | .bps_start(bps_start)
41 | );
42 |
43 | endmodule
44 |
--------------------------------------------------------------------------------
/control.v:
--------------------------------------------------------------------------------
1 | module control(clk,rst,led0,led1,dianji0,dianji2,dianji,led2,led3,flag1
2 | );
3 | input clk;
4 | input rst;
5 | input led0;//z
6 | input led1;//q
7 | input flag1;
8 | input [1:0]dianji0;
9 | input [1:0]dianji2;
10 | output reg[1:0]dianji;
11 | output reg led2;
12 | output reg led3;
13 | always@(posedge clk or negedge rst)
14 | if(!rst)
15 | dianji <= 2'd0;
16 | else if(led0==0&&led1==0 && flag1 == 0)
17 | begin
18 | dianji <= dianji0;
19 | led2 <= 1;
20 | led3 <= 0;
21 | end
22 | else if((led1==1||led0 == 1)&& flag1 ==1 )
23 | begin
24 | dianji <= dianji2;
25 | led3 <= 1;
26 | led2 <= 0;
27 | end
28 | else
29 | begin
30 | dianji <= dianji;
31 | led2 <= 0;
32 | led3 <= 0;
33 | end
34 |
35 | /*always@(posedge clk or negedge rst)
36 | if(!rst)
37 | begin
38 | led2 <= 0;
39 | led3 <= 0;
40 | end
41 | else if(dianji == dianji0)
42 | led2 <= 1;
43 | else if(dianji == dianji2)
44 | led3 <= 1;
45 | else
46 | begin
47 | led2 <= 0;
48 | led3 <= 0;
49 | end*/
50 | endmodule
51 |
--------------------------------------------------------------------------------
/HC_SR04.v:
--------------------------------------------------------------------------------
1 | module HC_SR04(
2 | input clk,
3 | input rst_n,
4 | input en,
5 | input echo ,
6 | output reg trig,
7 | output [8:0] dis
8 | );
9 | reg [23:0]cnt;
10 | reg [31:0] cnt_t;
11 | parameter T=24'd15000000;//300ms
12 | parameter C=10'd600;
13 | always@(posedge clk or negedge rst_n)
14 | begin
15 | if(!rst_n)
16 | cnt<=0;
17 | else if(cnt==T-1)
18 | cnt<=0;
19 | else
20 | cnt<=cnt+1;
21 |
22 | end
23 |
24 | always@(posedge clk or negedge rst_n)
25 | begin
26 | if(!rst_n)
27 | trig<=0;
28 | else if(cnt>=1&&cnt<=C)
29 | trig<=1;
30 | else
31 | trig<=0;
32 | end
33 |
34 | always@(posedge clk or negedge rst_n)
35 | begin
36 | if(!rst_n)
37 | cnt_t<=0;
38 | else if(echo==1)
39 | cnt_t<=cnt_t+1;
40 | else if(cnt==T-1)
41 | cnt_t<=0;
42 | else
43 | cnt_t<=cnt_t;
44 | end
45 | reg [31:0]distance ;
46 | always@(posedge clk or negedge rst_n)
47 | begin
48 | if(!rst_n)
49 | distance<=0;
50 | else if(cnt==T-2'd2)
51 | distance<=(cnt_t*11)>>15;
52 | end
53 |
54 | assign dis=distance;
55 |
56 | endmodule
57 |
--------------------------------------------------------------------------------
/hc_sr042.v:
--------------------------------------------------------------------------------
1 | module hc_sr042(input clk,
2 | input rst_n,
3 | input en,
4 | input echo2 ,
5 | output reg trig2,
6 | output [8:0] dis
7 | );
8 | reg [23:0]cnt;
9 | reg [31:0] cnt_t;
10 | parameter T=24'd15000000;//300ms
11 | parameter C=10'd600;
12 | always@(posedge clk or negedge rst_n)
13 | begin
14 | if(!rst_n)
15 | cnt<=0;
16 | else if(cnt==T-1)
17 | cnt<=0;
18 | else
19 | cnt<=cnt+1;
20 |
21 | end
22 |
23 | always@(posedge clk or negedge rst_n)
24 | begin
25 | if(!rst_n)
26 | trig2<=0;
27 | else if(cnt>=1&&cnt<=C)
28 | trig2<=1;
29 | else
30 | trig2<=0;
31 | end
32 |
33 | always@(posedge clk or negedge rst_n)
34 | begin
35 | if(!rst_n)
36 | cnt_t<=0;
37 | else if(echo2==1)
38 | cnt_t<=cnt_t+1;
39 | else if(cnt==T-1)
40 | cnt_t<=0;
41 | else
42 | cnt_t<=cnt_t;
43 | end
44 | reg [31:0]distance ;
45 | always@(posedge clk or negedge rst_n)
46 | begin
47 | if(!rst_n)
48 | distance<=0;
49 | else if(cnt==T-2'd2)
50 | distance<=(cnt_t*11)>>15;
51 | end
52 |
53 | assign dis=distance;
54 |
55 |
56 | endmodule
57 |
--------------------------------------------------------------------------------
/uart_tx_dzj.v:
--------------------------------------------------------------------------------
1 | module uart_tx_dzj(
2 | input clk,
3 | input rst_n,
4 | input over_tx,
5 |
6 | output reg [7:0]data_rx,
7 | output reg send_en,
8 | output reg over_all
9 | );
10 | reg[3:0] cnt; //最大要记到14 I like FPGA,too 一共14个字符
11 | always@(posedge clk or negedge rst_n) //数每个字符结束 递 下一个字符的计数器
12 | begin
13 | if(!rst_n)begin
14 | cnt<=1'b0;over_all<=1'b0;end
15 | else if(cnt==4'd5)
16 | cnt<=1'b0;
17 | else if(cnt==4'd4)
18 | over_all<=1'b1;
19 | else if(over_tx)
20 | cnt<=cnt+1'b1;
21 | else begin cnt<=cnt; over_all<=over_all; end
22 | end
23 |
24 | always@(posedge clk or negedge rst_n)
25 | begin
26 | if(!rst_n)
27 | send_en<=1'b1;
28 | else if(cnt==4'b0011&over_tx)
29 | send_en<=1'b0;
30 | else send_en<=send_en;
31 | end
32 |
33 | always@(*)
34 | begin
35 | case(cnt)
36 | 4'd1 : data_rx <= 8'hA5; //0xA5+0x51:查询模式，直接返回角度值，需每次读取都发送
37 | 4'd2 : data_rx <= 8'h54; //矫正俯仰角0度
38 | 4'd3 : data_rx <= 8'hA5; //0xA5+0x52:自动模式，直接返回角度值，只需要初始化时发一次
39 | 4'd4 : data_rx <= 8'h52;
40 | endcase
41 | end
42 | endmodule
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/bps_set.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 17:08:22 11/20/2018
7 | // Design Name:
8 | // Module Name: bps_set
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module bps_set(
22 | input clk,
23 | input rst_n,
24 | input bps_start,
25 | output bps_clk
26 | );
27 | reg[12:0]cnt_bps;
28 | parameter bps=13'd434; //(50_000_000/9600)
29 | always@(posedge clk or negedge rst_n)
30 | begin
31 | if(!rst_n) cnt_bps<= 13'd0;
32 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
33 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
34 | else cnt_bps<= 1'b0;
35 | end
36 | assign bps_clk=(cnt_bps==13'd217)?1'b1:1'b0;
37 | endmodule
38 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/bps_set_115200.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 17:08:22 11/20/2018
7 | // Design Name:
8 | // Module Name: bps_set_9600
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module bps_set_115200(
22 | input clk,
23 | input rst_n,
24 | input bps_start,
25 | output bps_clk
26 | );
27 | reg[12:0]cnt_bps;
28 | parameter bps=13'd434; //(50_000_000/115200)
29 | always@(posedge clk or negedge rst_n)
30 | begin
31 | if(!rst_n) cnt_bps<= 13'd0;
32 | else if(cnt_bps==bps-1'b1) cnt_bps<= 13'd0;
33 | else if(bps_start) cnt_bps<= cnt_bps+1'b1;
34 | else cnt_bps<= 1'b0;
35 | end
36 | assign bps_clk=(cnt_bps==13'd217)?1'b1:1'b0;
37 | endmodule
38 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/Top_uart_tx.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 19:40:43 11/24/2018
7 | // Design Name:
8 | // Module Name: Top_uart_tx
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module Top_uart_tx(
22 | input clk,
23 | input send_en,
24 | input rst_n,
25 | input[7:0]data_rx,
26 |
27 | output RX232,
28 | output over_rx //结束后会有一个高电平
29 | );
30 | bps_set a (
31 | .clk(clk),
32 | .rst_n(rst_n),
33 | .bps_start(bps_start),
34 | .bps_clk(bps_clk)
35 | );
36 | uart_tx ab (
37 | .clk(clk),
38 | .bps_clk(bps_clk),
39 | .send_en(send_en),
40 | .rst_n(rst_n),
41 | .data_rx(data_rx),
42 | .RX232(RX232),
43 | .over_rx(over_rx),
44 | .bps_start(bps_start)
45 | );
46 |
47 |
48 |
49 |
50 | endmodule
51 |
--------------------------------------------------------------------------------
/TOP_GY_25.v:
--------------------------------------------------------------------------------
1 | module TOP_GY_25(
2 | input clk_24m,
3 | input rst_n,
4 | input rs232_rx,
5 |
6 | output RX232,
7 | output [1:0]led
8 | );
9 | wire [7:0]bps_cnt;
10 | wire [7:0]data_byte;
11 | wire [7:0]angle;
12 |
13 | wire clk_72m;
14 | wire clk_50m;
15 |
16 |
17 | PLL_50M_GY_25 u_PLL_50M_GY_25(
18 | .refclk(clk_24m),
19 | .clk0_out(clk_72m),
20 | .clk1_out(clk_50m)
21 | );
22 |
23 |
24 |
25 | GY25_RX a (
26 | .clk(clk_50m),
27 | .rst_n(rst_n),
28 | .rs232_rx(rs232_rx),
29 | .data_byte(data_byte),
30 | .rx_done(rx_done),
31 | .bps_cnt(bps_cnt)
32 | );
33 |
34 | data_extract ab (
35 | .clk(clk_50m),
36 | .rst_n(rst_n),
37 | .date_byte(data_byte),
38 | .angle(angle),
39 | .rx_done(rx_done),
40 | .bps_cnt(bps_cnt),
41 | .byte1(byte1)
42 | );
43 |
44 |
45 |
46 | Top_gy_25_tx abc (
47 | .clk(clk_50m),
48 | .rst_n(rst_n),
49 | .RX232(RX232),
50 | .over_rx(over_rx),
51 | .over_all(over_all)
52 | );
53 |
54 | chuli abcd (
55 | .clk(clk_50m),
56 | .rst_n(rst_n),
57 | .angle(angle),
58 | .led(led)
59 | );
60 |
61 |
62 |
63 | endmodule
64 |
--------------------------------------------------------------------------------
/select_addr.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:35:57 11/02/2019
7 | // Design Name:
8 | // Module Name: select_addr
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module select_addr(
22 | input clk,
23 | input rst_n,
24 | input [15:0] flag_square_begin,
25 | input [15:0] rom_addr13,//VGA_square
26 | input [15:0] rom_addr16,//VGA_bsprite
27 |
28 | output [15:0] rom_addr //选择后的地址
29 |
30 | );
31 |
32 |
33 | assign rom_addr = (flag_square_begin > 3*200)? rom_addr16 : rom_addr13;
34 |
35 |
36 |
37 | //3行像素数量
38 | //always @ (posedge clk or negedge rst_n)begin
39 | // if(!rst_n)
40 | // rom_addr <= 13'd0;
41 | // else if(flag_square_begin > 3*200)
42 | // rom_addr <= rom_addr16;
43 | // else
44 | // rom_addr <= rom_addr13;
45 | // end
46 |
47 |
48 |
49 | endmodule
50 |
51 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/lora.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:18:20 11/21/2019
7 | // Design Name:
8 | // Module Name: lora
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module lora(
22 | input [3:0]in_key_en,
23 | input clk,
24 | input rst_n,
25 | input co,
26 | input zhendong,
27 | input data_rx,
28 |
29 | output [6:0] smg_duan,
30 | output [3:0] smg_wei,
31 | output dp,
32 | output RX232,
33 | output fengshan
34 | );
35 | Top_uart_tx_dzj tx (
36 | .in_key_en(in_key_en),
37 | .clk(clk),
38 | .rst_n(rst_n),
39 | .co(co),
40 | .zhendong(zhendong),
41 | .RX232(RX232),
42 | .over_rx(),
43 | .fengshan(fengshan)
44 | );
45 | lora_rx rx (
46 | .clk(clk),
47 | .rst_n(rst_n),
48 | .data_rx(data_rx),
49 | .smg_duan(smg_duan),
50 | .smg_wei(smg_wei),
51 | .dp(dp)
52 | );
53 | endmodule
54 |
--------------------------------------------------------------------------------
/top_xinlv.v:
--------------------------------------------------------------------------------
1 | module top_xinlv(
2 | input clk,
3 | input rst_n,
4 | input data_rx,
5 |
6 | output reg [7:0] xinlv
7 | );
8 |
9 | wire [7:0] data_tx;
10 | wire rx_int;
11 | wire [7:0] xinlv_1;
12 |
13 | reg [25:0] cnt;
14 |
15 | always @(posedge clk or negedge rst_n)begin
16 | if(!rst_n)
17 | cnt <= 26'd0;
18 | else if(cnt == 26'd5000_0000 - 1)
19 | cnt <= 26'd0;
20 | else
21 | cnt <= cnt + 1;
22 | end
23 |
24 |
25 | always @(posedge clk or negedge rst_n)begin
26 | if(!rst_n)
27 | xinlv <= 8'b0;
28 | else if(cnt == 26'd5000_0000 - 1)
29 | xinlv <= xinlv_1;
30 | else
31 | xinlv <= xinlv;
32 | end
33 |
34 |
35 | xinlv_rx xinlv_rx (
36 | .clk(clk),
37 | .rst_n(rst_n),
38 | .data_rx(data_tx),
39 | .rx_int(rx_int),
40 | .xinlv(xinlv_1)
41 | );
42 |
43 | uart_bps_xinlv u_uart_bps_xinlv (
44 | .clk(clk),
45 | .rst_n(rst_n),
46 | .cnt_start(bps_start),
47 | .bps_sig(clk_bps)
48 | );
49 |
50 | uart_receive_xinlv u_uart_receive_xinlv (
51 | .clk(clk),
52 | .rst_n(rst_n),
53 | .clk_bps(clk_bps),
54 | .data_rx(data_rx),
55 | .rx_int(rx_int),
56 | .data_tx(data_tx),
57 | .bps_start(bps_start)
58 | );
59 |
60 |
61 | endmodule
62 |
--------------------------------------------------------------------------------
/uart_tx_lora.v:
--------------------------------------------------------------------------------
1 | module uart_tx_lora(
2 | input clk,
3 | input bps_clk,
4 | input send_en,
5 | input rst_n,
6 | input[7:0]data_rx,
7 |
8 | output reg RX232,
9 | output reg over_rx, //结束后会有一个高电平
10 | output reg bps_start
11 | );
12 | reg [3:0]cnt; //数高电平用的计数器
13 | always@(posedge clk or negedge rst_n) //计数器
14 | begin
15 | if(!rst_n)
16 | cnt<=1'b0;
17 | else if(cnt==4'd11)
18 | cnt<=4'd0;
19 | else if(bps_clk)
20 | cnt<=cnt+1'b1;
21 | else cnt<=cnt;
22 | end
23 |
24 | always@(posedge clk or negedge rst_n)
25 | begin
26 | if(!rst_n)
27 | over_rx<=1'b0;
28 | else if(cnt==4'd11)
29 | over_rx<=1'b1;
30 | else over_rx<=1'b0;
31 | end
32 |
33 | always@(posedge clk or negedge rst_n)
34 | begin
35 | if(!rst_n)
36 | bps_start<=1'b0;
37 | else if(send_en)
38 | bps_start<=1'b1;
39 | else if(over_rx)
40 | bps_start<=1'b0;
41 | else bps_start<=bps_start;
42 | end
43 |
44 | always@(posedge clk or negedge rst_n)
45 | begin
46 | if(!rst_n)
47 | RX232<=1'b1;
48 | else
49 | begin
50 | case(cnt)
51 | 0: RX232<=1'b1;
52 | 1: RX232<=1'b0;
53 | 2: RX232<=data_rx[0];
54 | 3: RX232<=data_rx[1];
55 | 4: RX232<=data_rx[2];
56 | 5: RX232<=data_rx[3];
57 | 6: RX232<=data_rx[4];
58 | 7: RX232<=data_rx[5];
59 | 8: RX232<=data_rx[6];
60 | 9: RX232<=data_rx[7];
61 | 10:RX232<=1'b1;
62 | endcase
63 | end
64 | end
65 | endmodule
66 |
--------------------------------------------------------------------------------
/uart_tx.v:
--------------------------------------------------------------------------------
1 | module uart_tx(
2 | input clk,
3 | input bps_clk,
4 | input send_en,
5 | input rst_n,
6 | input[7:0]data_rx,
7 |
8 | output reg RX232,
9 | output reg over_rx, //结束后会有一个高电平
10 | output reg bps_start
11 | );
12 | reg [3:0]cnt; //数高电平用的计数器
13 | always@(posedge clk or negedge rst_n) //计数器
14 | begin
15 | if(!rst_n)
16 | cnt<=1'b0;
17 | else if(cnt==4'd11)
18 | cnt<=4'd0;
19 | else if(bps_clk)
20 | cnt<=cnt+1'b1;
21 | else cnt<=cnt;
22 | end
23 |
24 | always@(posedge clk or negedge rst_n)
25 | begin
26 | if(!rst_n)
27 | over_rx<=1'b0;
28 | else if(cnt==4'd11)
29 | over_rx<=1'b1;
30 | else over_rx<=1'b0;
31 | end
32 |
33 | always@(posedge clk or negedge rst_n)
34 | begin
35 | if(!rst_n)
36 | bps_start<=1'b0;
37 | else if(send_en)
38 | bps_start<=1'b1;
39 | else if(over_rx)
40 | bps_start<=1'b0;
41 | else bps_start<=bps_start;
42 | end
43 |
44 | always@(posedge clk or negedge rst_n)
45 | begin
46 | if(!rst_n)
47 | RX232<=1'b1;
48 | else
49 | begin
50 | case(cnt)
51 | 0: RX232<=1'b1;
52 | 1: RX232<=1'b0;
53 | 2: RX232<=data_rx[0];
54 | 3: RX232<=data_rx[1];
55 | 4: RX232<=data_rx[2];
56 | 5: RX232<=data_rx[3];
57 | 6: RX232<=data_rx[4];
58 | 7: RX232<=data_rx[5];
59 | 8: RX232<=data_rx[6];
60 | 9: RX232<=data_rx[7];
61 | 10:RX232<=1'b1;
62 | endcase
63 | end
64 | end
65 | endmodule
66 |
67 |
68 |
--------------------------------------------------------------------------------
/tb_top.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 22:45:40 11/02/2019
8 | // Design Name: top
9 | // Module Name: C:/Users/13743/Desktop/DongNan/VGA_200_164/tb_top.v
10 | // Project Name: VGA_200_164
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: top
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module tb_top;
26 |
27 | // Inputs
28 | reg clk;
29 | reg rst_n;
30 | reg pic_en;
31 |
32 | // Outputs
33 | wire VGA_HS;
34 | wire VGA_VS;
35 | wire [1:0] Red_Green;
36 | wire [7:0] RGB;
37 |
38 | // Instantiate the Unit Under Test (UUT)
39 | top uut (
40 | .clk(clk),
41 | .rst_n(rst_n),
42 | .pic_en(pic_en),
43 | .VGA_HS(VGA_HS),
44 | .VGA_VS(VGA_VS),
45 | .Red_Green(Red_Green),
46 | .RGB(RGB)
47 | );
48 |
49 | initial begin
50 | // Initialize Inputs
51 | clk = 0;
52 | rst_n = 0;
53 |
54 | // Wait 100 ns for global reset to finish
55 | #100;
56 | rst_n = 1'b1;
57 | pic_en = 1'b1;
58 | // Add stimulus here
59 |
60 | end
61 |
62 | always #10 clk = ~clk;
63 |
64 |
65 |
66 |
67 | endmodule
68 |
69 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/Top_uart_tx_dzj_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 12:08:43 11/25/2018
8 | // Design Name: Top_uart_tx_dzj
9 | // Module Name: F:/Xilinx/uart/uart_tx/Top_uart_tx_dzj_test.v
10 | // Project Name: uart_tx
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: Top_uart_tx_dzj
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module Top_uart_tx_dzj_test;
26 |
27 | // Inputs
28 | reg [3:0] in_key_en;
29 | reg clk;
30 | reg rst_n;
31 |
32 | // Outputs
33 | wire RX232;
34 | wire over_rx;
35 |
36 | // Instantiate the Unit Under Test (UUT)
37 | Top_uart_tx_dzj uut (
38 | .in_key_en(in_key_en),
39 | .clk(clk),
40 | .rst_n(rst_n),
41 | .RX232(RX232),
42 | .over_rx(over_rx)
43 | );
44 |
45 | initial begin
46 | // Initialize Inputs
47 | in_key_en = 0;
48 | clk = 0;
49 | rst_n = 0;
50 |
51 | // Wait 100 ns for global reset to finish
52 | #10;
53 | rst_n=1'b1;
54 | in_key_en=4'b0100;
55 | #1000000;
56 | in_key_en=4'b0;
57 | // Add stimulus here
58 |
59 | end
60 | always #10 clk=~clk;
61 | endmodule
62 |
63 |
--------------------------------------------------------------------------------
/tp_z.v:
--------------------------------------------------------------------------------
1 | module tp_z(
2 |
3 | clk,rst,du_en,flag_gy26,data_rx,RX232,smg_duan,smg_wei,dp,a,b,dianji
4 | );
5 | input clk;
6 | input rst;
7 | input du_en;
8 | input a;
9 | input b;
10 | input flag_gy26;
11 | input data_rx;
12 |
13 | output RX232;
14 | output [1:0]dianji;
15 | output [6:0]smg_duan;
16 | output [3:0]smg_wei;
17 | output dp;
18 |
19 |
20 | wire [9:0]jiaodu;
21 | wire [60:0]jishu;
22 | wire rst;
23 |
24 | wire [7:0]licheng;
25 |
26 | //wire [9:0]jiaodu;
27 |
28 | shumaguan sh (
29 | .jishu(jishu),
30 | .jiaodu(jiaodu),
31 | .clk(clk),
32 | .smg_duan(smg_duan),
33 | .smg_wei(smg_wei),
34 | .dp(dp),
35 | .rst(rst),
36 | .licheng1(licheng)
37 | );
38 | zhuti zh (
39 | .clk(clk),
40 | .rst(rst),
41 | .du_en(du_en),
42 | .a(a),
43 | .b(b),
44 | .jiaodu(jiaodu),
45 | .dianji(dianji),
46 | .baidu_JD(baidu_JD),
47 | .jishu(jishu),
48 | .JD(JD),
49 | .licheng(licheng)
50 | );
51 | top_gy_26 to (
52 | .flag_gy26(flag_gy26),
53 | .clk(clk),
54 | .rst(rst),
55 | .data_rx(data_rx),
56 | .jiaodu(jiaodu),
57 | .RX232(RX232)
58 | );
59 |
60 | /*top to (
61 | .clk(clk),
62 | .rst(rst),
63 | .a(a),
64 | .b(b),
65 | .smg_duan(smg_duan),
66 | .smg_wei(smg_wei),
67 | .dp(dp),
68 | .turn1(turn1),
69 | .key1(key1),
70 | .key2(key2)
71 | );*/
72 |
73 |
74 | endmodule
75 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/Top_uart_tx_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 20:00:08 11/24/2018
8 | // Design Name: Top_uart_tx
9 | // Module Name: F:/Xilinx/uart/uart_tx/Top_uart_tx_test.v
10 | // Project Name: uart_tx
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: Top_uart_tx
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module Top_uart_tx_test;
26 |
27 | // Inputs
28 | reg clk;
29 | reg send_en;
30 | reg rst_n;
31 | reg [7:0] data_rx;
32 |
33 | // Outputs
34 | wire RX232;
35 | wire over_rx;
36 |
37 | // Instantiate the Unit Under Test (UUT)
38 | Top_uart_tx uut (
39 | .clk(clk),
40 | .send_en(send_en),
41 | .rst_n(rst_n),
42 | .data_rx(data_rx),
43 | .RX232(RX232),
44 | .over_rx(over_rx)
45 | );
46 |
47 | initial begin
48 | // Initialize Inputs
49 | clk = 0;
50 | send_en = 0;
51 | rst_n = 0;
52 | data_rx = 0;
53 |
54 | // Wait 100 ns for global reset to finish
55 | #10;
56 | send_en=1'b1;
57 | rst_n=1'b1;
58 | data_rx=8'b01001001;
59 |
60 | // Add stimulus here
61 |
62 | end
63 | always #10 clk=~clk;
64 | endmodule
65 |
66 |
--------------------------------------------------------------------------------
/top_bizhng.v:
--------------------------------------------------------------------------------
1 | module top_bizhng(clk,rst,echo,trig,dianji2,flag,echo2,trig2,data_rx,RX232,led1,led0,jiaodu,led4,led5,led6,led7,flag1
2 | );
3 | input clk;
4 | input rst;
5 | input echo;
6 | input echo2;
7 | input flag;
8 | input data_rx;
9 | output RX232;
10 | output [9:0]jiaodu;
11 | output trig;
12 | output trig2;
13 | output led1;
14 | output led0;
15 | output led7;
16 | output led6;
17 | output led5;
18 | output led4;
19 | output [1:0]dianji2;
20 | output flag1;
21 | wire [9:0]jiaodu;
22 | wire [9:0]jiaodu1;
23 | wire [9:0]hq;
24 | wire [9:0]hz;
25 | wire rst;
26 | bizhang bi (
27 | .clk(clk),
28 | .rst(rst),
29 | .hq(hq),
30 | .hz(hz),
31 | .jiaodu(jiaodu),
32 | .dianji2(dianji2),
33 | .led7(led7),
34 | .led6(led6),
35 | .led5(led5),
36 | .led4(led4),
37 | .jiaodu1(jiaodu1),
38 | .flag1(flag1)
39 | );
40 |
41 | top2 st (
42 | .clk(clk),
43 | .rst_n(rst),
44 | .echo2(echo2),
45 | .trig2(trig2),
46 | .led0(led0),
47 | .hz(hz)
48 | );
49 | top to (
50 | .clk(clk),
51 | .rst_n(rst),
52 | .echo(echo),
53 | .trig(trig),
54 | .led1(led1),
55 | .hq(hq)
56 | );
57 | /*top_gy_26 na (
58 | .flag(flag),
59 | .clk(clk),
60 | .rst_n(rst),
61 | .data_rx(data_rx),
62 | .RX232(RX232),
63 | .jiaodu(jiaodu)
64 | );*/
65 | top_gy_26 na (
66 | .flag(flag),
67 | .clk(clk),
68 | .rst(rst),
69 | .data_rx(data_rx),
70 | .jiaodu(jiaodu),
71 | .RX232(RX232)
72 | );
73 | endmodule
74 |
--------------------------------------------------------------------------------
/top2.v:
--------------------------------------------------------------------------------
1 | module top2(
2 | input clk ,
3 | input rst_n ,
4 | input echo2 ,
5 |
6 | //output [6:0] smg_duan,
7 | // output [3:0] smg_wei ,
8 | //output dp ,
9 | output trig2,
10 | output led0,
11 | output [9:0]hz
12 | );
13 |
14 |
15 | wire [8:0] dis ;
16 | wire tran_en;
17 |
18 | hc_sr042 HC_SR04_inst(
19 | .clk (clk ),
20 | .rst_n (rst_n ),
21 | .en (1'b1 ),
22 | .echo2 (echo2 ),
23 | .trig2 (trig2 ),
24 | .dis (dis )
25 | );
26 |
27 | reg [ 8:0] dis_reg;
28 | wire [ 8:0] dis_wire;
29 | wire [15:0] bcd;
30 | always @(posedge clk or negedge rst_n) begin
31 | if (!rst_n)
32 | dis_reg <= 0;
33 | else
34 | dis_reg <= dis;
35 | end
36 |
37 | assign dis_wire = dis_reg;
38 | assign tran_en = (dis_reg != dis)? 1'd1:1'd0;
39 |
40 | bcd2 bin_bcd_inst(
41 | .clk (clk ),
42 | .rst_n (rst_n ),
43 | .tran_en (1'd1 ),
44 | .data_in ({7'd0,dis_wire}),
45 | .tran_done ( ),
46 | .bcd (bcd )
47 |
48 | );
49 |
50 | smg2 x7seg_msg_inst(
51 | .x (bcd ),
52 | .clk (clk ),
53 | .rst_n (rst_n ),
54 | //.smg_duan (smg_duan),
55 | //.smg_wei (smg_wei ),
56 | //.dp (dp ),
57 | .led0 (led0),
58 | .hz(hz)
59 | );
60 |
61 | endmodule
62 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/fangdou.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 17:31:17 10/26/2018
7 | // Design Name:
8 | // Module Name: fangdou
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module fangdou(in_key_en,rst_n,clk,out_key_en);
22 | input [3:0]in_key_en;
23 | input clk,rst_n;
24 |
25 | output [3:0]out_key_en;
26 |
27 | parameter clk190 = 18'd263157;
28 |
29 | reg [24:0]cnt;
30 | reg [3:0]delay1,delay2,delay3;
31 | wire [3:0]out_key_en_r;
32 | reg [3:0]out_key_en_rr;
33 |
34 | always @(posedge clk or negedge rst_n)
35 | begin
36 | if(!rst_n)
37 | cnt <= 0;
38 | else if(cnt == clk190)
39 | cnt <= 0;
40 | else
41 | cnt <= cnt + 1;
42 | end
43 |
44 | always @(posedge clk or negedge rst_n)
45 | begin
46 | if(!rst_n)
47 | begin
48 | delay1 <= 4'b0000;
49 | delay2 <= 4'b0000;
50 | delay3 <= 4'b0000;
51 | end
52 | else if(cnt == clk190)
53 | begin
54 | delay1 <= in_key_en;
55 | delay2 <= delay1;
56 | delay3 <= delay2;
57 | end
58 | end
59 |
60 | assign out_key_en_r = delay1 & delay2 & delay3 ;
61 |
62 | always@(posedge clk)
63 | out_key_en_rr <= out_key_en_r;
64 |
65 | assign out_key_en = out_key_en_r & ~out_key_en_rr; //原始信号 & ~延时后的信号
66 |
67 | endmodule
68 |
--------------------------------------------------------------------------------
/top_music.v:
--------------------------------------------------------------------------------
1 | module top_music(
2 | //input key,
3 | input clk,
4 | input rst_n,
5 | input music_rx,
6 | input [17:0]shijian,
7 | input [1:0]flag_zhiwen,
8 | input [1:0]flag_GY25,
9 | input flag_music,//语音输入放歌
10 | input [1:0]flag_tu_ao,
11 |
12 | //input talk_rx,
13 | input flag_shijian,
14 | output RX232,
15 | output led,
16 | output over_all,
17 | output sj_en
18 | );
19 | //wire [17:0]shijian;
20 | wire [3:0]shi_1,shi_2,fen_1,fen_2;
21 | Top_uart_tx_dzj_music a (
22 | .shi_1(shi_1),
23 | .shi_2(shi_2),
24 | .fen_1(fen_1),
25 | .fen_2(fen_2),
26 | .flag_zhiwen(flag_zhiwen),
27 | .flag_music(flag_music),
28 | .flag_tu_ao(flag_tu_ao),
29 | .flag_GY25(flag_GY25),
30 | .sj_en(sj_en),
31 | .clk(clk),
32 | .rst_n(rst_n),
33 | .tx_en(tx_en),
34 | .shijian_en(flag_shijian),
35 | .RX232(RX232),
36 | .over_all(over_all)
37 | );
38 | uart_rx_dzj_music ab (
39 | .clk(clk),
40 | //.over_all(over_all),
41 | .rst_n(rst_n),
42 | .data_rx(music_rx),
43 | .flag(tx_en),
44 | .led(led)
45 | );
46 | /*uart_rx_talk abc (
47 | .clk(clk),
48 | .over_all(over_all),
49 | .rst_n(rst_n),
50 | .data_rx(talk_rx),
51 | .flag(shijian_en)
52 | );*/
53 | /*gps abcd (
54 | .key(key),
55 | .clk(clk),
56 | .rst_n(rst_n),
57 | .shijian(shijian)
58 | );*/
59 | time_ abcde (
60 | .shijian(shijian),
61 | .clk(clk),
62 | .rst_n(rst_n),
63 | .shijian_en(flag_shijian),
64 | .shi_1(shi_1),
65 | .shi_2(shi_2),
66 | .fen_1(fen_1),
67 | .fen_2(fen_2),
68 | .sj_en(sj_en)
69 | );
70 |
71 | endmodule
72 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/Top_uart_tx_dzj.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 11:45:17 11/25/2018
7 | // Design Name:
8 | // Module Name: Top_uart_tx_dzj
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module Top_uart_tx_dzj(
22 | input [3:0]in_key_en,
23 | input clk,
24 | input rst_n,
25 | input co,
26 | input zhendong,
27 |
28 | output RX232,
29 | output over_rx,
30 | output fengshan
31 | );
32 | wire [7:0]data_rx;
33 | wire [3:0]out_key_en;
34 | uart_tx_dzj a (
35 | .co(co),
36 | .zhendong(zhendong),
37 | .in_key_en(out_key_en),
38 | .clk(clk),
39 | .rst_n(rst_n),
40 | .over_tx(over_rx),
41 | .data_rx(data_rx),
42 | .send_en(send_en),
43 | .fengshan(fengshan)
44 | );
45 | fangdou ab (
46 | .in_key_en(in_key_en),
47 | .rst_n(rst_n),
48 | .clk(clk),
49 | .out_key_en(out_key_en)
50 | );
51 | uart_tx abc (
52 | .clk(clk),
53 | .bps_clk(bps_clk),
54 | .send_en(send_en),
55 | .rst_n(rst_n),
56 | .data_rx(data_rx),
57 | .RX232(RX232),
58 | .over_rx(over_rx),
59 | .bps_start(bps_start)
60 | );
61 | bps_set abcd (
62 | .clk(clk),
63 | .rst_n(rst_n),
64 | .bps_start(bps_start),
65 | .bps_clk(bps_clk)
66 | );
67 |
68 |
69 | endmodule
70 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/lora_rx.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 00:28:55 10/05/2019
7 | // Design Name:
8 | // Module Name: uart_rx_talk
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module lora_rx(
22 | input clk,
23 | input rst_n,
24 | input data_rx,
25 | input over_all,
26 |
27 | output [6:0] smg_duan,
28 | output [3:0] smg_wei,
29 | output dp
30 |
31 | );
32 | wire [7:0]data_tx;
33 | bps_set_115200 a (
34 | .clk(clk),
35 | .rst_n(rst_n),
36 | .bps_start(bps_start),
37 | .bps_clk(bps_clk)
38 | );
39 | uart_rx ab (
40 | .nedge(nedge),
41 | .clk(clk),
42 | .rst_n(rst_n),
43 | .bps_clk(bps_clk),
44 | .data_rx(data_rx),
45 | .data_tx(data_tx),
46 | .over_rx(over_rx),
47 | .bps_start(bps_start)
48 | );
49 | /*uart_rx_dzj_lora abc (
50 | .clk(clk),
51 | .over_all(over_all),
52 | .rst_n(rst_n),
53 | .data_tx(data_tx),
54 | .nedge(nedge),
55 | .over_rx(over_rx),
56 | .flag_lora(flag_lora)
57 | );*/
58 | wire [15:0] x;
59 | lora_rx_chuli abcd (
60 | .clk(clk),
61 | .rst_n(rst_n),
62 | .data_tx(data_tx),
63 | .x(x)
64 | );
65 | x7seg_msg abcde (
66 | .x(x),
67 | .clk(clk),
68 | .clr(!rst_n),
69 | .smg_duan(smg_duan),
70 | .smg_wei(smg_wei),
71 | .dp(dp)
72 | );
73 |
74 |
75 | endmodule
76 |
--------------------------------------------------------------------------------
/uart_sentdata_mess.v:
--------------------------------------------------------------------------------
1 | module uart_sentdata_mess(clk,rst,bps_sig,tx_data,tx,tx_enable,tx_done
2 | );
3 | input clk;
4 | input rst;
5 | input [7:0] tx_data;
6 | input tx_enable;
7 | input bps_sig;
8 | output tx;
9 | output tx_done;
10 |
11 | reg tx;
12 | reg tx_done;
13 | reg [3:0]stata;
14 |
15 | always@(posedge clk or negedge rst)
16 | begin
17 | if(!rst)
18 | begin
19 | stata <= 4'd0;
20 | tx <= 1'b1;
21 | tx_done <= 1'b0;
22 | end
23 | else
24 | begin
25 | case(stata)
26 | 0: if(tx_enable & bps_sig)
27 | begin
28 | stata <= stata + 1'b1;
29 | tx <= 1'b0;
30 | end
31 | else
32 | begin
33 | stata <= stata;
34 | tx <= 1'b1;
35 | end
36 | 1,2,3,4,5,6,7,8: if(bps_sig)
37 | begin
38 | tx <= tx_data[stata - 1'b1];
39 | stata <= stata + 1'b1;
40 | end
41 | else
42 | begin
43 | stata <= stata;
44 | tx <= tx;
45 | end
46 | 9,10: if(bps_sig)
47 | begin
48 | stata <= stata + 1'b1;
49 | tx <= 1'b1;
50 | end
51 | 11: begin
52 | stata <= stata + 1'b1;
53 | tx_done <= 1'b1;
54 | end
55 | 12: begin
56 | stata <= 1'b0;
57 | tx_done <= 1'b0;
58 | end
59 | endcase
60 | end
61 | end
62 |
63 | endmodule
64 |
--------------------------------------------------------------------------------
/百度LBS开放平台显示的HTML代码/html代码.txt:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
9 |
10 | 单个标注点沿直线的轨迹运动
11 |
12 |
13 |
14 |
15 |
16 |
--------------------------------------------------------------------------------
/uart_receive.v:
--------------------------------------------------------------------------------
1 | module uart_receive(
2 | input clk,
3 | input rst_n,
4 | input clk_bps,//clk_bps控制的反馈的拍子
5 | input data_rx,//接收数据
6 | output reg rx_int,//反馈信号，正常接收信号反馈“1”，接收结束停止接收反馈“0”。
7 | output [7:0] data_tx,//接收到数据后发送个uart_tx
8 | output reg bps_start //开始检测到uart_rx接受完数据了，启动clk_bps模块，调节时钟
9 | );
10 |
11 | //-------------------------
12 | reg [1:0] rx;
13 |
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) rx <= 2'b11;
16 | else begin
17 | rx[0] <= data_rx;
18 | rx[1] <= rx[0];
19 | end
20 | end
21 | wire nege_edge;
22 | assign nege_edge= rx[1] &~rx[0];//检测下降沿
23 |
24 | reg [3:0]num;
25 |
26 | always@(posedge clk or negedge rst_n)begin
27 | if(!rst_n) begin
28 | bps_start <= 1'b0;
29 | rx_int <= 1'b0;
30 | end
31 | else if(nege_edge)begin
32 | bps_start <= 1'b1;
33 | rx_int <= 1'b1;
34 | end
35 | else if(num == 4'd10)begin
36 | bps_start <= 1'b0;
37 | rx_int <= 1'b0;
38 | end
39 | end
40 |
41 | reg [7:0] rx_data_temp_r;//当前数据接收寄存器
42 | reg [7:0] rx_data_r;//用来锁存数据
43 | always@(posedge clk or negedge rst_n)begin
44 | if(!rst_n) begin
45 | rx_data_r <= 8'd0;
46 | rx_data_temp_r <= 8'd0;
47 | num <= 4'd0;
48 | end
49 | else if(rx_int)begin
50 | if(clk_bps)begin
51 | num <= num + 1'b1;
52 | case(num)
53 | 4'd1: rx_data_temp_r[0] <= data_rx; //锁存第0bit
54 | 4'd2: rx_data_temp_r[1] <= data_rx; //锁存第1bit
55 | 4'd3: rx_data_temp_r[2] <= data_rx; //锁存第2bit
56 | 4'd4: rx_data_temp_r[3] <= data_rx; //锁存第3bit
57 | 4'd5: rx_data_temp_r[4] <= data_rx; //锁存第4bit
58 | 4'd6: rx_data_temp_r[5] <= data_rx; //锁存第5bit
59 | 4'd7: rx_data_temp_r[6] <= data_rx; //锁存第6bit
60 | 4'd8: rx_data_temp_r[7] <= data_rx; //锁存第7bit
61 | default: ;
62 | endcase
63 | end
64 | else if(num == 4'd10)begin
65 | rx_data_r <=rx_data_temp_r;
66 | num <= 4'd0;
67 | end
68 | end
69 | end
70 |
71 | assign data_tx = rx_data_r;
72 |
73 | endmodule
74 |
--------------------------------------------------------------------------------
/uart_receive_1.v:
--------------------------------------------------------------------------------
1 | module uart_receive_1(
2 | input clk,
3 | input rst_n,
4 | input clk_bps,//clk_bps控制的反馈的拍子
5 | input data_rx,//接收数据
6 | output reg rx_int,//反馈信号，正常接收信号反馈“1”，接收结束停止接收反馈“0”。
7 | output [7:0] data_tx,//接收到数据后发送个uart_tx
8 | output reg bps_start //开始检测到uart_rx接受完数据了，启动clk_bps模块，调节时钟
9 | );
10 |
11 | //-------------------------
12 | reg [1:0] rx;
13 |
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) rx <= 2'b11;
16 | else begin
17 | rx[0] <= data_rx;
18 | rx[1] <= rx[0];
19 | end
20 | end
21 | wire nege_edge;
22 | assign nege_edge= rx[1] & ~rx[0];//检测下降沿
23 |
24 | reg [3:0]num;
25 |
26 | always@(posedge clk or negedge rst_n)begin
27 | if(!rst_n) begin
28 | bps_start <= 1'b0;
29 | rx_int <= 1'b0;
30 | end
31 | else if(nege_edge)begin
32 | bps_start <= 1'b1;
33 | rx_int <= 1'b1;
34 | end
35 | else if(num == 4'd10)begin
36 | bps_start <= 1'b0;
37 | rx_int <= 1'b0;
38 | end
39 | end
40 |
41 | reg [7:0] rx_data_temp_r;//当前数据接收寄存器
42 | reg [7:0] rx_data_r;//用来锁存数据
43 | always@(posedge clk or negedge rst_n)begin
44 | if(!rst_n) begin
45 | rx_data_r <= 8'd0;
46 | rx_data_temp_r <= 8'd0;
47 | num <= 4'd0;
48 | end
49 | else if(rx_int)begin
50 | if(clk_bps)begin
51 | num <= num + 1'b1;
52 | case(num)
53 | 4'd1: rx_data_temp_r[0] <= data_rx; //锁存第0bit
54 | 4'd2: rx_data_temp_r[1] <= data_rx; //锁存第1bit
55 | 4'd3: rx_data_temp_r[2] <= data_rx; //锁存第2bit
56 | 4'd4: rx_data_temp_r[3] <= data_rx; //锁存第3bit
57 | 4'd5: rx_data_temp_r[4] <= data_rx; //锁存第4bit
58 | 4'd6: rx_data_temp_r[5] <= data_rx; //锁存第5bit
59 | 4'd7: rx_data_temp_r[6] <= data_rx; //锁存第6bit
60 | 4'd8: rx_data_temp_r[7] <= data_rx; //锁存第7bit
61 | default: ;
62 | endcase
63 | end
64 | else if(num == 4'd10)begin
65 | rx_data_r <=rx_data_temp_r;
66 | num <= 4'd0;
67 | end
68 | end
69 | end
70 |
71 | assign data_tx = rx_data_r;
72 |
73 | endmodule
74 |
--------------------------------------------------------------------------------
/uart_receive_9600.v:
--------------------------------------------------------------------------------
1 | module uart_receive_9600(
2 | input clk,
3 | input rst_n,
4 | input clk_bps,//clk_bps控制的反馈的拍子
5 | input data_rx,//接收数据
6 | output reg rx_int,//反馈信号，正常接收信号反馈“1”，接收结束停止接收反馈“0”。
7 | output [7:0] data_tx,//接收到数据后发送个uart_tx
8 | output reg bps_start //开始检测到uart_rx接受完数据了，启动clk_bps模块，调节时钟
9 | );
10 |
11 | //-------------------------
12 | reg [1:0] rx;
13 |
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) rx <= 2'b11;
16 | else begin
17 | rx[0] <= data_rx;
18 | rx[1] <= rx[0];
19 | end
20 | end
21 | wire nege_edge;
22 | assign nege_edge= rx[1] &~rx[0];//检测下降沿
23 |
24 | reg [3:0]num;
25 |
26 | always@(posedge clk or negedge rst_n)begin
27 | if(!rst_n) begin
28 | bps_start <= 1'b0;
29 | rx_int <= 1'b0;
30 | end
31 | else if(nege_edge)begin
32 | bps_start <= 1'b1;
33 | rx_int <= 1'b1;
34 | end
35 | else if(num == 4'd10)begin
36 | bps_start <= 1'b0;
37 | rx_int <= 1'b0;
38 | end
39 | end
40 |
41 | reg [7:0] rx_data_temp_r;//当前数据接收寄存器
42 | reg [7:0] rx_data_r;//用来锁存数据
43 | always@(posedge clk or negedge rst_n)begin
44 | if(!rst_n) begin
45 | rx_data_r <= 8'd0;
46 | rx_data_temp_r <= 8'd0;
47 | num <= 4'd0;
48 | end
49 | else if(rx_int)begin
50 | if(clk_bps)begin
51 | num <= num + 1'b1;
52 | case(num)
53 | 4'd1: rx_data_temp_r[0] <= data_rx; //锁存第0bit
54 | 4'd2: rx_data_temp_r[1] <= data_rx; //锁存第1bit
55 | 4'd3: rx_data_temp_r[2] <= data_rx; //锁存第2bit
56 | 4'd4: rx_data_temp_r[3] <= data_rx; //锁存第3bit
57 | 4'd5: rx_data_temp_r[4] <= data_rx; //锁存第4bit
58 | 4'd6: rx_data_temp_r[5] <= data_rx; //锁存第5bit
59 | 4'd7: rx_data_temp_r[6] <= data_rx; //锁存第6bit
60 | 4'd8: rx_data_temp_r[7] <= data_rx; //锁存第7bit
61 | default: ;
62 | endcase
63 | end
64 | else if(num == 4'd10)begin
65 | rx_data_r <=rx_data_temp_r;
66 | num <= 4'd0;
67 | end
68 | end
69 | end
70 |
71 | assign data_tx = rx_data_r;
72 |
73 | endmodule
74 |
--------------------------------------------------------------------------------
/uart_receive_xinlv.v:
--------------------------------------------------------------------------------
1 | module uart_receive_xinlv(
2 | input clk,
3 | input rst_n,
4 | input clk_bps,//clk_bps控制的反馈的拍子
5 | input data_rx,//接收数据
6 | output reg rx_int,//反馈信号，正常接收信号反馈“1”，接收结束停止接收反馈“0”。
7 | output [7:0] data_tx,//接收到数据后发送个uart_tx
8 | output reg bps_start //开始检测到uart_rx接受完数据了，启动clk_bps模块，调节时钟
9 | );
10 |
11 | //-------------------------
12 | reg [1:0] rx;
13 |
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) rx <= 2'b11;
16 | else begin
17 | rx[0] <= data_rx;
18 | rx[1] <= rx[0];
19 | end
20 | end
21 | wire nege_edge;
22 | assign nege_edge= rx[1] & ~rx[0];//检测下降沿
23 |
24 | reg [3:0]num;
25 |
26 | always@(posedge clk or negedge rst_n)begin
27 | if(!rst_n) begin
28 | bps_start <= 1'b0;
29 | rx_int <= 1'b0;
30 | end
31 | else if(nege_edge)begin
32 | bps_start <= 1'b1;
33 | rx_int <= 1'b1;
34 | end
35 | else if(num == 4'd10)begin
36 | bps_start <= 1'b0;
37 | rx_int <= 1'b0;
38 | end
39 | end
40 |
41 | reg [7:0] rx_data_temp_r;//当前数据接收寄存器
42 | reg [7:0] rx_data_r;//用来锁存数据
43 | always@(posedge clk or negedge rst_n)begin
44 | if(!rst_n) begin
45 | rx_data_r <= 8'd0;
46 | rx_data_temp_r <= 8'd0;
47 | num <= 4'd0;
48 | end
49 | else if(rx_int)begin
50 | if(clk_bps)begin
51 | num <= num + 1'b1;
52 | case(num)
53 | 4'd1: rx_data_temp_r[0] <= data_rx; //锁存第0bit
54 | 4'd2: rx_data_temp_r[1] <= data_rx; //锁存第1bit
55 | 4'd3: rx_data_temp_r[2] <= data_rx; //锁存第2bit
56 | 4'd4: rx_data_temp_r[3] <= data_rx; //锁存第3bit
57 | 4'd5: rx_data_temp_r[4] <= data_rx; //锁存第4bit
58 | 4'd6: rx_data_temp_r[5] <= data_rx; //锁存第5bit
59 | 4'd7: rx_data_temp_r[6] <= data_rx; //锁存第6bit
60 | 4'd8: rx_data_temp_r[7] <= data_rx; //锁存第7bit
61 | default: ;
62 | endcase
63 | end
64 | else if(num == 4'd10)begin
65 | rx_data_r <=rx_data_temp_r;
66 | num <= 4'd0;
67 | end
68 | end
69 | end
70 |
71 | assign data_tx = rx_data_r;
72 |
73 | endmodule
74 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/uart_tx.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 17:05:49 11/24/2018
7 | // Design Name:
8 | // Module Name: uart_tx
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module uart_tx(
22 | input clk,
23 | input bps_clk,
24 | input send_en,
25 | input rst_n,
26 | input[7:0]data_rx,
27 |
28 | output reg RX232,
29 | output reg over_rx, //结束后会有一个高电平
30 | output reg bps_start
31 | );
32 | reg [3:0]cnt; //数高电平用的计数器
33 | always@(posedge clk or negedge rst_n) //计数器
34 | begin
35 | if(!rst_n)
36 | cnt<=1'b0;
37 | else if(cnt==4'd11)
38 | cnt<=4'd0;
39 | else if(bps_clk)
40 | cnt<=cnt+1'b1;
41 | else cnt<=cnt;
42 | end
43 |
44 | always@(posedge clk or negedge rst_n)
45 | begin
46 | if(!rst_n)
47 | over_rx<=1'b0;
48 | else if(cnt==4'd11)
49 | over_rx<=1'b1;
50 | else over_rx<=1'b0;
51 | end
52 |
53 | always@(posedge clk or negedge rst_n)
54 | begin
55 | if(!rst_n)
56 | bps_start<=1'b0;
57 | else if(send_en)
58 | bps_start<=1'b1;
59 | else if(over_rx)
60 | bps_start<=1'b0;
61 | else bps_start<=bps_start;
62 | end
63 |
64 | always@(posedge clk or negedge rst_n)
65 | begin
66 | if(!rst_n)
67 | RX232<=1'b1;
68 | else
69 | begin
70 | case(cnt)
71 | 0: RX232<=1'b1;
72 | 1: RX232<=1'b0;
73 | 2: RX232<=data_rx[0];
74 | 3: RX232<=data_rx[1];
75 | 4: RX232<=data_rx[2];
76 | 5: RX232<=data_rx[3];
77 | 6: RX232<=data_rx[4];
78 | 7: RX232<=data_rx[5];
79 | 8: RX232<=data_rx[6];
80 | 9: RX232<=data_rx[7];
81 | 10:RX232<=1'b1;
82 | endcase
83 | end
84 | end
85 | endmodule
86 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/lora_rx_chuli.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 12:57:18 11/20/2019
7 | // Design Name:
8 | // Module Name: lora_rx_chuli
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module lora_rx_chuli(
22 | input clk,
23 | input rst_n,
24 | input [7:0]data_tx,
25 |
26 | output reg [15:0] x
27 | );
28 | reg [7:0]data;
29 | reg [25:0]cnt_1s;
30 | always@(posedge clk or negedge rst_n) //1秒计数器
31 | begin
32 | if(!rst_n)
33 | cnt_1s<=1'b0;
34 | else if(cnt_1s==26'd50000000)//else if(cnt_1s==26'd50000000)
35 | cnt_1s<=1'b0;
36 | else cnt_1s<=cnt_1s+1'b1;
37 | end
38 | reg [15:0] x_reg;
39 | reg flag;
40 | always@(posedge clk or negedge rst_n)
41 | begin
42 | if(!rst_n)
43 | begin x_reg<=1'b0; data<=1'b0;flag<=1'b0; end
44 | else
45 | begin
46 | if(cnt_1s==26'd50000000)//if(cnt_1s==26'd50000000) //1秒
47 | begin data<=data_tx; x_reg<=1'b0;end
48 | else if(data>=10'd1000)
49 | begin
50 | x_reg[15:12]<=x_reg[15:12]+1'b1;
51 | data<=data-10'd1000;
52 | end
53 | else if(data>=8'd100)
54 | begin
55 | x_reg[11:8]<=x_reg[11:8]+1'b1;
56 | data<=data-8'd100;
57 | end
58 | else if(data>=4'd10)
59 | begin
60 | x_reg[7:4]<=x_reg[7:4]+1'b1;
61 | data<=data-4'd10;
62 | end
63 | else if(data>=1'd1)
64 | begin
65 | x_reg[3:0]<=x_reg[3:0]+1'b1;
66 | data<=data-1'd1;
67 | flag<=1'b1;
68 | end
69 | else if(data==1'd0)
70 | flag<=1'b1;
71 | else flag<=1'b0;
72 | end
73 | end
74 | always@(*)
75 | begin
76 | if(flag)
77 | x<=x_reg;
78 | else x<=x;
79 | end
80 | endmodule
81 |
--------------------------------------------------------------------------------
/uart_rx.v:
--------------------------------------------------------------------------------
1 | module uart_rx(
2 | input clk,
3 | input rst_n,
4 | input bps_clk,
5 | input data_rx,
6 | output [7:0]data_tx,
7 | output reg over_rx, //接受结束标志 0表示没在接受数据 1表示正在接受数据
8 | output reg bps_start,
9 | output nedge //开始位 下降沿检测标志
10 | );
11 | reg [1:0]tmp_rx; //下降沿检测所用寄存器
12 |
13 | reg[3:0]num; //最大到10 计数
14 | reg[7:0]data_rx0; //第一个寄存器 存每个bit位的数据
15 | reg[7:0]data_rx1; //第二个寄存器 存一个字节的
16 | always@(posedge clk or negedge rst_n) //移位寄存器 检测下降沿
17 | begin
18 | if(!rst_n) tmp_rx<=2'b11;
19 | else
20 | begin
21 | tmp_rx[0]<=data_rx;
22 | tmp_rx[1]<=tmp_rx[0];
23 | end
24 | end
25 | assign nedge=~tmp_rx[0]&tmp_rx[1];
26 |
27 | always@(posedge clk or negedge rst_n)
28 | begin
29 | if(!rst_n)
30 | begin
31 | bps_start<=1'b0;
32 | over_rx <=1'b0;
33 | end
34 | else if(!over_rx)
35 | begin
36 | if(nedge)
37 | begin
38 | bps_start<=1'b1;
39 | over_rx <=1'b1;
40 | end
41 | end
42 | else if(num==4'd10)
43 | begin
44 | bps_start<=1'b0;
45 | over_rx <=1'b0;
46 | end
47 | end
48 |
49 | always@(posedge clk or negedge rst_n)
50 | begin
51 | if(!rst_n)
52 | begin
53 | data_rx0<=1'd0;
54 | data_rx1<=1'd0;
55 | num <=1'd0;
56 | end
57 | else if(over_rx)
58 | begin
59 | if(bps_clk)
60 | begin
61 | num<=num+1'b1;
62 | case(num)
63 | 4'd1: data_rx0[0]<=data_rx;
64 | 4'd2: data_rx0[1]<=data_rx;
65 | 4'd3: data_rx0[2]<=data_rx;
66 | 4'd4: data_rx0[3]<=data_rx;
67 | 4'd5: data_rx0[4]<=data_rx;
68 | 4'd6: data_rx0[5]<=data_rx;
69 | 4'd7: data_rx0[6]<=data_rx;
70 | 4'd8: data_rx0[7]<=data_rx;
71 | default: ;
72 | endcase
73 | end
74 | else if(num==4'd10)
75 | begin
76 | data_rx1<=data_rx0;
77 | num<=4'd0;
78 | end
79 | end
80 | end
81 | assign data_tx=data_rx1;
82 | endmodule
83 |
--------------------------------------------------------------------------------
/uart_rx_dzj.v:
--------------------------------------------------------------------------------
1 | module uart_rx_dzj(
2 | input clk,
3 | input rst_n,
4 | input [7:0]data_tx,
5 | input over_rx,
6 | input nedge,
7 |
8 | output reg [9:0] jiaodu
9 | );
10 |
11 | wire nedge_over_rx;
12 | reg [1:0]tmp_rx; //下降沿检测所用寄存器
13 | always@(posedge clk or negedge rst_n) //移位寄存器 检测下降沿
14 | begin
15 | if(!rst_n) tmp_rx<=2'b11;
16 | else
17 | begin
18 | tmp_rx[0]<=over_rx;
19 | tmp_rx[1]<=tmp_rx[0];
20 | end
21 | end
22 | assign nedge_over_rx=~tmp_rx[0]&tmp_rx[1];
23 |
24 | parameter s0=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4,s5=4'd5;//,s6=4'd6,s7=4'd7,s8=4'd8,s9=4'd9,s10=4'd10,s11=4'd12;
25 | reg[3:0] present_state,next_state;
26 | always@(posedge clk or negedge rst_n)
27 | begin
28 | if(!rst_n)
29 | begin
30 | present_state<=s0;
31 | end
32 | else if(~over_rx&nedge) present_state<=next_state;
33 | end
34 | //[9:8]百位 [7:4]十位 [3:0]个位
35 | reg[1:0]baiwei;
36 | reg[3:0]shiwei;
37 | reg[3:0]gewei;
38 | always@(posedge clk or negedge rst_n)
39 | begin
40 | if(!rst_n)
41 | begin next_state<=s0; baiwei<=1'b0;shiwei<=1'b0;gewei<=1'b0;end
42 | else begin
43 | case(present_state)
44 | s0: if(data_tx==8'h0D/*8'b01001001*/) //0D
45 | next_state<=s1;
46 | else next_state<=s0;
47 | s1: if(data_tx==8'h0A) //0A
48 | next_state<=s2;
49 | else next_state<=s0;
50 | s2: if(data_tx[7:4]==4'b0011)
51 | begin //角度百位
52 | if(nedge_over_rx)begin next_state<=s3;
53 | baiwei<=data_tx[3:0]; end
54 | end
55 | else next_state<=s0;
56 | s3: if(data_tx[7:4]==4'b0011)
57 | begin
58 | if(nedge_over_rx) begin next_state<=s4; //角度十位
59 | shiwei<=data_tx[3:0]; end
60 | end
61 | else next_state<=s0;
62 | s4: if(data_tx[7:4]==4'b0011)
63 | begin //角度个位
64 | if(nedge_over_rx) begin next_state<=s5;
65 | gewei<=data_tx[3:0]; end
66 | end
67 | else next_state<=s0;
68 | s5: next_state<=s0;
69 |
70 | default: next_state<=s0;
71 | endcase
72 | end
73 | end
74 | always@(posedge clk or negedge rst_n)
75 | begin
76 | if(!rst_n)
77 | jiaodu<=1'b0;
78 | else if(next_state==s5)
79 | jiaodu<={baiwei,shiwei,gewei};
80 | else jiaodu<=jiaodu;
81 | end
82 | endmodule
--------------------------------------------------------------------------------
/time_.v:
--------------------------------------------------------------------------------
1 | module time_(
2 | input [17:0]shijian,
3 | input clk,
4 | input rst_n,
5 | input shijian_en, //语音输入一个高电平
6 | output reg [3:0]shi_1,
7 | output reg [3:0]shi_2,
8 | output reg [3:0]fen_1,
9 | output reg [3:0]fen_2,
10 | output reg sj_en
11 | );
12 |
13 | /* always@(*) //拿出时分各位
14 | begin
15 | if((shijian%10000+4'd8)>5'd24) //UTC时间加8为北京时间
16 | begin
17 | shi_1<=(shijian%10000+4'd8-5'd24)%10;
18 | shi_2<=(shijian%10000+4'd8-5'd24)-shi_1*10;
19 | end
20 | else begin
21 | shi_1<=(shijian%10000+4'd8)%10;
22 | shi_2<=(shijian%10000+4'd8)-shi_1*10;
23 | end
24 | fen_1<=(shijian%1000-(shijian%10000)*10);
25 | fen_2<=(shijian%100-(shijian%1000)*10);
26 | end*/
27 |
28 | reg [1:0]tmp_rx; //shijian_en信号上升沿检测所用寄存器
29 | wire podge;
30 | always@(posedge clk or negedge rst_n) //移位寄存器 检测上升沿
31 | begin
32 | if(!rst_n) tmp_rx<=2'b00;
33 | else
34 | begin
35 | tmp_rx[0]<=shijian_en;
36 | tmp_rx[1]<=tmp_rx[0];
37 | end
38 | end
39 | assign podge=tmp_rx[0]&~tmp_rx[1];
40 | reg [17:0]sj;
41 | always@(posedge clk or negedge rst_n) //拿出时分各位
42 | begin
43 | if(!rst_n)
44 | begin shi_1<=4'd0; shi_2<=4'd0;sj<=1'b0;
45 | fen_1<=4'd0; fen_2<=4'd0; sj_en<=1'b0;end
46 | else if(podge)begin sj<=shijian; shi_1<=4'd0; shi_2<=4'd0;fen_1<=4'd0; fen_2<=4'd0;end
47 | else if(sj>=17'd100000)begin
48 | sj<=sj-17'd100000;
49 | shi_1<=shi_1+1'b1; end
50 | else if(sj>=14'd10000)begin
51 | sj<=sj-14'd10000;
52 | shi_2<=shi_2+1'b1; end
53 | else if((shi_1*4'd10+shi_2+4'd8)>5'd24) //UTC时间加8为北京时间
54 | begin //eg 小时是28 28-24=4 再把0和4拿出来
55 | /*sj_yichu<=shi_1*4'd10+shi_2+4'd8-5'd24;
56 | if(sj_yichu<4'd10) //时间最多235959 23+8=31 31-24=7 所以最多就是7
57 | begin shi_2<=sj_yichu;
58 | shi_1<=1'b0; end*/
59 | shi_2<=shi_1*4'd10+shi_2+4'd8-5'd24;
60 | shi_1<=1'b0;
61 | end
62 | else if(sj>=10'd1000) begin
63 | sj<=sj-10'd1000;
64 | fen_1<=fen_1+1'b1; end
65 | else if(sj>=7'd100) begin
66 | sj<=sj-7'd100;
67 | fen_2<=fen_2+1'b1;end
68 | else if(sj>1'b1&sj<7'd100)sj_en<=1'b1;
69 | else sj_en<=1'b0;
70 | end
71 | endmodule
72 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/uart_rx_dzj_lora.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 00:34:12 10/05/2019
7 | // Design Name:
8 | // Module Name: uart_rx_dzj_talk
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module uart_rx_dzj_lora(
22 | input clk,
23 | input rst_n,
24 | input [7:0]data_tx,
25 | input over_rx,
26 | input nedge,
27 | input over_all,
28 | output reg flag_lora
29 | );
30 |
31 | always@(posedge clk or negedge rst_n)
32 | begin
33 | if(!rst_n)
34 | flag_lora<=2'b00;
35 | else if(data_tx==8'd01) //烟雾
36 | flag_lora<=2'b01;
37 | else if(data_tx==8'd2) //震动
38 | flag_lora<=2'b10;
39 | else if(data_tx==8'd3) //门铃
40 | flag_lora<=2'b11;
41 | else flag_lora<=flag_lora;
42 | end
43 |
44 |
45 | //parameter s0=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4;
46 | // reg[3:0] present_state,next_state;
47 | // always@(posedge clk or negedge rst_n)
48 | // begin
49 | // if(!rst_n)
50 | // begin
51 | // present_state<=s0;
52 | // end
53 | // else if(~over_rx&nedge) present_state<=next_state;
54 | // end
55 | //
56 | // always@(*)
57 | // begin
58 | // case(present_state)
59 | // s0: if(data_tx==8'h31/*8'b01001001*/) //时间
60 | // next_state<=s1;
61 | // else next_state<=s0;
62 | // s1: if(data_tx==8'h02/*8'b00100000*/)
63 | // next_state<=s2;
64 | // else next_state<=s0;
65 | // s2: if(data_tx==8'h80/*8'b01001100*/)
66 | // next_state<=s3;
67 | // else next_state<=s0;
68 | // s3: if(data_tx==8'hEF/*8'b01101001*/)
69 | // next_state<=s4;
70 | // else next_state<=s0;
71 | // s4: if(data_tx==8'hAA/*8'b01001001*/)
72 | // next_state<=s1;
73 | // else next_state<=s0;
74 | // default: next_state<=s0;
75 | // endcase
76 | // end
77 | // always@(posedge clk or negedge rst_n)
78 | // begin
79 | // if(!rst_n)
80 | // flag<=0;
81 | // /*else if(over_all)
82 | // flag<=1'b0;*/
83 | // else if(next_state==s1)
84 | // flag<=1'b1;
85 | // else flag<=flag;
86 | // end
87 | endmodule
88 |
--------------------------------------------------------------------------------
/top_calling.v:
--------------------------------------------------------------------------------
1 | module top_calling(
2 | input clk,
3 | input rst_n,
4 | input calling_sent_en_cheng, //打电话使能，连接按键
5 | input calling_sent_en_zhi, //第二个紧急联系人
6 |
7 | output calling_tx
8 |
9 | );
10 |
11 | wire bps_sig;
12 | wire cnt_start;
13 | wire rx_int;
14 | wire [7:0] data1;
15 | wire [47:0] ymr_out;
16 | wire [47:0] time_out;
17 | wire calling_sent_en_1;
18 |
19 | assign calling_sent_en_1 = ~calling_sent_en_cheng;
20 | assign calling_sent_en_2 = ~calling_sent_en_zhi;
21 |
22 |
23 | reg tx_enable;
24 | reg [7:0] tx_data;
25 | wire bps_sig_tx;
26 | wire tx_done;
27 | wire [7:0] tx_data2 ;
28 | wire tx_enable1;
29 | wire tx_enable2;
30 | wire tx_enable3;
31 | wire tx_enable4;
32 | wire [7:0] tx_data1;
33 | wire bps_sig_ring;
34 | wire cnt_start_ring;
35 |
36 |
37 | uart_receive u1_uart_receive (
38 | .clk(clk),
39 | .rst_n(rst_n),
40 | .clk_bps(bps_sig),
41 | .data_rx(data_rx),
42 | .rx_int(rx_int),
43 | .data_tx(data1),
44 | .bps_start(cnt_start)
45 | );
46 |
47 | uart_bps u11_uart_bps (
48 | .clk(clk),
49 | .rst_n(rst_n),
50 | .cnt_start(cnt_start),
51 | .bps_sig(bps_sig)
52 | );
53 |
54 | pick_up_rx u2_pick_up_rx (
55 | .clk(clk),
56 | .rst_n(rst_n),
57 | .data_rx(data1),
58 | .rx_int(rx_int),
59 | .data_rx_end(data_rx_end),
60 | .time_out(time_out),
61 | .ymr_out(ymr_out)
62 | );
63 |
64 | uart_bps mess_u1_uart_bps (
65 | .clk(clk),
66 | .rst_n(rst_n),
67 | .cnt_start(cnt_start_ring),
68 | .bps_sig(bps_sig_ring)
69 | );
70 |
71 | //打电话
72 | calling mess_u5_calling (
73 | .tx_enable(tx_enable2),
74 | .tx_data(tx_data2),
75 | .clk(clk),
76 | .rst(rst_n),
77 | .tx_done(tx_done),
78 | .calling_sent_enable_1(calling_sent_en_1),
79 | .calling_sent_enable_2(calling_sent_en_2)
80 | );
81 |
82 |
83 | uart_bps_mess u2_uart_bps_mess (
84 | .clk(clk),
85 | .rst_n(rst_n),
86 | .bps_sig(bps_sig_tx),
87 | .cnt_start(tx_enable2)
88 | );
89 |
90 | uart_sentdata_mess u3_uart_sentdata_mess (
91 | .clk(clk),
92 | .rst(rst_n),
93 | .bps_sig(bps_sig_tx),
94 | .tx_data(tx_data2),
95 | .tx(calling_tx),
96 | .tx_enable(tx_enable2),
97 | .tx_done(tx_done)
98 | );
99 |
100 | endmodule
101 |
102 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/x7seg_msg.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 16:08:19 10/26/2017
7 | // Design Name:
8 | // Module Name: x7seg_msg
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module x7seg_msg(
22 | input [15:0] x,
23 | input clk,
24 | input clr,
25 | output reg [6:0] smg_duan,
26 | output reg [3:0] smg_wei,
27 | output reg dp
28 | );
29 |
30 | reg [1:0] s;
31 | reg [3:0] digit;
32 | wire [3:0] aen;
33 |
34 | parameter t1=18'd250000;
35 | reg [17:0] cnt1;
36 |
37 | assign aen=4'b1111;
38 |
39 | always@(posedge clk or posedge clr)
40 | begin
41 | if(clr==1) begin
42 | cnt1<=0;
43 | end
44 | else if(cnt1==t1-1) begin
45 | cnt1<=0;
46 | end
47 | else begin
48 | cnt1<=cnt1+1;
49 | end
50 | end
51 |
52 | always@(*)
53 | begin
54 | case(s)
55 | 0: digit=x[3:0];
56 | 1: digit=x[7:4];
57 | 2: digit=x[11:8];
58 | 3: digit=x[15:12];
59 | default: digit=x[3:0];
60 | endcase
61 | end
62 |
63 | //7段解码器
64 | always@(*)
65 | begin
66 | case(digit)
67 | 0: smg_duan=7'b0000001;
68 | 1: smg_duan=7'b1001111;
69 | 2: smg_duan=7'b0010010;
70 | 3: smg_duan=7'b0000110;
71 | 4: smg_duan=7'b1001100;
72 | 5: smg_duan=7'b0100100;
73 | 6: smg_duan=7'b0100000;
74 | 7: smg_duan=7'b0001111;
75 | 8: smg_duan=7'b0000000;
76 | 9: smg_duan=7'b0000100;
77 | 'ha: smg_duan=7'b0001000;
78 | 'hb: smg_duan=7'b1100000;
79 | 'hc: smg_duan=7'b0110001;
80 | 'hd: smg_duan=7'b1000010;
81 | 'he: smg_duan=7'b0110000;
82 | 'hf: smg_duan=7'b0111000;//空白
83 | default:smg_duan=7'b1111111;
84 | endcase
85 | end
86 |
87 | //数字选择
88 | always@(*)
89 | begin
90 | smg_wei=4'b1111;
91 | if(aen[s]==1)
92 | smg_wei[s]=0;
93 | end
94 |
95 | //2位计数器
96 | always@(posedge clk or posedge clr)
97 | begin
98 | if(clr==1) begin
99 | s<=0;
100 | dp<=1;
101 | end
102 | else if(cnt1==t1-1) begin
103 | s<=s+1;
104 | if(s==1) begin
105 | dp<=0;
106 | end
107 | else begin
108 | dp<=1;
109 | end
110 | end
111 | else begin
112 | s<=s;
113 | end
114 | end
115 | endmodule
116 |
--------------------------------------------------------------------------------
/judge_Red_Green.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:35:32 11/02/2019
7 | // Design Name:
8 | // Module Name: judge_Red_Green
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module judge_Red_Green(
22 | input clk,
23 | input rst_n,
24 | input [7:0] RGB,
25 |
26 | output reg [1:0] Red_Green //01代表红色 , 10代表绿色
27 | );
28 |
29 |
30 | wire [7:0] r1;
31 | wire [7:0] g1;
32 | wire [7:0] b1;
33 | wire red0;
34 | wire green0;
35 | wire blue0;
36 | wire red1;
37 | wire green1;
38 | wire blue1;
39 | wire red_en;
40 | wire green_en;
41 |
42 |
43 | assign r1 = {RGB[7:5],RGB[7:5],RGB[7:6]};
44 | assign g1 = {RGB[4:2],RGB[4:2],RGB[4:3]};
45 | assign b1 = {RGB[1:0],RGB[1:0],RGB[1:0],RGB[1:0]};
46 |
47 | //红色阈值
48 | assign red0 = (r1 > 8'd0 && r1 <= 8'd185) ? 1'b1 : 1'b0;
49 | assign green0 = (g1 >= 8'd0 && g1 <= 8'd38) ? 1'b1 : 1'b0;
50 | assign blue0 = (b1 >= 8'd0 && b1 <= 8'd10) ? 1'b1 : 1'b0;
51 |
52 | //绿色阈值
53 | assign red1 = (r1 > 8'd0 && r1 <= 8'd20) ? 1'b1 : 1'b0;
54 | assign green1 = (g1 > 8'd0 && g1 <= 8'd70) ? 1'b1 : 1'b0;
55 | assign blue1 = (b1 > 8'd0 && b1 <= 8'd20) ? 1'b1 : 1'b0;
56 |
57 |
58 | assign red_en = (red0 && green0 && blue0) ? 1'b1 : 1'b0;
59 | assign green_en = (red1 && green1 && blue1) ? 1'b1 : 1'b0;
60 |
61 |
62 |
63 |
64 |
65 | reg [9:0] R_cnt;
66 |
67 |
68 | always @(posedge clk or negedge rst_n)
69 | begin
70 | if(!rst_n)
71 | R_cnt <= 10'd0;
72 | else if(red_en)
73 | R_cnt <= R_cnt + 1'b1;
74 | else
75 | R_cnt <= R_cnt;
76 | end
77 |
78 | reg [9:0] G_cnt;
79 |
80 | always @(posedge clk or negedge rst_n)
81 | begin
82 | if(!rst_n)
83 | G_cnt <= 10'd0;
84 | else if(green_en)
85 | G_cnt <= G_cnt + 1'b1;
86 | else
87 | G_cnt <= G_cnt;
88 | end
89 |
90 | always @(posedge clk or negedge rst_n)
91 | begin
92 | if(!rst_n)
93 | Red_Green <= 2'b0;
94 | else if(R_cnt >= 200)
95 | Red_Green <= 2'b01; //01代表红色
96 | else if(G_cnt >= 200)
97 | Red_Green <= 2'b10; //10代表绿色
98 | else
99 | Red_Green <= 2'b0;
100 | end
101 |
102 |
103 |
104 | endmodule
105 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/uart_rx.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:25:16 11/25/2018
7 | // Design Name:
8 | // Module Name: uart_rx
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module uart_rx(
22 | input clk,
23 | input rst_n,
24 | input bps_clk,
25 | input data_rx,
26 | output [7:0]data_tx,
27 | output reg over_rx, //接受结束标志 0表示没在接受数据 1表示正在接受数据
28 | output reg bps_start,
29 | output nedge //开始位 下降沿检测标志
30 | );
31 | reg [1:0]tmp_rx; //下降沿检测所用寄存器
32 |
33 | reg[3:0]num; //最大到10 计数
34 | reg[7:0]data_rx0; //第一个寄存器 存每个bit位的数据
35 | reg[7:0]data_rx1; //第二个寄存器 存一个字节的
36 | always@(posedge clk or negedge rst_n) //移位寄存器 检测下降沿
37 | begin
38 | if(!rst_n) tmp_rx<=2'b11;
39 | else
40 | begin
41 | tmp_rx[0]<=data_rx;
42 | tmp_rx[1]<=tmp_rx[0];
43 | end
44 | end
45 | assign nedge=~tmp_rx[0]&tmp_rx[1];
46 |
47 | always@(posedge clk or negedge rst_n)
48 | begin
49 | if(!rst_n)
50 | begin
51 | bps_start<=1'b0;
52 | over_rx <=1'b0;
53 | end
54 | else if(!over_rx)
55 | begin
56 | if(nedge)
57 | begin
58 | bps_start<=1'b1;
59 | over_rx <=1'b1;
60 | end
61 | end
62 | else if(num==4'd10)
63 | begin
64 | bps_start<=1'b0;
65 | over_rx <=1'b0;
66 | end
67 | end
68 |
69 | always@(posedge clk or negedge rst_n)
70 | begin
71 | if(!rst_n)
72 | begin
73 | data_rx0<=1'd0;
74 | data_rx1<=1'd0;
75 | num <=1'd0;
76 | end
77 | else if(over_rx)
78 | begin
79 | if(bps_clk)
80 | begin
81 | num<=num+1'b1;
82 | case(num)
83 | 4'd1: data_rx0[0]<=data_rx;
84 | 4'd2: data_rx0[1]<=data_rx;
85 | 4'd3: data_rx0[2]<=data_rx;
86 | 4'd4: data_rx0[3]<=data_rx;
87 | 4'd5: data_rx0[4]<=data_rx;
88 | 4'd6: data_rx0[5]<=data_rx;
89 | 4'd7: data_rx0[6]<=data_rx;
90 | 4'd8: data_rx0[7]<=data_rx;
91 | default: ;
92 | endcase
93 | end
94 | else if(num==4'd10)
95 | begin
96 | data_rx1<=data_rx0;
97 | num<=4'd0;
98 | end
99 | end
100 | end
101 | assign data_tx=data_rx1;
102 | endmodule
103 |
--------------------------------------------------------------------------------
/top.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:34:38 11/02/2019
7 | // Design Name:
8 | // Module Name: top
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module top(
22 | input clk,
23 | input rst_n,
24 | input pic_en,
25 |
26 | output VGA_HS,
27 | output VGA_VS,
28 | output [1:0] Red_Green,
29 | output [7:0] RGB
30 |
31 | );
32 |
33 | wire VGA_clk;
34 | wire disp_valid;//判断是否在有效的显示区域
35 | wire [7:0] M;
36 | wire [7:0] M_pic;
37 | wire [15:0] rom_addr16;
38 | wire [15:0] rom_addr13;
39 | wire flag_addr;
40 | wire [15:0] flag_square_begin;
41 | wire [15:0] flag_square_end;
42 | wire [6:0] cnt_x;
43 | wire [6:0] cnt_y;
44 | wire [7:0] a;
45 | wire [15:0] rom_addr;
46 |
47 |
48 |
49 | div_25HZ U_div_25HZ (
50 | .clk(clk),
51 | .rst_n(rst_n),
52 | .VGA_clk(VGA_clk)
53 | );
54 |
55 |
56 | VGA U_VGA (
57 | .clk(clk),
58 | .rst_n(rst_n),
59 | .M(a),
60 | .cnt_x(cnt_x),
61 | .cnt_y(cnt_y),
62 | .pic_en(pic_en),
63 | .VGA_HS(VGA_HS),
64 | .VGA_VS(VGA_VS),
65 | .flag_addr(flag_addr),
66 | .flag_square_begin(flag_square_begin),
67 | .flag_square_end(flag_square_end),
68 | .rom_addr16(rom_addr16),
69 | .RGB(RGB)
70 | );
71 |
72 |
73 | VGA_pic_double U_VGA_pic_double (
74 | .clka(VGA_clk), // input clka
75 | .addra(rom_addr), // input [12 : 0] addra
76 | .douta(a) // output [7 : 0] douta
77 | );
78 |
79 |
80 | VGA_square U_VGA_square (
81 | .clk(VGA_clk),
82 | .rst_n(rst_n),
83 | .M_pic(a),
84 | .cnt_x(cnt_x),
85 | .cnt_y(cnt_y),
86 | .flag_addr(flag_addr),
87 | .rom_addr13(rom_addr13),
88 | .flag_square_begin(flag_square_begin),
89 | .flag_square_end(flag_square_end)
90 | );
91 |
92 |
93 | judge_Red_Green U_judge_Red_Green (
94 | .clk(clk),
95 | .rst_n(rst_n),
96 | .RGB(RGB),
97 | .Red_Green(Red_Green)
98 | );
99 |
100 |
101 | select_addr U_select_addr (
102 | .clk(clk),
103 | .rst_n(rst_n),
104 | .flag_square_begin(flag_square_begin),
105 | .rom_addr13(rom_addr13), //VGA_square
106 | .rom_addr16(rom_addr16), //VGA_bsprite
107 | .rom_addr(rom_addr)
108 | );
109 |
110 |
111 | endmodule
112 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/lora_rx_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 |
3 | ////////////////////////////////////////////////////////////////////////////////
4 | // Company:
5 | // Engineer:
6 | //
7 | // Create Date: 17:28:52 11/20/2019
8 | // Design Name: lora_rx
9 | // Module Name: F:/Xilinx/lora_home_new/lora_rx_test.v
10 | // Project Name: uart_tx
11 | // Target Device:
12 | // Tool versions:
13 | // Description:
14 | //
15 | // Verilog Test Fixture created by ISE for module: lora_rx
16 | //
17 | // Dependencies:
18 | //
19 | // Revision:
20 | // Revision 0.01 - File Created
21 | // Additional Comments:
22 | //
23 | ////////////////////////////////////////////////////////////////////////////////
24 |
25 | module lora_rx_test;
26 |
27 | // Inputs
28 | reg clk;
29 | reg rst_n;
30 | reg data_rx;
31 | reg over_all;
32 |
33 | // Outputs
34 | wire [6:0] smg_duan;
35 | wire [3:0] smg_wei;
36 | wire dp;
37 |
38 | // Instantiate the Unit Under Test (UUT)
39 | lora_rx uut (
40 | .clk(clk),
41 | .rst_n(rst_n),
42 | .data_rx(data_rx),
43 | .over_all(over_all),
44 | .smg_duan(smg_duan),
45 | .smg_wei(smg_wei),
46 | .dp(dp)
47 | );
48 |
49 | initial begin
50 | // Initialize Inputs
51 | clk = 0;
52 | rst_n = 0;
53 | data_rx = 0;
54 | over_all = 0;
55 |
56 | // Wait 100 ns for global reset to finish
57 | #20;
58 | rst_n=1'b1;
59 | data_rx=1'b1;
60 | #8680; //434*20=8680
61 | data_rx=1'b0;
62 | #8680;
63 | data_rx=1'b1;
64 | #8680;
65 | data_rx=1'b1;
66 | #8680;
67 | data_rx=1'b1;
68 | #8680;
69 | data_rx=1'b1;
70 | #8680;
71 | data_rx=1'b1;
72 | #8680;
73 | data_rx=1'b0;
74 | #8680;
75 | data_rx=1'b0;
76 | #8680;
77 | data_rx=1'b0;
78 | #8680;
79 | data_rx=1'b1;//31
80 | #8680; //434*20=8680
81 | data_rx=1'b0;
82 | #8680;
83 | data_rx=1'b1;
84 | #8680;
85 | data_rx=1'b1;
86 | #8680;
87 | data_rx=1'b1;
88 | #8680;
89 | data_rx=1'b1;
90 | #8680;
91 | data_rx=1'b1;
92 | #8680;
93 | data_rx=1'b0;
94 | #8680;
95 | data_rx=1'b0;
96 | #8680;
97 | data_rx=1'b0;
98 | #8680;
99 | data_rx=1'b1;//31
100 | #8680; //434*20=8680
101 | data_rx=1'b0;
102 | #8680;
103 | data_rx=1'b1;
104 | #8680;
105 | data_rx=1'b1;
106 | #8680;
107 | data_rx=1'b1;
108 | #8680;
109 | data_rx=1'b1;
110 | #8680;
111 | data_rx=1'b0;
112 | #8680;
113 | data_rx=1'b0;
114 | #8680;
115 | data_rx=1'b1;
116 | #8680;
117 | data_rx=1'b0;
118 | #8680;
119 | data_rx=1'b1;//79
120 | #8680; //434*20=8680
121 | data_rx=1'b0;
122 | #8680;
123 | data_rx=1'b0;
124 | #8680;
125 | data_rx=1'b0;
126 | #8680;
127 | data_rx=1'b1;
128 | #8680;
129 | data_rx=1'b0;
130 | #8680;
131 | data_rx=1'b0;
132 | #8680;
133 | data_rx=1'b0;
134 | #8680;
135 | data_rx=1'b1;
136 | #8680;
137 | data_rx=1'b0;
138 | #8680;
139 | data_rx=1'b1;//68
140 | // Add stimulus here
141 |
142 | end
143 | always #10 clk=~clk;
144 | endmodule
145 |
146 |
--------------------------------------------------------------------------------
/data_extract.v:
--------------------------------------------------------------------------------
1 | module data_extract(clk,rst_n,date_byte,angle,rx_done,bps_cnt,byte1
2 | );
3 | input wire clk;
4 | input wire rst_n;
5 | input wire [7:0] date_byte;
6 | input wire rx_done;
7 | input wire [7:0] bps_cnt;
8 |
9 | output reg [7:0] angle;
10 | output reg [7:0] byte1 ;
11 |
12 | reg s_sign ; //帧头高电平标志
13 |
14 | reg s_sign_1;
15 | reg s_sign_2;
16 | wire neged ; //帧头高电平标志下降沿
17 | reg [1:0] fy_byte_cnt; //对俯仰角的BYTE计数
18 | reg [3:0] byte_cnt ; //对所有byte计数
19 | reg fuyang_angle; //俯仰角高电平标志
20 | reg [7:0] freq_cnt ; //采样频率计数器
21 | reg [7:0] byte2; //俯仰角高 8 位 ,航向角低 8 位
22 | wire [15:0] fs; //负数
23 |
24 | always @(posedge clk or negedge rst_n)
25 | begin
26 | if(!rst_n)
27 | byte_cnt <= 0;
28 | else if(byte_cnt==8) //帧结束标志
29 | byte_cnt <= 0;
30 | else if( rx_done == 1)
31 | byte_cnt <= byte_cnt + 1;
32 | else
33 | byte_cnt <= byte_cnt;
34 | end
35 |
36 | always @(posedge clk or negedge rst_n)
37 | begin
38 | if(!rst_n)
39 | s_sign <= 0;
40 | else if(byte_cnt==4'b0011)
41 | s_sign <= 1;
42 | else
43 | s_sign <= 0;
44 | end
45 | always @(posedge clk or negedge rst_n)
46 | begin
47 | if(!rst_n)
48 | begin
49 | s_sign_1 <= 0;
50 | s_sign_2 <= 0;
51 | end
52 | else
53 | begin
54 | s_sign_1 <= s_sign;
55 | s_sign_2 <= s_sign_1;
56 | end
57 | end
58 |
59 | assign neged = ~s_sign_1 & s_sign_2;
60 |
61 | always @(posedge clk or negedge rst_n)
62 | begin
63 | if(!rst_n)
64 | fuyang_angle <= 0;
65 | else if (neged == 1 && freq_cnt == 1 )
66 | fuyang_angle <= 1;
67 | else if(fy_byte_cnt == 2)
68 | fuyang_angle <= 0;
69 | else
70 | fuyang_angle <= fuyang_angle;
71 | end
72 |
73 | always @(posedge clk or negedge rst_n)
74 | begin
75 | if(!rst_n)
76 | freq_cnt <= 0 ;
77 | else if(freq_cnt == 3)
78 | freq_cnt <= 0;
79 | else if(neged == 1)
80 | freq_cnt <= freq_cnt+1;
81 | else
82 | freq_cnt <= freq_cnt;
83 | end
84 | always @(posedge clk or negedge rst_n)
85 | begin
86 | if(!rst_n)
87 | fy_byte_cnt <= 0;
88 | else if(freq_cnt == 2 && fuyang_angle == 1)
89 | if(rx_done == 1)
90 | fy_byte_cnt <= fy_byte_cnt + 1;
91 | else
92 | fy_byte_cnt <= fy_byte_cnt ;
93 | else
94 | fy_byte_cnt <= 0;
95 | end
96 | always @(posedge clk or negedge rst_n)
97 | begin
98 | if(!rst_n)
99 | begin
100 | byte1 <= 0;
101 | byte2 <= 0;
102 | end
103 | else if(fuyang_angle == 1)
104 | begin
105 | if(fy_byte_cnt == 0 && bps_cnt== 80)
106 | byte1 <= date_byte;
107 | else if(fy_byte_cnt == 1 && bps_cnt== 80)
108 | byte2 <= date_byte;
109 | else
110 | begin
111 | byte1 <= byte1;
112 | byte2 <= byte2;
113 | end
114 | end
115 | else
116 | begin
117 | byte1 <= byte1;
118 | byte2 <= byte2;
119 | end
120 | end
121 |
122 | assign fs = (byte1[7] == 1) ? ( ~{byte1[7:0], byte2[7:0]}) : 0;
123 | always@(posedge clk or negedge rst_n)
124 | begin
125 | if(!rst_n)
126 | angle <= 0;
127 | else if(fy_byte_cnt == 2)
128 | begin
129 | if(byte1[7] == 1'b1) //负数的时候取反加一
130 | angle <= (fs +1'b1)*41>>12; //*41>>12 = /100
131 | else
132 | angle <= ({byte1[7:0] , byte2[7:0]})*41>>12;
133 | end
134 | else
135 | angle <= angle;
136 | end
137 | endmodule
138 |
--------------------------------------------------------------------------------
/top_duanxin.v:
--------------------------------------------------------------------------------
1 | module top_duanxin(
2 | input clk,
3 | input rst_n,
4 | input mess_phone_number_prepared_enable,//短信发送使能，连接按键
5 | input data_rx,//gps的接收
6 |
7 | output gsm_tx
8 |
9 | );
10 |
11 | wire emergency_contact_1 = 1;//紧急联系人1
12 | wire emergency_contact_2 = 0;//紧急联系人2
13 | wire emergency_contact_3 = 0;//紧急联系人3
14 | wire bps_sig;
15 | wire cnt_start;
16 | wire rx_int;
17 | wire [7:0] data1;
18 | // wire [383:0] data_rx_end;
19 | wire [47:0] ymr_out;
20 | wire [47:0] time_out;
21 |
22 |
23 | reg [87:0] calling_number_end;
24 | reg [2:0] out_message_or_calling_en_or_receive;//选择输出，011是发短信功能，10是打电话功能，11是接电话功能
25 |
26 | always@(posedge clk )begin
27 | case ({0,emergency_contact_1,emergency_contact_2,emergency_contact_3})
28 | 4'b1000:calling_number_end<= 88'h0;
29 | 4'b0100:calling_number_end<= 88'h34_38_32_31_37_36_32_38_33_37_31;//程宁勃
30 | 4'b0010:calling_number_end<= 88'h30_36_34_38_34_33_31_39_36_37_31;//刘仰猛;
31 | 4'b0001:calling_number_end<= 88'h37_39_38_38_37_38_37_38_32_33_31;//张胜亭;
32 | default:calling_number_end<=calling_number_end;
33 | endcase
34 | end
35 |
36 | reg tx_enable;
37 | reg [7:0] tx_data;
38 | wire bps_sig_tx;
39 | wire tx_done;
40 | wire tx_enable1;
41 | wire tx_enable2;
42 | wire tx_enable3;
43 | wire tx_enable4;
44 | wire [7:0] tx_data1;
45 | wire bps_sig_ring;
46 | wire cnt_start_ring;
47 | wire [183:0] data_rx_end_jingduweidu;
48 |
49 |
50 | uart_receive u1_uart_receive (
51 | .clk(clk),
52 | .rst_n(rst_n),
53 | .clk_bps(bps_sig),
54 | .data_rx(data_rx),
55 | .rx_int(rx_int),
56 | .data_tx(data1),
57 | .bps_start(cnt_start)
58 | );
59 |
60 | uart_bps u11_uart_bps (
61 | .clk(clk),
62 | .rst_n(rst_n),
63 | .cnt_start(cnt_start),
64 | .bps_sig(bps_sig)
65 | );
66 |
67 | pick_up_rx u2_pick_up_rx (
68 | .clk(clk),
69 | .rst_n(rst_n),
70 | .data_rx(data1),
71 | .rx_int(rx_int),
72 | .data_rx_end(data_rx_end),
73 | .time_out(time_out),
74 | .ymr_out(ymr_out)
75 | );
76 |
77 | uart_bps mess_u1_uart_bps (
78 | .clk(clk),
79 | .rst_n(rst_n),
80 | .cnt_start(cnt_start_ring),
81 | .bps_sig(bps_sig_ring)
82 | );
83 |
84 | //短信的发送
85 | gsm mess_u4_gsm (
86 | .tx_enable(tx_enable1),
87 | .tx_data(tx_data1),
88 | .clk(clk),
89 | .rst(rst_n),
90 | .tx_done(tx_done),
91 | .mess_phone_number_prepared_enable(mess_phone_number_prepared_enable), //短信发送使能
92 | .TEXT_buf(data_rx_end_jingduweidu)
93 | );
94 |
95 | always@(posedge clk ) begin
96 | if(mess_phone_number_prepared_enable)
97 | out_message_or_calling_en_or_receive <= 3'b011;
98 | else
99 | out_message_or_calling_en_or_receive <= out_message_or_calling_en_or_receive;
100 | end
101 |
102 |
103 |
104 | always@(posedge clk )
105 | begin
106 | case(out_message_or_calling_en_or_receive)
107 | 3'b011: begin
108 | tx_data <= tx_data1;
109 | tx_enable <= tx_enable1;
110 | end
111 | default:;
112 | endcase
113 | end
114 |
115 | uart_bps_mess u2_uart_bps_mess (
116 | .clk(clk),
117 | .rst_n(rst_n),
118 | .bps_sig(bps_sig_tx),
119 | .cnt_start(tx_enable)
120 | );
121 |
122 | uart_sentdata_mess u3_uart_sentdata_mess (
123 | .clk(clk),
124 | .rst(rst_n),
125 | .bps_sig(bps_sig_tx),
126 | .tx_data(tx_data),
127 | .tx(gsm_tx),
128 | .tx_enable(tx_enable),
129 | .tx_done(tx_done)
130 | );
131 |
132 |
133 | top_gps u_top_gps(
134 | .clk(clk),
135 | .rst_n(rst_n),
136 | .data_rx(data_rx),//gps的接收端
137 | .data_rx_end(data_rx_end_jingduweidu)
138 | );
139 |
140 | endmodule
141 |
--------------------------------------------------------------------------------
/shumaguan.v:
--------------------------------------------------------------------------------
1 | module shumaguan( jishu,jiaodu,clk,smg_duan,smg_wei,dp,rst,licheng1
2 | );
3 | input [60:0] jishu;
4 | input [9:0]jiaodu;
5 | input clk;
6 | input rst;
7 | output reg [6:0] smg_duan;
8 | output reg [3:0] smg_wei;
9 | output reg dp;
10 | output [7:0]licheng1;
11 | reg [1:0] s;
12 | reg [3:0] digit;
13 | wire [3:0] aen;
14 |
15 | parameter t1=18'd250000;
16 | reg [17:0] cnt6;
17 |
18 | assign aen=4'b1111;
19 |
20 | always@(posedge clk or negedge rst)
21 | begin
22 | if(rst==0) begin
23 | cnt6<=0;
24 | end
25 | else if(cnt6==t1-1) begin
26 | cnt6<=0;
27 | end
28 | else begin
29 | cnt6<=cnt6+1;
30 | end
31 | end
32 |
33 | reg [60:0]jishu_dis;
34 | reg [60:0] jishu_reg1;
35 | reg [60:0] jishu_reg2;
36 | reg [7:0]a;
37 | reg [3:0]b;
38 | reg [3:0]c;
39 | reg [3:0]d;
40 | assign change = (jishu_reg1 == jishu_reg2)?0:1;
41 |
42 | always@(posedge clk or negedge rst)
43 | begin
44 | if(!rst)
45 | begin
46 | jishu_reg1 <= 39'b0;
47 | jishu_reg2 <= 39'b0;
48 | end
49 | else
50 | begin
51 | jishu_reg1 <= jishu;
52 | jishu_reg2 <= jishu_reg1;
53 | end
54 | end
55 |
56 | always@(posedge clk or negedge rst)
57 | begin
58 | if(!rst)
59 | begin
60 | jishu_dis <= 39'd0;
61 | a <= 4'd0;
62 | b <= 4'd0;
63 | c <= 4'd0;
64 | d <= 4'd0;
65 | end
66 | else if(change)
67 | begin
68 | a <= 4'd0;
69 | b <= 4'd0;
70 | c <= 4'd0;
71 | d <= 4'd0;
72 | jishu_dis <= jishu;
73 | end
74 | else
75 | begin
76 | if(jishu_dis >= 20'd1000000)//if(jishu_dis >= 16'd1000)
77 | begin
78 | jishu_dis <= jishu_dis - 20'd1000000;
79 | a <= a + 1;
80 | end
81 | else
82 | if(jishu_dis >= 17'd100000)//if(jishu_dis >= 16'd100)
83 | begin
84 | jishu_dis <= jishu_dis - 17'd100000;
85 | b <= b + 1;
86 | end
87 | else
88 | if(jishu_dis >= 14'd10000)//if(jishu_dis >= 16'd10)
89 | begin
90 | jishu_dis <= jishu_dis - 14'd10000;
91 | c <= c + 1;
92 | end
93 | else
94 | if(jishu_dis >= 10'd1000)//if(jishu_dis >= 16'd1)
95 | begin
96 | jishu_dis <= jishu_dis - 10'd1000;
97 | d <= d + 1;
98 | end
99 | else
100 | begin
101 | a <= a;
102 | b <= b;
103 | c <= c;
104 | d <= d;
105 | jishu_dis <= jishu_dis;
106 | end
107 | end
108 |
109 | end
110 |
111 | assign licheng1= d*1+c*10+b*100+a*1000;
112 | always@(*)
113 | begin
114 | case(s)
115 | 0: digit=d;// 0: digit=jiaodu[3:0];//0: digit=d;
116 | 1: digit=c;// 1: digit=jiaodu[7:4];//1: digit=c;
117 | 2: digit=b;// 2: digit=jiaodu[9:8];//2: digit=b;
118 | 3: digit=a;// 3: digit=1'b0; //3: digit=a;
119 | default: digit=a;//default: digit=jiaodu[3:0];
120 | endcase
121 | end
122 |
123 | //7段解码器
124 | always@(*)
125 | begin
126 | case(digit)
127 | 0: smg_duan=7'b0000001;
128 | 1: smg_duan=7'b1001111;
129 | 2: smg_duan=7'b0010010;
130 | 3: smg_duan=7'b0000110;
131 | 4: smg_duan=7'b1001100;
132 | 5: smg_duan=7'b0100100;
133 | 6: smg_duan=7'b0100000;
134 | 7: smg_duan=7'b0001111;
135 | 8: smg_duan=7'b0000000;
136 | 9: smg_duan=7'b0000100;
137 | 'ha: smg_duan=7'b0001000;
138 | 'hb: smg_duan=7'b1100000;
139 | 'hc: smg_duan=7'b0110001;
140 | 'hd: smg_duan=7'b1111110;
141 | 'he: smg_duan=7'b0110000;
142 | 'hf: smg_duan=7'b1111111;//空白
143 | default:smg_duan=7'b1111111;
144 | endcase
145 | end
146 |
147 | //数字选择
148 | always@(*)
149 | begin
150 | smg_wei=4'b1111;
151 | if(aen[s]==1)
152 | smg_wei[s]=0;
153 | end
154 |
155 | //2位计数器
156 | always@(posedge clk or negedge rst)
157 | begin
158 | if(rst==0) begin
159 | s<=0;
160 | dp<=1;
161 | end
162 | else if(cnt6==t1-1) begin
163 | s<=s+1;
164 | if(s==1) begin
165 | dp<=0;
166 | end
167 | else begin
168 | dp<=1;
169 | end
170 | end
171 | else begin
172 | s<=s;
173 | end
174 | end
175 |
176 |
177 |
178 | endmodule
179 |
--------------------------------------------------------------------------------
/盲人家中板子的FPGA代码/uart_tx_dzj.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 20:44:32 11/24/2018
7 | // Design Name:
8 | // Module Name: uart_tx_dzj
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module uart_tx_dzj(
22 | input [3:0]in_key_en,
23 | input co,
24 | input zhendong,
25 | input clk,
26 | input rst_n,
27 | input over_tx,
28 |
29 | output reg [7:0]data_rx,
30 | output reg send_en,
31 | output reg fengshan
32 | );
33 | reg [3:0]cnt; //最大要记到14 I like verilog 一共14个字符
34 | reg[1:0] flag; //判断哪个按键按下 输出不同的话
35 | always@(posedge clk or negedge rst_n) //数每个字符结束 递 下一个字符的计数器
36 | begin
37 | if(!rst_n)
38 | cnt<=1'b0;
39 | else if(over_tx)
40 | cnt<=cnt+1'b1;
41 | else if(|in_key_en)
42 | cnt<=1'b0;
43 | end
44 | reg [1:0]tmp_co;
45 | always@(posedge clk or negedge rst_n)
46 | begin
47 | if(!rst_n)
48 | tmp_co<=2'b00;
49 | else begin
50 | tmp_co[1]<=co;
51 | tmp_co[0]<=tmp_co[1];
52 | end
53 | end
54 |
55 | assign co_h=~tmp_co[1]&tmp_co[0];
56 |
57 | reg [27:0] cnt_3s;
58 | always@(posedge clk or negedge rst_n)
59 | begin
60 | if(!rst_n)
61 | cnt_3s<=1'b0;
62 | else if(cnt_3s==28'd150000000)
63 | cnt_3s<=1'b0;
64 | else cnt_3s<=cnt_3s+1'b1;
65 | end
66 | always@(posedge clk or negedge rst_n)
67 | begin
68 | if(!rst_n)
69 | fengshan<=1'b0;
70 | else if(!co/*&&cnt_3s==28'd150000000*/)
71 | fengshan<=1'b1;
72 | else fengshan<=1'b0;
73 | end
74 |
75 |
76 |
77 | always@(posedge clk or negedge rst_n)
78 | begin
79 | if(!rst_n)
80 | flag<=1'b0;
81 | else if(co_h)
82 | flag<=2'b01;
83 | else if(zhendong)
84 | flag<=2'b10;
85 | else if(in_key_en[2])
86 | flag<=2'b11;
87 | else flag<=flag;
88 | end
89 |
90 | always@(posedge clk or negedge rst_n)
91 | begin
92 | if(!rst_n)
93 | send_en<=1'b0;
94 | else if(co_h|(over_tx&cnt<4'd14))
95 | send_en<=1'b1;
96 | else if(zhendong|(over_tx&cnt<4'd2))
97 | send_en<=1'b1;
98 | else if(in_key_en[2]|(over_tx&cnt<4'd2))
99 | send_en<=1'b1;
100 | else send_en<=1'b0;
101 | end
102 |
103 |
104 | always@(*)
105 | begin
106 | case(flag)
107 | 0: ;
108 | 2'd1:
109 | begin
110 | case(cnt) //烟雾
111 | 4'd0:data_rx=8'b00000001; //I
112 | /*4'd1:data_rx=8'b00100000; //
113 | 4'd2:data_rx=8'b01001100; //L
114 | 4'd3:data_rx=8'b01101001; //i
115 | 4'd4:data_rx=8'b01101011; //k
116 | 4'd5:data_rx=8'b01100101; //e
117 | 4'd6:data_rx=8'b00100000; //
118 | 4'd7:data_rx=8'b01000110; //F
119 | 4'd8:data_rx=8'b01010000; //P
120 | 4'd9:data_rx=8'b01000111; //G
121 | 4'd10:data_rx=8'b01000001; //A */
122 | endcase
123 | end
124 | 2'd2:
125 | begin //震动
126 | case(cnt)
127 | 4'd0:data_rx=8'b00000010; //I
128 | /*4'd1:data_rx=8'b00100000; //
129 | 4'd2:data_rx=8'b01001100; //L
130 | 4'd3:data_rx=8'b01101001; //i
131 | 4'd4:data_rx=8'b01101011; //k
132 | 4'd5:data_rx=8'b01100101; //e
133 | 4'd6:data_rx=8'b00100000; //
134 | 4'd7:data_rx=8'b01010110; //V
135 | 4'd8:data_rx=8'b01100101; //e
136 | 4'd9:data_rx=8'b01110010; //r
137 | 4'd10:data_rx=8'b01101001; //i
138 | 4'd11:data_rx=8'b01101100; //l
139 | 4'd12:data_rx=8'b01101111; //o
140 | 4'd13:data_rx=8'b01100111; //g */
141 | endcase
142 | end
143 | 2'd3:
144 | begin //门铃
145 | case(cnt)
146 | 4'd0:data_rx=8'b00000011; //I
147 | /*4'd1:data_rx=8'b00100000; //
148 | 4'd2:data_rx=8'b01001100; //L
149 | 4'd3:data_rx=8'b01101001; //i
150 | 4'd4:data_rx=8'b01101011; //k
151 | 4'd5:data_rx=8'b01100101; //e
152 | 4'd6:data_rx=8'b00100000; //
153 | 4'd7:data_rx=8'b00110001; //1
154 | 4'd8:data_rx=8'b00110000; //0
155 | 4'd9:data_rx=8'b00110111; //7 */
156 | endcase
157 | end
158 | endcase
159 | end
160 | endmodule
--------------------------------------------------------------------------------
/bcd2.v:
--------------------------------------------------------------------------------
1 | module bcd2(input clk,
2 | input rst_n,
3 | input tran_en,
4 | input [15:0] data_in,
5 | output reg tran_done,
6 | output [15:0] bcd
7 |
8 | );
9 | parameter DATA_WIDTH = 16;
10 | parameter SHIFT_WIDTH = 5;
11 | parameter SHIFT_DEPTH = 16;
12 |
13 | //-------------------------------------------------------
14 | localparam IDLE = 3'b001;
15 | localparam SHIFT = 3'b010;
16 | localparam DONE = 3'b100;
17 |
18 | //-------------------------------------------------------
19 | reg [2:0] pre_state;
20 | reg [2:0] next_state;
21 | //
22 | reg [SHIFT_DEPTH-1:0] shift_cnt;
23 | //
24 | reg [DATA_WIDTH:0] data_reg;
25 | reg [3:0] thou_reg;
26 | reg [3:0] hund_reg;
27 | reg [3:0] tens_reg;
28 | reg [3:0] unit_reg;
29 | reg [3:0] thou_out;
30 | reg [3:0] hund_out;
31 | reg [3:0] tens_out;
32 | reg [3:0] unit_out;
33 | wire [3:0] thou_tmp;
34 | wire [3:0] hund_tmp;
35 | wire [3:0] tens_tmp;
36 | wire [3:0] unit_tmp;
37 |
38 | //-------------------------------------------------------
39 | //FSM step1
40 | always @(posedge clk or negedge rst_n)begin
41 | if(rst_n == 1'b0)begin
42 | pre_state <= IDLE;
43 | end
44 | else begin
45 | pre_state <= next_state;
46 | end
47 | end
48 |
49 | //FSM step2
50 | always @(*)begin
51 | case(pre_state)
52 | IDLE:begin
53 | if(tran_en == 1'b1)
54 | next_state = SHIFT;
55 | else
56 | next_state = IDLE;
57 | end
58 | SHIFT:begin
59 | if(shift_cnt == SHIFT_DEPTH + 1)
60 | next_state = DONE;
61 | else
62 | next_state = SHIFT;
63 | end
64 | DONE:begin
65 | next_state = IDLE;
66 | end
67 | default:next_state = IDLE;
68 | endcase
69 | end
70 |
71 | //FSM step3
72 | always @(posedge clk or negedge rst_n)begin
73 | if(rst_n == 1'b0)begin
74 | thou_reg <= 4'b0;
75 | hund_reg <= 4'b0;
76 | tens_reg <= 4'b0;
77 | unit_reg <= 4'b0;
78 | tran_done <= 1'b0;
79 | shift_cnt <= 'd0;
80 | data_reg <= 'd0;
81 | end
82 | else begin
83 | case(next_state)
84 | IDLE:begin
85 | thou_reg <= 4'b0;
86 | hund_reg <= 4'b0;
87 | tens_reg <= 4'b0;
88 | unit_reg <= 4'b0;
89 | tran_done <= 1'b0;
90 | shift_cnt <= 'd0;
91 | data_reg <= data_in;
92 | end
93 | SHIFT:begin
94 | if(shift_cnt == SHIFT_DEPTH + 1)
95 | shift_cnt <= 'd0;
96 | else begin
97 | shift_cnt <= shift_cnt + 1'b1;
98 | data_reg <= data_reg << 1;
99 | unit_reg <= {unit_tmp[2:0], data_reg[16]};
100 | tens_reg <= {tens_tmp[2:0], unit_tmp[3]};
101 | hund_reg <= {hund_tmp[2:0], tens_tmp[3]};
102 | thou_reg <= {thou_tmp[2:0], hund_tmp[3]};
103 | end
104 | end
105 | DONE:begin
106 | tran_done <= 1'b1;
107 | end
108 | default:begin
109 | thou_reg <= thou_reg;
110 | hund_reg <= hund_reg;
111 | tens_reg <= tens_reg;
112 | unit_reg <= unit_reg;
113 | tran_done <= tran_done;
114 | shift_cnt <= shift_cnt;
115 | end
116 | endcase
117 | end
118 | end
119 | //-------------------------------------------------------
120 | always @(posedge clk or negedge rst_n)begin
121 | if(rst_n == 1'b0)begin
122 | thou_out <= 'd0;
123 | hund_out <= 'd0;
124 | tens_out <= 'd0;
125 | unit_out <= 'd0;
126 | end
127 | else if(tran_done == 1'b1)begin
128 | thou_out <= thou_reg;
129 | hund_out <= hund_reg;
130 | tens_out <= tens_reg;
131 | unit_out <= unit_reg;
132 | end
133 | else begin
134 | thou_out <= thou_out;
135 | hund_out <= hund_out;
136 | tens_out <= tens_out;
137 | unit_out <= unit_out;
138 | end
139 | end
140 |
141 |
142 | //-------------------------------------------------------
143 | assign thou_tmp = (thou_reg > 4'd4)? (thou_reg + 2'd3) : thou_reg;
144 | assign hund_tmp = (hund_reg > 4'd4)? (hund_reg + 2'd3) : hund_reg;
145 | assign tens_tmp = (tens_reg > 4'd4)? (tens_reg + 2'd3) : tens_reg;
146 | assign unit_tmp = (unit_reg > 4'd4)? (unit_reg + 2'd3) : unit_reg;
147 |
148 | assign bcd = {thou_out,hund_out,tens_out,unit_out};
149 |
150 |
151 | endmodule
152 |
--------------------------------------------------------------------------------
/bin_bcd.v:
--------------------------------------------------------------------------------
1 | module bin_bcd(
2 | input clk,
3 | input rst_n,
4 | input tran_en,
5 | input [15:0] data_in,
6 | output reg tran_done,
7 | output [15:0] bcd
8 |
9 | );
10 | parameter DATA_WIDTH = 16;
11 | parameter SHIFT_WIDTH = 5;
12 | parameter SHIFT_DEPTH = 16;
13 |
14 | //-------------------------------------------------------
15 | localparam IDLE = 3'b001;
16 | localparam SHIFT = 3'b010;
17 | localparam DONE = 3'b100;
18 |
19 | //-------------------------------------------------------
20 | reg [2:0] pre_state;
21 | reg [2:0] next_state;
22 | //
23 | reg [SHIFT_DEPTH-1:0] shift_cnt;
24 | //
25 | reg [DATA_WIDTH:0] data_reg;
26 | reg [3:0] thou_reg;
27 | reg [3:0] hund_reg;
28 | reg [3:0] tens_reg;
29 | reg [3:0] unit_reg;
30 | reg [3:0] thou_out;
31 | reg [3:0] hund_out;
32 | reg [3:0] tens_out;
33 | reg [3:0] unit_out;
34 | wire [3:0] thou_tmp;
35 | wire [3:0] hund_tmp;
36 | wire [3:0] tens_tmp;
37 | wire [3:0] unit_tmp;
38 |
39 | //-------------------------------------------------------
40 | //FSM step1
41 | always @(posedge clk or negedge rst_n)begin
42 | if(rst_n == 1'b0)begin
43 | pre_state <= IDLE;
44 | end
45 | else begin
46 | pre_state <= next_state;
47 | end
48 | end
49 |
50 | //FSM step2
51 | always @(*)begin
52 | case(pre_state)
53 | IDLE:begin
54 | if(tran_en == 1'b1)
55 | next_state = SHIFT;
56 | else
57 | next_state = IDLE;
58 | end
59 | SHIFT:begin
60 | if(shift_cnt == SHIFT_DEPTH + 1)
61 | next_state = DONE;
62 | else
63 | next_state = SHIFT;
64 | end
65 | DONE:begin
66 | next_state = IDLE;
67 | end
68 | default:next_state = IDLE;
69 | endcase
70 | end
71 |
72 | //FSM step3
73 | always @(posedge clk or negedge rst_n)begin
74 | if(rst_n == 1'b0)begin
75 | thou_reg <= 4'b0;
76 | hund_reg <= 4'b0;
77 | tens_reg <= 4'b0;
78 | unit_reg <= 4'b0;
79 | tran_done <= 1'b0;
80 | shift_cnt <= 'd0;
81 | data_reg <= 'd0;
82 | end
83 | else begin
84 | case(next_state)
85 | IDLE:begin
86 | thou_reg <= 4'b0;
87 | hund_reg <= 4'b0;
88 | tens_reg <= 4'b0;
89 | unit_reg <= 4'b0;
90 | tran_done <= 1'b0;
91 | shift_cnt <= 'd0;
92 | data_reg <= data_in;
93 | end
94 | SHIFT:begin
95 | if(shift_cnt == SHIFT_DEPTH + 1)
96 | shift_cnt <= 'd0;
97 | else begin
98 | shift_cnt <= shift_cnt + 1'b1;
99 | data_reg <= data_reg << 1;
100 | unit_reg <= {unit_tmp[2:0], data_reg[16]};
101 | tens_reg <= {tens_tmp[2:0], unit_tmp[3]};
102 | hund_reg <= {hund_tmp[2:0], tens_tmp[3]};
103 | thou_reg <= {thou_tmp[2:0], hund_tmp[3]};
104 | end
105 | end
106 | DONE:begin
107 | tran_done <= 1'b1;
108 | end
109 | default:begin
110 | thou_reg <= thou_reg;
111 | hund_reg <= hund_reg;
112 | tens_reg <= tens_reg;
113 | unit_reg <= unit_reg;
114 | tran_done <= tran_done;
115 | shift_cnt <= shift_cnt;
116 | end
117 | endcase
118 | end
119 | end
120 | //-------------------------------------------------------
121 | always @(posedge clk or negedge rst_n)begin
122 | if(rst_n == 1'b0)begin
123 | thou_out <= 'd0;
124 | hund_out <= 'd0;
125 | tens_out <= 'd0;
126 | unit_out <= 'd0;
127 | end
128 | else if(tran_done == 1'b1)begin
129 | thou_out <= thou_reg;
130 | hund_out <= hund_reg;
131 | tens_out <= tens_reg;
132 | unit_out <= unit_reg;
133 | end
134 | else begin
135 | thou_out <= thou_out;
136 | hund_out <= hund_out;
137 | tens_out <= tens_out;
138 | unit_out <= unit_out;
139 | end
140 | end
141 |
142 |
143 | //-------------------------------------------------------
144 | assign thou_tmp = (thou_reg > 4'd4)? (thou_reg + 2'd3) : thou_reg;
145 | assign hund_tmp = (hund_reg > 4'd4)? (hund_reg + 2'd3) : hund_reg;
146 | assign tens_tmp = (tens_reg > 4'd4)? (tens_reg + 2'd3) : tens_reg;
147 | assign unit_tmp = (unit_reg > 4'd4)? (unit_reg + 2'd3) : unit_reg;
148 |
149 | assign bcd = {thou_out,hund_out,tens_out,unit_out};
150 |
151 |
152 | endmodule
--------------------------------------------------------------------------------
/GY25_RX.v:
--------------------------------------------------------------------------------
1 | module GY25_RX(clk,rst_n,rs232_rx,data_byte,rx_done,bps_cnt
2 | );
3 | input wire clk;
4 | input wire rst_n;
5 | input wire rs232_rx;
6 |
7 | output reg [7:0]data_byte;
8 | output reg rx_done;
9 | output reg [7:0]bps_cnt;
10 |
11 | wire neged;
12 | reg UART_state;
13 | reg [8:0] cnt;
14 | reg bps_clk;
15 | reg [2:0] r_date_byte[7:0];
16 | reg [7:0] tmp_date_byte;
17 | reg s0_rs232_rx;
18 | reg s1_rs232_rx;
19 | reg tmp0_rs232_rx;
20 | reg tmp1_rs232_rx;
21 | reg [2:0] start_bit;
22 | reg [2:0] end_bite;
23 |
24 | //同步寄存，消除亚稳态//////////////////////
25 | always @(posedge clk or negedge rst_n)
26 | begin
27 | if(!rst_n)
28 | begin
29 | s0_rs232_rx<=0;
30 | s1_rs232_rx<=0;
31 | end
32 | else
33 | begin
34 | s0_rs232_rx<=rs232_rx;
35 | s1_rs232_rx<=s0_rs232_rx;
36 | end
37 | end
38 | //检测下降沿/////////////////////////////////////
39 | always @(posedge clk or negedge rst_n)
40 | begin
41 | if(!rst_n)
42 | begin
43 | tmp0_rs232_rx<=0;
44 | tmp1_rs232_rx<=0;
45 | end
46 | else
47 | begin
48 | tmp0_rs232_rx<=s1_rs232_rx;
49 | tmp1_rs232_rx<=tmp0_rs232_rx;
50 | end
51 | end
52 | assign neged=!tmp0_rs232_rx & tmp1_rs232_rx;//检测下降沿/
53 | //串口状态////////////////////////////
54 | always @(posedge clk or negedge rst_n)
55 | begin
56 | if(!rst_n)
57 | UART_state<=0;
58 | else if(neged)
59 | UART_state<=1;
60 | else if(bps_cnt==159||((bps_cnt==12)&&(start_bit>2)))
61 | UART_state<=0;
62 | end
63 | /////////////////////////////////////////
64 | always @(posedge clk or negedge rst_n)
65 | begin
66 | if(!rst_n)
67 | cnt<=0;
68 | else if(UART_state) begin
69 | if(cnt==26)
70 | cnt<=0;
71 | else
72 | cnt<=cnt+1;
73 | end
74 | else
75 | cnt<=0;
76 | end
77 | //波特率时钟///////////////////////////////
78 | always @(posedge clk or negedge rst_n)
79 | begin
80 | if(!rst_n)
81 | bps_clk<=0;
82 | else if(cnt==1)
83 | bps_clk<=1;
84 | else
85 | bps_clk<=0;
86 | end
87 | //发送完成信号////////////////////////////
88 | always @(posedge clk or negedge rst_n)
89 | begin
90 | if(!rst_n)
91 | rx_done<=0;
92 | else if(bps_cnt==159)
93 | rx_done<=1;
94 | else
95 | rx_done<=0;
96 | end
97 | //波特率时钟计数器//////////////////////////
98 | always @(posedge clk or negedge rst_n)
99 | begin
100 | if(!rst_n)
101 | bps_cnt<=0;
102 | else if(bps_cnt==159||((bps_cnt==12)&&(start_bit>2)))
103 | bps_cnt<=0;
104 | else if(bps_clk)
105 | bps_cnt<=bps_cnt+1;
106 | end
107 |
108 | always @(posedge clk or negedge rst_n)
109 | begin
110 | if(!rst_n)
111 | begin
112 | start_bit<=3'b0;
113 | r_date_byte[0]<=3'b0;
114 | r_date_byte[1]<=3'b0;
115 | r_date_byte[2]<=3'b0;
116 | r_date_byte[3]<=3'b0;
117 | r_date_byte[4]<=3'b0;
118 | r_date_byte[5]<=3'b0;
119 | r_date_byte[6]<=3'b0;
120 | r_date_byte[7]<=3'b0;
121 | end_bite<=3'b0;
122 | end
123 | else if(bps_clk) begin
124 | case(bps_cnt)
125 | 1:begin
126 | start_bit<=3'b0;
127 | r_date_byte[0]<=3'b0;
128 | r_date_byte[1]<=3'b0;
129 | r_date_byte[2]<=3'b0;
130 | r_date_byte[3]<=3'b0;
131 | r_date_byte[4]<=3'b0;
132 | r_date_byte[5]<=3'b0;
133 | r_date_byte[6]<=3'b0;
134 | r_date_byte[7]<=3'b0;
135 | end_bite<=3'b0;
136 | end
137 | 6,7,8,9,10,11: start_bit<=start_bit+rs232_rx;
138 | 22,23,24,25,26,27: r_date_byte[0]<=r_date_byte[0]+rs232_rx;
139 | 38,39,40,41,42,43: r_date_byte[1]<=r_date_byte[1]+rs232_rx;
140 | 54,55,56,57,58,59: r_date_byte[2]<=r_date_byte[2]+rs232_rx;
141 | 70,71,72,73,74,75: r_date_byte[3]<=r_date_byte[3]+rs232_rx;
142 | 86,87,88,89,90,91: r_date_byte[4]<=r_date_byte[4]+rs232_rx;
143 | 102,103,104,105,106,107: r_date_byte[5]<=r_date_byte[5]+rs232_rx;
144 | 118,119,120,121,122,123: r_date_byte[6]<=r_date_byte[6]+rs232_rx;
145 | 134,135,136,137,138,139: r_date_byte[7]<=r_date_byte[7]+rs232_rx;
146 | 150,151,152,153,154,155: end_bite<=end_bite+rs232_rx;
147 | default: ;
148 | endcase
149 | end
150 | end
151 | always @(posedge clk or negedge rst_n)
152 | begin
153 | if(!rst_n)
154 | tmp_date_byte<=0;
155 | else if(bps_cnt==159)begin
156 | tmp_date_byte[0]<=r_date_byte[0][2];
157 | tmp_date_byte[1]<=r_date_byte[1][2];
158 | tmp_date_byte[2]<=r_date_byte[2][2];
159 | tmp_date_byte[3]<=r_date_byte[3][2];
160 | tmp_date_byte[4]<=r_date_byte[4][2];
161 | tmp_date_byte[5]<=r_date_byte[5][2];
162 | tmp_date_byte[6]<=r_date_byte[6][2];
163 | tmp_date_byte[7]<=r_date_byte[7][2];
164 | end
165 | else
166 | tmp_date_byte<=8'b0;
167 | end
168 | always @(posedge clk or negedge rst_n)
169 | begin
170 | if(!rst_n)
171 | data_byte<=0;
172 | else if(rx_done)
173 | data_byte<=tmp_date_byte;
174 | else
175 | data_byte<=data_byte;
176 |
177 | end
178 | endmodule
179 |
--------------------------------------------------------------------------------
/VGA.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:34:55 11/02/2019
7 | // Design Name:
8 | // Module Name: VGA
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module VGA(
22 | input clk,
23 | input rst_n,
24 | input [7:0] M,
25 | input pic_en,//控制是否进行特征识别
26 | input flag_addr,//表示边框xy比例检测成功，VGA可以进行计数
27 | input [15:0] flag_square_begin,//显示起点
28 | input [15:0] flag_square_end,//显示终点
29 | input [6:0] cnt_x,//特征边沿的x
30 | input [6:0] cnt_y,//特征边沿的y
31 |
32 | output VGA_HS,
33 | output VGA_VS,
34 | output reg [15:0] rom_addr16,
35 | output reg [7:0] RGB
36 | );
37 |
38 |
39 |
40 | //行参数
41 | parameter H_SP = 10'd96;//同步头脉冲(负极性)
42 | parameter H_BP = 10'd48;//显示后沿
43 | parameter H_FP = 10'd16;//显示前沿
44 | parameter H_DISP = 10'd640;//显示时序段
45 | parameter H_pixels = 10'd800;//行像素点
46 |
47 | //列参数
48 | parameter V_SP = 10'd2;//同步头脉冲(负极性)
49 | parameter V_BP = 10'd29;
50 | parameter V_FP = 10'd14;
51 | parameter V_DISP = 10'd480;
52 | parameter V_lines = 10'd525;//总行数
53 |
54 |
55 | //显示图片 高(H)宽(W)
56 | parameter H = 8'd200;
57 | parameter W = 8'd164;
58 |
59 | //图片起点
60 | parameter xpic = 8'd5;
61 | parameter ypic = 8'd5;
62 |
63 |
64 |
65 |
66 |
67 | reg VGA_clk;
68 | reg [9:0] h_cnt;//行计数
69 | reg [9:0] v_cnt;//场计数
70 |
71 | wire disp_valid;
72 |
73 |
74 | //分频
75 | always @(posedge clk or negedge rst_n)begin
76 | if(!rst_n)
77 | VGA_clk <= 1'b0;
78 | else
79 | VGA_clk <= ~VGA_clk;
80 | end
81 |
82 | //行同步信号发生器
83 | always @(posedge VGA_clk or negedge rst_n)begin
84 | if(!rst_n)
85 | h_cnt <= 10'b0;
86 | else begin
87 | if( h_cnt == H_pixels - 1'b1)
88 | h_cnt <= 10'b0;
89 | else
90 | h_cnt <= h_cnt + 1'b1;
91 | end
92 | end
93 |
94 | //场同步信号发生器
95 | always @(posedge VGA_clk or negedge rst_n)begin
96 | if(!rst_n)
97 | v_cnt <= 10'b0;
98 | else begin
99 | if(h_cnt == H_pixels - 1'b1)begin
100 | if( v_cnt == V_lines - 1'b1)
101 | v_cnt <= 10'b0;
102 | else
103 | v_cnt <= v_cnt + 1'b1;
104 | end
105 | end
106 | end
107 |
108 | //HS 和 VS
109 | assign VGA_VS = (v_cnt >= 0 && v_cnt < V_SP) ? 1'b0:1'b1;
110 | assign VGA_HS = (h_cnt >= 0 && h_cnt < H_SP) ? 1'b0:1'b1;
111 |
112 |
113 | assign disp_valid = (h_cnt >= (H_SP + H_BP + H_FP) && h_cnt <= H_pixels && v_cnt >= (V_SP + V_BP + V_FP) && v_cnt < V_lines)&&
114 | ((h_cnt - (H_SP + H_BP + H_FP)) > 0 && (h_cnt - (H_SP + H_BP + H_FP)) < (0 + W))&&
115 | ((v_cnt - (V_SP + V_BP + V_FP) ) > 0 && (v_cnt - (V_SP + V_BP + V_FP) ) < (0 + H)) ? 1'b1:1'b0;
116 |
117 |
118 |
119 | //时序电路,用来给rom_addr16寄存器赋值
120 | always@(posedge clk or negedge rst_n)begin
121 | if(!rst_n)
122 | rom_addr16 <= 16'd0;
123 | else if(disp_valid)
124 | rom_addr16 <= (h_cnt - 160) + (v_cnt - 45) * W;
125 | else
126 | rom_addr16 <= 16'd0;
127 | end
128 |
129 |
130 |
131 | reg [6:0] N;
132 | reg [6:0] n;
133 |
134 | always @(posedge VGA_clk or negedge rst_n)begin
135 | if(!rst_n)
136 | N <= 7'd0;
137 | else if( (N + 1'b1) > cnt_y - 2 )//减2,目的红绿灯下面背景黄线
138 | N <= 7'd0;
139 | else if(n == cnt_x )
140 | N <= N + 1'b1;
141 | else
142 | N <= N;
143 | end
144 |
145 | reg [6:0] f;
146 |
147 | always @(posedge VGA_clk or negedge rst_n)begin
148 | if(!rst_n)
149 | f <= 7'd0;
150 | else if(rom_addr16 >= flag_square_begin + N*200 && n == cnt_x && cnt_x >= 1'b1)
151 | f <= f + 1'b1;
152 | else
153 | f <= 7'd0;
154 | end
155 |
156 |
157 | //时序电路,用来给RGB寄存器赋值
158 | always @ (posedge VGA_clk or negedge rst_n) begin //每个时钟上升沿赋值
159 | if(!rst_n)begin
160 | n <= 7'd0;
161 | RGB <= 8'd0;
162 | end
163 | else if(!pic_en)
164 | RGB <= M;
165 |
166 | else if(n == cnt_x)
167 | n <= 7'd0;
168 | else begin
169 | if( disp_valid == 1'b1)
170 | begin
171 |
172 | case (f)
173 |
174 | 0: if(rom_addr16 >= flag_square_begin + N*200 && rom_addr16 <= flag_square_begin + (N+1)*cnt_x + N*80)
175 | begin
176 | RGB <= M;
177 | n <= n + 1;
178 | end
179 | else begin
180 | RGB <= 8'd0;
181 | n <= 1'b0;
182 | end
183 |
184 |
185 | N : if(rom_addr16 >= flag_square_begin + N*200 && rom_addr16 <= flag_square_begin + (N+1)*cnt_x + N*80)
186 | begin
187 | RGB <= M;
188 | n <= n + 1;
189 | end
190 | else begin
191 | RGB <= 8'd0;
192 | n <= 1'b0;
193 | end
194 |
195 | endcase
196 |
197 | end
198 | end
199 | end
200 |
201 | endmodule
202 |
203 |
--------------------------------------------------------------------------------
/zhuti.v:
--------------------------------------------------------------------------------
1 | module zhuti(
2 | input clk,
3 | input rst,
4 | input du_en,
5 | input a,
6 | input b,
7 | input [9:0]jiaodu, //GY_26传过来的角度，正北是0°，0-360度
8 |
9 | output reg [1:0]dianji,
10 | output [60:0]jishu,
11 | output wire[8:0]JD,
12 | output reg [8:0]baidu_JD,
13 | input [7:0]licheng
14 | );
15 | wire podge;
16 | reg [1:0]tmp_rx; //上升沿检测所用寄存器
17 | always@(posedge clk or negedge rst) //移位寄存器 检测下降沿
18 | begin
19 | if(!rst) tmp_rx<=2'b00;
20 | else
21 | begin
22 | tmp_rx[0]<=du_en;
23 | tmp_rx[1]<=tmp_rx[0];
24 | end
25 | end
26 | assign podge=tmp_rx[0]&~tmp_rx[1];
27 |
28 |
29 |
30 | reg wea;
31 | reg [6:0] addra;
32 | wire [92:0] douta;
33 |
34 |
35 | daohang_ram u_daohang_ram(
36 | .clka(clka),
37 | .rsta(!rsta),
38 | .ocea(1),
39 | .addra(addra), //[2:0]
40 | .doa(douta) //[92:0]
41 | );
42 |
43 |
44 | reg [92:0]addra1;
45 | always@(posedge clk or negedge rst) //地址打一拍
46 | begin
47 | if(!rst) begin addra1<=1'b0; end
48 | else
49 | begin
50 | addra1<=addra;
51 | end
52 | end
53 |
54 | reg flag; //检测输出的地址有没有变化，没有变化是1 有变化是0 flag
55 | always@(*)
56 | begin
57 | if(addra1==addra)
58 | flag<=1'b1;
59 | else flag<=1'b0;
60 | end
61 |
62 | /*wire nedge;
63 | reg [1:0]tmp_rx1; //flag下降沿检测所用寄存器
64 | always@(posedge clk or negedge rst) //移位寄存器 检测下降沿
65 | begin
66 | if(!rst) tmp_rx1<=2'b11;
67 | else
68 | begin
69 | tmp_rx1[0]<=flag;
70 | tmp_rx1[1]<=tmp_rx1[0];
71 | end
72 | end
73 | assign nedge=~tmp_rx1[0]&tmp_rx1[1];*/
74 |
75 |
76 | assign JD=jiaodu[9:8]*100+jiaodu[7:4]*10+jiaodu[3:0];
77 |
78 | //对百度传回来的角度进行翻译 枚举值，返回值在0-11之间的一个值，共12个枚举值，以30度递进，即每个值代表角度范围为30度；其中返回"0"代表345度到15度，以此类推，返回"11"代表315度到345度"；分别代表的含义是：0-[345°-15°]；1-[15°-45°]；2-[45°-75°]；3-[75°-105°]；4-[105°-135°]；5-[135°-165°]；6-[165°-195°]；7-[195°-225°]；8-[225°-255°]；9-[255°-285°]；10-[285°-315°]；11-[315°-345°]
79 | //reg [8:0]baidu_JD;
80 | always@(posedge clk)
81 | begin
82 | if(douta[84])
83 | case(douta[83:80])
84 | 4'd0: baidu_JD<=1'b0;
85 | 4'd1: baidu_JD<=9'd30;
86 | 4'd2: baidu_JD<=9'd60;
87 | 4'd3: baidu_JD<=9'd90;
88 | 4'd4: baidu_JD<=9'd120;
89 | 4'd5: baidu_JD<=9'd150;
90 | 4'd6: baidu_JD<=9'd180;
91 | 4'd7: baidu_JD<=9'd195;
92 | 4'd8: baidu_JD<=9'd240;
93 | 4'd9: baidu_JD<=9'd270;
94 | 4'd10: baidu_JD<=9'd300;
95 | 4'd11: baidu_JD<=9'd330;
96 | endcase
97 | end
98 | reg data_a1;
99 | reg data_a2;
100 | always @(posedge clk or negedge rst)
101 | begin
102 | if(!rst)
103 | begin
104 | data_a1 <= 1'b0;
105 | data_a2 <= 1'b0;
106 | end
107 | else
108 | begin
109 | data_a1 <= a;
110 | data_a2 <= data_a1;
111 | end
112 | end
113 | assign double_a = data_a1 ^ data_a2;//双边沿 编码器1A相
114 |
115 |
116 |
117 | reg data_b1;
118 | reg data_b2;
119 | always @(posedge clk or negedge rst)
120 | begin
121 | if(!rst)
122 | begin
123 | data_b1 <= 1'b0;
124 | data_b2 <= 1'b0;
125 | end
126 | else
127 | begin
128 | data_b1 <= b;
129 | data_b2 <= data_b1;
130 | end
131 | end
132 | assign double_b = data_b1 ^ data_b2;//双边沿 编码器1B相
133 |
134 |
135 |
136 |
137 | reg clk1;
138 | reg data_clk1;
139 | reg data_clk2;
140 | always @ (posedge clk,negedge rst)
141 | begin
142 | if(!rst)
143 | begin data_clk1 <= 1'b0; data_clk2 <= 1'b0; end
144 | else
145 | begin data_clk1 <= clk1; data_clk2 <= data_clk1;end
146 | end
147 | assign raising_clk1 = data_clk1 & (~data_clk2);//上升沿
148 |
149 |
150 | reg [27:0]cnt1;
151 | reg [60:0]cnt2;
152 | always@(posedge clk or negedge rst)
153 | begin
154 | if(!rst)
155 | begin
156 | cnt1 <= 28'd0;
157 | cnt2 <= 61'd0;
158 | end
159 | else if(flag==1'b0)
160 | cnt2<=1'b0;
161 | else if(double_a==1|double_b==1)
162 | cnt1 <= cnt1 + 1'b1;
163 | else if(raising_clk1 == 1 /*&& flag *//*&& JD==baidu_JD */)
164 | begin
165 | cnt1 <= 0;
166 | cnt2 <= cnt2 + 1'b1;
167 | end
168 | else
169 | begin
170 | cnt1 <= cnt1;
171 | cnt2 <= cnt2;
172 | end
173 | end
174 | always@(posedge clk or negedge rst)//2,632,500
175 | if(!rst)
176 | begin
177 | clk1 <= 0;
178 | end
179 | else if(cnt1 == 38'd195)
180 | begin
181 | clk1 <= 1;
182 | end
183 | else
184 | clk1 <= 0;
185 | assign jishu = ((((cnt2*13*5)*13)*24*41)>>12)/8;
186 |
187 | always@(posedge clk or negedge rst)
188 | begin
189 | if(!rst)
190 | dianji<=2'b00;
191 | else begin
192 | if(podge)
193 | begin wea<=1'b0; addra<=1'b0;end
194 | if(douta[84]&&du_en)//需要转弯 1001右转 0110左转 1010直走
195 | begin
196 | if(JD==baidu_JD) begin //小车的角度等于需要转的角度
197 | dianji<=2'b11;
198 | if(licheng==douta[92:85]&flag)
199 | addra<=addra+1'b1;
200 | else addra<=addra;
201 | end
202 | else if (JDbaidu_JD) //小车现在的角度大于需要转到的角度 左转
205 | dianji<=2'b01;
206 |
207 | end
208 | else
209 | dianji <= 2'b00;
210 | end
211 | end
212 |
213 |
214 |
215 | endmodule
216 |
--------------------------------------------------------------------------------
/bizhang.v:
--------------------------------------------------------------------------------
1 | module bizhang(clk,rst,hq,hz,jiaodu,dianji2,led7,led6,led5,led4,/*led3,led2,*/jiaodu1,flag1
2 | );
3 | input clk;
4 | input rst;
5 | input [9:0]hq;
6 | input [9:0]hz;
7 | input [9:0]jiaodu;
8 | output [9:0]jiaodu1;
9 | output reg[1:0]dianji2;
10 | output reg led7;
11 | output reg led6;
12 | output reg led5;
13 | output reg led4;
14 | output flag1;
15 | /*output reg led3;
16 | output reg led2;*/
17 | reg [3:0]state;
18 | reg [9:0]jiaodu1;
19 | parameter safe= 60;
20 | wire [9:0]JD;
21 | assign JD=jiaodu[9:8]*100+jiaodu[7:4]*10+jiaodu[3:0];
22 |
23 | /*reg data_in_d1;
24 | reg data_in_d2;
25 |
26 | always @ (posedge clk,negedge rst)
27 | begin
28 | if(!rst)
29 | begin data_in_d1 <= 1'b0; data_in_d2 <= 1'b0; end
30 | else
31 | begin data_in_d1 <= flag; data_in_d2 <= data_in_d1;end
32 | end
33 | assign raising_flag = data_in_d1 & (~data_in_d2);//上升沿*/
34 | /*reg [30:0]cnt;
35 | always@(posedge clk or negedge rst)
36 | if(!rst)
37 | cnt <= 31'd0;
38 | else if(cnt == 30'd250_000_000)
39 | cnt <= 31'd0;
40 | else
41 | cnt <= cnt;
42 | reg [30:0]cnt2;
43 | always@(posedge clk or negedge rst)
44 | if(!rst)
45 | cnt2 <= 31'd0;
46 | else if(cnt == 30'd250_000_000&&(JD==jiaodu1 + 90))
47 | cnt2 <= cnt2 + 1'b1;
48 | else
49 | cnt2 <= cnt2;*/
50 |
51 | reg [30:0]cnt1;
52 | reg [30:0]cnt3;
53 | always@(posedge clk or negedge rst)
54 | if(!rst)
55 | begin
56 | cnt1 <= 31'd0;
57 | cnt3 <= 31'd0;
58 | end
59 | else if(cnt3 == 30'd50_000_000)
60 | begin
61 | cnt1 <= cnt1 + 1'b1;
62 | cnt3 <= 31'd0;
63 | end
64 | else
65 | begin
66 | cnt1 <= cnt1;
67 | cnt3 <= cnt3 + 1'b1;
68 | end
69 |
70 |
71 | always@(posedge clk or negedge rst)
72 | if(!rst)
73 | jiaodu1 <= 10'd0;
74 | else if(cnt1 == 1)
75 | jiaodu1 <= JD;
76 | else
77 | jiaodu1 <= jiaodu1;
78 | always@(posedge clk or negedge rst)
79 | if(!rst)
80 | begin
81 | led7 <= 1'b0;
82 | led6 <= 1'b0;
83 | led5 <= 1'b0;
84 | led4 <= 1'b0;
85 | // led3 <= 1'b0;
86 | // led2 <= 1'b0;
87 | end
88 | else if(state == 4'd0)
89 | led7 <= 1;
90 | else if(state == 4'd1)
91 | led6 <= 1;
92 | else if(state == 4'd2)
93 | led5 <= 1;
94 | else if(state == 4'd3)
95 | led4 <= 1;
96 | // else if(state == 4'd4)
97 | // led3 <= 1;
98 | //else if(state == 4'd5)
99 | //led2 <= 1;
100 | else
101 | begin
102 | led7 <= led7;
103 | led6 <= led6;
104 | led5 <= led5;
105 | led4 <= led4;
106 | //led3 <= led3;
107 | // led2 <= led2;
108 | end
109 |
110 |
111 | /*reg [30:0]cnt5;
112 | /*always@(posedge clk or negedge rst)
113 | if(!rst)
114 | begin
115 | cnt4 <= 31'd0;
116 | cnt5 <= 31'd0;
117 | end
118 | else if((cnt5 == 30'd50_000_000) && (state == 4'd2))
119 | begin
120 | cnt4 <= cnt4 + 1'b1;
121 | cnt5 <= 31'd0;
122 | end
123 | else
124 | begin
125 | cnt4 <= cnt4;
126 | cnt5 <= cnt5 + 1'b1;
127 | end*/
128 |
129 | reg flag1;
130 | always@(posedge clk or negedge rst)
131 | if(!rst)
132 | begin
133 | dianji2 <= 2'b00;
134 | state <= 4'd0;
135 | flag1 <= 0;
136 | end
137 | else
138 | if(hq != 0)
139 | begin
140 | case(state)
141 | 0: if(hq > 50)
142 | begin
143 | dianji2 <= 2'b11;
144 | state <= 4'd0;
145 | end
146 | else
147 | begin
148 | dianji2 <= 2'b10;
149 | state <= 4'd1;
150 | flag1 <= 1;
151 | end
152 | 1: if(JD==jiaodu1 + 70)
153 | begin
154 | dianji2 <= 2'b11;
155 | state <= 4'd2;
156 | end
157 | else
158 | begin
159 | if(JD < jiaodu1 + 70)
160 | begin
161 | dianji2 <= 2'b10;
162 | state <= 4'd1;
163 | end
164 | else if(JD > jiaodu1 + 70)
165 | begin
166 | dianji2 <= 2'b01;
167 | state <= 4'd1;
168 | end
169 | end
170 | 2: if(hz > 80)
171 | begin
172 | dianji2 <= 2'b01;
173 | state <= 4'd3;
174 | flag1 <= 0;
175 | end
176 | else
177 | begin
178 | dianji2 <= 2'b11;
179 | state <= 4'd2;
180 | end
181 | 3: if(JD==jiaodu1)
182 | begin
183 | dianji2 <= 2'b11;
184 | state <= 4'd4;
185 | end
186 | else
187 | begin
188 | if(JD < jiaodu1 )
189 | begin
190 | dianji2 <= 2'b10;
191 | state <= 4'd3;
192 | end
193 | else if(JD > jiaodu1 )
194 | begin
195 | dianji2 <= 2'b01;
196 | state <= 4'd3;
197 | end
198 | end
199 | 4: if(hz > 80)
200 | begin
201 | dianji2 <= 2'b01;
202 | state <= 4'd5;
203 | end
204 | else
205 | begin
206 | dianji2 <= 2'b11;
207 | state <= 4'd4;
208 | end
209 | 5: if(JD == jiaodu1 - 70 )
210 | begin
211 | dianji2 <= 2'b11;
212 | state <= 4'd6;
213 | end
214 | else
215 | begin
216 | if(JD < jiaodu1 )
217 | begin
218 | dianji2 <= 2'b10;
219 | state <= 4'd5;
220 | end
221 | else if(JD > jiaodu1 )
222 | begin
223 | dianji2 <= 2'b01;
224 | state <= 4'd5;
225 | end
226 | end
227 | 6: begin
228 | state <= state;
229 | dianji2 <= 2'b00;
230 | end
231 |
232 | endcase
233 | end
234 | else
235 | dianji2 <= 2'b00;
236 |
237 |
238 |
239 | endmodule
240 |
--------------------------------------------------------------------------------
/xinlv_rx.v:
--------------------------------------------------------------------------------
1 | module xinlv_rx(
2 | input clk,
3 | input rst_n,
4 | input [7:0] data_rx,
5 | input rx_int,//当uart_rx模块接收完对方的数据后，传给uart_tx,此为标志位，标志uart_tx要开始工作
6 |
7 | output reg [7:0] xinlv//
8 | );
9 |
10 |
11 | //-------------------------------------------------------
12 | //每个8位数据接收完整的标志
13 | reg [1:0] rx_int_r;
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) begin
16 | rx_int_r[0] <= 1'b0;
17 | rx_int_r[1] <= 1'b0;
18 | end
19 | else begin
20 | rx_int_r[0] <= rx_int;
21 | rx_int_r[1] <= rx_int_r[0];
22 | end
23 | end
24 |
25 | wire nege_edge = rx_int_r[1] & ~rx_int_r[0];//下降沿
26 |
27 |
28 | //---------------------------------------------------
29 | reg [7:0] data_rx_r;//用来接收传过来的data_rx
30 | //将rx接来的数据存下来
31 | always@(posedge clk or negedge rst_n)begin
32 | if(!rst_n) begin
33 | data_rx_r <= 8'd0;
34 | end
35 | else if(nege_edge)begin
36 | data_rx_r <= data_rx;
37 | end
38 | end
39 |
40 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
41 | // //
42 | // 检测分段距离 //
43 | // //
44 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
45 |
46 | parameter length = 4; //更方便地更改状态长度
47 |
48 | parameter [length-1 : 0] //one-hot code
49 | S_IDLE = 11'b0001,
50 | S_State1 = 11'b0010,
51 | S_State2 = 11'b0100,
52 | S_State3 = 11'b1000;
53 |
54 | reg [length-1 : 0] c_state;
55 | reg [length-1 : 0] n_state;
56 | //三段式状态机
57 | always @(posedge clk or negedge rst_n) begin
58 | if (!rst_n) begin
59 | c_state <= S_IDLE; // reset低电平复位
60 | end
61 | else begin
62 | c_state <= n_state; //next state logic
63 | end
64 | end
65 |
66 | always @(*) begin //state register
67 | case(c_state)
68 | S_IDLE :
69 | if (data_rx_r == 8'h42 && nege_edge)//B
70 | n_state = S_State1;
71 | else
72 | n_state = S_IDLE;
73 | S_State1 :
74 | if (data_rx_r == 8'h50 && nege_edge)//P
75 | n_state = S_State2;
76 | else
77 | n_state = S_State1;
78 | S_State2 :
79 | if (data_rx_r == 8'h4d && nege_edge)//M
80 | n_state = S_State3;
81 | else
82 | n_state = S_State2;
83 | S_State3 :
84 | if (data_rx_r && nege_edge)
85 | n_state = S_IDLE;
86 | else
87 | n_state = S_IDLE;
88 | default :
89 | n_state = S_IDLE;
90 | endcase
91 | end
92 |
93 |
94 | reg detected_o;
95 | //状态机输出output logic
96 | always @ (posedge clk or negedge rst_n) begin
97 | if(!rst_n) begin
98 | detected_o <= 1'b0;
99 | end
100 | else if( c_state == S_State3) begin
101 | detected_o <= 1'b1;
102 | end
103 | else begin
104 | detected_o <= 1'b0;
105 | end
106 | end
107 |
108 |
109 | ///检测到上升沿信号后持续输出高电平
110 | reg [5:0] num; //包传到哪个数据了
111 | reg start_reg;
112 | reg timeout;
113 | always@(posedge clk)
114 | start_reg <= detected_o;
115 |
116 | always@(posedge clk or negedge rst_n) begin
117 | if (!rst_n)
118 | timeout <= 0;
119 | else if(start_reg == 0 && detected_o ==1)//检测上升沿的
120 | timeout <= 1;
121 | else
122 | timeout <= timeout;
123 | end
124 |
125 |
126 |
127 | reg [7:0] data_pickup_r;//用来提取接收传过来的data_rx
128 | //将rx接来的数据存下来
129 | always@(posedge clk or negedge rst_n)begin
130 | if(!rst_n) begin
131 | data_pickup_r <= 8'd0;
132 | end
133 | else if(timeout) begin
134 | data_pickup_r <= data_rx_r; //此时已经是传完$GPRMC，后面传的均为数据
135 | end
136 | end
137 |
138 |
139 | //-------------------------------------------------------
140 | //判断包头，确定开始，以及识别号
141 | always@(posedge clk or negedge rst_n)
142 | begin
143 | if(!rst_n)
144 | num <= 4'd0;
145 | else if(num == 3)
146 | num <= 0;
147 | else if( start_reg == 0 && detected_o ==1 )
148 | num <= 0;
149 | else if( (timeout && nege_edge) || (timeout && start_reg))
150 | num <= num + 1'b1;
151 | else
152 | num <= num;
153 | end
154 |
155 |
156 | reg [15:0] xinlv_ascii;
157 |
158 | always@(posedge clk or negedge rst_n)begin
159 | if(!rst_n)
160 | xinlv_ascii <= 16'b0000_0000_1111_1111;
161 | else if(nege_edge && data_pickup_r >= 8'h30 && data_pickup_r <= 8'h39)begin
162 | case(num)
163 | 4'd1: xinlv_ascii[15:8] <= data_pickup_r;
164 | 4'd2: xinlv_ascii[7:0] <= data_pickup_r;
165 | default:;
166 | endcase
167 | end
168 | end
169 |
170 |
171 | reg [5:0] cnt;
172 | //打50拍
173 | always@(posedge clk or negedge rst_n)
174 | begin
175 | if(!rst_n)
176 | cnt <= 6'b0;
177 | else if(num == 1)
178 | cnt <= 6'b0;
179 | else if(cnt == 51)
180 | cnt <= cnt;
181 | else if(num == 2)
182 | cnt <= cnt + 1;
183 | else
184 | cnt <= 6'b0;
185 | end
186 |
187 | wire flag_distance;
188 | //取红外距离值使能
189 | assign flag_distance = (cnt == 50)?1:0;
190 |
191 | reg [7:0] xinlv_10jinzhi;
192 |
193 | always@(posedge clk or negedge rst_n)begin
194 | if(!rst_n)
195 | xinlv_10jinzhi <= 8'b0;
196 | else if(num == 3)
197 | xinlv_10jinzhi <= xinlv_ascii[11:8]*10 + xinlv_ascii[3:0];
198 | else
199 | xinlv_10jinzhi <= xinlv_10jinzhi;
200 | end
201 |
202 |
203 | always@(posedge clk or negedge rst_n)begin
204 | if(!rst_n)
205 | xinlv <= 8'b0;
206 | else if( xinlv_10jinzhi >= 60 && xinlv_10jinzhi <= 90)
207 | xinlv <= xinlv_10jinzhi;
208 | else
209 | xinlv <= xinlv;
210 | end
211 |
212 | endmodule
213 |
214 |
--------------------------------------------------------------------------------
/top_surf_net.v:
--------------------------------------------------------------------------------
1 | module top_surf_net(
2 | input clk_24m,
3 | input rst_n,
4 | input mess_phone_number_prepared_enable,//发送使能，连接按键
5 | input data_rx,
6 |
7 | output gsm_tx,//输出给sim900a信号
8 |
9 |
10 | input du_en,
11 | input a,
12 | input b,//1
13 | input flag,
14 | input data_rx_jiaodu,
15 |
16 | output [6:0] smg_duan,
17 | output [3:0] smg_wei,
18 | output dp,
19 | output RX232,
20 | output [1:0] dianji,
21 | output [8:0] baidu_JD
22 |
23 |
24 |
25 |
26 |
27 | );
28 |
29 | wire emergency_contact_1 = 1;//紧急联系人1
30 | wire emergency_contact_2 = 0;
31 | wire emergency_contact_3 = 0;
32 | wire bps_sig;
33 | wire cnt_start;
34 | wire rx_int;
35 | wire [7:0] data1;
36 | wire [47:0] ymr_out;
37 | wire [47:0] time_out;
38 | wire clk_25m;
39 | wire clk_50m;
40 | wire clk_72m;
41 |
42 |
43 |
44 |
45 | reg [87:0] calling_number_end;
46 | reg [2:0] out_message_or_calling_en_or_receive;//选择输出，011是发短信功能，10是打电话功能，11是接电话功能
47 |
48 | always@(posedge clk_50m )begin
49 | case ({0,emergency_contact_1,emergency_contact_2,emergency_contact_3})
50 | 4'b1000:calling_number_end<= 88'h0;
51 | 4'b0100:calling_number_end<= 88'h34_38_32_31_37_36_32_38_33_37_31;//程宁勃
52 | 4'b0010:calling_number_end<= 88'h30_36_34_38_34_33_31_39_36_37_31;//刘仰猛;
53 | 4'b0001:calling_number_end<= 88'h37_39_38_38_37_38_37_38_32_33_31;//张胜亭;
54 | default:calling_number_end<=calling_number_end;
55 | endcase
56 | end
57 |
58 | reg tx_enable;
59 | reg [7:0] tx_data;
60 | wire bps_sig_tx;
61 | wire tx_done;
62 | wire tx_enable1;
63 | wire tx_enable2;
64 | wire tx_enable3;
65 | wire tx_enable4;
66 | wire [7:0] tx_data1;
67 | wire bps_sig_ring;
68 | wire cnt_start_ring;
69 |
70 |
71 |
72 |
73 | PLL_50M u_PLL_50M (
74 | .refclk(clk_24m),
75 | .clk0_out(clk_72m),
76 | .clk1_out(clk_50m),
77 | .clk2_out(clk_25m)
78 | );
79 |
80 | uart_receive u1_uart_receive (
81 | .clk(clk_50m),
82 | .rst_n(rst_n),
83 | .clk_bps(bps_sig),
84 | .data_rx(data_rx),
85 | .rx_int(rx_int),
86 | .data_tx(data1),
87 | .bps_start(cnt_start)
88 | );
89 |
90 | uart_bps u11_uart_bps (
91 | .clk(clk_50m),
92 | .rst_n(rst_n),
93 | .cnt_start(cnt_start),
94 | .bps_sig(bps_sig)
95 | );
96 |
97 | pick_up_rx u2_pick_up_rx (
98 | .clk(clk_50m),
99 | .rst_n(rst_n),
100 | .data_rx(data1),
101 | .rx_int(rx_int),
102 | .data_rx_end(data_rx_end),
103 | .time_out(time_out),
104 | .ymr_out(ymr_out)
105 | );
106 |
107 | uart_bps mess_u1_uart_bps (
108 | .clk(clk_50m),
109 | .rst_n(rst_n),
110 | .cnt_start(cnt_start_ring),
111 | .bps_sig(bps_sig_ring)
112 | );
113 |
114 | //访问网址
115 | surf_internet mess_u4_surf_internet (
116 | .tx_enable(tx_enable1),
117 | .tx_data(tx_data1),
118 | .clk(clk_50m),
119 | .rst(rst_n),
120 | .tx_done(tx_done),
121 | .mess_phone_number_prepared_enable(mess_phone_number_prepared_enable) //上网发送使能
122 | );
123 |
124 | always@(posedge clk_50m ) begin
125 | if(mess_phone_number_prepared_enable)
126 | out_message_or_calling_en_or_receive <= 3'b011;
127 | else
128 | out_message_or_calling_en_or_receive <= out_message_or_calling_en_or_receive;
129 | end
130 |
131 |
132 |
133 | always@(posedge clk_50m )
134 | begin
135 | case(out_message_or_calling_en_or_receive)
136 | 3'b011: begin
137 | tx_data <= tx_data1;
138 | tx_enable <= tx_enable1;
139 | end
140 | default:;
141 | endcase
142 | end
143 |
144 | uart_bps_mess u2_uart_bps_mess (
145 | .clk(clk_50m),
146 | .rst_n(rst_n),
147 | .bps_sig(bps_sig_tx),
148 | .cnt_start(tx_enable)
149 | );
150 |
151 | uart_sentdata_mess u3_uart_sentdata_mess (
152 | .clk(clk_50m),
153 | .rst(rst_n),
154 | .bps_sig(bps_sig_tx),
155 | .tx_data(tx_data),
156 | .tx(gsm_tx),
157 | .tx_enable(tx_enable),
158 | .tx_done(tx_done)
159 | );
160 |
161 | wire [92:0] data_rx_end_internet;
162 | wire flag_en_1;
163 | wire [2:0] addr_daohang_data;
164 |
165 |
166 | //read internet data
167 | top_rx_surf u_top_rx_surf (
168 | .clk(clk_50m),
169 | .rst_n(rst_n),
170 | .data_rx(data_rx),
171 | .flag_en_1(flag_en_1),//ram写使能
172 | .addr_daohang_data(addr_daohang_data),//ram写地址
173 | .data_rx_end_internet(data_rx_end_internet)//ram写数据
174 | );
175 |
176 |
177 | wire [2:0] addr_daohang;
178 | wire [92:0] dout_daohang;
179 |
180 | reg [3:0] cnt_flag_en_1;
181 |
182 | always @(posedge clk_50m or negedge rst_n)
183 | begin
184 | if(!rst_n)
185 | cnt_flag_en_1 <= 1'b0;
186 | else if(cnt_flag_en_1 >= 7)
187 | cnt_flag_en_1 <= cnt_flag_en_1;
188 | else if(flag_en_1)
189 | cnt_flag_en_1 <= cnt_flag_en_1 + 1'b1;
190 | else
191 | cnt_flag_en_1 <= cnt_flag_en_1;
192 | end
193 |
194 | reg [26:0] cnt_3s;
195 |
196 | always @(posedge clk_24m or negedge rst_n)
197 | begin
198 | if(!rst_n)
199 | cnt_3s <= 27'b0;
200 | else if(cnt_3s == 27'd7200_0000 - 1)
201 | cnt_3s <= cnt_3s;
202 | else if(cnt_flag_en_1 == 7)
203 | cnt_3s <= cnt_3s + 1;
204 | else
205 | cnt_3s <= 27'b0;
206 | end
207 |
208 | assign read_en = (cnt_3s == 27'd7200_0000 - 1)?1:0;
209 |
210 |
211 |
212 | //导航RAM
213 | ram_daohang_data u_ram_daohang_data (
214 | //write
215 | .clka(clk_50m),
216 | .cea(flag_en_1),
217 | .addra(addr_daohang_data),
218 | .dia(data_rx_end_internet),
219 | //read
220 | .clkb(clk_50m),
221 | .rstb(!rst_n),
222 | .addrb(addr_daohang),
223 | .dob(dout_daohang)
224 | );
225 |
226 |
227 |
228 |
229 | top2 u_daohang(
230 | .clk_24m(clk_24m),
231 | .rst(rst_n),
232 | .du_en(du_en),
233 | .a(a),
234 | .b(b),//1
235 | .flag(flag),
236 | .data_rx_jiaodu(data_rx_jiaodu),
237 | .smg_duan(smg_duan),
238 | .smg_wei(smg_wei),
239 | .dp(dp),
240 | .RX232(RX232),
241 | .dianji(dianji),
242 | .baidu_JD(baidu_JD),
243 | .addra(addr_daohang),
244 | .douta(dout_daohang)
245 | );
246 |
247 |
248 |
249 |
250 |
251 | endmodule
252 |
--------------------------------------------------------------------------------
/calling.v:
--------------------------------------------------------------------------------
1 | module calling(
2 |
3 | input clk,rst,
4 | input tx_done, //uart结束使能,该输入只维持一个时钟周期
5 | input calling_sent_enable_1, //一个段时间的高电平（源自 点击确认键）
6 | input calling_sent_enable_2,
7 |
8 | output reg tx_enable,
9 | output reg [7:0] tx_data
10 | );
11 |
12 | wire [87:0] calling_number_cheng = 88'h34_38_32_31_37_36_32_38_33_37_31;//程宁勃
13 | wire [87:0] calling_number_zhi = 88'h39_32_33_36_35_38_31_39_35_35_31;//支梦巡
14 | reg [87:0] calling_number;
15 |
16 | always @(*)
17 | if(calling_sent_enable_1 == 1)
18 | calling_number <= calling_number_cheng;
19 | else if(calling_sent_enable_2 == 1)
20 | calling_number <= calling_number_zhi;
21 | else
22 | calling_number <= calling_number_cheng;
23 |
24 |
25 | reg [31:0] AT;//AT命令寄存器；
26 | reg [5:0] num;
27 |
28 | reg [47:0] ATE1; //设置回显，即模块将收到的指令完整的返回给发送给设备，方便调试
29 | reg [135:0] ATD; //ATD+"phone_number"+;
30 | reg [39:0] ATH; //挂断电话
31 | reg [87:0] COLP;
32 |
33 | reg [87:0] phone_number_buf;
34 | //手机号的处理
35 | always@(posedge clk or negedge rst)
36 | if(!rst) begin
37 | phone_number_buf <= 0 ;
38 | end
39 | else begin
40 | phone_number_buf <= calling_number ;
41 | end
42 |
43 | //短发送使能信号的处理 (延时了一个时钟周期，并且获得了两个系统时钟周期的高电平使能信叿)
44 | reg mess_phone_number_prepared_enable_r1 ;
45 | reg mess_phone_number_prepared_enable_r2 ;
46 | reg mess_phone_number_prepared_enable_r3 ;
47 | always@(posedge clk or negedge rst)
48 | if(!rst) begin
49 | mess_phone_number_prepared_enable_r1 <= 0 ;
50 | mess_phone_number_prepared_enable_r2 <= 0 ;
51 | mess_phone_number_prepared_enable_r3 <= 0 ;
52 | end
53 | else begin
54 | mess_phone_number_prepared_enable_r1 <= (calling_sent_enable_1 || calling_sent_enable_2) ;
55 | mess_phone_number_prepared_enable_r2 <= mess_phone_number_prepared_enable_r1 ;
56 | mess_phone_number_prepared_enable_r3 <= mess_phone_number_prepared_enable_r2 ;
57 | end
58 | wire mess_phone_number_prepared_enable_r ;
59 | assign mess_phone_number_prepared_enable_r = mess_phone_number_prepared_enable_r2 | mess_phone_number_prepared_enable_r3 ;
60 |
61 | reg calling_sent_enable;
62 | always@(posedge clk or negedge rst)
63 | if(!rst)
64 | calling_sent_enable <= 0 ;
65 | else
66 | calling_sent_enable <= mess_phone_number_prepared_enable_r ;
67 |
68 | reg message_sent_enable_r1;
69 | reg message_sent_enable_r2;
70 | wire message_sent_enable_r;
71 | assign message_sent_enable_r = message_sent_enable_r1 & ~message_sent_enable_r2 ;
72 | always@(posedge clk or negedge rst)
73 | if(!rst) begin
74 | message_sent_enable_r1 <= 0;
75 | message_sent_enable_r2 <= 0;
76 | end
77 | else begin
78 | message_sent_enable_r1 <= calling_sent_enable;
79 | message_sent_enable_r2 <= message_sent_enable_r1 ;
80 | end
81 |
82 | parameter T1s = 27'd90_000;
83 |
84 | reg[26:0]cnt_T1s;
85 | reg[10:0]cnt_T5s;
86 | always@(posedge clk or negedge rst)
87 | begin
88 | if(!rst)
89 | begin
90 | cnt_T1s <= 26'd0;
91 | end
92 | else if(message_sent_enable_r==1)
93 | begin
94 | cnt_T1s <= 0 ;
95 | end
96 | else if(cnt_T1s == T1s) //每完成一次计数，就是结束了一绿8bit的ASCII码的发鿿
97 | begin
98 | cnt_T1s <= 26'd0;
99 | end
100 | else
101 | begin
102 | cnt_T1s <= cnt_T1s + 1'b1;
103 | end
104 | end
105 |
106 | always@(posedge clk or negedge rst)
107 | begin
108 | if(!rst)
109 | begin
110 | cnt_T5s <= 26'd0;
111 | end
112 | else if(message_sent_enable_r==1)
113 | begin
114 | cnt_T5s <= 0 ;
115 | end
116 | else if(cnt_T1s == T1s)
117 | begin
118 | cnt_T5s <= cnt_T5s + 1'b1;
119 | end
120 | else
121 | begin
122 | cnt_T5s <= cnt_T5s;
123 | end
124 | end
125 |
126 | reg message_sent_done_flag ; //来自下一个发送模块，发鿁完成一组指令的使能信号。高"1"有效,维持丿小段时钟周期
127 | reg message_sent_enable_en ; //真正启动发鿁的使能信号。可以发送的期间，长期置高电广"1"有效
128 | always@(posedge clk or negedge rst) begin
129 | if(!rst) //复位
130 | message_sent_enable_en <= 0 ;
131 | else if(message_sent_done_flag==1) //若结束一组发逿
132 | message_sent_enable_en <= 0 ; //可发送使能拉低，不再发鿁，且一直维持低电平
133 | else if(message_sent_enable_r==1) //若得到一次发送使胿
134 | message_sent_enable_en <= 1 ; //可发送的信号拉高，开始发送，且维持高电平
135 | end
136 |
137 |
138 | always@(posedge clk or negedge rst)
139 | begin
140 | if(!rst)
141 | begin
142 | tx_enable <= 1'b0;
143 | AT <= 32'h0a_0d_54_41;
144 | COLP <= 88'h0a_0d_31_3d_50_4c_4f_43_2b_54_41;//换行、回车㿁AT+COLP=1的忒序,11
145 | tx_data <= 8'b0;
146 | ATE1<=48'h0a_0d_31_45_54_41;
147 | ATH<=40'h0a_0d_48_54_41;
148 | num <= 0;
149 | ATD <= 0 ;
150 | end
151 | else if(tx_done)
152 | begin
153 | tx_enable <= 1'b0;
154 | end
155 |
156 | else if(cnt_T1s == T1s && num <= 6'd60 && message_sent_enable_en==1) //每次发鿁完丿个字符的ASCII码（在时间上），执行丿次下列内宿
157 | begin
158 | if((num <= 3) && (cnt_T5s <= 400) )//AT 发鿁A T 回车 换行 => 4*4*8=128，要发鿿128位二进制数，cnt_T5s计到400卿128的发送一条指令时闿+272的时延（等待返回丿个OK＿
159 | begin
160 | tx_enable <= 1'b1;
161 | tx_data <= AT;
162 | AT <= AT >> 8;
163 | num <= num + 1'b1;
164 | ATD <= {24'h0a0d3b,phone_number_buf,24'h445441};
165 | end
166 | //设置号码显示＿6个字笿
167 | else if( 4 <= num && num <= 9 && 401 <= cnt_T5s && cnt_T5s <= 700 )//CMGF 6*4*8=192,400+352+148=900 ，故本条指令延时亿148（这个数随意定）
168 | begin
169 | tx_enable <= 1'b1;
170 | tx_data <= ATE1;
171 | ATE1 <= ATE1 >> 8;
172 | num <= num + 1'b1;
173 | end
174 |
175 | //拨打号码＿ 17个字笿
176 | else if( 10 <= num && num <= 26 && 701 <= cnt_T5s && cnt_T5s <= 1400 )
177 | begin
178 | tx_enable <= 1'b1;
179 | tx_data <= ATD;
180 | ATD <= ATD >> 8;
181 | num <= num + 1'b1;
182 | end
183 |
184 | //电话显示 发鿁AT+COLP=1 11个字笿
185 | else if( 27 <= num && num <= 37 && 1401 <= cnt_T5s && cnt_T5s <= 1900)
186 | ///&& 901 <= cnt_T5s && cnt_T5s <= 1400 )//COLP
187 | begin
188 | tx_enable <= 1'b1;
189 | tx_data <= COLP;
190 | COLP <= COLP >> 8;
191 | num <= num + 1'b1;
192 | end
193 | else if(38 <= num && num <= 39 )begin
194 | num <= num+1'b1 ;
195 | end
196 | else if(40 <= num && num <= 41 )begin
197 | tx_enable <= 1'b0;
198 | num <= 0 ;
199 | end
200 | else
201 | begin
202 | tx_enable <= 1'b0;
203 | tx_data <= tx_data;
204 | num <= num;
205 | AT <= 32'h0a_0d_54_41;
206 | COLP <= 88'h0a_0d_31_3d_50_4c_4f_43_2b_54_41;//换行、回车㿁AT+COLP=1的忒序,11
207 | ATE1<=48'h0a_0d_31_45_54_41;
208 | ATH<=40'h0a_0d_48_54_41;
209 | end
210 | end
211 | end
212 |
213 | always@(posedge clk or negedge rst)
214 | if(!rst)
215 | message_sent_done_flag <= 0 ;
216 | else if(1908 <= cnt_T5s && cnt_T5s <= 1999)
217 | message_sent_done_flag <= 0 ;
218 | else if(1905 <= cnt_T5s && cnt_T5s <= 1906) //注意咿223之后还有丿小段时间间隔
219 | message_sent_done_flag <= 1 ;
220 | else
221 | message_sent_done_flag <= message_sent_done_flag ;
222 |
223 | endmodule
224 |
--------------------------------------------------------------------------------
/hongwai_rx.v:
--------------------------------------------------------------------------------
1 | module hongwai_rx(
2 | input clk,
3 | input rst_n,
4 | input [7:0] data_rx,
5 | input rx_int,//当uart_rx模块接收完对方的数据后，传给uart_tx,此为标志位，标志uart_tx要开始工作
6 |
7 | output reg [1:0] flag_tu_ao//10凸起 01凹陷
8 | );
9 |
10 |
11 | //-------------------------------------------------------
12 | //每个8位数据接收完整的标志
13 | reg [1:0] rx_int_r;
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) begin
16 | rx_int_r[0] <= 1'b0;
17 | rx_int_r[1] <= 1'b0;
18 | end
19 | else begin
20 | rx_int_r[0] <= rx_int;
21 | rx_int_r[1] <= rx_int_r[0];
22 | end
23 | end
24 |
25 | wire nege_edge = rx_int_r[1] & ~rx_int_r[0];//下降沿
26 |
27 |
28 | //---------------------------------------------------
29 | reg [7:0] data_rx_r;//用来接收传过来的data_rx
30 | //将rx接来的数据存下来
31 | always@(posedge clk or negedge rst_n)begin
32 | if(!rst_n) begin
33 | data_rx_r <= 8'd0;
34 | end
35 | else if(nege_edge)begin
36 | data_rx_r <= data_rx;
37 | end
38 | end
39 |
40 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
41 | // //
42 | // 检测分段距离 //
43 | // //
44 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
45 |
46 | parameter length = 4; //更方便地更改状态长度
47 |
48 | parameter [length-1 : 0] //one-hot code
49 | S_IDLE = 11'b0001,
50 | S_State1 = 11'b0010,
51 | S_State2 = 11'b0100,
52 | S_State3 = 11'b1000;
53 |
54 | reg [length-1 : 0] c_state;
55 | reg [length-1 : 0] n_state;
56 | //三段式状态机
57 | always @(posedge clk or negedge rst_n) begin
58 | if (!rst_n) begin
59 | c_state <= S_IDLE; // reset低电平复位
60 | end
61 | else begin
62 | c_state <= n_state; //next state logic
63 | end
64 | end
65 |
66 | always @(*) begin //state register
67 | case(c_state)
68 | S_IDLE :
69 | if (data_rx_r == 8'h41 && nege_edge)//A
70 | n_state = S_State1;
71 | else
72 | n_state = S_IDLE;
73 | S_State1 :
74 | if (data_rx_r == 8'h42 && nege_edge)//B
75 | n_state = S_State2;
76 | else
77 | n_state = S_State1;
78 | S_State2 :
79 | if (data_rx_r == 8'h43 && nege_edge)//C
80 | n_state = S_State3;
81 | else
82 | n_state = S_State2;
83 | S_State3 :
84 | if (data_rx_r && nege_edge)
85 | n_state = S_IDLE;
86 | else
87 | n_state = S_IDLE;
88 | default :
89 | n_state = S_IDLE;
90 | endcase
91 | end
92 |
93 |
94 | reg detected_o;
95 | //状态机输出output logic
96 | always @ (posedge clk or negedge rst_n) begin
97 | if(!rst_n) begin
98 | detected_o <= 1'b0;
99 | end
100 | else if( c_state == S_State3) begin
101 | detected_o <= 1'b1;
102 | end
103 | else begin
104 | detected_o <= 1'b0;
105 | end
106 | end
107 |
108 |
109 | ///检测到上升沿信号后持续输出高电平
110 | reg [5:0] num; //包传到哪个数据了
111 | reg start_reg;
112 | reg timeout;
113 | always@(posedge clk)
114 | start_reg <= detected_o;
115 |
116 | always@(posedge clk or negedge rst_n) begin
117 | if (!rst_n)
118 | timeout <= 0;
119 | else if(start_reg == 0 && detected_o ==1)//检测上升沿的
120 | timeout <= 1;
121 | else
122 | timeout <= timeout;
123 | end
124 |
125 |
126 |
127 | reg [7:0] data_pickup_r;//用来提取接收传过来的data_rx
128 | //将rx接来的数据存下来
129 | always@(posedge clk or negedge rst_n)begin
130 | if(!rst_n) begin
131 | data_pickup_r <= 8'd0;
132 | end
133 | else if(timeout) begin
134 | data_pickup_r <= data_rx_r; //此时已经是传完$GPRMC，后面传的均为数据
135 | end
136 | end
137 |
138 |
139 | //-------------------------------------------------------
140 | //判断包头，确定开始，以及识别号
141 | always@(posedge clk or negedge rst_n)
142 | begin
143 | if(!rst_n)
144 | num <= 4'd0;
145 | else if(num == 4)
146 | num <= 0;
147 | else if( start_reg == 0 && detected_o ==1 )
148 | num <= 0;
149 | else if( (timeout && nege_edge) || (timeout && start_reg))
150 | num <= num + 1'b1;
151 | else
152 | num <= num;
153 | end
154 |
155 |
156 | reg [23:0] hongwai_distance;
157 |
158 | always@(posedge clk or negedge rst_n)begin
159 | if(!rst_n)
160 | hongwai_distance <= 24'b0000_0000_0000_0000_1111_1111;
161 | else if(nege_edge && data_pickup_r >= 8'h30 && data_pickup_r <= 8'h39)begin
162 | case(num)
163 | 4'd1: hongwai_distance[23:16] <= data_pickup_r;
164 | 4'd2: hongwai_distance[15:8] <= data_pickup_r;
165 | 4'd3: hongwai_distance[7:0] <= data_pickup_r;
166 | default:;
167 | endcase
168 | end
169 | end
170 |
171 |
172 | reg [5:0] cnt;
173 | //打50拍
174 | always@(posedge clk or negedge rst_n)
175 | begin
176 | if(!rst_n)
177 | cnt <= 6'b0;
178 | else if(num == 1)
179 | cnt <= 6'b0;
180 | else if(cnt == 51)
181 | cnt <= cnt;
182 | else if(num == 3)
183 | cnt <= cnt + 1;
184 | else
185 | cnt <= 6'b0;
186 | end
187 |
188 | wire flag_distance;
189 | //取红外距离值使能
190 | assign flag_distance = (cnt == 50)?1:0;
191 |
192 | reg [8:0] distance;
193 |
194 | always@(posedge clk or negedge rst_n)begin
195 | if(!rst_n)
196 | distance <= 9'b0;
197 | // else if(nege_edge &&(num == 1 || num == 2 || num == 3)) //距离为3位十进制
198 | else if(num == 4)
199 | distance <= hongwai_distance[19:16]*100 + hongwai_distance[11:8]*10 + hongwai_distance[3:0];
200 | else
201 | distance <= distance;
202 | end
203 |
204 |
205 |
206 |
207 |
208 | reg [8:0] distance_1;
209 |
210 | always@(posedge clk)
211 | distance_1 <= distance;
212 |
213 |
214 | wire a;
215 |
216 | assign a = (distance_1 <= 70 && distance_1 >= 60)?1:0;
217 |
218 |
219 | reg a0;
220 | reg a1;
221 | reg a2;
222 | reg a3;
223 | reg a4;
224 | reg a5;
225 | reg a6;
226 | reg a7;
227 | reg a8;
228 | reg a9;
229 | reg a10;
230 | reg a11;
231 | reg a12;
232 | reg a13;
233 | reg a14;
234 | reg a15;
235 | reg a16;
236 | reg a17;
237 | reg a18;
238 | reg a19;
239 | reg a20;
240 | reg a21;
241 |
242 |
243 |
244 | always @(posedge clk or negedge rst_n)
245 | if(!rst_n)begin
246 | a0 <= 1'b0;
247 | a1 <= 1'b0;
248 | a2 <= 1'b0;
249 | a3 <= 1'b0;
250 | a4 <= 1'b0;
251 | a5 <= 1'b0;
252 | a6 <= 1'b0;
253 | a7 <= 1'b0;
254 | a8 <= 1'b0;
255 | a9 <= 1'b0;
256 | a10 <= 1'b0;
257 | a11 <= 1'b0;
258 | a12 <= 1'b0;
259 | a13 <= 1'b0;
260 | a14 <= 1'b0;
261 | a15 <= 1'b0;
262 | a16 <= 1'b0;
263 | a17 <= 1'b0;
264 | a18 <= 1'b0;
265 | a19 <= 1'b0;
266 | a20 <= 1'b0;
267 | a21 <= 1'b0;
268 |
269 | end
270 | else begin
271 | a0 <= a;
272 | a1 <= a0;
273 | a2 <= a1;
274 | a3 <= a2;
275 | a4 <= a3;
276 | a5 <= a4;
277 | a6 <= a5;
278 | a7 <= a6;
279 | a8 <= a7;
280 | a9 <= a8;
281 | a10 <= a9;
282 | a11 <= a10;
283 | a12 <= a11;
284 | a13 <= a12;
285 | a14 <= a13;
286 | a15 <= a14;
287 | a16 <= a15;
288 | a17 <= a16;
289 | a18 <= a17;
290 | a19 <= a18;
291 | a20 <= a19;
292 | a21 <= a20;
293 | end
294 |
295 | wire b;
296 |
297 | assign b = (distance_1 <= 97 && distance_1 >= 82)?1:0;
298 |
299 |
300 | reg b0;
301 | reg b1;
302 | reg b2;
303 | reg b3;
304 |
305 | always @(posedge clk or negedge rst_n)
306 | if(!rst_n)begin
307 | b0 <= 1'b0;
308 | b1 <= 1'b0;
309 | b2 <= 1'b0;
310 | b3 <= 1'b0;
311 | end
312 | else begin
313 | b0 <= b;
314 | b1 <= b0;
315 | b2 <= b1;
316 | b3 <= b2;
317 | end
318 |
319 | wire aoxian;
320 | assign aoxian = ((a0 && a1 && a2 && a3 && a4 && a5 && a6 && a7 && a8 && a9 && a10 && a11 && a12 && a13 && a14 && a15 && a16 && a17 && a18 && a19 && a20 && a21 )==1)?1:0;
321 |
322 | always@(posedge clk or negedge rst_n)
323 | begin
324 | if(!rst_n)
325 | flag_tu_ao <= 2'b0;
326 | else if((b0 && b1 && b2 && b3) == 1)
327 | flag_tu_ao <= 2'b11;
328 | else if(aoxian == 1)//凹陷 01
329 | flag_tu_ao <= 2'b01;
330 | else
331 | flag_tu_ao <= 2'b0;
332 | end
333 |
334 |
335 |
336 | endmodule
337 |
338 |
--------------------------------------------------------------------------------
/gsm.v:
--------------------------------------------------------------------------------
1 | module gsm(
2 | input clk,rst,
3 | input [183:0] TEXT_buf,
4 | input tx_done,//uart结束使能,该输入只维持一个时钟周期
5 | input mess_phone_number_prepared_enable, //一个段时间的高电平（源自 点击确认键）
6 |
7 | output reg tx_enable,
8 | output reg [7:0] tx_data
9 | );
10 |
11 | wire [183:0] TEXT_buf_r;
12 |
13 |
14 | assign TEXT_buf_r[7:0] = TEXT_buf[183:176];
15 | assign TEXT_buf_r[15:8] = TEXT_buf[175:168];
16 | assign TEXT_buf_r[23:16] = TEXT_buf[167:160];
17 | assign TEXT_buf_r[31:24] = TEXT_buf[159:152];
18 | assign TEXT_buf_r[39:32] = TEXT_buf[151:144];
19 | assign TEXT_buf_r[47:40] = TEXT_buf[143:136];
20 | assign TEXT_buf_r[55:48] = TEXT_buf[135:128];
21 | assign TEXT_buf_r[63:56] = TEXT_buf[127:120];
22 | assign TEXT_buf_r[71:64] = TEXT_buf[119:112];
23 | assign TEXT_buf_r[79:72] = TEXT_buf[111:104];
24 | assign TEXT_buf_r[87:80] = TEXT_buf[103:96];
25 | assign TEXT_buf_r[95:88] = TEXT_buf[95:88];
26 | assign TEXT_buf_r[103:96] = TEXT_buf[87:80];
27 | assign TEXT_buf_r[111:104] = TEXT_buf[79:72];
28 | assign TEXT_buf_r[119:112] = TEXT_buf[71:64];
29 | assign TEXT_buf_r[127:120] = TEXT_buf[63:56];
30 | assign TEXT_buf_r[135:128] = TEXT_buf[55:48];
31 | assign TEXT_buf_r[143:136] = TEXT_buf[47:40];
32 | assign TEXT_buf_r[151:144] = TEXT_buf[39:32];
33 | assign TEXT_buf_r[159:152] = TEXT_buf[31:24];
34 | assign TEXT_buf_r[167:160] = TEXT_buf[23:16];
35 | assign TEXT_buf_r[175:168] = TEXT_buf[15:8];
36 | assign TEXT_buf_r[183:176] = TEXT_buf[7:0];
37 |
38 |
39 |
40 |
41 | reg [383:0] TEXT_buf_1;
42 |
43 | always@(posedge clk or negedge rst)
44 | if(!rst)
45 | TEXT_buf_1 <= 1'b0;
46 | else
47 | TEXT_buf_1 <= { TEXT_buf_r,
48 | 8'h0A,
49 | 8'h21,8'h67,8'h6E,8'h69,8'h6E,8'h72,8'h61,8'h77,
50 | 8'h21,8'h67,8'h6E,8'h69,8'h6E,8'h72,8'h61,8'h77,
51 | 8'h21,8'h67,8'h6E,8'h69,8'h6E,8'h72,8'h61,8'h77};
52 |
53 |
54 | wire [87:0] phone_number_buf=88'h34_38_32_31_37_36_32_38_33_37_31;//程宁勃
55 | reg [31:0] AT;//AT命令寄存器;
56 | reg [119:0] CSCS;//AT+CSCS="GSM",设置为 GSM 编码字符集
57 | reg [87:0] CMGF;//AT+CMGF=1
58 | reg [183:0] CMGS;//AT + CMGS="phone_number"
59 | reg [383:0] TEXT;//message
60 | reg [7:0] jieshu;
61 | reg [6:0] num;
62 |
63 | reg message_sent_enable;
64 | //短信发送使能信号的处理 (延时了一个时钟周期，并且获得了两个系统时钟周期的高电平使能信号)
65 | reg mess_phone_number_prepared_enable_r1 ;
66 | reg mess_phone_number_prepared_enable_r2 ;
67 | reg mess_phone_number_prepared_enable_r3 ;
68 | always@(posedge clk or negedge rst)
69 | if(!rst) begin
70 | mess_phone_number_prepared_enable_r1 <= 0 ;
71 | mess_phone_number_prepared_enable_r2 <= 0 ;
72 | mess_phone_number_prepared_enable_r3 <= 0 ;
73 | end
74 | else begin
75 | mess_phone_number_prepared_enable_r1 <= mess_phone_number_prepared_enable ;
76 | mess_phone_number_prepared_enable_r2 <= mess_phone_number_prepared_enable_r1 ;
77 | mess_phone_number_prepared_enable_r3 <= mess_phone_number_prepared_enable_r2 ;
78 | end
79 | wire mess_phone_number_prepared_enable_r ;
80 | assign mess_phone_number_prepared_enable_r = mess_phone_number_prepared_enable_r2 | mess_phone_number_prepared_enable_r3 ;
81 | always@(posedge clk or negedge rst)
82 | if(!rst)
83 | message_sent_enable <= 0 ;
84 | else
85 | message_sent_enable <= mess_phone_number_prepared_enable_r ;
86 |
87 | reg message_sent_enable_r1;
88 | reg message_sent_enable_r2;
89 | wire message_sent_enable_r;
90 | assign message_sent_enable_r = message_sent_enable_r1 & ~message_sent_enable_r2 ;
91 | always@(posedge clk or negedge rst)
92 | if(!rst) begin
93 | message_sent_enable_r1 <= 0;
94 | message_sent_enable_r2 <= 0;
95 | end
96 | else begin
97 | message_sent_enable_r1 <= mess_phone_number_prepared_enable;
98 | message_sent_enable_r2 <= message_sent_enable_r1 ;
99 | end
100 |
101 | parameter T1s = 27'd90_000;
102 |
103 | reg[26:0]cnt_T1s;
104 | reg[25:0]cnt_T5s;
105 |
106 | always@(posedge clk or negedge rst)
107 | begin
108 | if(!rst) begin
109 | cnt_T1s <= 26'd0;
110 | end
111 | else if(message_sent_enable_r==1'b1) begin
112 | cnt_T1s <= 0 ;
113 | end
114 | else if(cnt_T1s == T1s) begin //每完成一次计数，就是结束了一组8bit的ASCII码的发送
115 | cnt_T1s <= 26'd0;
116 | end
117 | else begin
118 | cnt_T1s <= cnt_T1s + 1'b1;
119 | end
120 | end
121 |
122 | always@(posedge clk or negedge rst)
123 | begin
124 | if(!rst) begin
125 | cnt_T5s <= 26'd0;
126 | end
127 | else if(message_sent_enable_r==1'b1) begin
128 | cnt_T5s <= 0 ;
129 | end
130 | else if(cnt_T1s == T1s) begin
131 | cnt_T5s <= cnt_T5s + 1'b1;
132 | end
133 | else begin
134 | cnt_T5s <= cnt_T5s;
135 | end
136 | end
137 |
138 | reg message_sent_done_flag ; //来自下一个发送模块，发送完成一组指令的使能信号。高"1"有效,维持一小段时钟周期
139 | reg message_sent_enable_en ; //真正启动发送的使能信号。可以发送的期间，长期置高电平"1"有效
140 | always@(posedge clk or negedge rst)
141 | begin
142 | if(!rst) //复位
143 | message_sent_enable_en <= 0 ;
144 | else if(message_sent_done_flag==1'b1) //若结束一组发送
145 | message_sent_enable_en <= 0 ; //可发送使能拉低，不再发送，且一直维持低电平
146 | else if(message_sent_enable_r==1'b1) //若得到一次发送使能
147 | message_sent_enable_en <= 1 ; //可发送的信号拉高，开始发送，且维持高电平
148 | end
149 |
150 |
151 | always@(posedge clk or negedge rst)
152 | begin
153 | if(!rst) begin
154 | tx_enable <= 1'b0;
155 | AT <= 32'h0a_0d_54_41;
156 | tx_data <= 8'b0;
157 | CSCS <= 120'h0a_0d_22_4d_53_47_22_3d_53_43_53_43_2b_54_41;//换行、回车、AT+CSCS="GSM"的倒序,15
158 | CMGF <= 88'h0a_0d_31_3d_46_47_4d_43_2b_54_41;//换行、回车、AT+CMGF=1的倒序,11
159 | jieshu <= 8'h1A;
160 | TEXT <= 0;
161 | num <= 0;
162 | CMGS <= 0 ;
163 | end
164 | else if(tx_done) begin
165 | tx_enable <= 1'b0;
166 | end
167 | else if(cnt_T1s == T1s && num <= 10'd110 && message_sent_enable_en==1) begin //每次发送完一个字符的ASCII码（在时间上），执行一次下列内容
168 |
169 | if((num <= 2'd3) && (cnt_T5s <= 9'd400) ) begin //AT 发送A T 回车 换行 => 4*4*8=128，要发送128位二进制数，cnt_T5s计到400即128的发送一条指令时间+272的时延（等待返回一个OK）
170 | tx_enable <= 1'b1;
171 | tx_data <= AT;
172 | AT <= AT >> 4'd8;
173 | num <= num + 1'b1; //这个num还真不能拿到这个always块的外边去做累加，因为他和每次发送一组指令后的等待有关，发送一个数num加一次一，但是发完一组指令需要等待，此时cnt_5s累加，但是num不用累加
174 | TEXT <= TEXT_buf_1 ;
175 | CMGS <= {24'h0a0d22,phone_number_buf,72'h223d53474d432b5441};
176 | end
177 | //ATTENTION PLEASE!!! num记到3之后到cnt_T5s之间的这一段时间是空的，因为下一条只有在cnt_T5s记到401时才会开始发送对应指令
178 | //发送AT+CSCS="GSM"回车换行，15个字符
179 | else if( 3'd4 <= num && num <= 5'd18 && 9'd401 <= cnt_T5s && cnt_T5s <= 10'd900 )//CMGF 11*4*8=352,400+352+148=900 ，故本条指令延时了148（这个数随意定）
180 | begin
181 | tx_enable <= 1'b1;
182 | tx_data <= CSCS;
183 | CSCS <= CSCS >> 4'd8;
184 | num <= num + 1'b1;
185 | end
186 | //发送AT+CMGF=1， 11个字符
187 | else if( 5'd19 <= num && num <= 5'd29 && 10'd901 <= cnt_T5s && cnt_T5s <= 11'd1400 )//CSMP
188 | begin
189 | tx_enable <= 1'b1;
190 | tx_data <= CMGF;
191 | CMGF <= CMGF >> 8;
192 | num <= num + 1'b1;
193 | end
194 | //发送CMGS="",23字符
195 | else if( 30 <= num && num <= 52 && 1401 <= cnt_T5s && cnt_T5s <= 2500 )//CSCS
196 | begin
197 | tx_enable <= 1'b1;
198 | tx_data <= CMGS;
199 | CMGS <= CMGS >> 4'd8;
200 | num <= num + 1'b1;
201 | end
202 | //发短信，48，字符
203 | else if( 53 <= num && num <= 100 && 2501 <= cnt_T5s && cnt_T5s <= 4200)//CMGS//1700s
204 | begin
205 | tx_enable <= 1'b1;
206 | tx_data <= TEXT;
207 | TEXT <= TEXT >> 8;
208 | num <= num + 1'b1;
209 | end
210 | //发1A
211 | else if( num >= 101 && num <= 102 && 4201 <= cnt_T5s && cnt_T5s <= 4300)//CMGS
212 | begin
213 | tx_enable <= 1'b1;
214 | tx_data <= jieshu;
215 | jieshu <= jieshu >> 8;
216 | num <= num + 1'b1;
217 | end
218 | else if(103 <= num && num <= 104 && 4301 <= cnt_T5s && cnt_T5s <= 4305) begin
219 | num <= num+1 ;
220 | end
221 | else if(105 <= num && num <= 106 && 4306 <= cnt_T5s && cnt_T5s <= 4308) begin
222 |
223 | tx_enable <= 1'b0;
224 | num <= num + 1'b1 ;
225 | // num <= 0;
226 | end
227 | else if(4309 <= cnt_T5s && cnt_T5s <= 4310)
228 | num <= 0 ;
229 | else
230 | begin
231 | tx_enable <= 1'b0;
232 | tx_data <= tx_data;
233 | num <= num;
234 | CSCS <= 120'h0a_0d_22_4d_53_47_22_3d_53_43_53_43_2b_54_41;//换行、回车、AT+CSCS="GSM"的倒序,15
235 | CMGF <= 88'h0a_0d_31_3d_46_47_4d_43_2b_54_41;//换行、回车、AT+CMGF=1的倒序,11
236 | AT <= 32'h0a_0d_54_41;
237 | jieshu <= 8'h1A;
238 | CMGS <= {24'h0a0d22,phone_number_buf,72'h223d53474d432b5441};
239 | end
240 | end
241 | end
242 |
243 | always@(posedge clk or negedge rst)
244 | if(!rst)
245 | message_sent_done_flag <= 0 ;
246 | else if(4313 <= cnt_T5s && cnt_T5s <= 4314)
247 | message_sent_done_flag <= 0 ;
248 | else if(4311 <= cnt_T5s && cnt_T5s <= 4312) //注意和223之后还有一小段时间间隔
249 | message_sent_done_flag <= 1 ;
250 | else
251 | message_sent_done_flag <= message_sent_done_flag ;
252 |
253 | endmodule
254 |
--------------------------------------------------------------------------------
/VGA_square.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 22:35:16 11/02/2019
7 | // Design Name:
8 | // Module Name: VGA_square
9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module VGA_square(
22 |
23 | input clk,
24 | input rst_n,
25 | input [7:0] M_pic,
26 |
27 | output flag_addr,//表示边框xy比例检测成功，VGA可以进行显示
28 | output reg [6:0] cnt_x,
29 | output reg [7:0] cnt_y,//127超值
30 | output reg [15:0] rom_addr13,
31 | output reg [15:0] flag_square_begin,
32 | output reg [15:0] flag_square_end
33 | );
34 |
35 | wire [7:0] r1;
36 | wire [7:0] g1;
37 | wire [7:0] b1;
38 | wire red0;
39 | wire green0;
40 | wire blue0;
41 | wire black;
42 | wire black_x;
43 |
44 |
45 | reg clear;
46 | reg [15:0] black_reg0;
47 | reg [15:0] black_reg1;
48 | reg [15:0] black_reg2;
49 | reg [6:0] N;
50 | reg [15:0] rom_addr13_1;
51 | reg [15:0] rom_addr13_2;
52 | reg [2:0] B;
53 | reg [2:0] BiLi;
54 |
55 |
56 | assign r1 = {M_pic[7:5],M_pic[7:5],M_pic[7:6]};
57 | assign g1 = {M_pic[4:2],M_pic[4:2],M_pic[4:3]};
58 | assign b1 = {M_pic[1:0],M_pic[1:0],M_pic[1:0],M_pic[1:0]};
59 |
60 | assign red0 = ((r1 <= 8'd36 && r1 <= 8'd73) || r1 == 8'd0 || r1 == 8'd109) ? 1'b1 : 1'b0;
61 | assign green0 = ((g1 >= 8'd36 && g1 <= 8'd73) || g1 == 8'd0 || g1 == 8'd146) ? 1'b1 : 1'b0;//
62 | assign blue0 = ((b1 >= 8'd80 && b1 <= 8'd85) || b1 == 8'd0) ? 1'b1 : 1'b0;
63 | assign black = (red0 & green0 & blue0)? 1'b1 : 1'b0;//近似黑色提取
64 |
65 | wire [15:0] a;
66 | assign a = (cnt_x > 30)?black_reg0:0;
67 |
68 |
69 | //检测横向特征黑
70 | always @ (posedge clk or negedge rst_n)begin
71 | if(!rst_n)
72 | black_reg0 <= 16'd0;
73 | else if(black && (cnt_x == 6'd1))
74 | black_reg0 <= rom_addr13_1 - 3'd3 + 3'd4;//加4:为了cnt_y检测保持黑色black像素点
75 | else
76 | black_reg0 <= black_reg0;
77 | end
78 |
79 |
80 | always @ (posedge clk or negedge rst_n)begin
81 | if(!rst_n)begin
82 | black_reg1 <= 16'd0;
83 | black_reg2 <= 16'd0;
84 | end
85 | else if(black)begin
86 | black_reg1 <= rom_addr13_1;
87 | black_reg2 <= black_reg1;
88 | end
89 | else begin
90 | black_reg1 <= 16'd0;
91 | black_reg2 <= 16'd0;
92 | end
93 | end
94 |
95 |
96 | //判断两个 特征黑 地址是否相邻
97 | assign black_x =(black_reg1 - black_reg2 == 1)?1'b1:1'b0;
98 |
99 |
100 | reg [6:0] j0;
101 | reg [6:0] j1;
102 | wire [6:0] h;
103 |
104 | assign h = (j0 - j1 == 1'b0)?j0:1'b0;
105 |
106 |
107 | always @(posedge clk or negedge rst_n)begin
108 | if(!rst_n)begin
109 | j0 <= 7'd0;
110 | j1 <= 7'd0;
111 | end
112 | else if(cnt_x > 0)begin
113 | j0 <= cnt_x;
114 | j1 <= j0;
115 | end
116 | else begin
117 | j0 <= 7'd0;
118 | j1 <= 7'd0;
119 | end
120 | end
121 |
122 | //记黑色边框的宽
123 | always @(posedge clk or negedge rst_n)begin
124 | if(!rst_n)
125 | cnt_x <= 7'd0;
126 | else if(clear)
127 | cnt_x <= 7'd0;
128 | else if( cnt_x > (h-1'b1) )///////////22特殊值,即cnt_x计数特征黑的一行像素点数
129 | cnt_x <= cnt_x;
130 | else if(black_x == 1'b1)
131 | cnt_x <= cnt_x + 1'b1;
132 | else
133 | cnt_x <= cnt_x;
134 | end
135 |
136 |
137 | //特征黑色小于cnt_x <= 30不进行运算
138 | always @(posedge clk or negedge rst_n)begin
139 | if(!rst_n)
140 | clear <= 1'b0;
141 | else if((cnt_x <= 30 && cnt_x > 0 && !black_x) || (cnt_x >= 80 && !black_x))
142 | clear <= 1'b1;
143 | else
144 | clear <= 1'b0;
145 | end
146 |
147 |
148 |
149 |
150 | always @(posedge clk or negedge rst_n)begin
151 | if(!rst_n)
152 | rom_addr13_1 <= 16'd0;
153 | else if(rom_addr13 >= 16'd32800)
154 | rom_addr13_1 <= 16'd0;
155 | else if(cnt_x > (h-1'b1))
156 | rom_addr13_1 <= rom_addr13_1;
157 | else if(cnt_y == 8'd0)
158 | rom_addr13_1 <= rom_addr13_1 + 1'b1;
159 | else
160 | rom_addr13_1 <= rom_addr13_1;
161 | end
162 |
163 |
164 | wire [15:0] c;
165 |
166 | assign c = rom_addr13 - cnt_x - 3'd5 + 3'd4;
167 |
168 |
169 | always @(posedge clk or negedge rst_n)begin
170 | if(!rst_n)begin
171 | cnt_y <= 8'd0;
172 | N <= 7'd0;
173 | rom_addr13_2 <= 16'd0;
174 | end
175 | else begin
176 | rom_addr13 <= rom_addr13_1 + rom_addr13_2 + 1'b1;
177 |
178 | if(!black_x && cnt_x >= 7'd6)
179 | begin
180 |
181 | case (c)
182 |
183 | black_reg0 + N*200: begin
184 | rom_addr13 <= rom_addr13 - (h+5);
185 |
186 | if(black)begin
187 | cnt_y <= cnt_y + 1'b1;
188 | rom_addr13_2 <= rom_addr13_2 + 200;
189 | N <= N + 1'b1;
190 | end
191 | else begin
192 | N <= 7'd0;
193 | cnt_y <= cnt_y;
194 | end
195 | end
196 |
197 | black_reg0 + N*200: if(black)begin
198 | cnt_y <= cnt_y + 1'b1;
199 | rom_addr13_2 <= rom_addr13_2 + 200;
200 | N <= N + 1'b1;
201 | end
202 | else begin
203 | N <= 7'd0;
204 | cnt_y <= cnt_y;
205 | end
206 |
207 | black_reg0 + N*200: if(black)begin
208 | cnt_y <= cnt_y + 1'b1;
209 | rom_addr13_2 <= rom_addr13_2 + 200;
210 | N <= N + 1'b1;
211 | end
212 | else begin
213 | N <= 7'd0;
214 | cnt_y <= cnt_y;
215 | rom_addr13_2 <= rom_addr13_2;
216 | end
217 | endcase
218 | end
219 | end
220 | end
221 |
222 |
223 | reg clk_4;
224 | reg [2:0] cnt_clk_4;
225 | //同上
226 | always @(posedge clk or negedge rst_n)begin
227 | if(!rst_n)
228 | cnt_clk_4 <= 3'd0;
229 | else if(cnt_clk_4 == 3'd5)
230 | cnt_clk_4 <= 3'd0;
231 | else
232 | cnt_clk_4 <= cnt_clk_4 + 1'b1;
233 | end
234 | //同上
235 | always @(posedge clk or negedge rst_n)begin
236 | if(!rst_n)
237 | clk_4 <= 1'b0;
238 | else if(cnt_clk_4 == 3'd5)
239 | clk_4 <= 3'd0;
240 | else if(cnt_clk_4 == 3'd3)
241 | clk_4 <= ~clk_4;
242 | else
243 | clk_4 <= clk_4;
244 | end
245 |
246 | reg [6:0] i_0;
247 | reg [6:0] i_1;
248 |
249 | //使比例在cnt_y稳定时进行计算
250 | always @(posedge clk or negedge rst_n)
251 | if(!rst_n)begin
252 | i_0 <= 7'd0;
253 | i_1 <= 7'd0;
254 | end
255 | else if(cnt_y)begin
256 | i_0 <= cnt_y;
257 | i_1 <= i_0;
258 | end
259 | else begin
260 | i_0 <= 7'd0;
261 | i_1 <= 7'd0;
262 | end
263 |
264 |
265 | reg flag_cnt_y;
266 | //同上
267 | always @(posedge clk_4 or negedge rst_n)begin
268 | if(!rst_n)
269 | flag_cnt_y <= 1'b0;
270 | else if(i_0 - i_1 == 1'b0 && cnt_y > 1'b0)
271 | flag_cnt_y <= 1'b1;
272 | else
273 | flag_cnt_y <= 1'b0;
274 | end
275 |
276 |
277 |
278 | //确定长宽比
279 | always @(posedge clk or negedge rst_n)begin
280 | if(!rst_n)
281 | B <= 3'd0;
282 | else begin
283 | if(flag_cnt_y)
284 | begin
285 | if((cnt_y < 6*cnt_x)&& (cnt_y > 5*cnt_x))
286 | B <= 3'd4;
287 | else if((cnt_y < 5*cnt_x)&& (cnt_y > 4*cnt_x))
288 | B <= 3'd3;
289 | else if((cnt_y < 4*cnt_x)&& (cnt_y > 2*cnt_x))
290 | B <= 3'd2;
291 | else if((cnt_y < 2*cnt_x)&& (cnt_y > 1*cnt_x))
292 | B <= 3'd1;
293 | end
294 | end
295 |
296 | end
297 |
298 | //产生比例值,判断是否为特定框
299 | always @(posedge clk or negedge rst_n)begin
300 | if(!rst_n)
301 | BiLi <= 3'd0;
302 | else if(clear)
303 | BiLi <= 3'd0;
304 | else begin
305 | case (B)
306 | 1: BiLi <= 3'd1;
307 | 2: BiLi <= 3'd2;
308 | 3: BiLi <= 3'd3;
309 | 4: BiLi <= 3'd4;
310 | default: BiLi <= 3'd0;
311 | endcase
312 | end
313 | end
314 |
315 | reg clr;
316 |
317 | //检测到第一个非红绿灯比例的黑色特征框,清零所有寄存器的值
318 | always @(posedge clk or negedge rst_n)begin
319 | if(!rst_n)
320 | clr <= 1'b0;
321 | else if(BiLi > 3'd2 | BiLi == 3'd1)
322 | clr <= 1'b1;
323 | else
324 | clr <= 1'b0;
325 | end
326 |
327 |
328 | reg [6:0] d0;
329 | reg [6:0] d1;
330 | reg VGA_clk;
331 |
332 | //为了保持cnt_y稳定时的值
333 | always @(posedge clk or negedge rst_n)begin
334 | if(!rst_n)
335 | VGA_clk <= 1'b0;
336 | else
337 | VGA_clk <= ~VGA_clk;
338 | end
339 |
340 | //同上
341 | always @(posedge VGA_clk or negedge rst_n)
342 | if(!rst_n)begin
343 | d0 <= 7'd0;
344 | d1 <= 7'd0;
345 | end
346 | else begin
347 | d0 <= cnt_y;
348 | d1 <= d0;
349 | end
350 |
351 | //cnt_y稳定不变的信号
352 | assign flag_addr = ((d0 - d1)== 1'b0 && cnt_y > 1'b0)?1'b1:1'b0;
353 |
354 |
355 | //VGA显示边框的始末
356 | always @(posedge clk or negedge rst_n)
357 | if(!rst_n)begin
358 | flag_square_begin <= 16'd0;
359 | flag_square_end <= 16'd0;
360 | end
361 | else if(BiLi == 3'd2)begin
362 | flag_square_begin <= black_reg0;
363 | if(flag_addr)
364 | flag_square_end <= black_reg0 + cnt_x + cnt_y * 200;
365 | end
366 | else begin
367 | flag_square_begin <= 16'd0;
368 | flag_square_end <= 16'd0;
369 | end
370 |
371 |
372 |
373 | endmodule
374 |
--------------------------------------------------------------------------------
/gps_rx.v:
--------------------------------------------------------------------------------
1 | module gps_rx(
2 | input clk,
3 | input rst_n,
4 | input [7:0] data_rx,
5 | input rx_int,//当uart_rx模块接收完对方的数据后，传给uart_tx,此为标志位，标志uart_tx要开始工作
6 | output reg [183:0] data_rx_end,
7 | output [47:0] ymr_out,
8 | output reg [71:0] time_out
9 | );
10 |
11 | //-------------------------------------------------------
12 | //每个8位数据接收完整的标志
13 | reg [1:0] rx_int_r;
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) begin
16 | rx_int_r[0] <= 1'b0;
17 | rx_int_r[1] <= 1'b0;
18 | end
19 | else begin
20 | rx_int_r[0] <= rx_int;
21 | rx_int_r[1] <= rx_int_r[0];
22 | end
23 | end
24 |
25 | wire nege_edge = rx_int_r[1] & ~rx_int_r[0];//下降沿
26 |
27 |
28 | //---------------------------------------------------
29 | reg [7:0] data_rx_r;//用来接收传过来的data_rx
30 | //将rx接来的数据存下来
31 | always@(posedge clk or negedge rst_n)begin
32 | if(!rst_n) begin
33 | data_rx_r <= 8'd0;
34 | end
35 | else if(nege_edge)begin
36 | data_rx_r <= data_rx;
37 | end
38 | end
39 |
40 | reg detected_o;
41 | parameter length = 7; //更方便地更改状态长度
42 |
43 | parameter [length-1 : 0] //one-hot code
44 | S_IDLE = 7'b0000001,
45 | S_State1 = 7'b0000010,
46 | S_State2 = 7'b0000100,
47 | S_State3 = 7'b0001000,
48 | S_State4 = 7'b0010000,
49 | S_State5 = 7'b0100000,
50 | S_State6 = 7'b1000000;
51 |
52 | reg [length-1 : 0] c_state;
53 | reg [length-1 : 0] n_state;
54 | //三段式状态机
55 | always @(posedge clk or negedge rst_n) begin
56 | if (!rst_n) begin
57 | c_state <= S_IDLE; // reset低电平复位
58 | end
59 | else begin
60 | c_state <= n_state; //next state logic
61 | end
62 | end
63 |
64 | always @(*) begin //state register
65 | case(c_state)
66 | S_IDLE :
67 | if (data_rx_r == 8'h24 && nege_edge)//$
68 | n_state = S_State1;
69 | else
70 | n_state = S_IDLE;
71 | S_State1 :
72 | if (data_rx_r == 8'h47 && nege_edge)//G
73 | n_state = S_State2;
74 | else
75 | n_state = S_State1;
76 | S_State2 :
77 | if (data_rx_r == 8'h50 && nege_edge)//P
78 | n_state = S_State3;
79 | else
80 | n_state = S_State2;
81 | S_State3 :
82 | if (data_rx_r == 8'h52 && nege_edge)//R
83 | n_state = S_State4;
84 | else
85 | n_state = S_State3;
86 | S_State4 :
87 | if (data_rx_r == 8'h4D && nege_edge)//M
88 | n_state = S_State5;
89 | else
90 | n_state = S_State4;
91 | S_State5 :
92 | if (data_rx_r == 8'h43 && nege_edge)//C
93 | n_state = S_State6;
94 | else
95 | n_state = S_State5;
96 | S_State6 :
97 | if (data_rx_r && nege_edge)
98 | n_state = S_IDLE;
99 | else
100 | n_state = S_IDLE;
101 | default :
102 | n_state = S_IDLE;
103 | endcase
104 | end
105 | //4，$GPRMC（推荐定位信息，Recommended Minimum Specific GPS/Transit Data） $GPRMC语句的基本格式如下： $GPRMC,(1),(2),(3),(4),(5),(6),(7),(8),(9),(10),(11),(12)*hh(CR)(LF) (1) UTC时间，hhmmss（时分秒） (2) 定位状态，A=有效定位，V=无效定位 (3) 纬度ddmm.mmmmm（度分） (4) 纬度半球N（北半球）或S（南半球） (5) 经度dddmm.mmmmm（度分） (6) 经度半球E（东经）或W（西经） (7) 地面速率（000.0~999.9节） (8) 地面航向（000.0~359.9度，以真北方为参考基准） (9) UTC日期，ddmmyy（日月年） (10)磁偏角（000.0~180.0度，前导位数不足则补0） (11) 磁偏角方向，E（东）或W（西） (12) 模式指示（A=自主定位，D=差分，E=估算，N=数据无效） 举例如下： $GPRMC,023543.00,A,2308.28715,N,11322.09875,E,0.195,,240213,,,A*78
106 |
107 |
108 | //状态机输出output logic
109 | always @ (posedge clk or negedge rst_n) begin
110 | if(!rst_n) begin
111 | detected_o <= 1'b0;
112 | end
113 | else if( c_state == S_State6) begin
114 | detected_o <= 1'b1;
115 | end
116 | else begin
117 | detected_o <= 1'b0;
118 | end
119 | end
120 |
121 | ///检测到上升沿信号后持续输出高电平
122 | reg [3:0] num; //包传到哪个数据了
123 | // reg a_flag; //UTC位置标识位
124 | reg start_reg;
125 | reg timeout;
126 | always@(posedge clk)
127 | start_reg <= detected_o;
128 |
129 | reg [3:0] count;
130 | always@(posedge clk or negedge rst_n) begin
131 | if (!rst_n)
132 | timeout <= 0;
133 | else if(start_reg == 0 && detected_o ==1)
134 | timeout <= 1;
135 | else if(count == 4'd10) //count记,的
136 | timeout <= 0;
137 | else
138 | timeout <= timeout;
139 | end
140 | /////
141 |
142 | reg [7:0] data_pickup_r;//用来提取接收传过来的data_rx
143 | //将rx接来的数据存下来
144 | always@(posedge clk or negedge rst_n)begin
145 | if(!rst_n) begin
146 | data_pickup_r <= 8'd0;
147 | end
148 | else if(timeout) begin
149 | data_pickup_r <= data_rx_r; //此时已经是传完$GPRMC，后面传的均为数据
150 | end
151 | end
152 |
153 | // reg [3:0] count;
154 | always@(posedge clk or negedge rst_n) //count加——逗号与逗号之间 num加——各个数据每一个字
155 | begin
156 | if(!rst_n)
157 | count <= 0;
158 | else if(data_pickup_r==8'h2C && nege_edge)
159 | count <= count + 1;
160 | else if(start_reg == 0 && detected_o ==1)
161 | count <= 0;
162 | else
163 | count <= count;
164 | end
165 |
166 | //-------------------------------------------------------
167 | //判断包头，确定开始，以及识别号
168 | always@(posedge clk or negedge rst_n)begin
169 | if(!rst_n) num <= 4'd0;
170 | else if(start_reg == 0 && detected_o ==1) num <= 0;
171 | else if(data_pickup_r==8'h2C&&nege_edge ) num <= 4'd1;
172 | else if(timeout&&nege_edge) num <= num + 1'b1;
173 | else num <= num;
174 | end
175 |
176 |
177 | //-----------------------------------------------------
178 | //根据标识位分类给寄存器赋值
179 | reg [79:0] Latitude ; //纬度
180 | reg [87:0] longitude ; //经度
181 | reg [71:0] UTC_time ; //UTC时间
182 | reg [47:0] ddmmyy;
183 | reg [7:0] E_flag;
184 | reg [7:0] N_flag;
185 | always@(posedge clk or negedge rst_n)begin
186 | if(!rst_n) begin
187 | Latitude <= 0;
188 | longitude <= 0;
189 | UTC_time <= 0;
190 | ddmmyy <= 0;
191 | E_flag <= 0;
192 | N_flag <= 0;
193 | end //$GPRMC,023543.00,A,2308.28715,N,11322.09875,E,0.195,,240213,,,A*78
194 | else if(count == 4'd1&&nege_edge&& data_pickup_r!=8'h2C )begin //时间
195 | case(num)
196 | 4'd1: UTC_time[71:64] <= data_pickup_r; // 134104.00 13点41分04秒[3133343130342e3030]
197 | 4'd2: UTC_time[63:56] <= data_pickup_r;
198 | 4'd3: UTC_time[55:48] <= data_pickup_r;
199 | 4'd4: UTC_time[47:40] <= data_pickup_r;
200 | 4'd5: UTC_time[39:32] <= data_pickup_r;
201 | 4'd6: UTC_time[31:24] <= data_pickup_r;
202 | 4'd7: UTC_time[23:16] <= data_pickup_r; //小数点
203 | 4'd8: UTC_time[15:8] <= data_pickup_r;
204 | 4'd9: UTC_time[7:0] <= data_pickup_r;
205 | default:;
206 | endcase
207 | end
208 | else if(count == 4'd3&&nege_edge&& data_pickup_r!=8'h2C)begin //维度
209 | case(num)
210 | 4'd1: Latitude[79:72] <= data_pickup_r;// 3 3409.22851 [33342e30393232383531] 9.22851/60 34.1538085
211 | 4'd2: Latitude[71:64] <= data_pickup_r;// 4
212 | 4'd5: Latitude[63:56] <= data_pickup_r;//.
213 | 4'd3: Latitude[55:48] <= data_pickup_r;//0
214 | 4'd4: Latitude[47:40] <= data_pickup_r;//9
215 | 4'd6: Latitude[39:32] <= data_pickup_r;//
216 | 4'd7: Latitude[31:24] <= data_pickup_r;//
217 | 4'd8: Latitude[23:16] <= data_pickup_r;//
218 | 4'd9: Latitude[15:8] <= data_pickup_r;//
219 | 4'd10: Latitude[7:0] <= data_pickup_r;//
220 | default:;
221 | endcase
222 | end
223 | else if(count == 4'd4&&nege_edge&& data_pickup_r!=8'h2C)begin
224 | N_flag[7:0] <= data_pickup_r;//N
225 | end
226 | else if(count == 4'd5&&nege_edge&& data_pickup_r!=8'h2C)begin //经度
227 | case(num)
228 | 4'd1: longitude[87:80] <= data_pickup_r;//1 10853.63286 [3130382e35333633323836]
229 | 4'd2: longitude[79:72] <= data_pickup_r;//0
230 | 4'd3: longitude[71:64] <= data_pickup_r;//8
231 | 4'd6: longitude[63:56] <= data_pickup_r;//.
232 | 4'd4: longitude[55:48] <= data_pickup_r;//5
233 | 4'd5: longitude[47:40] <= data_pickup_r;//3
234 | 4'd7: longitude[39:32] <= data_pickup_r;
235 | 4'd8: longitude[31:24] <= data_pickup_r;
236 | 4'd9: longitude[23:16] <= data_pickup_r;
237 | 4'd10: longitude[15:8] <= data_pickup_r;
238 | 4'd11: longitude[7:0] <= data_pickup_r;
239 | default:;
240 | endcase
241 | end
242 | else if(count == 4'd6&&nege_edge&& data_pickup_r!=8'h2C)begin
243 | E_flag[7:0] <= data_pickup_r;//E
244 | end
245 | else if(count == 4'd9&&nege_edge&& data_pickup_r!=8'h2C)begin
246 | case(num) //171019 19年10月17日 [313931303137]
247 | 4'd5: ddmmyy[47:40] <= data_pickup_r;
248 | 4'd6: ddmmyy[39:32] <= data_pickup_r;
249 | 4'd3: ddmmyy[31:24] <= data_pickup_r;
250 | 4'd4: ddmmyy[23:16] <= data_pickup_r;
251 | 4'd1: ddmmyy[15:8] <= data_pickup_r;
252 | 4'd2: ddmmyy[7:0] <= data_pickup_r;
253 | default:;
254 | endcase
255 | end
256 | end
257 |
258 | assign ymr_out = ddmmyy;
259 | always@(*)
260 | begin
261 | if(E_flag[7:4]==4'b0100)
262 | data_rx_end ={N_flag,Latitude,E_flag,longitude};
263 | else data_rx_end=1'b0;
264 | end
265 | always@(*)
266 | begin
267 | if(UTC_time[7:4]==4'b0011)
268 | time_out =UTC_time;
269 | else time_out=1'b0;
270 | end
271 |
272 | endmodule
273 |
--------------------------------------------------------------------------------
/Arudino代码/Tricycle_For_Arduino.ino:
--------------------------------------------------------------------------------
1 | #include
2 | #include //外部中断
3 | #include //定时中断
4 | //#include
5 | //SoftwareSerial Serial(11, A2); // RX, TX
6 | /////////TB6612驱动引脚////
7 | //#define AIN1 11
8 | //#define AIN2 5
9 | #define AIN1 10
10 | #define AIN2 9
11 | #define BIN1 6
12 | #define BIN2 3
13 | #define SERVO 9
14 | /////////编码器引脚////////
15 | #define ENCODER_L 8 //编码器采集引脚 每路2个 共4个
16 | #define DIRECTION_L 4
17 | #define ENCODER_R 7
18 | #define DIRECTION_R 2
19 | #define key1 12
20 | #define key2 13
21 | /////////按键引脚////////
22 | //#define KEY 18
23 | //#define T 0.156f
24 | //#define L 0.1445f
25 | //#define pi 3.1415926
26 |
27 | volatile long Velocity_L, Velocity_R ; //左右轮编码器数据
28 | int Velocity_Left, Velocity_Right = 0 ; //左右轮速度
29 | float Velocity_KP =10 , Velocity_KI = 1, Velocity = 0, turn =0;
30 | unsigned char Flag_Stop = 0; //停止标志位
31 | float Target_A, Target_B;
32 |
33 | int sensorValue = 0;
34 |
35 | void (* resetFunc) (void) = 0;// Reset func
36 |
37 | //心率*************************************************
38 |
39 | #include
40 | #include "MAX30105.h"
41 |
42 | #include "heartRate.h"
43 |
44 | MAX30105 particleSensor;
45 |
46 | const byte RATE_SIZE = 4; //Increase this for more averaging. 4 is good.
47 | byte rates[RATE_SIZE]; //Array of heart rates
48 | byte rateSpot = 0;
49 | long lastBeat = 0; //Time at which the last beat occurred
50 |
51 | float beatsPerMinute;
52 | int beatAvg;
53 |
54 | //****************************************************
55 |
56 | void get_key(void)
57 | {
58 | if(digitalRead(key1) == HIGH && digitalRead(key2) == LOW)
59 | {turn =2 ;Velocity=-7;}
60 | else if(digitalRead(key1) == LOW && digitalRead(key2) == HIGH)
61 | {turn = -2;Velocity=-7;}
62 | else if(digitalRead(key1) == HIGH && digitalRead(key2) == HIGH)
63 | {turn = 0;Velocity=-7;}
64 | else if(digitalRead(key1) == LOW && digitalRead(key2) == LOW)
65 | {turn = 0;Velocity=0;}
66 | }
67 |
68 | /**************************************************************************
69 | 函数功能：赋值给PWM寄存器 作者：平衡小车之家
70 | 入口参数：PWM
71 | **************************************************************************/
72 | void Set_Pwm(int motora, int motorb) {
73 | if (motora >= 0) analogWrite(AIN1, motora), digitalWrite(AIN2, LOW); //赋值给PWM寄存器
74 | else digitalWrite(AIN2, HIGH), analogWrite(AIN1, 255 + motora); //赋值给PWM寄存器
75 |
76 | if (motorb >= 0) digitalWrite(BIN2, LOW), analogWrite(BIN1, motorb); //赋值给PWM寄存器
77 | else analogWrite(BIN1,255 + motorb), digitalWrite(BIN2, HIGH); //赋值给PWM寄存器
78 | }
79 | /**************************************************************************
80 | 函数功能：异常关闭电机
81 | 入口参数：电压
82 | 返回 值：1：异常 0：正常
83 | /**************************************************************************/
84 | unsigned char Turn_Off() {
85 | byte temp;
86 | if (Flag_Stop == 1) { //Flag_Stop置1或者电压太低关闭电机
87 | temp = 1;
88 | digitalWrite(AIN1, LOW); //电机驱动的电平控制
89 | digitalWrite(AIN2, LOW); //电机驱动的电平控制
90 | digitalWrite(BIN1, LOW); //电机驱动的电平控制
91 | digitalWrite(BIN2, LOW); //电机驱动的电平控制
92 | }
93 | else temp = 0;
94 | return temp;
95 | }
96 | /**************************************************************************
97 | 函数功能：小车运动数学模型
98 | 入口参数：速度和转角
99 | //**************************************************************************/
100 | void Kinematic_Analysis(float velocity, float turn) {
101 | Target_A=velocity+turn;
102 | Target_B=velocity-turn; //后轮差速
103 | }
104 |
105 | /**************************************************************************
106 | 函数功能：增量PI控制器
107 | 入口参数：编码器测量值，目标速度
108 | 返回 值：电机PWM
109 | 根据增量式离散PID公式
110 | pwm+=Kp[e（k）-e(k-1)]+Ki*e(k)+Kd[e(k)-2e(k-1)+e(k-2)]
111 | e(k)代表本次偏差
112 | e(k-1)代表上一次的偏差 以此类推
113 | pwm代表增量输出
114 | 在我们的速度控制闭环系统里面，只使用PI控制
115 | pwm+=Kp[e（k）-e(k-1)]+Ki*e(k)
116 | **************************************************************************/
117 | int Incremental_PI_A (int Encoder,int Target)
118 | {
119 | static float Bias,Pwm,Last_bias;
120 | Bias=Encoder-Target; //计算偏差
121 | Pwm+=Velocity_KP*(Bias-Last_bias)+Velocity_KI*Bias; //增量式PI控制器
122 | if(Pwm>255)Pwm=255; //限幅
123 | if(Pwm<-255)Pwm=-255; //限幅
124 | Last_bias=Bias; //保存上一次偏差
125 | return Pwm; //增量输出
126 | }
127 | int Incremental_PI_B (int Encoder,int Target)
128 | {
129 | static float Bias,Pwm,Last_bias;
130 | Bias=Encoder-Target; //计算偏差
131 | Pwm+=Velocity_KP*(Bias-Last_bias)+Velocity_KI*Bias; //增量式PI控制器
132 | if(Pwm>255)Pwm=255; //限幅
133 | if(Pwm<-255)Pwm=-255; //限幅
134 | Last_bias=Bias; //保存上一次偏差
135 | return Pwm; //增量输出
136 | }
137 |
138 | /*********函数功能：5ms控制函数 核心代码 作者：平衡小车之家*******/
139 | void control() {
140 | int Temp, Temp2, Motora, Motorb; //临时变量
141 | static unsigned char Position_Count,Voltage_Count; //位置控制分频用的变量
142 | sei();//全局中断开启
143 | Velocity_Left = Velocity_L; Velocity_L = 0; //读取左轮编码器数据，并清零，这就是通过M法测速（单位时间内的脉冲数）得到速度。
144 | Velocity_Right = Velocity_R; Velocity_R = 0; //读取右轮编码器数据，并清零
145 | Kinematic_Analysis(Velocity,turn); //小车运动学分析
146 | Motora = Incremental_PI_A(Target_A, Velocity_Left); //===速度PI控制器
147 | Motorb = Incremental_PI_B(Target_B, Velocity_Right); //===速度PI控制器
148 | Set_Pwm(Motora, Motorb); //如果不存在异常，使能电机
149 |
150 | get_key();
151 |
152 | //Serial.println("Velocity_Left:");
153 | //Serial.print(Velocity_Left);
154 | //Serial.print(",");
155 | //Serial.println("Velocity_Right:");
156 | //Serial.println(Velocity_Right);
157 | if (Temp == 1)Flag_Stop = !Flag_Stop;
158 | }
159 |
160 | /***********函数功能：初始化 相当于STM32里面的Main函数 作者：平衡小车之家************/
161 | void setup() {
162 | char error;
163 | pinMode(AIN1, OUTPUT); //电机控制引脚
164 | pinMode(AIN2, OUTPUT); //电机控制引脚，
165 | pinMode(BIN1, OUTPUT); //电机速度控制引脚
166 | pinMode(BIN2, OUTPUT); //电机速度控制引脚
167 |
168 | pinMode(ENCODER_L, INPUT); //编码器引脚
169 | pinMode(DIRECTION_L, INPUT); //编码器引脚
170 | pinMode(ENCODER_R, INPUT); //编码器引脚
171 | pinMode(DIRECTION_R, INPUT); //编码器引脚
172 |
173 | pinMode(key1, INPUT);
174 | pinMode(key2, INPUT);
175 |
176 | delay(200); //延时等待初始化完成
177 | attachInterrupt(0, READ_ENCODER_R, CHANGE); //开启外部中断 编码器接口1
178 | attachPinChangeInterrupt(4, READ_ENCODER_L, CHANGE); //开启外部中断 编码器接口2
179 |
180 | MsTimer2::set(10, control); //使用Timer2设置5ms定时中断
181 | MsTimer2::start(); //中断使能
182 |
183 |
184 | Serial.begin(9600); //开启串口
185 | // Serial.begin(9600);
186 |
187 | //心率*************************************************
188 |
189 | if (!particleSensor.begin(Wire, I2C_SPEED_FAST)) //Use default I2C port, 400kHz speed
190 | {
191 | Serial.println("MAX30105 was not found. Please check wiring/power. ");
192 | while (1);
193 | }
194 | Serial.println("Place your index finger on the sensor with steady pressure.");
195 |
196 | particleSensor.setup(); //Configure sensor with default settings
197 | particleSensor.setPulseAmplitudeRed(0x0A); //Turn Red LED to low to indicate sensor is running
198 | particleSensor.setPulseAmplitudeGreen(0); //Turn off Green LED
199 |
200 | //心率*************************************************
201 | }
202 |
203 | /******函数功能：主循环程序体*******/
204 | void loop(){
205 | //Serial.print("Left: ");
206 | //Serial.println(Velocity_Left);
207 | // Serial.print("Right: ");
208 | // Serial.println(Velocity_Right);
209 | // delay(500);
210 | sensorValue = analogRead(A0);
211 | Serial.print("ABC");
212 | Serial.print(sensorValue);
213 | //心率*************************************************
214 |
215 | long irValue = particleSensor.getIR();
216 |
217 | if (checkForBeat(irValue) == true)
218 | {
219 | //We sensed a beat!
220 | long delta = millis() - lastBeat;
221 | lastBeat = millis();
222 |
223 | beatsPerMinute = 60 / (delta / 1000.0);
224 |
225 | if (beatsPerMinute < 255 && beatsPerMinute > 20)
226 | {
227 | rates[rateSpot++] = (byte)beatsPerMinute; //Store this reading in the array
228 | rateSpot %= RATE_SIZE; //Wrap variable
229 |
230 | //Take average of readings
231 | beatAvg = 0;
232 | for (byte x = 0 ; x < RATE_SIZE ; x++)
233 | beatAvg += rates[x];
234 | beatAvg /= RATE_SIZE;
235 | }
236 | }
237 | //Serial.print("IR=");
238 | //Serial.print(irValue);
239 | Serial.print("BPM=");
240 | // Serial.print(beatsPerMinute);
241 | // Serial.print(", Avg BPM=");
242 | Serial.print(beatAvg);
243 |
244 | // if (irValue < 50000)
245 | // Serial.print(" No finger?");
246 |
247 | // Serial.println();
248 |
249 | //心率*************************************************
250 | }
251 |
252 | /*****函数功能：外部中断读取编码器数据，具有二倍频功能 注意外部中断是跳变沿触发********/
253 | void READ_ENCODER_L() {
254 | if (digitalRead(ENCODER_L) == LOW) { //如果是下降沿触发的中断
255 | if (digitalRead(DIRECTION_L) == LOW) Velocity_L--; //根据另外一相电平判定方向
256 | else Velocity_L++;
257 | }
258 | else { //如果是上升沿触发的中断
259 | if (digitalRead(DIRECTION_L) == LOW) Velocity_L++; //根据另外一相电平判定方向
260 | else Velocity_L--;
261 | }
262 | }
263 |
264 | /*****函数功能：外部中断读取编码器数据，具有二倍频功能 注意外部中断是跳变沿触发********/
265 | void READ_ENCODER_R() {
266 | if (digitalRead(ENCODER_R) == LOW) { //如果是下降沿触发的中断
267 | if (digitalRead(DIRECTION_R) == LOW) Velocity_R++;//根据另外一相电平判定方向
268 | else Velocity_R--;
269 | }
270 | else { //如果是上升沿触发的中断
271 | if (digitalRead(DIRECTION_R) == LOW) Velocity_R--; //根据另外一相电平判定方向
272 | else Velocity_R++;
273 | }
274 | }
275 |
--------------------------------------------------------------------------------
/pick_up_rx.v:
--------------------------------------------------------------------------------
1 | module pick_up_rx(
2 | input clk,
3 | input rst_n,
4 | input [7:0] data_rx,
5 | input rx_int,//当uart_rx模块接收完对方的数据后，传给uart_tx,此为标志位，标志uart_tx要开始工作
6 | output [383:0] data_rx_end,
7 | output [47:0] ymr_out,
8 | output [31:0] time_out
9 | );
10 |
11 | //-------------------------------------------------------
12 | //每个8位数据接收完整的标志
13 | reg [1:0] rx_int_r;
14 | always@(posedge clk or negedge rst_n)begin
15 | if(!rst_n) begin
16 | rx_int_r[0] <= 1'b0;
17 | rx_int_r[1] <= 1'b0;
18 | end
19 | else begin
20 | rx_int_r[0] <= rx_int;
21 | rx_int_r[1] <= rx_int_r[0];
22 | end
23 | end
24 |
25 | wire nege_edge = rx_int_r[1] & ~rx_int_r[0];//下降沿
26 |
27 |
28 | //---------------------------------------------------
29 | reg [7:0] data_rx_r;//用来接收传过来的data_rx
30 | //将rx接来的数据存下来
31 | always@(posedge clk or negedge rst_n)begin
32 | if(!rst_n) begin
33 | data_rx_r <= 8'd0;
34 | end
35 | else if(nege_edge)begin
36 | data_rx_r <= data_rx;
37 | end
38 | end
39 |
40 | reg detected_o;
41 | parameter length = 7; //更方便地更改状态长度
42 |
43 | parameter [length-1 : 0] //one-hot code
44 | S_IDLE = 7'b0000001,
45 | S_State1 = 7'b0000010,
46 | S_State2 = 7'b0000100,
47 | S_State3 = 7'b0001000,
48 | S_State4 = 7'b0010000,
49 | S_State5 = 7'b0100000,
50 | S_State6 = 7'b1000000;
51 |
52 | reg [length-1 : 0] c_state;
53 | reg [length-1 : 0] n_state;
54 | //三段式状态机
55 | always @(posedge clk or negedge rst_n) begin
56 | if (!rst_n) begin
57 | c_state <= S_IDLE; // reset低电平复位
58 | end
59 | else begin
60 | c_state <= n_state; //next state logic
61 | end
62 | end
63 |
64 | always @(*) begin //state register
65 | case(c_state)
66 | S_IDLE :
67 | if (data_rx_r == 8'h24 && nege_edge)//$
68 | n_state = S_State1;
69 | else
70 | n_state = S_IDLE;
71 | S_State1 :
72 | if (data_rx_r == 8'h47 && nege_edge)//G
73 | n_state = S_State2;
74 | else
75 | n_state = S_State1;
76 | S_State2 :
77 | if (data_rx_r == 8'h50 && nege_edge)//P
78 | n_state = S_State3;
79 | else
80 | n_state = S_State2;
81 | S_State3 :
82 | if (data_rx_r == 8'h52 && nege_edge)//R//G
83 | n_state = S_State4;
84 | else
85 | n_state = S_State3;
86 | S_State4 :
87 | if (data_rx_r == 8'h4D && nege_edge)//M//L
88 | n_state = S_State5;
89 | else
90 | n_state = S_State4;
91 | S_State5 :
92 | if (data_rx_r == 8'h43 && nege_edge)//C//L
93 | n_state = S_State6;
94 | else
95 | n_state = S_State5;
96 | S_State6 :
97 | if (data_rx_r && nege_edge)
98 | n_state = S_IDLE;
99 | else
100 | n_state = S_State4;
101 | default :
102 | n_state = S_IDLE;
103 | endcase
104 | end
105 |
106 | //状态机输出output logic
107 | always @ (posedge clk or negedge rst_n) begin
108 | if(!rst_n) begin
109 | detected_o <= 1'b0;
110 | end
111 | else if( c_state == S_State6) begin
112 | detected_o <= 1'b1;
113 | end
114 | else begin
115 | detected_o <= 1'b0;
116 | end
117 | end
118 |
119 | ///检测到上升沿信号后持续输出高电平
120 | reg [3:0] num; //包传到哪个数据了
121 | // reg a_flag; //UTC位置标识位
122 | reg start_reg;
123 | reg timeout;
124 | always@(posedge clk)
125 | start_reg <= detected_o;
126 |
127 | reg [3:0] count;
128 | always@(posedge clk or negedge rst_n) begin
129 | if (!rst_n)
130 | timeout <= 0;
131 | else if(start_reg == 0 && detected_o ==1)
132 | timeout <= 1;
133 | else if(count == 4'd10)
134 | timeout <= 0;
135 | else
136 | timeout <= timeout;
137 | end
138 | /////
139 |
140 | reg [7:0] data_pickup_r;//用来提取接收传过来的data_rx
141 | //将rx接来的数据存下来
142 | always@(posedge clk or negedge rst_n)begin
143 | if(!rst_n) begin
144 | data_pickup_r <= 8'd0;
145 | end
146 | else if(timeout) begin
147 | data_pickup_r <= data_rx_r;
148 | end
149 | end
150 |
151 | // reg [3:0] count;
152 | always@(posedge clk or negedge rst_n)
153 | begin
154 | if(!rst_n)
155 | count <= 0;
156 | else if(data_pickup_r==8'h2C && nege_edge)
157 | count <= count + 1;
158 | else if(start_reg == 0 && detected_o ==1)
159 | count <= 0;
160 | else
161 | count <= count;
162 | end
163 |
164 | //-------------------------------------------------------
165 | //判断包头，确定开始，以及识别号
166 | always@(posedge clk or negedge rst_n)begin
167 | if(!rst_n) num <= 4'd0;
168 | else if(start_reg == 0 && detected_o ==1) num <= 0;
169 | else if(data_pickup_r==8'h2C&&nege_edge ) num <= 4'd1;
170 | else if(timeout&&nege_edge) num <= num + 1'b1;
171 | else num <= num;
172 | end
173 |
174 |
175 | //-----------------------------------------------------
176 | //根据标识位分类给寄存器赋值
177 | reg [79:0] Latitude ; //纬度
178 | reg [87:0] longitude ; //经度
179 | reg [71:0] UTC_time ; //UTC时间
180 | reg [47:0] ddmmyy;
181 | reg [7:0] E_flag;
182 | reg [7:0] N_flag;
183 | always@(posedge clk or negedge rst_n)begin
184 | if(!rst_n) begin
185 | Latitude <= 0;
186 | longitude <= 0;
187 | UTC_time <= 0;
188 | ddmmyy <= 0;
189 | E_flag <= 0;
190 | N_flag <= 0;
191 | end
192 | else if(count == 4'd1&&nege_edge&& data_pickup_r!=8'h2C )begin
193 | case(num)
194 | 4'd9: UTC_time[71:64] <= data_pickup_r;
195 | 4'd8: UTC_time[63:56] <= data_pickup_r;
196 | 4'd7: UTC_time[55:48] <= data_pickup_r;
197 | 4'd6: UTC_time[47:40] <= data_pickup_r;
198 | 4'd5: UTC_time[39:32] <= data_pickup_r;
199 | 4'd4: UTC_time[31:24] <= data_pickup_r;
200 | 4'd3: UTC_time[23:16] <= data_pickup_r;
201 | 4'd2: UTC_time[15:8] <= data_pickup_r;//di
202 | 4'd1: UTC_time[7:0] <= data_pickup_r;//gao
203 | default:;
204 | endcase
205 | end
206 | else if(count == 4'd3&&nege_edge&& data_pickup_r!=8'h2C)begin
207 | case(num)
208 | 4'd10: Latitude[79:72] <= data_pickup_r;//
209 | 4'd9: Latitude[71:64] <= data_pickup_r;//
210 | 4'd8: Latitude[63:56] <= data_pickup_r;//
211 | 4'd7: Latitude[55:48] <= data_pickup_r;//
212 | 4'd6: Latitude[47:40] <= data_pickup_r;//
213 | 4'd5: Latitude[23:16] <= data_pickup_r;//9
214 | 4'd4: Latitude[39:32] <= data_pickup_r;//0
215 | 4'd3: Latitude[31:24] <= data_pickup_r;//小数点
216 | 4'd2: Latitude[15:8] <= data_pickup_r;//4
217 | 4'd1: Latitude[7:0] <= data_pickup_r;//3
218 | default:;
219 | endcase
220 | end
221 | else if(count == 4'd4&&nege_edge&& data_pickup_r!=8'h2C)begin
222 | N_flag[7:0] <= data_pickup_r;//N
223 | end
224 | else if(count == 4'd5&&nege_edge&& data_pickup_r!=8'h2C)begin
225 | case(num)
226 | 4'd11: longitude[87:80] <= data_pickup_r;
227 | 4'd10: longitude[79:72] <= data_pickup_r;
228 | 4'd9: longitude[71:64] <= data_pickup_r;
229 | 4'd8: longitude[63:56] <= data_pickup_r;
230 | 4'd7: longitude[55:48] <= data_pickup_r;
231 | 4'd6: longitude[31:24] <= data_pickup_r;//3
232 | 4'd5: longitude[47:40] <= data_pickup_r;//5
233 | 4'd4: longitude[39:32] <= data_pickup_r;//小数点
234 | 4'd3: longitude[23:16] <= data_pickup_r;//8
235 | 4'd2: longitude[15:8] <= data_pickup_r;//0
236 | 4'd1: longitude[7:0] <= data_pickup_r;//1
237 | default:;
238 | endcase
239 | end
240 | else if(count == 4'd6&&nege_edge&& data_pickup_r!=8'h2C)begin
241 | E_flag[7:0] <= data_pickup_r;//E
242 | end
243 | else if(count == 4'd9&&nege_edge&& data_pickup_r!=8'h2C)begin
244 | case(num)
245 | 4'd6: ddmmyy[15:8] <= data_pickup_r;//8
246 | 4'd5: ddmmyy[7:0] <= data_pickup_r;//1
247 | 4'd4: ddmmyy[31:24] <= data_pickup_r;//0
248 | 4'd3: ddmmyy[23:16] <= data_pickup_r;//1
249 | 4'd2: ddmmyy[47:40] <= data_pickup_r;//1
250 | 4'd1: ddmmyy[39:32] <= data_pickup_r;//3
251 | default:;
252 | endcase
253 | end
254 | end
255 |
256 | reg [15:0] UTC_time_OUT;
257 | //数值换算
258 | always@(posedge clk or negedge rst_n)begin
259 | if(!rst_n)
260 | UTC_time_OUT <= 0;
261 | else if(UTC_time[7:0]==8'h30&&nege_edge) begin
262 | if((UTC_time[15:8] == 8'h30) || (UTC_time[15:8] == 8'h31)) begin
263 | UTC_time_OUT[15:8] <= UTC_time[15:8] + 8'd8;
264 | UTC_time_OUT[7:0] <= UTC_time[7:0];
265 | end
266 | else begin
267 | UTC_time_OUT[7:0] <= 8'h31;
268 | UTC_time_OUT[15:8] <= UTC_time[15:8] - 8'd2;
269 | end
270 | end
271 | else if(UTC_time[7:0]==8'h31&&nege_edge) begin
272 | if((UTC_time[15:8] == 8'h30) || (UTC_time[15:8] == 8'h31)) begin
273 | UTC_time_OUT[15:8] <= UTC_time[15:8] + 8'd8;
274 | UTC_time_OUT[7:0] <= UTC_time[7:0];
275 | end
276 | else if((8'h32 <= UTC_time[15:8] <= 8'h35)&&nege_edge) begin
277 | UTC_time_OUT[7:0] <= 8'h32;
278 | UTC_time_OUT[15:8] <= UTC_time[15:8] - 8'd2;
279 | end
280 | else begin
281 | UTC_time_OUT[7:0] <= 8'h30;
282 | UTC_time_OUT[15:8] <= UTC_time[15:8] - 8'd6;
283 | end
284 | end
285 | else if(UTC_time[7:0]==8'h32&&nege_edge) begin
286 | UTC_time_OUT[7:0] <= 8'h30;
287 | UTC_time_OUT[15:8] <= UTC_time[15:8] + 8'd4;
288 | end
289 | else
290 | UTC_time_OUT <= UTC_time_OUT;
291 | end
292 | //经度 //纬度
293 | // assign data_rx_end = {N_flag,Latitude,8'h0A,E_flag,longitude,8'h0A,UTC_time[71:16],UTC_time_OUT,8'h3A,8'h74,8'h0A,ddmmyy,8'h3A,8'h61,8'h74,8'h61,8'h64};
294 |
295 |
296 | wire [79:0] Latitude_1 =0;
297 | wire [87:0] longitude_1 =0;
298 | wire [71:0] UTC_time_1 =0;
299 | wire [15:0] UTC_time_OUT_1 =0;
300 | wire [47:0] ddmmyy_1 =0;
301 |
302 |
303 | assign data_rx_end = {N_flag,Latitude_1,8'h0A,E_flag,longitude_1,8'h0A,UTC_time_1[71:16],UTC_time_OUT_1,8'h3A,8'h74,8'h0A,ddmmyy_1,8'h3A,8'h61,8'h74,8'h61,8'h64};
304 |
305 | assign ymr_out = ddmmyy;
306 | assign time_out = {UTC_time_OUT,UTC_time[31:16]};
307 |
308 | endmodule
309 |
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