├── README.md ├── matlab_sim ├── PRBS.m ├── add_cp.m ├── cp_real_output.txt ├── hermitian_conj.m ├── insert_pilot.m ├── map.m ├── ofdm_sim.m └── test_fpgadout.m ├── scripts ├── tx_msim.tcl └── tx_sim.do ├── sim ├── cp_imag_output.txt ├── cp_real_output.txt └── vsim.wlf ├── source ├── clk │ ├── clk_pll.qip │ ├── clk_pll.v │ ├── clk_pll.vo │ ├── clk_pll │ │ ├── clk_pll_0002.qip │ │ └── clk_pll_0002.v │ ├── clk_pll_0002.v │ ├── clk_pll_sim.do │ ├── clk_pll_tb.v │ └── sim_lib │ │ ├── 220model.v │ │ ├── altera_lnsim.sv │ │ ├── altera_mf.v │ │ ├── altera_primitives.v │ │ ├── cyclonev_atoms.v │ │ ├── cyclonev_atoms_ncrypt.v │ │ ├── cyclonev_hmi_atoms_ncrypt.v │ │ ├── cyclonev_hssi_atoms.v │ │ ├── cyclonev_hssi_atoms_ncrypt.v │ │ ├── cyclonev_pcie_hip_atoms.v │ │ ├── cyclonev_pcie_hip_atoms_ncrypt.v │ │ └── sgate.v ├── cp │ ├── add_cyclic_prefix.v │ ├── add_cyclic_prefix_tb.v │ ├── cp_ram2port.v │ ├── cp_sim.do │ ├── data │ │ ├── im_data.txt │ │ └── re_data.txt │ ├── sim_lib │ │ ├── altera_mf.v │ │ └── cp_ram2port.v │ └── vsim.wlf ├── hermitian │ ├── data │ │ ├── im_data.txt │ │ ├── imag.txt │ │ ├── re_data.txt │ │ └── real.txt │ ├── her_ram2port.v │ ├── her_sim.do │ ├── hermitian.v │ ├── hermitian_tb.v │ ├── sim_lib │ │ └── altera_mf.v │ └── vsim.wlf ├── ifft │ ├── Readme.txt │ ├── ifft_project │ │ ├── .qsys_edit │ │ │ ├── fft_ipcore.xml │ │ │ ├── fft_ipcore_schematic.nlv │ │ │ ├── filters.xml │ │ │ └── preferences.xml │ │ ├── fft_ipcore.qsys │ │ ├── fft_ipcore.sopcinfo │ │ ├── fft_ipcore │ │ │ ├── fft_ii_0_example_design_model.m │ │ │ ├── fft_ii_0_example_design_tb.m │ │ │ ├── fft_ipcore.bsf │ │ │ ├── fft_ipcore.cmp │ │ │ ├── fft_ipcore.html │ │ │ ├── fft_ipcore.xml │ │ │ ├── fft_ipcore_generation.rpt │ │ │ ├── src │ │ │ │ ├── altera_avalon_clock_source.sv │ │ │ │ ├── altera_avalon_reset_source.sv │ │ │ │ ├── altera_avalon_st_sink_bfm.sv │ │ │ │ ├── altera_avalon_st_source_bfm.sv │ │ │ │ ├── avalon_utilities_pkg.sv │ │ │ │ ├── fft_ii_0_example_design.v │ │ │ │ ├── fft_ii_0_example_design_core.vo │ │ │ │ ├── fft_ii_0_example_design_core_1n64cos.hex │ │ │ │ ├── fft_ii_0_example_design_core_1n64sin.hex │ │ │ │ ├── fft_ii_0_example_design_core_2n64cos.hex │ │ │ │ ├── fft_ii_0_example_design_core_2n64sin.hex │ │ │ │ ├── fft_ii_0_example_design_core_3n64cos.hex │ │ │ │ ├── fft_ii_0_example_design_core_3n64sin.hex │ │ │ │ ├── fft_ii_0_example_design_tb.v │ │ │ │ ├── fft_ii_0_example_design_test_program.sv │ │ │ │ └── verbosity_pkg.sv │ │ │ ├── synthesis │ │ │ │ ├── fft_ipcore.debuginfo │ │ │ │ ├── fft_ipcore.qip │ │ │ │ ├── fft_ipcore.v │ │ │ │ └── submodules │ │ │ │ │ ├── altera_fft_dual_port_ram.vhd │ │ │ │ │ ├── altera_fft_dual_port_rom.vhd │ │ │ │ │ ├── altera_fft_mult_add.vhd │ │ │ │ │ ├── altera_fft_single_port_rom.vhd │ │ │ │ │ ├── apn_fft_cmult_cpx.vhd │ │ │ │ │ ├── apn_fft_cmult_cpx2.vhd │ │ │ │ │ ├── apn_fft_mult_can.vhd │ │ │ │ │ ├── apn_fft_mult_cpx.vhd │ │ │ │ │ ├── apn_fft_mult_cpx_1825.v │ │ │ │ │ ├── asj_fft_1dp_ram.vhd │ │ │ │ │ ├── asj_fft_1tdp_rom.vhd │ │ │ │ │ ├── asj_fft_3dp_rom.vhd │ │ │ │ │ ├── asj_fft_3pi_mram.vhd │ │ │ │ │ ├── asj_fft_3tdp_rom.vhd │ │ │ │ │ ├── asj_fft_4dp_ram.vhd │ │ │ │ │ ├── asj_fft_6tdp_rom.vhd │ │ │ │ │ ├── asj_fft_alt_shift_tdl.vhd │ │ │ │ │ ├── asj_fft_bfp_ctrl.vhd │ │ │ │ │ ├── asj_fft_bfp_i.vhd │ │ │ │ │ ├── asj_fft_bfp_i_1pt.vhd │ │ │ │ │ ├── asj_fft_bfp_o.vhd │ │ │ │ │ ├── asj_fft_bfp_o_1pt.vhd │ │ │ │ │ ├── asj_fft_burst_ctrl.vhd │ │ │ │ │ ├── asj_fft_burst_ctrl_de.vhd │ │ │ │ │ ├── asj_fft_burst_ctrl_qe.vhd │ │ │ │ │ ├── asj_fft_cmult_can.vhd │ │ │ │ │ ├── asj_fft_cmult_std.vhd │ │ │ │ │ ├── asj_fft_cnt_ctrl.vhd │ │ │ │ │ ├── asj_fft_cnt_ctrl_de.vhd │ │ │ │ │ ├── asj_fft_cxb_addr.vhd │ │ │ │ │ ├── asj_fft_cxb_data.vhd │ │ │ │ │ ├── asj_fft_cxb_data_mram.vhd │ │ │ │ │ ├── asj_fft_cxb_data_r.vhd │ │ │ │ │ ├── asj_fft_data_ram.vhd │ │ │ │ │ ├── asj_fft_data_ram_dp.vhd │ │ │ │ │ ├── asj_fft_dataadgen.vhd │ │ │ │ │ ├── asj_fft_dft_bfp.vhd │ │ │ │ │ ├── asj_fft_dft_bfp_sgl.vhd │ │ │ │ │ ├── asj_fft_dp_mram.vhd │ │ │ │ │ ├── asj_fft_dpi_mram.vhd │ │ │ │ │ ├── asj_fft_dualstream.ocp │ │ │ │ │ ├── asj_fft_dualstream.vhd │ │ │ │ │ ├── asj_fft_in_write_sgl.vhd │ │ │ │ │ ├── asj_fft_lcm_mult.vhd │ │ │ │ │ ├── asj_fft_lcm_mult_2m.vhd │ │ │ │ │ ├── asj_fft_lpp.vhd │ │ │ │ │ ├── asj_fft_lpp_serial.vhd │ │ │ │ │ ├── asj_fft_lpp_serial_r2.vhd │ │ │ │ │ ├── asj_fft_lpprdadgen.vhd │ │ │ │ │ ├── asj_fft_lpprdadr2gen.vhd │ │ │ │ │ ├── asj_fft_m_k_counter.vhd │ │ │ │ │ ├── asj_fft_mult_add.vhd │ │ │ │ │ ├── asj_fft_pround.vhd │ │ │ │ │ ├── asj_fft_sglstream.ocp │ │ │ │ │ ├── asj_fft_sglstream.vhd │ │ │ │ │ ├── asj_fft_si_de_so_b.ocp │ │ │ │ │ ├── asj_fft_si_de_so_b.vhd │ │ │ │ │ ├── asj_fft_si_de_so_bb.ocp │ │ │ │ │ ├── asj_fft_si_de_so_bb.vhd │ │ │ │ │ ├── asj_fft_si_qe_so_b.ocp │ │ │ │ │ ├── asj_fft_si_qe_so_b.vhd │ │ │ │ │ ├── asj_fft_si_qe_so_bb.ocp │ │ │ │ │ ├── asj_fft_si_qe_so_bb.vhd │ │ │ │ │ ├── asj_fft_si_se_so_b.ocp │ │ │ │ │ ├── asj_fft_si_se_so_b.vhd │ │ │ │ │ ├── asj_fft_si_se_so_bb.ocp │ │ │ │ │ ├── asj_fft_si_se_so_bb.vhd │ │ │ │ │ ├── asj_fft_si_so_se_so_b.ocp │ │ │ │ │ ├── asj_fft_si_sose_so_b.ocp │ │ │ │ │ ├── asj_fft_si_sose_so_b.vhd │ │ │ │ │ ├── asj_fft_tdl.vhd │ │ │ │ │ ├── asj_fft_tdl_bit.vhd │ │ │ │ │ ├── asj_fft_tdl_bit_rst.vhd │ │ │ │ │ ├── asj_fft_tdl_rst.vhd │ │ │ │ │ ├── asj_fft_twadgen.vhd │ │ │ │ │ ├── asj_fft_twadgen_dual.vhd │ │ │ │ │ ├── asj_fft_twadsogen.vhd │ │ │ │ │ ├── asj_fft_twadsogen_q.vhd │ │ │ │ │ ├── asj_fft_twid_rom_tdp.vhd │ │ │ │ │ ├── asj_fft_twiddle_ctrl_qe.vhd │ │ │ │ │ ├── asj_fft_unbburst_ctrl.vhd │ │ │ │ │ ├── asj_fft_unbburst_ctrl_de.vhd │ │ │ │ │ ├── asj_fft_unbburst_ctrl_qe.vhd │ │ │ │ │ ├── asj_fft_unbburst_sose_ctrl.vhd │ │ │ │ │ ├── asj_fft_wrengen.vhd │ │ │ │ │ ├── asj_fft_wrswgen.vhd │ │ │ │ │ ├── auk_dspip_avalon_streaming_block_sink.vhd │ │ │ │ │ ├── auk_dspip_avalon_streaming_block_source.vhd │ │ │ │ │ ├── auk_dspip_avalon_streaming_controller.vhd │ │ │ │ │ ├── auk_dspip_avalon_streaming_sink.vhd │ │ │ │ │ ├── auk_dspip_avalon_streaming_source.vhd │ │ │ │ │ ├── auk_dspip_lib_pkg.vhd │ │ │ │ │ ├── auk_dspip_math_pkg.vhd │ │ │ │ │ ├── auk_dspip_roundsat.vhd │ │ │ │ │ ├── auk_dspip_text_pkg.vhd │ │ │ │ │ ├── auk_fft_pkg.vhd │ │ │ │ │ ├── fft_ipcore_fft_ii_0.sv │ │ │ │ │ ├── fft_ipcore_fft_ii_0_1n64cos.hex │ │ │ │ │ ├── fft_ipcore_fft_ii_0_1n64sin.hex │ │ │ │ │ ├── fft_ipcore_fft_ii_0_2n64cos.hex │ │ │ │ │ ├── fft_ipcore_fft_ii_0_2n64sin.hex │ │ │ │ │ ├── fft_ipcore_fft_ii_0_3n64cos.hex │ │ │ │ │ ├── fft_ipcore_fft_ii_0_3n64sin.hex │ │ │ │ │ ├── fft_pack.vhd │ │ │ │ │ └── twid_rom.vhd │ │ │ └── test_data │ │ │ │ ├── fft_ii_0_example_design_imag_input.txt │ │ │ │ ├── fft_ii_0_example_design_inverse_report.txt │ │ │ │ └── fft_ii_0_example_design_real_input.txt │ │ ├── ifft_clac.qpf │ │ ├── ifft_clac.qsf │ │ └── ifft_clac.v │ └── ifft_sim │ │ ├── data │ │ ├── exp.txt │ │ ├── im_din.txt │ │ ├── im_dout.txt │ │ ├── re_din.txt │ │ └── re_dout.txt │ │ ├── fft_core.vo │ │ ├── fft_core_1n64cos.hex │ │ ├── fft_core_1n64sin.hex │ │ ├── fft_core_2n64cos.hex │ │ ├── fft_core_2n64sin.hex │ │ ├── fft_core_3n64cos.hex │ │ ├── fft_core_3n64sin.hex │ │ ├── ifft_clac.v │ │ ├── ifft_clac_tb.v │ │ ├── ifft_sim.do │ │ ├── modelsim.ini │ │ ├── sim_lib │ │ ├── 220model.v │ │ ├── altera_lnsim.sv │ │ ├── altera_mf.v │ │ ├── altera_primitives.v │ │ ├── cyclonev_atoms.v │ │ ├── cyclonev_atoms_ncrypt.v │ │ ├── cyclonev_hmi_atoms_ncrypt.v │ │ ├── cyclonev_hssi_atoms.v │ │ ├── cyclonev_hssi_atoms_ncrypt.v │ │ ├── cyclonev_pcie_hip_atoms.v │ │ ├── cyclonev_pcie_hip_atoms_ncrypt.v │ │ └── sgate.v │ │ └── vsim.wlf ├── map │ ├── QAM16_MAP.v │ ├── QAM16_MAP_tb.v │ ├── QAM_MAP_Test.m │ ├── data_in.txt │ ├── qam_sim.do │ └── vsim.wlf ├── pilot │ ├── Insert_Pilot.v │ ├── Insert_Pilot_tb.v │ ├── Readme.txt │ ├── create_inidata.m │ ├── data │ │ ├── im_data.txt │ │ ├── pilot_data.mif │ │ └── re_data.txt │ ├── pilot_data.mif │ ├── pilot_ram2port.qip │ ├── pilot_ram2port.v │ ├── pilot_sim.do │ ├── sim_lib │ │ └── altera_mf.v │ └── vsim.wlf ├── prbs │ ├── prbs15.v │ ├── prbs15_sim.do │ ├── prbs15_tb.v │ └── rom │ │ ├── prbs_data.mif │ │ ├── prbs_data.qip │ │ ├── prbs_data.v │ │ ├── prbs_data_inst.v │ │ └── prbs_gen_data.m ├── scale_clip │ ├── data │ │ ├── exp.txt │ │ ├── im_din.txt │ │ ├── im_dout.txt │ │ ├── re_din.txt │ │ └── re_dout.txt │ ├── sc_sim.do │ ├── scale_clip.v │ └── scale_clip_tb.v └── tx_top.v └── tb └── tx_top_tb.v /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/README.md -------------------------------------------------------------------------------- /matlab_sim/PRBS.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/matlab_sim/PRBS.m -------------------------------------------------------------------------------- /matlab_sim/add_cp.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/matlab_sim/add_cp.m -------------------------------------------------------------------------------- /matlab_sim/hermitian_conj.m: -------------------------------------------------------------------------------- 1 | function conj_data = hermitian_conj(data_din) 2 | %%对输入序列进行 共轭对称 变换 3 | %%共轭对称求法 4 | %% Xe(n) = 0.5*( X(n) + conj(X(N-n)) ) 0<= n <=N-1 5 | %% 6 | [conja,conjb] = size(data_din); 7 | 8 | condata = conj(data_din); 9 | conj_data = zeros(conja,conjb); 10 | 11 | for i = 1:conja 12 | conj_data(i,1) = 0.5*( data_din(i,1) + condata(i,1) ); 13 | for j = 2:conjb 14 | conj_data(i,j) = 0.5*( data_din(i,j) + condata(i, conjb+2-j) ); 15 | end 16 | end 17 | 18 | -------------------------------------------------------------------------------- /matlab_sim/insert_pilot.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/matlab_sim/insert_pilot.m -------------------------------------------------------------------------------- /matlab_sim/map.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/matlab_sim/map.m -------------------------------------------------------------------------------- /matlab_sim/ofdm_sim.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/matlab_sim/ofdm_sim.m -------------------------------------------------------------------------------- /matlab_sim/test_fpgadout.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/matlab_sim/test_fpgadout.m -------------------------------------------------------------------------------- /scripts/tx_msim.tcl: -------------------------------------------------------------------------------- 1 | ## QUARTUS 15.0.0 Build 145 04/22/2015 SJ Full Version 2 | #------------------------------------------------------------------------------ 3 | # Directory locations 4 | 5 | set quartus_sim_lib "D:/altera/15.0/quartus/eda/sim_lib" 6 | set quartus_sim_lib_mentor "D:/altera/15.0/quartus/eda/sim_lib/mentor" 7 | 8 | set proj_topdir ".." 9 | 10 | set workdir "$proj_topdir/sim" 11 | set srcdir "$proj_topdir/source" 12 | set scriptdir "$proj_topdir/scripts" 13 | set tbdir "$proj_topdir/tb" 14 | 15 | #------------------------------------------------------------------------------ 16 | # Set Simulation timing parameters 17 | set SimTime 409600 18 | 19 | set TimeResolution 1ps 20 | 21 | set bForceRecompile 0 22 | 23 | # Project name 24 | set proj_nam "ofdm_tx" 25 | 26 | # Close existing ModelSim simulation 27 | quit -sim 28 | 29 | # Top level 30 | set top_level "tx_top_tb" 31 | 32 | #------------------------------------------------------------------------------ 33 | # Open/Create Modelsim Project 34 | #------------------------------------------------------------------------------ 35 | if {[file exist [project env]] > 0} {project close} 36 | cd $workdir 37 | 38 | if {[file exist "${workdir}//${proj_nam}.mpf"] == 0} { 39 | project new ${workdir}// ${proj_nam} 40 | } else { 41 | project open ${proj_nam} 42 | } 43 | 44 | #------------------------------------------------------------------------------ 45 | # Create WORK directory IF it does not already exist 46 | #------------------------------------------------------------------------------ 47 | # Create default work directory if not present 48 | if {[file exist work] ==0} { 49 | exec vlib work 50 | exec vmap work work} 51 | 52 | #------------------------------------------------------------------------------ 53 | # Compile ALTERA LIBRARIES 54 | #------------------------------------------------------------------------------ 55 | vlib altera_ver 56 | vmap altera_ver altera_ver 57 | vlog -vlog01compat -work altera_ver $quartus_sim_lib/altera_primitives.v 58 | 59 | vlib lpm_ver 60 | vmap lpm_ver lpm_ver 61 | vlog -vlog01compat -work lpm_ver $quartus_sim_lib/220model.v 62 | 63 | vlib sgate_ver 64 | vmap sgate_ver sgate_ver 65 | vlog -vlog01compat -work sgate_ver $quartus_sim_lib/sgate.v 66 | 67 | vlib altera_mf_ver 68 | vmap altera_mf_ver altera_mf_ver 69 | vlog -vlog01compat -work altera_mf_ver $quartus_sim_lib/altera_mf.v 70 | 71 | vlib altera_lnsim_ver 72 | vmap altera_lnsim_ver altera_lnsim_ver 73 | vlog -sv -work altera_lnsim_ver $quartus_sim_lib/altera_lnsim.sv 74 | 75 | vlib cyclonev_hssi_ver 76 | vmap cyclonev_hssi_ver cyclonev_hssi_ver 77 | vlog -vlog01compat -work cyclonev_hssi_ver $quartus_sim_lib/cyclonev_hssi_atoms.v 78 | vlog -work cyclonev_hssi_ver $quartus_sim_lib_mentor/cyclonev_hssi_atoms_ncrypt.v 79 | 80 | vlib cyclonev_pcie_hip_ver 81 | vmap cyclonev_pcie_hip_ver cyclonev_pcie_hip_ver 82 | vlog -vlog01compat -work cyclonev_pcie_hip_ver $quartus_sim_lib/cyclonev_pcie_hip_atoms.v 83 | vlog -work cyclonev_pcie_hip_ver $quartus_sim_lib_mentor/cyclonev_pcie_hip_atoms_ncrypt.v 84 | 85 | vlib cyclonev_ver 86 | vmap cyclonev_ver cyclonev_ver 87 | vlog -vlog01compat -work cyclonev_ver $quartus_sim_lib/cyclonev_atoms.v 88 | vlog -work cyclonev_ver $quartus_sim_lib_mentor/cyclonev_atoms_ncrypt.v 89 | vlog -work cyclonev_ver $quartus_sim_lib_mentor/cyclonev_hmi_atoms_ncrypt.v 90 | #------------------------------------------------------------------------------ 91 | # Compile Source Verilog files 92 | #------------------------------------------------------------------------------ 93 | vlog -vlog01compat -work work "$srcdir/clk/clk_pll.vo" 94 | vlog -vlog01compat -work work "$srcdir/clk/clk_pll_0002.v" 95 | vlog -vlog01compat -work work "$srcdir/clk/clk_pll.v" 96 | 97 | vlog -vlog01compat -work work "$srcdir/prbs/prbs15.v" 98 | 99 | vlog -vlog01compat -work work "$srcdir/map/QAM16_MAP.v" 100 | 101 | vlog -vlog01compat -work work "$srcdir/pilot/Insert_Pilot.v" 102 | vlog -vlog01compat -work work "$srcdir/pilot/pilot_ram2port.v" 103 | 104 | vlog -vlog01compat -work work "$srcdir/hermitian/hermitian.v" 105 | vlog -vlog01compat -work work "$srcdir/hermitian/her_ram2port.v" 106 | 107 | vlog -vlog01compat -work work "$srcdir/ifft/ifft_sim/ifft_clac.v" 108 | vlog -vlog01compat -work work "$srcdir/ifft/ifft_sim/fft_core.vo" 109 | 110 | vlog -vlog01compat -work work "$srcdir/scale_clip/scale_clip.v" 111 | 112 | vlog -vlog01compat -work work "$srcdir/cp/add_cyclic_prefix.v" 113 | vlog -vlog01compat -work work "$srcdir/cp/cp_ram2port.v" 114 | 115 | vlog -vlog01compat -work work "$srcdir/tx_top.v" 116 | vlog -vlog01compat -work work "$tbdir/tx_top_tb.v" 117 | 118 | 119 | #------------------------------------------------------------------------------ 120 | # Copying files over to simulation directory 121 | #------------------------------------------------------------------------------ 122 | file copy -force $srcdir/pilot/pilot_data.mif $workdir 123 | 124 | file copy -force $srcdir/ifft/ifft_sim/fft_core_1n64sin.hex $workdir 125 | file copy -force $srcdir/ifft/ifft_sim/fft_core_2n64sin.hex $workdir 126 | file copy -force $srcdir/ifft/ifft_sim/fft_core_3n64sin.hex $workdir 127 | file copy -force $srcdir/ifft/ifft_sim/fft_core_1n64cos.hex $workdir 128 | file copy -force $srcdir/ifft/ifft_sim/fft_core_2n64cos.hex $workdir 129 | file copy -force $srcdir/ifft/ifft_sim/fft_core_3n64cos.hex $workdir 130 | 131 | 132 | #------------------------------------------------------------------------------ 133 | # LOAD Top level entity for simulation 134 | #------------------------------------------------------------------------------ 135 | vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L cyclonev_ver -L work $top_level 136 | 137 | #------------------------------------------------------------------------------ 138 | # Load Waveform File 139 | #------------------------------------------------------------------------------ 140 | do $scriptdir/tx_sim.do 141 | 142 | # #------------------------------------------------------------------------------ 143 | # # Run Simulation 144 | # #------------------------------------------------------------------------------ 145 | set StdArithNoWarnings 1 146 | 147 | run $SimTime ns; -------------------------------------------------------------------------------- /sim/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/sim/vsim.wlf -------------------------------------------------------------------------------- /source/clk/clk_pll/clk_pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*clk_pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET OFF -to "*clk_pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*clk_pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /source/clk/clk_pll/clk_pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module clk_pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'locked' 17 | output wire locked 18 | ); 19 | 20 | altera_pll #( 21 | .fractional_vco_multiplier("false"), 22 | .reference_clock_frequency("50.0 MHz"), 23 | .operation_mode("direct"), 24 | .number_of_clocks(2), 25 | .output_clock_frequency0("20.000000 MHz"), 26 | .phase_shift0("0 ps"), 27 | .duty_cycle0(50), 28 | .output_clock_frequency1("80.000000 MHz"), 29 | .phase_shift1("0 ps"), 30 | .duty_cycle1(50), 31 | .output_clock_frequency2("0 MHz"), 32 | .phase_shift2("0 ps"), 33 | .duty_cycle2(50), 34 | .output_clock_frequency3("0 MHz"), 35 | .phase_shift3("0 ps"), 36 | .duty_cycle3(50), 37 | .output_clock_frequency4("0 MHz"), 38 | .phase_shift4("0 ps"), 39 | .duty_cycle4(50), 40 | .output_clock_frequency5("0 MHz"), 41 | .phase_shift5("0 ps"), 42 | .duty_cycle5(50), 43 | .output_clock_frequency6("0 MHz"), 44 | .phase_shift6("0 ps"), 45 | .duty_cycle6(50), 46 | .output_clock_frequency7("0 MHz"), 47 | .phase_shift7("0 ps"), 48 | .duty_cycle7(50), 49 | .output_clock_frequency8("0 MHz"), 50 | .phase_shift8("0 ps"), 51 | .duty_cycle8(50), 52 | .output_clock_frequency9("0 MHz"), 53 | .phase_shift9("0 ps"), 54 | .duty_cycle9(50), 55 | .output_clock_frequency10("0 MHz"), 56 | .phase_shift10("0 ps"), 57 | .duty_cycle10(50), 58 | .output_clock_frequency11("0 MHz"), 59 | .phase_shift11("0 ps"), 60 | .duty_cycle11(50), 61 | .output_clock_frequency12("0 MHz"), 62 | .phase_shift12("0 ps"), 63 | .duty_cycle12(50), 64 | .output_clock_frequency13("0 MHz"), 65 | .phase_shift13("0 ps"), 66 | .duty_cycle13(50), 67 | .output_clock_frequency14("0 MHz"), 68 | .phase_shift14("0 ps"), 69 | .duty_cycle14(50), 70 | .output_clock_frequency15("0 MHz"), 71 | .phase_shift15("0 ps"), 72 | .duty_cycle15(50), 73 | .output_clock_frequency16("0 MHz"), 74 | .phase_shift16("0 ps"), 75 | .duty_cycle16(50), 76 | .output_clock_frequency17("0 MHz"), 77 | .phase_shift17("0 ps"), 78 | .duty_cycle17(50), 79 | .pll_type("General"), 80 | .pll_subtype("General") 81 | ) altera_pll_i ( 82 | .rst (rst), 83 | .outclk ({outclk_1, outclk_0}), 84 | .locked (locked), 85 | .fboutclk ( ), 86 | .fbclk (1'b0), 87 | .refclk (refclk) 88 | ); 89 | endmodule 90 | 91 | -------------------------------------------------------------------------------- /source/clk/clk_pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | module clk_pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'outclk1' 14 | output wire outclk_1, 15 | 16 | // interface 'locked' 17 | output wire locked 18 | ); 19 | 20 | altera_pll #( 21 | .fractional_vco_multiplier("false"), 22 | .reference_clock_frequency("50.0 MHz"), 23 | .operation_mode("direct"), 24 | .number_of_clocks(2), 25 | .output_clock_frequency0("20.000000 MHz"), 26 | .phase_shift0("0 ps"), 27 | .duty_cycle0(50), 28 | .output_clock_frequency1("80.000000 MHz"), 29 | .phase_shift1("0 ps"), 30 | .duty_cycle1(50), 31 | .output_clock_frequency2("0 MHz"), 32 | .phase_shift2("0 ps"), 33 | .duty_cycle2(50), 34 | .output_clock_frequency3("0 MHz"), 35 | .phase_shift3("0 ps"), 36 | .duty_cycle3(50), 37 | .output_clock_frequency4("0 MHz"), 38 | .phase_shift4("0 ps"), 39 | .duty_cycle4(50), 40 | .output_clock_frequency5("0 MHz"), 41 | .phase_shift5("0 ps"), 42 | .duty_cycle5(50), 43 | .output_clock_frequency6("0 MHz"), 44 | .phase_shift6("0 ps"), 45 | .duty_cycle6(50), 46 | .output_clock_frequency7("0 MHz"), 47 | .phase_shift7("0 ps"), 48 | .duty_cycle7(50), 49 | .output_clock_frequency8("0 MHz"), 50 | .phase_shift8("0 ps"), 51 | .duty_cycle8(50), 52 | .output_clock_frequency9("0 MHz"), 53 | .phase_shift9("0 ps"), 54 | .duty_cycle9(50), 55 | .output_clock_frequency10("0 MHz"), 56 | .phase_shift10("0 ps"), 57 | .duty_cycle10(50), 58 | .output_clock_frequency11("0 MHz"), 59 | .phase_shift11("0 ps"), 60 | .duty_cycle11(50), 61 | .output_clock_frequency12("0 MHz"), 62 | .phase_shift12("0 ps"), 63 | .duty_cycle12(50), 64 | .output_clock_frequency13("0 MHz"), 65 | .phase_shift13("0 ps"), 66 | .duty_cycle13(50), 67 | .output_clock_frequency14("0 MHz"), 68 | .phase_shift14("0 ps"), 69 | .duty_cycle14(50), 70 | .output_clock_frequency15("0 MHz"), 71 | .phase_shift15("0 ps"), 72 | .duty_cycle15(50), 73 | .output_clock_frequency16("0 MHz"), 74 | .phase_shift16("0 ps"), 75 | .duty_cycle16(50), 76 | .output_clock_frequency17("0 MHz"), 77 | .phase_shift17("0 ps"), 78 | .duty_cycle17(50), 79 | .pll_type("General"), 80 | .pll_subtype("General") 81 | ) altera_pll_i ( 82 | .rst (rst), 83 | .outclk ({outclk_1, outclk_0}), 84 | .locked (locked), 85 | .fboutclk ( ), 86 | .fbclk (1'b0), 87 | .refclk (refclk) 88 | ); 89 | endmodule 90 | 91 | -------------------------------------------------------------------------------- /source/clk/clk_pll_sim.do: -------------------------------------------------------------------------------- 1 | 2 | vlib work 3 | vmap work work 4 | 5 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/altera_primitives.v 6 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/220model.v 7 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/sgate.v 8 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/altera_mf.v 9 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/altera_lnsim.sv 10 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_atoms_ncrypt.v 11 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_hmi_atoms_ncrypt.v 12 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_atoms.v 13 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_hssi_atoms_ncrypt.v 14 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_hssi_atoms.v 15 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_pcie_hip_atoms_ncrypt.v 16 | vlog C:/Users/Administrator/Desktop/clk_div_test/sim_lib/cyclonev_pcie_hip_atoms.v 17 | 18 | 19 | vlog clk_pll.vo 20 | vlog clk_pll_0002.v 21 | vlog clk_pll.v 22 | vlog clk_pll_tb.v 23 | vsim clk_pll_tb 24 | 25 | add wave -label clk_in /clk_pll_tb/clk_in 26 | add wave -label clk_pll_rst /clk_pll_tb/clk_pll_rst 27 | add wave -color Yellow -label clk_20M /clk_pll_tb/clk_20M 28 | add wave -color Magenta -label clk_80M /clk_pll_tb/clk_80M 29 | 30 | run -all; -------------------------------------------------------------------------------- /source/clk/clk_pll_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ns 3 | 4 | module clk_pll_tb; 5 | 6 | reg clk_in; 7 | reg clk_pll_rst; 8 | wire clk_20M; 9 | wire clk_80M; 10 | 11 | initial begin 12 | clk_in = 0; 13 | clk_pll_rst = 1; 14 | #100; //100ns(20*5) 15 | clk_pll_rst = 0; 16 | #4000; 17 | $stop(); 18 | end 19 | 20 | always #10 clk_in = ~clk_in; //clk_in = 50M; 21 | 22 | clk_pll clk_inst( 23 | .refclk(clk_in), 24 | .rst(clk_pll_rst), 25 | .outclk_0(clk_20M), 26 | .outclk_1(clk_80M)); 27 | 28 | 29 | 30 | 31 | endmodule -------------------------------------------------------------------------------- /source/clk/sim_lib/altera_mf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/clk/sim_lib/altera_mf.v -------------------------------------------------------------------------------- /source/cp/add_cyclic_prefix.v: -------------------------------------------------------------------------------- 1 | //添加循环前缀 2 | 3 | module add_cyclic_prefix #( parameter DATAWIDTH = 18 )( 4 | input cp_clk, //时钟信号 5 | input cp_rst_n, //复位信号，低有效 6 | input [DATAWIDTH-1:0] cp_real_din, //数据实部输入 7 | input [DATAWIDTH-1:0] cp_imag_din, //数据虚部输入 8 | input din_valid, //输入数据有效 9 | input [5:0] din_index, //输入数据计数，index = 0~63 10 | 11 | output reg [DATAWIDTH-1:0] cp_real_dout, //数据实部输出 12 | output reg [DATAWIDTH-1:0] cp_imag_dout, //数据虚部输出 13 | //output reg [6:0] dout_index, //输出数据计数，index = 0~79 14 | output reg dout_valid //数据输出有效 15 | ); 16 | 17 | reg write_en; 18 | reg read_en; 19 | reg wctr; 20 | reg rctr; 21 | reg [5:0] cnt; 22 | reg [6:0] read_addr; 23 | reg [6:0] write_addr; 24 | 25 | reg [DATAWIDTH-1:0] ram_real_din; 26 | reg [DATAWIDTH-1:0] ram_imag_din; 27 | wire [DATAWIDTH-1:0] ram_real_dout; 28 | wire [DATAWIDTH-1:0] ram_imag_dout; 29 | 30 | //wctr=0，rctr=0分别像RAM中0-63写读数据，wctr=1，rctr=1分别像RAM中64-127写读数据， 31 | always@(posedge cp_clk) begin 32 | if(!cp_rst_n) begin 33 | wctr <= 0; 34 | rctr <= 0; 35 | end 36 | else begin 37 | if(din_index == 63) 38 | wctr <= ~wctr; 39 | else ; 40 | 41 | if(read_addr == 63 || read_addr == 127) 42 | rctr <= ~rctr; 43 | else ; 44 | end 45 | end 46 | 47 | //向RAM中写数据 48 | always@(posedge cp_clk) begin 49 | if(!cp_rst_n) begin 50 | //wctr <= 0; 51 | write_en <= 1'b0; 52 | write_addr <= 0; 53 | ram_real_din <= 0; 54 | ram_imag_din <= 0; 55 | end 56 | else begin 57 | if(din_valid) begin 58 | write_en <= 1'b1; 59 | write_addr[6] <= wctr; 60 | write_addr[5:0] <= din_index; 61 | ram_real_din <= cp_real_din; 62 | ram_imag_din <= cp_imag_din; 63 | end 64 | else begin 65 | write_en <= 0; 66 | write_addr <= 0; 67 | ram_real_din <= 0; 68 | ram_imag_din <= 0; 69 | end 70 | end 71 | end 72 | 73 | //读数据模块 74 | always@(posedge cp_clk) begin 75 | if(!cp_rst_n) begin 76 | read_en <= 0; 77 | cp_real_dout <= 0; 78 | cp_imag_dout <= 0; 79 | dout_valid <= 0; 80 | end 81 | else begin 82 | if(din_index == 62) begin 83 | read_en <= 1; 84 | end 85 | else ; 86 | if(cnt == 63) 87 | read_en <= 0; 88 | else ; 89 | 90 | if(din_index > 47) begin 91 | cp_real_dout <= cp_real_din; 92 | cp_imag_dout <= cp_imag_din; 93 | dout_valid <= 1'b1; 94 | end 95 | else begin 96 | if(read_en) begin 97 | cp_real_dout <= ram_real_dout; 98 | cp_imag_dout <= ram_imag_dout; 99 | dout_valid <= 1'b1; 100 | end 101 | else if((~read_en) && (~din_valid)) begin 102 | cp_real_dout <= 0; 103 | cp_imag_dout <= 0; 104 | dout_valid <= 1'b0; 105 | end 106 | else ; 107 | end 108 | end 109 | end 110 | 111 | //计数器单元0-63，输出计数信号作为双口RAM的读地址信号 112 | always@(posedge cp_clk) begin 113 | if(!cp_rst_n) begin 114 | read_addr <= 0; 115 | cnt <= 0; 116 | end 117 | else begin 118 | if(read_en) begin 119 | read_addr[6] <= rctr; 120 | read_addr[5:0] <= read_addr[5:0] + 1'b1; 121 | cnt <= read_addr[5:0]; 122 | end 123 | else begin 124 | read_addr[5:0] <= 0; 125 | end 126 | end 127 | end 128 | 129 | 130 | //调用128*32双口RAM 131 | 132 | cp_ram2port #(DATAWIDTH) cp_mem_re ( 133 | .data ( ram_real_din ), 134 | .rdaddress ( read_addr ), 135 | .rdclock ( cp_clk ), 136 | .rden ( read_en ), 137 | .wraddress ( write_addr ), 138 | .wrclock ( cp_clk ), 139 | .wren ( write_en ), 140 | .q ( ram_real_dout ) 141 | ); 142 | 143 | cp_ram2port #(DATAWIDTH) cp_mem_im ( 144 | .data ( ram_imag_din ), 145 | .rdaddress ( read_addr ), 146 | .rdclock ( cp_clk ), 147 | .rden ( read_en ), 148 | .wraddress ( write_addr ), 149 | .wrclock ( cp_clk ), 150 | .wren ( write_en ), 151 | .q ( ram_imag_dout ) 152 | ); 153 | endmodule -------------------------------------------------------------------------------- /source/cp/add_cyclic_prefix_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns/1ns 3 | 4 | module add_cyclic_prefix_tb(); 5 | parameter WIDTH = 20; 6 | reg cp_clk; //时钟信号 7 | reg cp_rst_n; //复位信号，低有效 8 | reg [WIDTH-1:0] cp_real_din; //数据实部输入 9 | reg [WIDTH-1:0] cp_imag_din; //数据虚部输入 10 | reg din_valid; //输入数据有效 11 | reg [5:0] din_index; //输入数据计数，index = 0~47 12 | 13 | wire [WIDTH-1:0] cp_real_dout; //数据实部输出 14 | wire [WIDTH-1:0] cp_imag_dout; //数据虚部输出 15 | wire [6:0] dout_index; //输出数据计数，index = 0~47 16 | wire dout_valid ; //数据输出有效 17 | 18 | integer data_re, data_im; 19 | 20 | add_cyclic_prefix #(WIDTH) i1( 21 | .cp_clk(cp_clk), 22 | .cp_rst_n(cp_rst_n), 23 | .din_index(din_index), 24 | .din_valid(din_valid), 25 | .cp_real_din(cp_real_din), 26 | .cp_imag_din(cp_imag_din), 27 | .cp_real_dout(cp_real_dout), 28 | .cp_imag_dout(cp_imag_dout), 29 | //.dout_index(dout_index), 30 | .dout_valid(dout_valid)); 31 | 32 | initial begin 33 | data_re = $fopen("C:/Users/Administrator/Desktop/code/data/re_data.txt","r"); 34 | data_im = $fopen("C:/Users/Administrator/Desktop/code/data/im_data.txt","r"); 35 | cp_clk = 0; 36 | cp_rst_n = 0; 37 | din_valid = 0; 38 | #80; //2*40 39 | cp_rst_n = 1; 40 | din_valid = 1; 41 | #2560; //64*40 42 | din_valid = 0; 43 | #640; //16*40 44 | din_valid = 1; 45 | #2560; //64*40 46 | din_valid = 0; 47 | #640; //16*40 48 | din_valid = 1; 49 | #2560; //64*40 50 | din_valid = 0; 51 | #640; //16*40 52 | $stop; 53 | end 54 | 55 | always #20 cp_clk = ~cp_clk; 56 | 57 | always@(posedge cp_clk) begin 58 | if(!cp_rst_n) begin 59 | din_index <= 0; 60 | end 61 | else begin 62 | if(din_valid) 63 | din_index <= din_index + 1'b1; 64 | else 65 | din_index <= 0; 66 | end 67 | end 68 | 69 | integer rc_x,ic_x,data_real_in_int,data_imag_in_int; 70 | 71 | always@(negedge cp_clk) begin 72 | if(!cp_rst_n) begin 73 | cp_real_din <= 0; 74 | cp_imag_din <= 0; 75 | end 76 | else begin 77 | if(din_valid) begin 78 | rc_x = $fscanf(data_re,"%d",data_real_in_int); 79 | cp_real_din <= data_real_in_int; 80 | ic_x = $fscanf(data_im,"%d",data_imag_in_int); 81 | cp_imag_din <= data_imag_in_int; 82 | end 83 | else begin 84 | cp_real_din <= 0; 85 | cp_imag_din <= 0; 86 | end 87 | end 88 | end 89 | endmodule 90 | -------------------------------------------------------------------------------- /source/cp/cp_sim.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | vlog C:/Users/Administrator/Desktop/code/sim_lib/altera_mf.v 4 | vlog add_cyclic_prefix.v 5 | vlog cp_ram2port.v 6 | vlog add_cyclic_prefix_tb.v 7 | vsim add_cyclic_prefix_tb 8 | 9 | 10 | add wave -label cp_clk /add_cyclic_prefix_tb/cp_clk 11 | add wave -label cp_rst_n /add_cyclic_prefix_tb/cp_rst_n 12 | add wave -label din_valid /add_cyclic_prefix_tb/din_valid 13 | ##add wave -label din_en /add_cyclic_prefix_tb/i1/din_en 14 | add wave -radix unsigned -label cp_real_din /add_cyclic_prefix_tb/cp_real_din 15 | add wave -radix unsigned -label cp_imag_din /add_cyclic_prefix_tb/cp_imag_din 16 | add wave -color Yellow -radix unsigned -label din_index /add_cyclic_prefix_tb/din_index 17 | ##add wave -color Yellow -radix unsigned -label index /add_cyclic_prefix_tb/i1/index 18 | add wave -color Yellow -label wctr /add_cyclic_prefix_tb/i1/wctr 19 | add wave -color Yellow -label write_en /add_cyclic_prefix_tb/i1/write_en 20 | add wave -color Yellow -radix unsigned -label write_addr /add_cyclic_prefix_tb/i1/write_addr 21 | add wave -radix unsigned -label ram_real_din /add_cyclic_prefix_tb/i1/ram_real_din 22 | add wave -radix unsigned -label ram_imag_din /add_cyclic_prefix_tb/i1/ram_imag_din 23 | ##add wave -color Yellow -radix unsigned -label state /add_cyclic_prefix_tb/i1/state 24 | add wave -color Cyan -label rctr /add_cyclic_prefix_tb/i1/rctr 25 | add wave -color Cyan -label read_en /add_cyclic_prefix_tb/i1/read_en 26 | add wave -color Cyan -radix unsigned -label read_addr /add_cyclic_prefix_tb/i1/read_addr 27 | ##add wave -color Cyan -label dout_en /add_cyclic_prefix_tb/i1/dout_en 28 | add wave -color Cyan -label dout_valid /add_cyclic_prefix_tb/dout_valid 29 | add wave -color Magenta -radix unsigned -label ram_imag_dout /add_cyclic_prefix_tb/i1/ram_imag_dout 30 | add wave -color Magenta -radix unsigned -label ram_real_dout /add_cyclic_prefix_tb/i1/ram_real_dout 31 | add wave -color Magenta -radix unsigned -label cp_imag_dout /add_cyclic_prefix_tb/cp_imag_dout 32 | add wave -color Magenta -radix unsigned -label cp_real_dout /add_cyclic_prefix_tb/cp_real_dout 33 | 34 | 35 | run -all; -------------------------------------------------------------------------------- /source/cp/data/im_data.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | 65 66 | 66 67 | 67 68 | 68 69 | 69 70 | 70 71 | 71 72 | 72 73 | 73 74 | 74 75 | 75 76 | 76 77 | 77 78 | 78 79 | 79 80 | 80 81 | 81 82 | 82 83 | 83 84 | 84 85 | 85 86 | 86 87 | 87 88 | 88 89 | 89 90 | 90 91 | 91 92 | 92 93 | 93 94 | 94 95 | 95 96 | 96 97 | 97 98 | 98 99 | 99 100 | 100 101 | 101 102 | 102 103 | 103 104 | 104 105 | 105 106 | 106 107 | 107 108 | 108 109 | 109 110 | 110 111 | 111 112 | 112 113 | 113 114 | 114 115 | 115 116 | 116 117 | 117 118 | 118 119 | 119 120 | 120 121 | 121 122 | 122 123 | 123 124 | 124 125 | 125 126 | 126 127 | 127 128 | 128 129 | -------------------------------------------------------------------------------- /source/cp/data/re_data.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | 65 66 | 66 67 | 67 68 | 68 69 | 69 70 | 70 71 | 71 72 | 72 73 | 73 74 | 74 75 | 75 76 | 76 77 | 77 78 | 78 79 | 79 80 | 80 81 | 81 82 | 82 83 | 83 84 | 84 85 | 85 86 | 86 87 | 87 88 | 88 89 | 89 90 | 90 91 | 91 92 | 92 93 | 93 94 | 94 95 | 95 96 | 96 97 | 97 98 | 98 99 | 99 100 | 100 101 | 101 102 | 102 103 | 103 104 | 104 105 | 105 106 | 106 107 | 107 108 | 108 109 | 109 110 | 110 111 | 111 112 | 112 113 | 113 114 | 114 115 | 115 116 | 116 117 | 117 118 | 118 119 | 119 120 | 120 121 | 121 122 | 122 123 | 123 124 | 124 125 | 125 126 | 126 127 | 127 128 | 128 129 | -------------------------------------------------------------------------------- /source/cp/sim_lib/altera_mf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/cp/sim_lib/altera_mf.v -------------------------------------------------------------------------------- /source/cp/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/cp/vsim.wlf -------------------------------------------------------------------------------- /source/hermitian/data/im_data.txt: -------------------------------------------------------------------------------- 1 | 1100001101001001 2 | 1110101111000011 3 | 0001010000111101 4 | 0011110010110111 5 | 1100001101001001 6 | 1110101111000011 7 | 0001010000111101 8 | 0011110010110111 9 | 1100001101001001 10 | 1110101111000011 11 | 0001010000111101 12 | 0011110010110111 13 | 1100001101001001 14 | 1110101111000011 15 | 0001010000111101 16 | 0011110010110111 17 | 1100001101001001 18 | 1110101111000011 19 | 0001010000111101 20 | 0011110010110111 21 | 1100001101001001 22 | 1110101111000011 23 | 0001010000111101 24 | 0011110010110111 25 | 1100001101001001 26 | 1110101111000011 27 | 0001010000111101 28 | 0011110010110111 29 | 1100001101001001 30 | 1110101111000011 31 | 0001010000111101 32 | 0011110010110111 33 | 1100001101001001 34 | 1110101111000011 35 | 0001010000111101 36 | 0011110010110111 37 | 1100001101001001 38 | 1110101111000011 39 | 0001010000111101 40 | 0011110010110111 41 | 1100001101001001 42 | 1110101111000011 43 | 0001010000111101 44 | 0011110010110111 45 | 1100001101001001 46 | 1110101111000011 47 | 0001010000111101 48 | 0011110010110111 49 | 1100001101001001 50 | 1110101111000011 51 | 0001010000111101 52 | 0011110010110111 53 | 1100001101001001 54 | 1110101111000011 55 | 0001010000111101 56 | 0011110010110111 57 | 1100001101001001 58 | 1110101111000011 59 | 0001010000111101 60 | 0011110010110111 61 | 1100001101001001 62 | 1110101111000011 63 | 0001010000111101 64 | 0011110010110111 -------------------------------------------------------------------------------- /source/hermitian/data/imag.txt: -------------------------------------------------------------------------------- 1 | -64 2 | -63 3 | -62 4 | -61 5 | -60 6 | -59 7 | -58 8 | -57 9 | -56 10 | -55 11 | -54 12 | -53 13 | -52 14 | -51 15 | -50 16 | -49 17 | -48 18 | -47 19 | -46 20 | -45 21 | -44 22 | -43 23 | -42 24 | -41 25 | -40 26 | -39 27 | -38 28 | -37 29 | -36 30 | -35 31 | -34 32 | -33 33 | -32 34 | -31 35 | -30 36 | -29 37 | -28 38 | -27 39 | -26 40 | -25 41 | -24 42 | -23 43 | -22 44 | -21 45 | -20 46 | -19 47 | -18 48 | -17 49 | -16 50 | -15 51 | -14 52 | -13 53 | -12 54 | -11 55 | -10 56 | -9 57 | -8 58 | -7 59 | -6 60 | -5 61 | -4 62 | -3 63 | -2 64 | -1 65 | -------------------------------------------------------------------------------- /source/hermitian/data/re_data.txt: -------------------------------------------------------------------------------- 1 | 1100001101001001 2 | 1110101111000011 3 | 0001010000111101 4 | 0011110010110111 5 | 1100001101001001 6 | 1110101111000011 7 | 0001010000111101 8 | 0011110010110111 9 | 1100001101001001 10 | 1110101111000011 11 | 0001010000111101 12 | 0011110010110111 13 | 1100001101001001 14 | 1110101111000011 15 | 0001010000111101 16 | 0011110010110111 17 | 1100001101001001 18 | 1110101111000011 19 | 0001010000111101 20 | 0011110010110111 21 | 1100001101001001 22 | 1110101111000011 23 | 0001010000111101 24 | 0011110010110111 25 | 1100001101001001 26 | 1110101111000011 27 | 0001010000111101 28 | 0011110010110111 29 | 1100001101001001 30 | 1110101111000011 31 | 0001010000111101 32 | 0011110010110111 33 | 1100001101001001 34 | 1110101111000011 35 | 0001010000111101 36 | 0011110010110111 37 | 1100001101001001 38 | 1110101111000011 39 | 0001010000111101 40 | 0011110010110111 41 | 1100001101001001 42 | 1110101111000011 43 | 0001010000111101 44 | 0011110010110111 45 | 1100001101001001 46 | 1110101111000011 47 | 0001010000111101 48 | 0011110010110111 49 | 1100001101001001 50 | 1110101111000011 51 | 0001010000111101 52 | 0011110010110111 53 | 1100001101001001 54 | 1110101111000011 55 | 0001010000111101 56 | 0011110010110111 57 | 1100001101001001 58 | 1110101111000011 59 | 0001010000111101 60 | 0011110010110111 61 | 1100001101001001 62 | 1110101111000011 63 | 0001010000111101 64 | 0011110010110111 -------------------------------------------------------------------------------- /source/hermitian/data/real.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | -------------------------------------------------------------------------------- /source/hermitian/her_sim.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | vlog C:/Users/Administrator/Desktop/code/sim_lib/altera_mf.v 4 | vlog her_ram2port.v 5 | vlog hermitian.v 6 | vlog hermitian_tb.v 7 | vsim hermitian_tb 8 | 9 | 10 | add wave -label her_clk /hermitian_tb/her_clk 11 | add wave -label her_rst_n /hermitian_tb/her_rst_n 12 | add wave -label din_valid /hermitian_tb/din_valid 13 | add wave -radix unsigned -label din_index /hermitian_tb/din_index 14 | add wave -label write_en /hermitian_tb/ins/write_en 15 | add wave -radix unsigned -label write_addrA /hermitian_tb/ins/write_addrA 16 | add wave -radix unsigned -label write_addrB /hermitian_tb/ins/write_addrB 17 | 18 | add wave -radix dec -label her_real_din /hermitian_tb/her_real_din 19 | add wave -radix dec -label her_imag_din /hermitian_tb/her_imag_din 20 | add wave -radix dec -label ramA_real_din /hermitian_tb/ins/ramA_real_din 21 | add wave -radix dec -label ramA_imag_din /hermitian_tb/ins/ramA_imag_din 22 | add wave -radix dec -label ramB_real_din /hermitian_tb/ins/ramB_real_din 23 | add wave -radix dec -label ramB_imag_din /hermitian_tb/ins/ramB_imag_din 24 | 25 | add wave -label read_en /hermitian_tb/ins/read_en 26 | add wave -label rctr /hermitian_tb/ins/rctr 27 | add wave -radix unsigned -label read_addr /hermitian_tb/ins/read_addr 28 | add wave -radix dec -label ramA_real_dout /hermitian_tb/ins/ramA_real_dout 29 | add wave -radix dec -label ramA_imag_dout /hermitian_tb/ins/ramA_imag_dout 30 | add wave -radix dec -label ramA_real_buf /hermitian_tb/ins/ramA_real_buf 31 | add wave -radix dec -label ramA_imag_buf /hermitian_tb/ins/ramA_imag_buf 32 | add wave -radix dec -label ramB_real_dout /hermitian_tb/ins/ramB_real_dout 33 | add wave -radix dec -label ramB_imag_dout /hermitian_tb/ins/ramB_imag_dout 34 | add wave -radix dec -label ramB_real_buf /hermitian_tb/ins/ramB_real_buf 35 | add wave -radix dec -label ramB_imag_buf /hermitian_tb/ins/ramB_imag_buf 36 | add wave -label dout_en /hermitian_tb/ins/dout_en 37 | add wave -radix unsigned -label dout_index /hermitian_tb/ins/dout_index 38 | add wave -radix dec -label her_real_dout /hermitian_tb/her_real_dout 39 | add wave -radix dec -label her_imag_dout /hermitian_tb/her_imag_dout 40 | add wave -label dout_valid /hermitian_tb/dout_valid 41 | 42 | run -all; -------------------------------------------------------------------------------- /source/hermitian/hermitian_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module hermitian_tb(); 4 | parameter WIDTH = 16; 5 | reg her_clk; 6 | reg her_rst_n; 7 | reg din_valid; 8 | reg [5:0] din_index; 9 | reg [WIDTH-1:0] her_real_din; 10 | reg [WIDTH-1:0] her_imag_din; 11 | 12 | wire dout_valid; 13 | wire [WIDTH-1:0] her_real_dout; 14 | wire [WIDTH-1:0] her_imag_dout; 15 | 16 | integer data_re, data_im; 17 | 18 | hermitian ins(.her_clk(her_clk), 19 | .her_rst_n(her_rst_n), 20 | .din_valid(din_valid), 21 | .din_index(din_index), 22 | .her_real_din(her_real_din), 23 | .her_imag_din(her_imag_din), 24 | .her_real_dout(her_real_dout), 25 | .her_imag_dout(her_imag_dout), 26 | .dout_valid(dout_valid)); 27 | 28 | 29 | initial begin 30 | data_re = $fopen("C:/Users/Administrator/Desktop/code/data/real.txt","r"); 31 | data_im = $fopen("C:/Users/Administrator/Desktop/code/data/imag.txt","r"); 32 | her_clk = 0; 33 | her_rst_n = 0; 34 | din_valid = 0; 35 | #120; //3*40 36 | her_rst_n = 1; 37 | din_valid = 1; 38 | #2560; //64*40 39 | din_valid = 0; 40 | #640; 41 | din_valid = 1; 42 | #2560; 43 | din_valid = 0; 44 | #640; 45 | din_valid = 1; 46 | #2560; 47 | din_valid = 0; 48 | #640; 49 | $stop(); 50 | end 51 | 52 | always #20 her_clk = ~her_clk; 53 | 54 | always@(posedge her_clk) begin 55 | if(!her_rst_n) begin 56 | din_index <= 0; 57 | end 58 | else begin 59 | if(din_valid) 60 | din_index <= din_index + 1'b1; 61 | else 62 | din_index <= 0; 63 | end 64 | end 65 | 66 | integer rc_x,ic_x,data_real_in_int,data_imag_in_int; 67 | always@(negedge her_clk) begin 68 | if(!her_rst_n) begin 69 | her_real_din <= 0; 70 | her_imag_din <= 0; 71 | end 72 | else begin 73 | if(din_valid) begin 74 | rc_x = $fscanf(data_re,"%d",data_real_in_int); 75 | her_real_din <= data_real_in_int; 76 | ic_x = $fscanf(data_im,"%d",data_imag_in_int); 77 | her_imag_din <= data_imag_in_int; 78 | end 79 | else begin 80 | her_real_din <= 0; 81 | her_imag_din <= 0; 82 | end 83 | end 84 | end 85 | 86 | endmodule 87 | 88 | 89 | 90 | -------------------------------------------------------------------------------- /source/hermitian/sim_lib/altera_mf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/hermitian/sim_lib/altera_mf.v -------------------------------------------------------------------------------- /source/hermitian/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/hermitian/vsim.wlf -------------------------------------------------------------------------------- /source/ifft/Readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/Readme.txt -------------------------------------------------------------------------------- /source/ifft/ifft_project/.qsys_edit/fft_ipcore_schematic.nlv: -------------------------------------------------------------------------------- 1 | # # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 2 | # 3 | preplace inst unsaved.fft_ii_0 -pg 1 -lvl 1 -y 30 4 | preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20 5 | preplace netloc EXPORTunsaved(SLAVE)unsaved.sink,(SLAVE)fft_ii_0.sink) 1 0 1 NJ 6 | preplace netloc EXPORTunsaved(SLAVE)unsaved.rst,(SLAVE)fft_ii_0.rst) 1 0 1 NJ 7 | preplace netloc EXPORTunsaved(SLAVE)fft_ii_0.clk,(SLAVE)unsaved.clk) 1 0 1 NJ 8 | preplace netloc EXPORTunsaved(SLAVE)unsaved.source,(SLAVE)fft_ii_0.source) 1 0 1 NJ 9 | levelinfo -pg 1 0 50 180 10 | levelinfo -hier unsaved 60 90 170 11 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/.qsys_edit/filters.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 76 | 77 | Block Floating Point 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/fft_ii_0_example_design_model.m: -------------------------------------------------------------------------------- 1 | % function [y, exp_out] = fft_ii_0_example_design_model(x,N,INVERSE) 2 | % 3 | % calculates the complex block-floating point FFT/IFFT of length N of a 4 | % complex input vector x 5 | % 6 | % Inputs: x : Input complex vector of length B*N, where B is 7 | % the number of blocks over which the length-N FFT is to 8 | % be applied. If the length of the vector is not 9 | % an integral multiple of N, zeros are 10 | % appended to the input sequence appropriately. 11 | % N : Transform Length 12 | % INVERSE : FFT direction 13 | % 0 => FFT 14 | % 1 => IFFT 15 | % 16 | % Outputs y : The transform-domain complex vector output 17 | % exp_out : Block exponent value 18 | % 19 | % Copyright Altera 20 | % 21 | % This file is automatically generated. DO NOT EDIT. 22 | % 23 | function [y, exp_out] = fft_ii_0_example_design_model(x,N,INVERSE) 24 | addpath(strcat(getenv('QUARTUS_ROOTDIR'),'/../ip/altera/fft/lib/')); 25 | % Parameterization Space 26 | THROUGHPUT=4; 27 | 28 | ARCH=0; 29 | 30 | DATA_PREC=16; 31 | TWIDDLE_PREC=16; 32 | input_vector_length = length(x); 33 | number_of_blocks = ceil(input_vector_length/N); 34 | % Zero-stuff last block if necessary 35 | x = [x, zeros(1,number_of_blocks * N - input_vector_length)]; 36 | y=[]; 37 | exp_out=[]; 38 | for i=1:number_of_blocks 39 | rin = real(x((i-1)*N + 1: i*N)); 40 | iin = imag(x((i-1)*N + 1: i*N)); 41 | [roc,ioc,eoc] = Sfftmodel(rin,iin,N,THROUGHPUT,ARCH,DATA_PREC,TWIDDLE_PREC,INVERSE); 42 | y = [y, roc+j*ioc]; 43 | exp_out = [exp_out, eoc]; 44 | end 45 | 46 | 47 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/fft_ii_0_example_design_tb.m: -------------------------------------------------------------------------------- 1 | 2 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 3 | 4 | % file : fft_ii_0_example_design_tb.m 5 | 6 | % 7 | 8 | % Description : The following Matlab testbench excercises the Altera FFT Model fft_ii_0_example_design_model.m 9 | 10 | % generated by Altera's FFT Megacore and outputs results to text files. 11 | 12 | % 13 | 14 | % Copyright Altera 15 | 16 | %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 17 | 18 | % Parameterization Space 19 | 20 | N=64; 21 | 22 | % Read input complex vector from source text files 23 | 24 | fidr = fopen('fft_ii_0_example_design_real_input.txt','r'); 25 | 26 | fidi = fopen('fft_ii_0_example_design_imag_input.txt','r'); 27 | 28 | xreali=fscanf(fidr,'%d'); 29 | 30 | ximagi=fscanf(fidi,'%d'); 31 | 32 | fclose(fidi); 33 | 34 | fclose(fidr); 35 | 36 | % Create input complex row vector from source text files 37 | 38 | x = xreali' + j*ximagi'; 39 | 40 | [y, exp_out] = fft_ii_0_example_design_model(x,N,0); 41 | 42 | fidro = fopen('fft_ii_0_example_design_real_output_c_model.txt','w'); 43 | 44 | fidio = fopen('fft_ii_0_example_design_imag_output_c_model.txt','w'); 45 | 46 | fideo = fopen('fft_ii_0_example_design_exponent_out_c_model.txt','w'); 47 | 48 | fprintf(fidro,'%d\n',real(y)); 49 | 50 | fprintf(fidio,'%d\n',imag(y)); 51 | 52 | fprintf(fideo,'%d\n',exp_out); 53 | 54 | fclose(fidro); 55 | 56 | fclose(fidio); 57 | 58 | fclose(fideo); 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/fft_ipcore.cmp: -------------------------------------------------------------------------------- 1 | component fft_ipcore is 2 | port ( 3 | clk : in std_logic := 'X'; -- clk 4 | reset_n : in std_logic := 'X'; -- reset_n 5 | sink_valid : in std_logic := 'X'; -- sink_valid 6 | sink_ready : out std_logic; -- sink_ready 7 | sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- sink_error 8 | sink_sop : in std_logic := 'X'; -- sink_sop 9 | sink_eop : in std_logic := 'X'; -- sink_eop 10 | sink_real : in std_logic_vector(15 downto 0) := (others => 'X'); -- sink_real 11 | sink_imag : in std_logic_vector(15 downto 0) := (others => 'X'); -- sink_imag 12 | inverse : in std_logic_vector(0 downto 0) := (others => 'X'); -- inverse 13 | source_valid : out std_logic; -- source_valid 14 | source_ready : in std_logic := 'X'; -- source_ready 15 | source_error : out std_logic_vector(1 downto 0); -- source_error 16 | source_sop : out std_logic; -- source_sop 17 | source_eop : out std_logic; -- source_eop 18 | source_real : out std_logic_vector(15 downto 0); -- source_real 19 | source_imag : out std_logic_vector(15 downto 0); -- source_imag 20 | source_exp : out std_logic_vector(5 downto 0) -- source_exp 21 | ); 22 | end component fft_ipcore; 23 | 24 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/fft_ipcore_generation.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create block symbol file (.bsf) 2 | Info: qsys-generate C:\Users\Administrator\Desktop\workepace\ffttest15\fft_ipcore.qsys --block-symbol-file --output-directory=C:\Users\Administrator\Desktop\workepace\ffttest15\fft_ipcore --family="Cyclone V" --part=5CSXFC6D6F31C6 3 | Progress: Loading ffttest15/fft_ipcore.qsys 4 | Progress: Reading input file 5 | Progress: Adding fft_ii_0 [altera_fft_ii 15.0] 6 | Progress: Parameterizing module fft_ii_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | Info: ip-generate succeeded. 12 | Info: Finished: Create block symbol file (.bsf) 13 | Info: 14 | Info: Starting: Create HDL design files for synthesis 15 | Info: qsys-generate C:\Users\Administrator\Desktop\workepace\ffttest15\fft_ipcore.qsys --synthesis=VERILOG --output-directory=C:\Users\Administrator\Desktop\workepace\ffttest15\fft_ipcore\synthesis --family="Cyclone V" --part=5CSXFC6D6F31C6 16 | Progress: Loading ffttest15/fft_ipcore.qsys 17 | Progress: Reading input file 18 | Progress: Adding fft_ii_0 [altera_fft_ii 15.0] 19 | Progress: Parameterizing module fft_ii_0 20 | Progress: Building connections 21 | Progress: Parameterizing connections 22 | Progress: Validating 23 | Progress: Done reading input file 24 | Info: fft_ipcore: Generating fft_ipcore "fft_ipcore" for QUARTUS_SYNTH 25 | Info: fft_ii_0: "fft_ipcore" instantiated altera_fft_ii "fft_ii_0" 26 | Info: fft_ipcore: Done "fft_ipcore" with 2 modules, 106 files 27 | Info: ip-generate succeeded. 28 | Info: Finished: Create HDL design files for synthesis 29 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/altera_avalon_clock_source.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2015 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $File: //acds/rel/15.0/ip/sopc/components/verification/altera_avalon_clock_source/altera_avalon_clock_source.sv $ 15 | // $Revision: #1 $ 16 | // $Date: 2015/02/08 $ 17 | // $Author: swbranch $ 18 | //------------------------------------------------------------------------------ 19 | // Clock generator 20 | 21 | `timescale 1ps / 1ps 22 | 23 | module altera_avalon_clock_source (clk); 24 | output clk; 25 | 26 | parameter int unsigned CLOCK_RATE = 10; // clock rate in MHz / kHz / Hz depends on the clock unit 27 | parameter CLOCK_UNIT = 1000000; // clock unit MHz / kHz / Hz 28 | 29 | // synthesis translate_off 30 | import verbosity_pkg::*; 31 | 32 | localparam time HALF_CLOCK_PERIOD = 1000000000000.000000/(CLOCK_RATE*CLOCK_UNIT*2); // half clock period in ps 33 | 34 | logic clk = 1'b0; 35 | 36 | string message = "*uninitialized*"; 37 | string freq_unit = (CLOCK_UNIT == 1)? "Hz" : 38 | (CLOCK_UNIT == 1000)? "kHz" : "MHz"; 39 | bit run_state = 1'b1; 40 | 41 | function automatic void __hello(); 42 | $sformat(message, "%m: - Hello from altera_clock_source."); 43 | print(VERBOSITY_INFO, message); 44 | $sformat(message, "%m: - $Revision: #1 $"); 45 | print(VERBOSITY_INFO, message); 46 | $sformat(message, "%m: - $Date: 2015/02/08 $"); 47 | print(VERBOSITY_INFO, message); 48 | $sformat(message, "%m: - CLOCK_RATE = %0d %s", CLOCK_RATE, freq_unit); 49 | print(VERBOSITY_INFO, message); 50 | print_divider(VERBOSITY_INFO); 51 | endfunction 52 | 53 | function automatic string get_version(); // public 54 | // Return BFM version as a string of three integers separated by periods. 55 | // For example, version 9.1 sp1 is encoded as "9.1.1". 56 | string ret_version = "15.0"; 57 | return ret_version; 58 | endfunction 59 | 60 | task automatic clock_start(); // public 61 | // Turn the clock on. By default the clock is initially turned on. 62 | $sformat(message, "%m: Clock started"); 63 | print(VERBOSITY_INFO, message); 64 | run_state = 1; 65 | endtask 66 | 67 | task automatic clock_stop(); // public 68 | // Turn the clock off. 69 | $sformat(message, "%m: Clock stopped"); 70 | print(VERBOSITY_INFO, message); 71 | run_state = 0; 72 | endtask 73 | 74 | function automatic get_run_state(); // public 75 | // Return the state of the clock source: running=1, stopped=0 76 | return run_state; 77 | endfunction 78 | 79 | initial begin 80 | __hello(); 81 | end 82 | 83 | always begin 84 | #HALF_CLOCK_PERIOD; 85 | clk = run_state; 86 | 87 | #HALF_CLOCK_PERIOD; 88 | clk = 1'b0; 89 | end 90 | // synthesis translate_on 91 | 92 | endmodule 93 | 94 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/altera_avalon_reset_source.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2015 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $File: //acds/rel/15.0/ip/sopc/components/verification/altera_avalon_reset_source/altera_avalon_reset_source.sv $ 15 | // $Revision: #1 $ 16 | // $Date: 2015/02/08 $ 17 | // $Author: swbranch $ 18 | //------------------------------------------------------------------------------ 19 | // Reset generator 20 | 21 | `timescale 1ps / 1ps 22 | 23 | module altera_avalon_reset_source ( 24 | clk, 25 | reset 26 | ); 27 | input clk; 28 | output reset; 29 | 30 | parameter ASSERT_HIGH_RESET = 1; // reset assertion level is high by default 31 | parameter INITIAL_RESET_CYCLES = 0; // deassert after number of clk cycles 32 | 33 | // synthesis translate_off 34 | import verbosity_pkg::*; 35 | 36 | logic reset = ASSERT_HIGH_RESET ? 1'b0 : 1'b1; 37 | 38 | string message = "*uninitialized*"; 39 | 40 | int clk_ctr = 0; 41 | 42 | always @(posedge clk) begin 43 | clk_ctr <= clk_ctr + 1; 44 | end 45 | 46 | always @(*) 47 | if (clk_ctr == INITIAL_RESET_CYCLES) 48 | reset_deassert(); 49 | 50 | 51 | function automatic void __hello(); 52 | $sformat(message, "%m: - Hello from altera_reset_source"); 53 | print(VERBOSITY_INFO, message); 54 | $sformat(message, "%m: - $Revision: #1 $"); 55 | print(VERBOSITY_INFO, message); 56 | $sformat(message, "%m: - $Date: 2015/02/08 $"); 57 | print(VERBOSITY_INFO, message); 58 | $sformat(message, "%m: - ASSERT_HIGH_RESET = %0d", ASSERT_HIGH_RESET); 59 | print(VERBOSITY_INFO, message); 60 | $sformat(message, "%m: - INITIAL_RESET_CYCLES = %0d", INITIAL_RESET_CYCLES); 61 | print(VERBOSITY_INFO, message); 62 | print_divider(VERBOSITY_INFO); 63 | endfunction 64 | 65 | function automatic string get_version(); // public 66 | // Return BFM version as a string of three integers separated by periods. 67 | // For example, version 9.1 sp1 is encoded as "9.1.1". 68 | string ret_version = "15.0"; 69 | return ret_version; 70 | endfunction 71 | 72 | task automatic reset_assert(); // public 73 | $sformat(message, "%m: Reset asserted"); 74 | print(VERBOSITY_INFO, message); 75 | 76 | if (ASSERT_HIGH_RESET > 0) begin 77 | reset = 1'b1; 78 | end else begin 79 | reset = 1'b0; 80 | end 81 | endtask 82 | 83 | task automatic reset_deassert(); // public 84 | $sformat(message, "%m: Reset deasserted"); 85 | print(VERBOSITY_INFO, message); 86 | 87 | if (ASSERT_HIGH_RESET > 0) begin 88 | reset = 1'b0; 89 | end else begin 90 | reset = 1'b1; 91 | end 92 | endtask 93 | 94 | initial begin 95 | __hello(); 96 | if (INITIAL_RESET_CYCLES > 0) 97 | reset_assert(); 98 | end 99 | // synthesis translate_on 100 | 101 | endmodule 102 | 103 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/avalon_utilities_pkg.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2015 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | // $Id: //acds/rel/15.0/ip/sopc/components/verification/lib/avalon_utilities_pkg.sv#1 $ 15 | // $Revision: #1 $ 16 | // $Date: 2015/02/08 $ 17 | //----------------------------------------------------------------------------- 18 | // =head1 NAME 19 | // avalon_utilities_pkg 20 | // =head1 SYNOPSIS 21 | // Package for shared types and functions 22 | //----------------------------------------------------------------------------- 23 | // =head1 COPYRIGHT 24 | // Copyright (c) 2008 Altera Corporation. All Rights Reserved. 25 | // The information contained in this file is the property of Altera 26 | // Corporation. Except as specifically authorized in writing by Altera 27 | // Corporation, the holder of this file shall keep all information 28 | // contained herein confidential and shall protect same in whole or in part 29 | // from disclosure and dissemination to all third parties. Use of this 30 | // program confirms your agreement with the terms of this license. 31 | //----------------------------------------------------------------------------- 32 | // =head1 DESCRIPTION 33 | // This package contains shared types and functions. 34 | // =cut 35 | `timescale 1ns / 1ns 36 | 37 | `ifndef _AVALON_UTILITIES_PKG_ 38 | `define _AVALON_UTILITIES_PKG_ 39 | 40 | package avalon_utilities_pkg; 41 | 42 | function automatic int clog2( 43 | bit [31:0] Depth 44 | ); 45 | int i= Depth; 46 | for(clog2 = 0; i > 0; clog2 = clog2 + 1) 47 | i = i >> 1; 48 | 49 | return clog2; 50 | endfunction 51 | 52 | function automatic int max( 53 | bit [31:0] one, 54 | bit [31:0] two 55 | ); 56 | if(one > two) 57 | return one; 58 | else 59 | return two; 60 | endfunction 61 | 62 | function automatic int lindex( 63 | bit [31:0] width 64 | ); 65 | // returns the left index for a vector having a declared width 66 | // when width is 0, then the left index is set to 0 rather than -1 67 | lindex = (width > 0) ? (width-1) : 0; 68 | endfunction 69 | 70 | typedef enum int { 71 | LOW = 0, 72 | HIGH = 1, 73 | RANDOM = 2, 74 | UNKNOWN = 3 75 | } IdleOutputValue_t; 76 | 77 | endpackage 78 | 79 | `endif 80 | 81 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design.v: -------------------------------------------------------------------------------- 1 | // fft_ii_0_example_design.v 2 | 3 | // Generated using ACDS version 15.0 145 4 | 5 | `timescale 1 ps / 1 ps 6 | module fft_ii_0_example_design ( 7 | input wire core_clk_clk, // core_clk.clk 8 | input wire core_rst_reset_n, // core_rst.reset_n 9 | input wire core_sink_valid, // core_sink.valid 10 | output wire core_sink_ready, // .ready 11 | input wire [1:0] core_sink_error, // .error 12 | input wire core_sink_startofpacket, // .startofpacket 13 | input wire core_sink_endofpacket, // .endofpacket 14 | input wire [32:0] core_sink_data, // .data 15 | output wire core_source_valid, // core_source.valid 16 | input wire core_source_ready, // .ready 17 | output wire [1:0] core_source_error, // .error 18 | output wire core_source_startofpacket, // .startofpacket 19 | output wire core_source_endofpacket, // .endofpacket 20 | output wire [37:0] core_source_data // .data 21 | ); 22 | 23 | wire [15:0] core_source_imag; // port fragment 24 | wire [15:0] core_source_real; // port fragment 25 | wire [5:0] core_source_exp; // port fragment 26 | 27 | fft_ii_0_example_design_core core ( 28 | .clk (core_clk_clk), // clk.clk 29 | .reset_n (core_rst_reset_n), // rst.reset_n 30 | .sink_valid (core_sink_valid), // sink.valid 31 | .sink_ready (core_sink_ready), // .ready 32 | .sink_error (core_sink_error), // .error 33 | .sink_sop (core_sink_startofpacket), // .startofpacket 34 | .sink_eop (core_sink_endofpacket), // .endofpacket 35 | .sink_real ({core_sink_data[32:17]}), // .data 36 | .sink_imag ({core_sink_data[16:1]}), // .data 37 | .inverse ({core_sink_data[0]}), // .data 38 | .source_valid (core_source_valid), // source.valid 39 | .source_ready (core_source_ready), // .ready 40 | .source_error (core_source_error), // .error 41 | .source_sop (core_source_startofpacket), // .startofpacket 42 | .source_eop (core_source_endofpacket), // .endofpacket 43 | .source_real (core_source_real), // .data 44 | .source_imag (core_source_imag), // .data 45 | .source_exp (core_source_exp) // .data 46 | ); 47 | 48 | assign core_source_data = { core_source_real[15:0], core_source_imag[15:0], core_source_exp[5:0] }; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design_core_1n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007f611d 3 | :020002007d89f6 4 | :020003007a7c05 5 | :02000400764143 6 | :0200050070e2a7 7 | :020006006a6d21 8 | :0200070062f1a4 9 | :020008005a821a 10 | :02000900513371 11 | :02000a00471c91 12 | :02000b003c5661 13 | :02000c0030fbc7 14 | :02000d002528a4 15 | :02000e0018f9df 16 | :02000f000c8c57 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design_core_1n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :020001000c8c65 3 | :0200020018f9eb 4 | :020003002528ae 5 | :0200040030fbcf 6 | :020005003c5667 7 | :02000600471c95 8 | :02000700513373 9 | :020008005a821a 10 | :0200090062f1a2 11 | :02000a006a6d1d 12 | :02000b0070e2a1 13 | :02000c0076413b 14 | :02000d007a7cfb 15 | :02000e007d89ea 16 | :02000f007f610f 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design_core_2n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007d89f7 3 | :02000200764145 4 | :020003006a6d24 5 | :020004005a821e 6 | :02000500471c96 7 | :0200060030fbcd 8 | :0200070018f9e6 9 | :020008000000f6 10 | :02000900e70707 11 | :02000a00cf0520 12 | :02000b00b8e457 13 | :02000c00a57ecf 14 | :02000d009593c9 15 | :02000e0089bfa8 16 | :02000f008277f6 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design_core_2n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :0200010018f9ec 3 | :0200020030fbd1 4 | :02000300471c98 5 | :020004005a821e 6 | :020005006a6d22 7 | :02000600764141 8 | :020007007d89f1 9 | :020008007fff78 10 | :020009007d89ef 11 | :02000a0076413d 12 | :02000b006a6d1c 13 | :02000c005a8216 14 | :02000d00471c8e 15 | :02000e0030fbc5 16 | :02000f0018f9de 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design_core_3n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007a7c07 3 | :020002006a6d25 4 | :02000300513377 5 | :0200040030fbcf 6 | :020005000c8c61 7 | :02000600e7070a 8 | :02000700c3aa8a 9 | :02000800a57ed3 10 | :020009008f1e48 11 | :02000a008277fb 12 | :02000b00809fd4 13 | :02000c0089bfaa 14 | :02000d009d0f45 15 | :02000e00b8e454 16 | :02000f00dad83d 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/src/fft_ii_0_example_design_core_3n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :020001002528b0 3 | :02000200471c99 4 | :0200030062f1a8 5 | :02000400764143 6 | :020005007f6119 7 | :020006007d89f2 8 | :0200070070e2a5 9 | :020008005a821a 10 | :020009003c5663 11 | :02000a0018f9e3 12 | :02000b00f3748c 13 | :02000c00cf051e 14 | :02000d00aecd76 15 | :02000e009593c8 16 | :02000f008584e6 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/fft_ipcore.v: -------------------------------------------------------------------------------- 1 | // fft_ipcore.v 2 | 3 | // Generated using ACDS version 15.0 145 4 | 5 | `timescale 1 ps / 1 ps 6 | module fft_ipcore ( 7 | input wire clk, // clk.clk 8 | input wire reset_n, // rst.reset_n 9 | input wire sink_valid, // sink.sink_valid 10 | output wire sink_ready, // .sink_ready 11 | input wire [1:0] sink_error, // .sink_error 12 | input wire sink_sop, // .sink_sop 13 | input wire sink_eop, // .sink_eop 14 | input wire [15:0] sink_real, // .sink_real 15 | input wire [15:0] sink_imag, // .sink_imag 16 | input wire [0:0] inverse, // .inverse 17 | output wire source_valid, // source.source_valid 18 | input wire source_ready, // .source_ready 19 | output wire [1:0] source_error, // .source_error 20 | output wire source_sop, // .source_sop 21 | output wire source_eop, // .source_eop 22 | output wire [15:0] source_real, // .source_real 23 | output wire [15:0] source_imag, // .source_imag 24 | output wire [5:0] source_exp // .source_exp 25 | ); 26 | 27 | fft_ipcore_fft_ii_0 fft_ii_0 ( 28 | .clk (clk), // clk.clk 29 | .reset_n (reset_n), // rst.reset_n 30 | .sink_valid (sink_valid), // sink.sink_valid 31 | .sink_ready (sink_ready), // .sink_ready 32 | .sink_error (sink_error), // .sink_error 33 | .sink_sop (sink_sop), // .sink_sop 34 | .sink_eop (sink_eop), // .sink_eop 35 | .sink_real (sink_real), // .sink_real 36 | .sink_imag (sink_imag), // .sink_imag 37 | .inverse (inverse), // .inverse 38 | .source_valid (source_valid), // source.source_valid 39 | .source_ready (source_ready), // .source_ready 40 | .source_error (source_error), // .source_error 41 | .source_sop (source_sop), // .source_sop 42 | .source_eop (source_eop), // .source_eop 43 | .source_real (source_real), // .source_real 44 | .source_imag (source_imag), // .source_imag 45 | .source_exp (source_exp) // .source_exp 46 | ); 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/altera_fft_dual_port_ram.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/ifft_project/fft_ipcore/synthesis/submodules/altera_fft_dual_port_ram.vhd -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/altera_fft_dual_port_rom.vhd: -------------------------------------------------------------------------------- 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All rights reserved. 2 | -- Your use of Altera Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Altera Program License Subscription 7 | -- Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Altera and sold by 10 | -- Altera or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | ------------------------------------------------------------------------- 15 | ------------------------------------------------------------------------- 16 | -- 17 | -- Revision Control Information 18 | -- 19 | -- $RCSfile: auk_dspip_avalon_streaming_controller.vhd,v $ 20 | -- $Source: /cvs/uksw/dsp_cores/lib/fu/avalon_streaming/rtl/auk_dspip_avalon_streaming_controller.vhd,v $ 21 | -- 22 | -- $Revision: #1 $ 23 | -- $Date: 2015/02/08 $ 24 | -- Check in by : $Author: swbranch $ 25 | -- Author : Suleyman Demirsoy 26 | -- 27 | -- Project : Avalon Streaming Wrapper for DSPIP 28 | -- 29 | -- Description : 30 | -- 31 | -- This file is the Interface controller for the Avalon Streaming Wrapper. 32 | -- The control signals between sink, core, and source modules are communicated 33 | -- via the controller. The stall output is used as the core enable signal in 34 | -- the wrapper. 35 | -- 36 | -- 37 | -- Revision 1.1.2.1 2006/09/18 13:39:16 sdemirso 38 | -- clk_en behaviour corrected 39 | -- 40 | -- Revision 1.1 2006/08/22 15:30:53 sdemirso 41 | -- name change for the interface controller 42 | -- 43 | -- Revision 1.1 2006/08/22 14:58:51 sdemirso 44 | -- new versions of the atlantic II blocks 45 | -- 46 | -- ALTERA Confidential and Proprietary 47 | -- Copyright 2006 (c) Altera Corporation 48 | -- All rights reserved 49 | -- 50 | ------------------------------------------------------------------------- 51 | ------------------------------------------------------------------------- 52 | library ieee; 53 | use ieee.std_logic_1164.all; 54 | use ieee.std_logic_arith.all; 55 | 56 | 57 | entity auk_dspip_avalon_streaming_controller is 58 | port( 59 | clk : in std_logic; 60 | clk_en : in std_logic := '1'; 61 | reset_n : in std_logic; 62 | ready : in std_logic; 63 | sink_packet_error : in std_logic_vector (1 downto 0); 64 | sink_stall : in std_logic; 65 | source_stall : in std_logic; 66 | valid : in std_logic; 67 | reset_design : out std_logic; 68 | sink_ready_ctrl : out std_logic; 69 | source_packet_error : out std_logic_vector (1 downto 0); 70 | source_valid_ctrl : out std_logic; 71 | stall : out std_logic 72 | ); 73 | 74 | -- Declarations 75 | 76 | end auk_dspip_avalon_streaming_controller; 77 | 78 | -- hds interface_end 79 | 80 | architecture struct of auk_dspip_avalon_streaming_controller is 81 | 82 | signal stall_int : std_logic; 83 | -- signal res : std_logic; 84 | signal sink_stall_reg : std_logic; 85 | signal source_stall_reg : std_logic; 86 | signal stall_reg : std_logic; 87 | 88 | -- attributes for stall_reg to limit max fanout 89 | attribute maxfan : integer; 90 | attribute maxfan of stall_reg : signal is 500; 91 | --attribute maxfan of res : signal is 500; 92 | 93 | -- attributes for res 94 | --attribute altera_attribute : string; 95 | --attribute altera_attribute of res : signal is "-name ADV_NETLIST_OPT_ALLOWED ""ALWAYS ALLOW"" "; 96 | 97 | begin 98 | 99 | reset_design <= not reset_n; 100 | 101 | stall_int <= sink_stall or source_stall; 102 | 103 | source_valid_ctrl <= valid and (not sink_stall_reg) and clk_en when source_stall_reg = '0' else 104 | valid; 105 | sink_ready_ctrl <= ready and (not source_stall_reg) and clk_en when sink_stall_reg = '0' else 106 | ready; 107 | stall <= stall_reg when clk_en = '1' else '1'; 108 | 109 | other_reg : process (clk, reset_n) 110 | begin -- process res_reg 111 | if reset_n = '0' then 112 | sink_stall_reg <= '1'; 113 | source_stall_reg <= '1'; 114 | stall_reg <= '1'; 115 | source_packet_error <= "00"; 116 | elsif rising_edge(clk) then 117 | sink_stall_reg <= sink_stall; 118 | source_stall_reg <= source_stall; 119 | stall_reg <= stall_int; 120 | source_packet_error <= sink_packet_error; 121 | end if; 122 | end process other_reg; 123 | end struct; 124 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/auk_dspip_text_pkg.vhd: -------------------------------------------------------------------------------- 1 | -- (C) 2001-2015 Altera Corporation. All rights reserved. 2 | -- Your use of Altera Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing (including device programming or simulation 5 | -- files), and any associated documentation or information are expressly subject 6 | -- to the terms and conditions of the Altera Program License Subscription 7 | -- Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | -- license agreement, including, without limitation, that your use is for the 9 | -- sole purpose of programming logic devices manufactured by Altera and sold by 10 | -- Altera or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | ------------------------------------------------------------------------- 15 | ------------------------------------------------------------------------- 16 | -- 17 | -- Revision Control Information 18 | -- 19 | -- $RCSfile: auk_dspip_text_pkg.vhd,v $ 20 | -- $Source: /cvs/uksw/dsp_cores/lib/packages/auk_dspip_text_pkg.vhd,v $ 21 | -- 22 | -- $Revision: #1 $ 23 | -- $Date: 2015/02/08 $ 24 | -- Check in by : $Author: swbranch $ 25 | -- Author : DSP_IP 26 | -- 27 | -- Project : 28 | -- 29 | -- Description : 30 | -- 31 | -- Common functions for DSP_IP cores. 32 | -- 33 | -- 34 | -- $Log: auk_dspip_text_pkg.vhd,v $ 35 | -- Revision 1.2 2007/05/04 15:33:11 sdemirso 36 | -- merge from 7.1 37 | -- 38 | -- Revision 1.1 2007/02/01 17:29:45 kmarks 39 | -- Initial commit 40 | -- 41 | -- Revision 1.5 2006/08/17 10:13:02 sdemirso 42 | -- log2_ceil_one function added 43 | -- 44 | -- Revision 1.4 2006/07/28 18:52:50 sdemirso 45 | -- no compilation errors with the new directory structure 46 | -- 47 | -- Revision 1.3 2006/07/28 10:27:30 sdemirso 48 | -- Header updated 49 | -- 50 | -- ALTERA Confidential and Proprietary 51 | -- Copyright 2006 (c) Altera Corporation 52 | -- All rights reserved 53 | -- 54 | ------------------------------------------------------------------------- 55 | ------------------------------------------------------------------------- 56 | 57 | LIBRARY ieee; 58 | USE ieee.std_logic_1164.all; 59 | use ieee.numeric_std.all; 60 | PACKAGE auk_dspip_text_pkg IS 61 | 62 | 63 | ----------------------------------------------------------------------------- 64 | -- NOTE that these log functions are not intended to synthesize directly 65 | -- into hardware, rather they are used to generate constants for 66 | -- synthesized hardware. 67 | ----------------------------------------------------------------------------- 68 | type array_natural_t is array (natural range <>) of integer; 69 | 70 | function parse_string_array (str : string; size : natural) return array_natural_t; 71 | 72 | function str_to_int (str : string; base : string) return integer; 73 | 74 | END PACKAGE auk_dspip_text_pkg; 75 | 76 | package body auk_dspip_text_pkg is 77 | --------------------------------------------------------------------------- 78 | -- str_to_int Function. Only parses positive decimal values 79 | --------------------------------------------------------------------------- 80 | function str_to_int(str : string; base : string) return integer is 81 | variable res : integer; 82 | variable base_cnt : integer; 83 | begin 84 | res := 0; 85 | base_cnt:=1; 86 | for i in str'length downto 1 loop 87 | if str(i) /= ' ' then 88 | res := res + (character'pos(str(i)) - character'pos('0'))*base_cnt; 89 | base_cnt:=base_cnt*10; 90 | end if; 91 | end loop; -- i 92 | return res; 93 | end str_to_int; 94 | 95 | --------------------------------------------------------------------------- 96 | -- parse_string_array Function. 97 | --------------------------------------------------------------------------- 98 | function parse_string_array(str : string; size : natural) return array_natural_t is 99 | variable this_str : string(1 to 32); 100 | variable cnt_char : natural; -- how many characters have we seen 101 | variable cnt_str : natural:=0; 102 | variable res : array_natural_t(0 to size-1); 103 | begin 104 | this_str := (others => ' '); 105 | cnt_char := 1; 106 | for i in str'left to str'right loop 107 | if str(i) = ',' then 108 | res(cnt_str) := str_to_int(this_str, "DEC"); 109 | cnt_char := 1; 110 | cnt_str := cnt_str + 1; 111 | this_str := (others => ' '); 112 | else 113 | this_str(cnt_char) := str(i); 114 | cnt_char := cnt_char+1; 115 | end if; 116 | end loop; -- i 117 | res(cnt_str) := str_to_int(this_str, "DEC"); 118 | return res; 119 | end parse_string_array; 120 | 121 | end package body auk_dspip_text_pkg; 122 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/auk_fft_pkg.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/ifft_project/fft_ipcore/synthesis/submodules/auk_fft_pkg.vhd -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0.sv: -------------------------------------------------------------------------------- 1 | // (C) 2001-2015 Altera Corporation. All rights reserved. 2 | // Your use of Altera Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Altera Program License Subscription 7 | // Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Altera and sold by 10 | // Altera or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | 15 | module fft_ipcore_fft_ii_0 ( 16 | input clk, 17 | input reset_n, 18 | input [0 : 0] inverse, 19 | input sink_valid, 20 | input sink_sop, 21 | input sink_eop, 22 | input logic [15 : 0] sink_real, 23 | input logic [15 : 0] sink_imag, 24 | input logic [1 : 0] sink_error, 25 | input source_ready, 26 | output [5 : 0] source_exp, 27 | output sink_ready, 28 | output [1 : 0] source_error, 29 | output source_sop, 30 | output source_eop, 31 | output source_valid, 32 | output [15 : 0] source_real, 33 | output [15 : 0] source_imag 34 | ); 35 | 36 | asj_fft_sglstream #( 37 | .device_family("Cyclone V"), 38 | .nps(64), 39 | .bfp(1), 40 | .nume(1), 41 | .mpr(16), 42 | .twr(16), 43 | .bpr(16), 44 | .bpb(4), 45 | .fpr(4), 46 | .mram(0), 47 | .m512(0), 48 | .mult_type(1), 49 | .mult_imp(0), 50 | .dsp_arch(2), 51 | .srr("AUTO_SHIFT_REGISTER_RECOGNITION=OFF"), 52 | .rfs1("fft_ipcore_fft_ii_0_1n64sin.hex"), 53 | .rfs2("fft_ipcore_fft_ii_0_2n64sin.hex"), 54 | .rfs3("fft_ipcore_fft_ii_0_3n64sin.hex"), 55 | .rfc1("fft_ipcore_fft_ii_0_1n64cos.hex"), 56 | .rfc2("fft_ipcore_fft_ii_0_2n64cos.hex"), 57 | .rfc3("fft_ipcore_fft_ii_0_3n64cos.hex") 58 | ) 59 | asj_fft_sglstream_inst ( 60 | .clk(clk), 61 | .clk_ena(1'b1), 62 | .reset_n(reset_n), 63 | .inverse(inverse), 64 | .sink_valid(sink_valid), 65 | .sink_sop(sink_sop), 66 | .sink_eop(sink_eop), 67 | .sink_real(sink_real), 68 | .sink_imag(sink_imag), 69 | .sink_ready(sink_ready), 70 | .sink_error(sink_error), 71 | .source_error(source_error), 72 | .source_ready(source_ready), 73 | .source_sop(source_sop), 74 | .source_eop(source_eop), 75 | .source_valid(source_valid), 76 | .source_exp(source_exp), 77 | .source_real(source_real), 78 | .source_imag(source_imag) 79 | ); 80 | endmodule 81 | 82 | 83 | 84 | 85 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0_1n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007f611d 3 | :020002007d89f6 4 | :020003007a7c05 5 | :02000400764143 6 | :0200050070e2a7 7 | :020006006a6d21 8 | :0200070062f1a4 9 | :020008005a821a 10 | :02000900513371 11 | :02000a00471c91 12 | :02000b003c5661 13 | :02000c0030fbc7 14 | :02000d002528a4 15 | :02000e0018f9df 16 | :02000f000c8c57 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0_1n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :020001000c8c65 3 | :0200020018f9eb 4 | :020003002528ae 5 | :0200040030fbcf 6 | :020005003c5667 7 | :02000600471c95 8 | :02000700513373 9 | :020008005a821a 10 | :0200090062f1a2 11 | :02000a006a6d1d 12 | :02000b0070e2a1 13 | :02000c0076413b 14 | :02000d007a7cfb 15 | :02000e007d89ea 16 | :02000f007f610f 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0_2n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007d89f7 3 | :02000200764145 4 | :020003006a6d24 5 | :020004005a821e 6 | :02000500471c96 7 | :0200060030fbcd 8 | :0200070018f9e6 9 | :020008000000f6 10 | :02000900e70707 11 | :02000a00cf0520 12 | :02000b00b8e457 13 | :02000c00a57ecf 14 | :02000d009593c9 15 | :02000e0089bfa8 16 | :02000f008277f6 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0_2n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :0200010018f9ec 3 | :0200020030fbd1 4 | :02000300471c98 5 | :020004005a821e 6 | :020005006a6d22 7 | :02000600764141 8 | :020007007d89f1 9 | :020008007fff78 10 | :020009007d89ef 11 | :02000a0076413d 12 | :02000b006a6d1c 13 | :02000c005a8216 14 | :02000d00471c8e 15 | :02000e0030fbc5 16 | :02000f0018f9de 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0_3n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007a7c07 3 | :020002006a6d25 4 | :02000300513377 5 | :0200040030fbcf 6 | :020005000c8c61 7 | :02000600e7070a 8 | :02000700c3aa8a 9 | :02000800a57ed3 10 | :020009008f1e48 11 | :02000a008277fb 12 | :02000b00809fd4 13 | :02000c0089bfaa 14 | :02000d009d0f45 15 | :02000e00b8e454 16 | :02000f00dad83d 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_ipcore_fft_ii_0_3n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :020001002528b0 3 | :02000200471c99 4 | :0200030062f1a8 5 | :02000400764143 6 | :020005007f6119 7 | :020006007d89f2 8 | :0200070070e2a5 9 | :020008005a821a 10 | :020009003c5663 11 | :02000a0018f9e3 12 | :02000b00f3748c 13 | :02000c00cf051e 14 | :02000d00aecd76 15 | :02000e009593c8 16 | :02000f008584e6 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_pack.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/ifft_project/fft_ipcore/synthesis/submodules/fft_pack.vhd -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/synthesis/submodules/twid_rom.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/ifft_project/fft_ipcore/synthesis/submodules/twid_rom.vhd -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/test_data/fft_ii_0_example_design_imag_input.txt: -------------------------------------------------------------------------------- 1 | 0 2 | 0 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 0 9 | 0 10 | 0 11 | 0 12 | 0 13 | 0 14 | 0 15 | 0 16 | 0 17 | 0 18 | 0 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 0 31 | 0 32 | 0 33 | 0 34 | 0 35 | 0 36 | 0 37 | 0 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 0 44 | 0 45 | 0 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 0 59 | 0 60 | 0 61 | 0 62 | 0 63 | 0 64 | 0 65 | 32767 66 | 0 67 | 0 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | 0 74 | 0 75 | 0 76 | 0 77 | 0 78 | 0 79 | 0 80 | 0 81 | 0 82 | 0 83 | 0 84 | 0 85 | 0 86 | 0 87 | 0 88 | 0 89 | 0 90 | 0 91 | 0 92 | 0 93 | 0 94 | 0 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 0 101 | 0 102 | 0 103 | 0 104 | 0 105 | 0 106 | 0 107 | 0 108 | 0 109 | 0 110 | 0 111 | 0 112 | 0 113 | 0 114 | 0 115 | 0 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | 0 128 | 0 129 | 0 130 | 0 131 | 0 132 | 0 133 | 0 134 | 0 135 | 0 136 | 0 137 | 0 138 | 0 139 | 0 140 | 0 141 | 0 142 | 0 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 0 151 | 0 152 | 0 153 | 0 154 | 0 155 | 0 156 | 0 157 | 0 158 | 0 159 | 0 160 | 0 161 | 0 162 | 0 163 | 0 164 | 0 165 | 0 166 | 0 167 | 0 168 | 0 169 | 0 170 | 0 171 | 0 172 | 0 173 | 0 174 | 0 175 | 0 176 | 0 177 | 0 178 | 0 179 | 0 180 | 0 181 | 0 182 | 0 183 | 0 184 | 0 185 | 0 186 | 0 187 | 0 188 | 0 189 | 0 190 | 0 191 | 0 192 | 0 193 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/test_data/fft_ii_0_example_design_inverse_report.txt: -------------------------------------------------------------------------------- 1 | 0 2 | 1 3 | 0 4 | 1 5 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/fft_ipcore/test_data/fft_ii_0_example_design_real_input.txt: -------------------------------------------------------------------------------- 1 | 32767 2 | 30273 3 | 23170 4 | 12539 5 | 0 6 | -12539 7 | -23170 8 | -30273 9 | -32767 10 | -30273 11 | -23170 12 | -12539 13 | 0 14 | 12539 15 | 23170 16 | 30273 17 | 32767 18 | 30273 19 | 23170 20 | 12539 21 | 0 22 | -12539 23 | -23170 24 | -30273 25 | -32767 26 | -30273 27 | -23170 28 | -12539 29 | 0 30 | 12539 31 | 23170 32 | 30273 33 | 32767 34 | 30273 35 | 23170 36 | 12539 37 | 0 38 | -12539 39 | -23170 40 | -30273 41 | -32767 42 | -30273 43 | -23170 44 | -12539 45 | 0 46 | 12539 47 | 23170 48 | 30273 49 | 32767 50 | 30273 51 | 23170 52 | 12539 53 | 0 54 | -12539 55 | -23170 56 | -30273 57 | -32767 58 | -30273 59 | -23170 60 | -12539 61 | 0 62 | 12539 63 | 23170 64 | 30273 65 | 32767 66 | 0 67 | 0 68 | 0 69 | 0 70 | 0 71 | 0 72 | 0 73 | 0 74 | 0 75 | 0 76 | 0 77 | 0 78 | 0 79 | 0 80 | 0 81 | 0 82 | 0 83 | 0 84 | 0 85 | 0 86 | 0 87 | 0 88 | 0 89 | 0 90 | 0 91 | 0 92 | 0 93 | 0 94 | 0 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 0 101 | 0 102 | 0 103 | 0 104 | 0 105 | 0 106 | 0 107 | 0 108 | 0 109 | 0 110 | 0 111 | 0 112 | 0 113 | 0 114 | 0 115 | 0 116 | 0 117 | 0 118 | 0 119 | 0 120 | 0 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | 0 128 | 0 129 | 32767 130 | 30273 131 | 23170 132 | 12539 133 | 0 134 | -12539 135 | -23170 136 | -30273 137 | -32767 138 | -30273 139 | -23170 140 | -12539 141 | 0 142 | 12539 143 | 23170 144 | 30273 145 | 32767 146 | 30273 147 | 23170 148 | 12539 149 | 0 150 | -12539 151 | -23170 152 | -30273 153 | -32767 154 | -30273 155 | -23170 156 | -12539 157 | 0 158 | 12539 159 | 23170 160 | 30273 161 | 32767 162 | 30273 163 | 23170 164 | 12539 165 | 0 166 | -12539 167 | -23170 168 | -30273 169 | -32767 170 | -30273 171 | -23170 172 | -12539 173 | 0 174 | 12539 175 | 23170 176 | 30273 177 | 32767 178 | 30273 179 | 23170 180 | 12539 181 | 0 182 | -12539 183 | -23170 184 | -30273 185 | -32767 186 | -30273 187 | -23170 188 | -12539 189 | 0 190 | 12539 191 | 23170 192 | 30273 193 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/ifft_clac.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Full Version 22 | # Date created = 20:41:09 December 08, 2015 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "15.0" 27 | DATE = "20:41:09 December 08, 2015" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "ifft_clac" 32 | -------------------------------------------------------------------------------- /source/ifft/ifft_project/ifft_clac.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2015 Altera Corporation. All rights reserved. 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, the Altera Quartus II License Agreement, 11 | # the Altera MegaCore Function License Agreement, or other 12 | # applicable license agreement, including, without limitation, 13 | # that your use is for the sole purpose of programming logic 14 | # devices manufactured by Altera and sold by Altera or its 15 | # authorized distributors. Please refer to the applicable 16 | # agreement for further details. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus II 64-Bit 21 | # Version 15.0.0 Build 145 04/22/2015 SJ Full Version 22 | # Date created = 20:41:09 December 08, 2015 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # ifft_clac_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus II software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone V" 41 | set_global_assignment -name DEVICE 5CSXFC6D6F31C6 42 | set_global_assignment -name TOP_LEVEL_ENTITY ifft_clac 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:41:09 DECEMBER 08, 2015" 45 | set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 50 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" 51 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 52 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 53 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 54 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 55 | set_global_assignment -name VERILOG_FILE ifft_clac.v 56 | set_global_assignment -name QSYS_FILE fft_ipcore.qsys 57 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 58 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 59 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 60 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -------------------------------------------------------------------------------- /source/ifft/ifft_project/ifft_clac.v: -------------------------------------------------------------------------------- 1 | //功能：ifft变换 2 | //方法：调用Altera FFT IP CORE 3 | //结构：流水线 4 | module ifft_clac #(parameter WIDTH = 16) ( 5 | input ifft_clk, 6 | input ifft_rst_n, 7 | input din_valid, 8 | 9 | input [WIDTH-1:0] ifft_real_din, 10 | input [WIDTH-1:0] ifft_imag_din, 11 | 12 | output [5:0] dout_exp, 13 | output dout_valid, 14 | output reg [5:0] dout_index, 15 | output [WIDTH-1:0] ifft_real_dout, 16 | output [WIDTH-1:0] ifft_imag_dout); 17 | 18 | reg [5:0] frame_cnt; 19 | reg sink_valid; 20 | reg [WIDTH-1:0] sink_real; 21 | reg [WIDTH-1:0] sink_imag; 22 | 23 | wire sink_ready; 24 | wire source_ready; 25 | wire inverse; 26 | wire [1:0] sink_error; 27 | wire sink_sop; 28 | wire sink_eop; 29 | 30 | wire source_sop; 31 | wire source_eop; 32 | wire [1:0] source_error; 33 | //wire source_valid; 34 | //wire source_exp; 35 | 36 | assign inverse = 1'b1; // '0' => FFT ,'1' => IFFT 37 | assign sink_error = 2'b0; //no input error 38 | assign source_ready = 1'b1; 39 | assign sink_sop = (frame_cnt == 0 & din_valid== 1'b1) ? 1'b1 : 1'b0 ; 40 | assign sink_eop = ( frame_cnt == 63) ? 1'b1 : 1'b0; 41 | 42 | //输入控制模块 43 | always@(posedge ifft_clk) begin 44 | if(!ifft_rst_n) begin 45 | sink_valid <= 1'b0; 46 | sink_real <= 0; 47 | sink_imag <= 0; 48 | end 49 | else begin 50 | if(din_valid) begin 51 | sink_valid <= din_valid; 52 | sink_real <= ifft_real_din; 53 | sink_imag <= ifft_imag_din; 54 | end 55 | else begin 56 | sink_valid <= 1'b0; 57 | sink_real <= 0; 58 | sink_imag <= 0; 59 | end 60 | end 61 | end 62 | 63 | //64计数模块 64 | always@(posedge ifft_clk) begin 65 | if(!ifft_rst_n) begin 66 | frame_cnt <= 1'b0; 67 | end 68 | else begin 69 | if(sink_valid) begin 70 | frame_cnt <= frame_cnt + 1'b1; 71 | end 72 | else begin 73 | frame_cnt <= 1'b0; 74 | end 75 | end 76 | end 77 | 78 | //输出计数模块0-63 79 | always@(posedge ifft_clk) begin 80 | if(!ifft_rst_n) begin 81 | dout_index <= 0; 82 | end 83 | else begin 84 | if(dout_valid) begin 85 | dout_index <= dout_index + 1'b1; 86 | end 87 | else begin 88 | dout_index <= 0; 89 | end 90 | end 91 | end 92 | 93 | //调用fft ip核 94 | fft_ipcore ifft_ins( 95 | .clk(ifft_clk), 96 | .reset_n(ifft_rst_n), 97 | .inverse(inverse), 98 | .sink_valid(sink_valid), 99 | .sink_sop(sink_sop), 100 | .sink_eop(sink_eop), 101 | .sink_real(sink_real), 102 | .sink_imag(sink_imag), 103 | .sink_error(sink_error), 104 | .source_ready(source_ready), 105 | .sink_ready(sink_ready), 106 | .source_error(source_error), 107 | .source_sop(source_sop), 108 | .source_eop(source_eop), 109 | .source_valid(dout_valid), 110 | .source_exp(dout_exp), 111 | .source_real(ifft_real_dout), 112 | .source_imag(ifft_imag_dout)); 113 | 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/data/exp.txt: -------------------------------------------------------------------------------- 1 | -4 2 | -4 3 | -4 4 | -4 5 | -4 6 | -4 7 | -4 8 | -4 9 | -4 10 | -4 11 | -4 12 | -4 13 | -4 14 | -4 15 | -4 16 | -4 17 | -4 18 | -4 19 | -4 20 | -4 21 | -4 22 | -4 23 | -4 24 | -4 25 | -4 26 | -4 27 | -4 28 | -4 29 | -4 30 | -4 31 | -4 32 | -4 33 | -4 34 | -4 35 | -4 36 | -4 37 | -4 38 | -4 39 | -4 40 | -4 41 | -4 42 | -4 43 | -4 44 | -4 45 | -4 46 | -4 47 | -4 48 | -4 49 | -4 50 | -4 51 | -4 52 | -4 53 | -4 54 | -4 55 | -4 56 | -4 57 | -4 58 | -4 59 | -4 60 | -4 61 | -4 62 | -4 63 | -4 64 | -4 65 | -4 66 | -4 67 | -4 68 | -4 69 | -4 70 | -4 71 | -4 72 | -4 73 | -4 74 | -4 75 | -4 76 | -4 77 | -4 78 | -4 79 | -4 80 | -4 81 | -4 82 | -4 83 | -4 84 | -4 85 | -4 86 | -4 87 | -4 88 | -4 89 | -4 90 | -4 91 | -4 92 | -4 93 | -4 94 | -4 95 | -4 96 | -4 97 | -4 98 | -4 99 | -4 100 | -4 101 | -4 102 | -4 103 | -4 104 | -4 105 | -4 106 | -4 107 | -4 108 | -4 109 | -4 110 | -4 111 | -4 112 | -4 113 | -4 114 | -4 115 | -4 116 | -4 117 | -4 118 | -4 119 | -4 120 | -4 121 | -4 122 | -4 123 | -4 124 | -4 125 | -4 126 | -4 127 | -4 128 | -4 129 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/data/im_din.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | 1 66 | 2 67 | 3 68 | 4 69 | 5 70 | 6 71 | 7 72 | 8 73 | 9 74 | 10 75 | 11 76 | 12 77 | 13 78 | 14 79 | 15 80 | 16 81 | 17 82 | 18 83 | 19 84 | 20 85 | 21 86 | 22 87 | 23 88 | 24 89 | 25 90 | 26 91 | 27 92 | 28 93 | 29 94 | 30 95 | 31 96 | 32 97 | 33 98 | 34 99 | 35 100 | 36 101 | 37 102 | 38 103 | 39 104 | 40 105 | 41 106 | 42 107 | 43 108 | 44 109 | 45 110 | 46 111 | 47 112 | 48 113 | 49 114 | 50 115 | 51 116 | 52 117 | 53 118 | 54 119 | 55 120 | 56 121 | 57 122 | 58 123 | 59 124 | 60 125 | 61 126 | 62 127 | 63 128 | 64 -------------------------------------------------------------------------------- /source/ifft/ifft_sim/data/im_dout.txt: -------------------------------------------------------------------------------- 1 | 132 2 | -43 3 | -23 4 | -15 5 | -12 6 | -10 7 | -10 8 | -6 9 | -7 10 | -7 11 | -5 12 | -6 13 | -5 14 | -5 15 | -4 16 | -4 17 | -4 18 | -3 19 | -4 20 | -4 21 | -4 22 | -2 23 | -4 24 | -3 25 | -3 26 | -4 27 | -3 28 | -3 29 | -3 30 | -3 31 | -3 32 | -2 33 | 0 34 | -2 35 | -1 36 | -2 37 | -2 38 | -1 39 | -1 40 | -1 41 | -1 42 | -1 43 | -1 44 | -1 45 | -1 46 | -1 47 | 0 48 | -1 49 | 0 50 | 0 51 | 0 52 | 1 53 | 1 54 | 2 55 | 2 56 | 2 57 | 3 58 | 3 59 | 5 60 | 6 61 | 8 62 | 12 63 | 19 64 | 39 65 | 132 66 | -43 67 | -23 68 | -15 69 | -12 70 | -10 71 | -10 72 | -6 73 | -7 74 | -7 75 | -5 76 | -6 77 | -5 78 | -5 79 | -4 80 | -4 81 | -4 82 | -3 83 | -4 84 | -4 85 | -4 86 | -2 87 | -4 88 | -3 89 | -3 90 | -4 91 | -3 92 | -3 93 | -3 94 | -3 95 | -3 96 | -2 97 | 0 98 | -2 99 | -1 100 | -2 101 | -2 102 | -1 103 | -1 104 | -1 105 | -1 106 | -1 107 | -1 108 | -1 109 | -1 110 | -1 111 | 0 112 | -1 113 | 0 114 | 0 115 | 0 116 | 1 117 | 1 118 | 2 119 | 2 120 | 2 121 | 3 122 | 3 123 | 5 124 | 6 125 | 8 126 | 12 127 | 19 128 | 39 129 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/data/re_din.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | 1 66 | 2 67 | 3 68 | 4 69 | 5 70 | 6 71 | 7 72 | 8 73 | 9 74 | 10 75 | 11 76 | 12 77 | 13 78 | 14 79 | 15 80 | 16 81 | 17 82 | 18 83 | 19 84 | 20 85 | 21 86 | 22 87 | 23 88 | 24 89 | 25 90 | 26 91 | 27 92 | 28 93 | 29 94 | 30 95 | 31 96 | 32 97 | 33 98 | 34 99 | 35 100 | 36 101 | 37 102 | 38 103 | 39 104 | 40 105 | 41 106 | 42 107 | 43 108 | 44 109 | 45 110 | 46 111 | 47 112 | 48 113 | 49 114 | 50 115 | 51 116 | 52 117 | 53 118 | 54 119 | 55 120 | 56 121 | 57 122 | 58 123 | 59 124 | 60 125 | 61 126 | 62 127 | 63 128 | 64 -------------------------------------------------------------------------------- /source/ifft/ifft_sim/data/re_dout.txt: -------------------------------------------------------------------------------- 1 | 132 2 | 39 3 | 19 4 | 11 5 | 8 6 | 6 7 | 6 8 | 2 9 | 3 10 | 3 11 | 1 12 | 2 13 | 1 14 | 1 15 | 0 16 | 0 17 | 0 18 | -1 19 | 0 20 | 0 21 | -1 22 | -2 23 | -1 24 | -1 25 | -1 26 | 0 27 | -2 28 | -1 29 | -2 30 | -2 31 | -2 32 | -2 33 | 0 34 | -2 35 | -3 36 | -2 37 | -3 38 | -3 39 | -4 40 | -3 41 | -3 42 | -4 43 | -3 44 | -3 45 | -4 46 | -4 47 | -4 48 | -3 49 | -4 50 | -4 51 | -4 52 | -5 53 | -5 54 | -6 55 | -6 56 | -6 57 | -7 58 | -7 59 | -9 60 | -10 61 | -12 62 | -16 63 | -23 64 | -43 65 | 132 66 | 39 67 | 19 68 | 11 69 | 8 70 | 6 71 | 6 72 | 2 73 | 3 74 | 3 75 | 1 76 | 2 77 | 1 78 | 1 79 | 0 80 | 0 81 | 0 82 | -1 83 | 0 84 | 0 85 | -1 86 | -2 87 | -1 88 | -1 89 | -1 90 | 0 91 | -2 92 | -1 93 | -2 94 | -2 95 | -2 96 | -2 97 | 0 98 | -2 99 | -3 100 | -2 101 | -3 102 | -3 103 | -4 104 | -3 105 | -3 106 | -4 107 | -3 108 | -3 109 | -4 110 | -4 111 | -4 112 | -3 113 | -4 114 | -4 115 | -4 116 | -5 117 | -5 118 | -6 119 | -6 120 | -6 121 | -7 122 | -7 123 | -9 124 | -10 125 | -12 126 | -16 127 | -23 128 | -43 129 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/fft_core_1n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007f611d 3 | :020002007d89f6 4 | :020003007a7c05 5 | :02000400764143 6 | :0200050070e2a7 7 | :020006006a6d21 8 | :0200070062f1a4 9 | :020008005a821a 10 | :02000900513371 11 | :02000a00471c91 12 | :02000b003c5661 13 | :02000c0030fbc7 14 | :02000d002528a4 15 | :02000e0018f9df 16 | :02000f000c8c57 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/fft_core_1n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :020001000c8c65 3 | :0200020018f9eb 4 | :020003002528ae 5 | :0200040030fbcf 6 | :020005003c5667 7 | :02000600471c95 8 | :02000700513373 9 | :020008005a821a 10 | :0200090062f1a2 11 | :02000a006a6d1d 12 | :02000b0070e2a1 13 | :02000c0076413b 14 | :02000d007a7cfb 15 | :02000e007d89ea 16 | :02000f007f610f 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/fft_core_2n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007d89f7 3 | :02000200764145 4 | :020003006a6d24 5 | :020004005a821e 6 | :02000500471c96 7 | :0200060030fbcd 8 | :0200070018f9e6 9 | :020008000000f6 10 | :02000900e70707 11 | :02000a00cf0520 12 | :02000b00b8e457 13 | :02000c00a57ecf 14 | :02000d009593c9 15 | :02000e0089bfa8 16 | :02000f008277f6 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/fft_core_2n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :0200010018f9ec 3 | :0200020030fbd1 4 | :02000300471c98 5 | :020004005a821e 6 | :020005006a6d22 7 | :02000600764141 8 | :020007007d89f1 9 | :020008007fff78 10 | :020009007d89ef 11 | :02000a0076413d 12 | :02000b006a6d1c 13 | :02000c005a8216 14 | :02000d00471c8e 15 | :02000e0030fbc5 16 | :02000f0018f9de 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/fft_core_3n64cos.hex: -------------------------------------------------------------------------------- 1 | :020000007fff80 2 | :020001007a7c07 3 | :020002006a6d25 4 | :02000300513377 5 | :0200040030fbcf 6 | :020005000c8c61 7 | :02000600e7070a 8 | :02000700c3aa8a 9 | :02000800a57ed3 10 | :020009008f1e48 11 | :02000a008277fb 12 | :02000b00809fd4 13 | :02000c0089bfaa 14 | :02000d009d0f45 15 | :02000e00b8e454 16 | :02000f00dad83d 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/fft_core_3n64sin.hex: -------------------------------------------------------------------------------- 1 | :020000000000fe 2 | :020001002528b0 3 | :02000200471c99 4 | :0200030062f1a8 5 | :02000400764143 6 | :020005007f6119 7 | :020006007d89f2 8 | :0200070070e2a5 9 | :020008005a821a 10 | :020009003c5663 11 | :02000a0018f9e3 12 | :02000b00f3748c 13 | :02000c00cf051e 14 | :02000d00aecd76 15 | :02000e009593c8 16 | :02000f008584e6 17 | :00000001FF 18 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/ifft_clac.v: -------------------------------------------------------------------------------- 1 | //功能：ifft变换 2 | //方法：调用Altera FFT IP CORE 3 | //结构：流水线 4 | module ifft_clac #(parameter WIDTH = 16) ( 5 | input ifft_clk, 6 | input ifft_rst_n, 7 | input din_valid, 8 | 9 | input [WIDTH-1:0] ifft_real_din, 10 | input [WIDTH-1:0] ifft_imag_din, 11 | 12 | output [5:0] dout_exp, 13 | output dout_valid, 14 | output reg [5:0] dout_index, 15 | output [WIDTH-1:0] ifft_real_dout, 16 | output [WIDTH-1:0] ifft_imag_dout); 17 | 18 | reg [5:0] frame_cnt; 19 | reg sink_valid; 20 | reg [WIDTH-1:0] sink_real; 21 | reg [WIDTH-1:0] sink_imag; 22 | 23 | wire sink_ready; 24 | wire source_ready; 25 | wire inverse; 26 | wire [1:0] sink_error; 27 | wire sink_sop; 28 | wire sink_eop; 29 | 30 | wire source_sop; 31 | wire source_eop; 32 | wire [1:0] source_error; 33 | //wire source_valid; 34 | //wire source_exp; 35 | 36 | assign inverse = 1'b1; // '0' => FFT ,'1' => IFFT 37 | assign sink_error = 2'b0; //no input error 38 | assign source_ready = 1'b1; 39 | assign sink_sop = (frame_cnt == 0 & sink_valid== 1'b1) ? 1'b1 : 1'b0 ; 40 | assign sink_eop = ( frame_cnt == 63) ? 1'b1 : 1'b0; 41 | 42 | //输入控制模块 43 | always@(posedge ifft_clk) begin 44 | if(!ifft_rst_n) begin 45 | sink_valid <= 1'b0; 46 | sink_real <= 0; 47 | sink_imag <= 0; 48 | end 49 | else begin 50 | if(din_valid) begin 51 | sink_valid <= din_valid; 52 | sink_real <= ifft_real_din; 53 | sink_imag <= ifft_imag_din; 54 | end 55 | else begin 56 | sink_valid <= 1'b0; 57 | sink_real <= 0; 58 | sink_imag <= 0; 59 | end 60 | end 61 | end 62 | 63 | //64计数模块 64 | always@(posedge ifft_clk) begin 65 | if(!ifft_rst_n) begin 66 | frame_cnt <= 1'b0; 67 | end 68 | else begin 69 | if(sink_valid) begin 70 | frame_cnt <= frame_cnt + 1'b1; 71 | end 72 | else begin 73 | frame_cnt <= 1'b0; 74 | end 75 | end 76 | end 77 | 78 | //输出计数模块0-63 79 | always@(posedge ifft_clk) begin 80 | if(!ifft_rst_n) begin 81 | dout_index <= 0; 82 | end 83 | else begin 84 | if(dout_valid) begin 85 | dout_index <= dout_index + 1'b1; 86 | end 87 | else begin 88 | dout_index <= 0; 89 | end 90 | end 91 | end 92 | 93 | //调用fft ip核 94 | fft_core ifft_ins( 95 | .clk(ifft_clk), 96 | .reset_n(ifft_rst_n), 97 | .inverse(inverse), 98 | .sink_valid(sink_valid), 99 | .sink_sop(sink_sop), 100 | .sink_eop(sink_eop), 101 | .sink_real(sink_real), 102 | .sink_imag(sink_imag), 103 | .sink_error(sink_error), 104 | .source_ready(source_ready), 105 | .sink_ready(sink_ready), 106 | .source_error(source_error), 107 | .source_sop(source_sop), 108 | .source_eop(source_eop), 109 | .source_valid(dout_valid), 110 | .source_exp(dout_exp), 111 | .source_real(ifft_real_dout), 112 | .source_imag(ifft_imag_dout)); 113 | 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/ifft_clac_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | module ifft_clac_tb; 4 | //inputs 5 | reg ifft_clk; 6 | reg ifft_rst_n; 7 | reg din_valid; 8 | reg [16 - 1:0] ifft_real_din; 9 | reg [16 - 1:0] ifft_imag_din; 10 | wire [5:0] dout_index; 11 | wire dout_valid; 12 | wire [5:0] dout_exp; 13 | wire [16 - 1: 0] ifft_real_dout; 14 | wire [16 - 1: 0] ifft_imag_dout; 15 | 16 | integer ifft_re, ifft_im; 17 | integer expf; 18 | integer data_re,data_im; 19 | 20 | initial begin 21 | data_re = $fopen("C:/Users/Administrator/Desktop/fft_test/data/re_din.txt","r"); 22 | data_im = $fopen("C:/Users/Administrator/Desktop/fft_test/data/im_din.txt","r"); 23 | ifft_re = $fopen("C:/Users/Administrator/Desktop/fft_test/data/re_dout.txt"); 24 | ifft_im = $fopen("C:/Users/Administrator/Desktop/fft_test/data/im_dout.txt"); 25 | expf = $fopen("C:/Users/Administrator/Desktop/fft_test/data/exp.txt"); 26 | ifft_clk = 0; 27 | ifft_rst_n = 0; 28 | din_valid = 0; 29 | #120; //3*40 30 | ifft_rst_n = 1; 31 | //@(posedge ifft_clk); 32 | din_valid = 1; 33 | #2560; //64*40 34 | din_valid = 0; 35 | #640; //16*40 36 | din_valid = 1; 37 | #2560; //64*40 38 | din_valid = 0; 39 | #4000; 40 | #4000; 41 | #4000; 42 | $stop(); 43 | end 44 | 45 | always #20 ifft_clk = ~ifft_clk; 46 | 47 | integer rc_x,ic_x,data_real_in_int,data_imag_in_int; 48 | always@(negedge ifft_clk) begin 49 | if(!ifft_rst_n) begin 50 | ifft_real_din <= 0; 51 | ifft_imag_din <= 0; 52 | end 53 | else begin 54 | if(din_valid) begin 55 | rc_x = $fscanf(data_re,"%d",data_real_in_int); 56 | ifft_real_din <= data_real_in_int; 57 | ic_x = $fscanf(data_im,"%d",data_imag_in_int); 58 | ifft_imag_din <= data_imag_in_int; 59 | end 60 | else begin 61 | ifft_real_din <= 0; 62 | ifft_imag_din <= 0; 63 | end 64 | end 65 | end 66 | 67 | 68 | parameter MAXVAL_c = 2**(16 -1); 69 | parameter OFFSET_c = 2**(16); 70 | parameter MAXVAL_EXP_c = 2**5; 71 | parameter OFFSET_EXP_c = 2**6; 72 | integer ifft_real_out_int,ifft_imag_out_int,exponent_out_int; 73 | //integer ifft_re_dout,ifft_im_dout; 74 | always @ (posedge ifft_clk) begin //注意Altera FFT核进行IFFT变换得到结果还需要进行处理 75 | if(dout_valid) begin //realvalud = dataout*2^(-exp)/N 76 | exponent_out_int = dout_exp ; 77 | ifft_real_out_int = ifft_real_dout; 78 | ifft_imag_out_int = ifft_imag_dout; 79 | //$fdisplay(ifft_re, "%d", ifft_real_out_int ); 80 | //$fdisplay(ifft_im, "%d", ifft_imag_out_int ); 81 | //$fdisplay(expf, "%d", exponent_out_int); 82 | $fdisplay(ifft_re, "%d", (ifft_real_out_int < MAXVAL_c) ? ifft_real_out_int : ifft_real_out_int - OFFSET_c); //转换成正负数 83 | $fdisplay(ifft_im, "%d", (ifft_imag_out_int < MAXVAL_c) ? ifft_imag_out_int : ifft_imag_out_int - OFFSET_c); 84 | $fdisplay(expf, "%d", (exponent_out_int < MAXVAL_EXP_c) ? exponent_out_int : exponent_out_int - OFFSET_EXP_c); 85 | end 86 | end 87 | ifft_clac dut( 88 | .ifft_clk(ifft_clk), 89 | .ifft_rst_n(ifft_rst_n), 90 | .din_valid(din_valid), 91 | .ifft_real_din(ifft_real_din), 92 | .ifft_imag_din(ifft_imag_din), 93 | .dout_valid(dout_valid), 94 | .ifft_real_dout(ifft_real_dout), 95 | .ifft_imag_dout(ifft_imag_dout), 96 | .dout_exp(dout_exp), 97 | .dout_index(dout_index)); 98 | endmodule 99 | -------------------------------------------------------------------------------- /source/ifft/ifft_sim/ifft_sim.do: -------------------------------------------------------------------------------- 1 | 2 | vlib work 3 | vmap work work 4 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/altera_primitives.v 5 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/220model.v 6 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/sgate.v 7 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/altera_mf.v 8 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/altera_lnsim.sv 9 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_atoms_ncrypt.v 10 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_hmi_atoms_ncrypt.v 11 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_atoms.v 12 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_hssi_atoms_ncrypt.v 13 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_hssi_atoms.v 14 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_pcie_hip_atoms_ncrypt.v 15 | vlog C:/Users/Administrator/Desktop/fft_test/sim_lib/cyclonev_pcie_hip_atoms.v 16 | 17 | 18 | vlog fft_core.vo 19 | vlog ifft_clac.v 20 | vlog ifft_clac_tb.v 21 | vsim ifft_clac_tb 22 | 23 | 24 | add wave -label ifft_clk /ifft_clac_tb/ifft_clk 25 | add wave -label ifft_rst_n /ifft_clac_tb/ifft_rst_n 26 | add wave -label din_valid /ifft_clac_tb/din_valid 27 | add wave -radix dec -label ifft_real_din /ifft_clac_tb/ifft_real_din 28 | add wave -radix dec -label ifft_imag_din /ifft_clac_tb/ifft_imag_din 29 | add wave -color Yellow -label sink_valid /ifft_clac_tb/dut/sink_valid 30 | add wave -color Yellow -label sink_ready /ifft_clac_tb/dut/sink_ready 31 | add wave -color Yellow -label inverse /ifft_clac_tb/dut/inverse 32 | add wave -color Yellow -label sink_sop /ifft_clac_tb/dut/sink_sop 33 | add wave -color Yellow -label sink_eop /ifft_clac_tb/dut/sink_eop 34 | add wave -color Yellow -radix dec -label sink_real /ifft_clac_tb/dut/sink_real 35 | add wave -color Yellow -radix dec -label sink_imag /ifft_clac_tb/dut/sink_imag 36 | 37 | add wave -color Magenta -radix dec -label ifft_real_dout /ifft_clac_tb/ifft_real_dout 38 | add wave -color Magenta -radix dec -label ifft_imag_dout /ifft_clac_tb/ifft_imag_dout 39 | add wave -color Magenta -radix unsigned -label dout_index /ifft_clac_tb/dout_index 40 | add wave -color Magenta -radix dec -label dout_exp /ifft_clac_tb/dout_exp 41 | add wave -color Magenta -label source_ready /ifft_clac_tb/dut/source_ready 42 | add wave -color Magenta -label source_sop /ifft_clac_tb/dut/source_sop 43 | add wave -color Magenta -label source_eop /ifft_clac_tb/dut/source_eop 44 | add wave -color Magenta -label dout_valid /ifft_clac_tb/dout_valid 45 | add wave -color Magenta -label source_error /ifft_clac_tb/dut/source_error 46 | run -all; -------------------------------------------------------------------------------- /source/ifft/ifft_sim/sim_lib/altera_mf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/ifft_sim/sim_lib/altera_mf.v -------------------------------------------------------------------------------- /source/ifft/ifft_sim/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/ifft/ifft_sim/vsim.wlf -------------------------------------------------------------------------------- /source/map/QAM16_MAP.v: -------------------------------------------------------------------------------- 1 | //16QAM map 2 | //定点数数据格式: 字长 16 bit 3 | // 符号位 1 bit 4 | // 整数位 1 bit 5 | // 小数位 14 bit 6 | 7 | // 编码表 8 | // b0b1 I | b3b4 Q 9 | // 00 -3 | 00 -3 10 | // 01 -1 | 01 -1 11 | // 11 1 | 11 1 12 | // 10 3 | 10 3 13 | 14 | module QAM16_MAP #(parameter WIDTH = 16) ( 15 | input qam_clk, //时钟 16 | input qam_rst_n, //复位 17 | input qam_din, //输入串行数据流 18 | input din_valid, 19 | 20 | output reg dout_valid, //输出数据有效 21 | output reg [5:0] dout_index, 22 | output reg [WIDTH-1:0] qam_dout_imag, //输出数据的虚部 23 | output reg [WIDTH-1:0] qam_dout_real); //输出数据的实部 24 | 25 | reg map_en; 26 | reg dout_en; 27 | reg [1:0] div_cnt; //4位计数器，将串行数据流每4位分成一组 28 | reg [1:0] end_cnt; 29 | reg [3:0] din_mem; 30 | reg [5:0] dout_cnt; 31 | reg [WIDTH-1:0] qam_dout_imag_mem; 32 | reg [WIDTH-1:0] qam_dout_real_mem; 33 | 34 | parameter map_dataa = 16'b1100001101001001; // -3/√10 归一化数据，调用matlab中fi函数 35 | parameter map_datab = 16'b1110101111000011; // -1/√10 a=fi(-3/(10^0.5),1,16,14);a.bin 36 | parameter map_datac = 16'b0001010000111101; // 1/√10 37 | parameter map_datad = 16'b0011110010110111; // 3/√10 38 | 39 | //4位计数器 40 | always@(posedge qam_clk) begin 41 | if(!qam_rst_n) begin 42 | div_cnt <= 2'd0; 43 | map_en <= 1'b0; 44 | end 45 | else begin 46 | if(din_valid) begin 47 | div_cnt <= div_cnt + 1'b1; 48 | if(div_cnt == 3) 49 | map_en <= 1'b1; 50 | else 51 | map_en <= 1'b0; 52 | end 53 | else begin 54 | div_cnt <= 2'd0; 55 | map_en <= 1'b0; 56 | end 57 | end 58 | end 59 | 60 | //缓存4位数据 61 | always@(posedge qam_clk) begin 62 | if(!qam_rst_n) begin 63 | din_mem <= 4'd0; 64 | end 65 | else begin 66 | case(div_cnt) 67 | 2'b00 : din_mem[0] <= qam_din; 68 | 2'b01 : din_mem[1] <= qam_din; 69 | 2'b10 : din_mem[2] <= qam_din; 70 | 2'b11 : din_mem[3] <= qam_din; 71 | endcase 72 | end 73 | end 74 | 75 | //映射 76 | always@(posedge qam_clk) begin 77 | if(!qam_rst_n) begin 78 | qam_dout_real_mem <= 0; 79 | qam_dout_imag_mem <= 0; 80 | dout_en <= 1'b0; 81 | end 82 | else begin 83 | if(map_en) begin 84 | case(din_mem[1:0]) 85 | 2'b00 : qam_dout_real_mem <= map_dataa; 86 | 2'b10 : qam_dout_real_mem <= map_datab; 87 | 2'b11 : qam_dout_real_mem <= map_datac; 88 | 2'b01 : qam_dout_real_mem <= map_datad; 89 | default : qam_dout_real_mem <= 0; 90 | endcase 91 | 92 | case(din_mem[3:2]) 93 | 2'b00 : qam_dout_imag_mem <= map_dataa; 94 | 2'b10 : qam_dout_imag_mem <= map_datab; 95 | 2'b11 : qam_dout_imag_mem <= map_datac; 96 | 2'b01 : qam_dout_imag_mem <= map_datad; 97 | default : qam_dout_imag_mem <= 0; 98 | endcase 99 | 100 | dout_en <= 1'b1; 101 | 102 | end 103 | else begin 104 | qam_dout_real_mem <= 0; 105 | qam_dout_imag_mem <= 0; 106 | dout_en <= 1'b0; 107 | end 108 | end 109 | end 110 | 111 | //数据输出模块 112 | always@(posedge qam_clk) begin 113 | if(!qam_rst_n) begin 114 | qam_dout_real <= 0; 115 | qam_dout_imag <= 0; 116 | dout_index <= 0; 117 | dout_valid <= 1'b0; 118 | end 119 | else begin 120 | if(dout_en) begin 121 | qam_dout_real <= qam_dout_real_mem; 122 | qam_dout_imag <= qam_dout_imag_mem; 123 | dout_index <= dout_cnt; 124 | dout_valid <= 1'b1; 125 | end 126 | else ; 127 | 128 | if(dout_index == 47) 129 | end_cnt <= end_cnt + 1'b1; 130 | else 131 | end_cnt <= 0; 132 | 133 | if(end_cnt==3) begin 134 | qam_dout_real <= 0; 135 | qam_dout_imag <= 0; 136 | dout_index <= 0; 137 | dout_valid <= 1'b0; 138 | end 139 | else ; 140 | 141 | end 142 | end 143 | 144 | //0-47计数模块 145 | always@(posedge qam_clk) begin 146 | if(!qam_rst_n) begin 147 | dout_cnt <= 0; 148 | end 149 | else begin 150 | if(dout_en) begin 151 | if(dout_cnt == 47) begin 152 | dout_cnt <= 0; 153 | end 154 | else begin 155 | dout_cnt <= dout_cnt + 1'b1; 156 | end 157 | end 158 | else ; 159 | end 160 | end 161 | 162 | endmodule 163 | 164 | 165 | 166 | 167 | -------------------------------------------------------------------------------- /source/map/QAM16_MAP_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns/ 1 ns 2 | module QAM16_MAP_tb(); 3 | reg qam_clk; 4 | reg qam_rst_n; 5 | reg qam_din; 6 | reg din_valid; 7 | reg[1:0] cnt; 8 | wire dout_valid; 9 | wire [5:0] dout_index; 10 | wire [15:0] qam_dout_imag; 11 | wire [15:0] qam_dout_real; 12 | integer dataa; 13 | integer datab; 14 | integer data_in; 15 | QAM16_MAP i1 ( 16 | .qam_clk(qam_clk), 17 | .qam_din(qam_din), 18 | .din_valid(din_valid), 19 | .dout_valid(dout_valid), 20 | .qam_dout_imag(qam_dout_imag), 21 | .qam_dout_real(qam_dout_real), 22 | .qam_rst_n(qam_rst_n), 23 | .dout_index(dout_index)); 24 | 25 | reg clk; 26 | initial 27 | begin 28 | data_in = $fopen("C:/Users/Administrator/Desktop/code/data_in.txt","r"); 29 | dataa = $fopen("QAM16_MAP_real_data.txt"); 30 | datab = $fopen("QAM16_MAP_imag_data.txt"); 31 | qam_clk = 0; 32 | qam_rst_n = 0; 33 | din_valid = 0; 34 | clk = 0; 35 | #100; 36 | qam_rst_n = 1; 37 | din_valid = 1; 38 | #1920; 39 | din_valid = 0; 40 | #1280; 41 | din_valid = 1; 42 | #1920; 43 | $stop; 44 | end 45 | 46 | always@(posedge qam_clk) begin 47 | if(!qam_rst_n) 48 | cnt <= 2'd0; 49 | else begin 50 | if(din_valid) 51 | cnt <= cnt + 1'b1; 52 | else 53 | cnt <= 0; 54 | end 55 | end 56 | 57 | integer rx,din; 58 | always@(negedge qam_clk) begin 59 | if(!qam_rst_n) 60 | qam_din <= 0; 61 | else begin 62 | if(din_valid) begin 63 | rx = $fscanf(data_in,"%b",din); 64 | qam_din <= din; 65 | end 66 | 67 | end 68 | end 69 | 70 | always@(negedge qam_clk) begin 71 | if(qam_rst_n==1'b1 && cnt == 2'd3) begin 72 | $fdisplay(dataa,"%b", qam_dout_real); 73 | $fdisplay(datab,"%b", qam_dout_imag); 74 | end 75 | end 76 | always #5 qam_clk = ~qam_clk; //100M 77 | //reg [1:0] cnnt; 78 | //always@(posedge qam_clk) begin //25M 79 | // if(!qam_rst_n) 80 | // cnnt <= 0; 81 | // else 82 | // cnnt <= cnnt + 1'b1; 83 | //end 84 | //always@(posedge qam_clk) begin //25M 85 | // if(!qam_rst_n) 86 | // clk <= 0; 87 | // else begin 88 | // if(cnnt[1]) 89 | // clk <= 1'b1; 90 | // else 91 | // clk <= 1'b0; 92 | // end 93 | //end 94 | endmodule 95 | 96 | -------------------------------------------------------------------------------- /source/map/QAM_MAP_Test.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/map/QAM_MAP_Test.m -------------------------------------------------------------------------------- /source/map/data_in.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 1 3 | 1 4 | 1 5 | 1 6 | 1 7 | 1 8 | 1 9 | 1 10 | 1 11 | 1 12 | 1 13 | 1 14 | 1 15 | 1 16 | 0 17 | 0 18 | 0 19 | 0 20 | 0 21 | 0 22 | 0 23 | 0 24 | 0 25 | 0 26 | 0 27 | 0 28 | 0 29 | 0 30 | 1 31 | 0 32 | 0 33 | 0 34 | 0 35 | 0 36 | 0 37 | 0 38 | 0 39 | 0 40 | 0 41 | 0 42 | 0 43 | 0 44 | 1 45 | 1 46 | 0 47 | 0 48 | 0 49 | 0 50 | 0 51 | 0 52 | 0 53 | 0 54 | 0 55 | 0 56 | 0 57 | 0 58 | 1 59 | 0 60 | 1 61 | 0 62 | 0 63 | 0 64 | 0 65 | 0 66 | 0 67 | 0 68 | 0 69 | 0 70 | 0 71 | 0 72 | 1 73 | 1 74 | 1 75 | 1 76 | 0 77 | 0 78 | 0 79 | 0 80 | 0 81 | 0 82 | 0 83 | 0 84 | 0 85 | 0 86 | 1 87 | 0 88 | 0 89 | 0 90 | 1 91 | 0 92 | 0 93 | 0 94 | 0 95 | 0 96 | 0 97 | 0 98 | 0 99 | 0 100 | 1 101 | 1 102 | 0 103 | 0 104 | 1 105 | 1 106 | 0 107 | 0 108 | 0 109 | 0 110 | 0 111 | 0 112 | 0 113 | 0 114 | 1 115 | 0 116 | 1 117 | 0 118 | 1 119 | 0 120 | 1 121 | 0 122 | 0 123 | 0 124 | 0 125 | 0 126 | 0 127 | 0 128 | 1 129 | 1 130 | 1 131 | 1 132 | 1 133 | 1 134 | 1 135 | 1 136 | 0 137 | 0 138 | 0 139 | 0 140 | 0 141 | 0 142 | 1 143 | 0 144 | 0 145 | 0 146 | 0 147 | 0 148 | 0 149 | 0 150 | 1 151 | 0 152 | 0 153 | 0 154 | 0 155 | 0 156 | 1 157 | 1 158 | 0 159 | 0 160 | 0 161 | 0 162 | 0 163 | 0 164 | 1 165 | 1 166 | 0 167 | 0 168 | 0 169 | 0 170 | 1 171 | 0 172 | 1 173 | 0 174 | 0 175 | 0 176 | 0 177 | 0 178 | 1 179 | 0 180 | 1 181 | 0 182 | 0 183 | 0 184 | 1 185 | 1 186 | 1 187 | 1 188 | 0 189 | 0 190 | 0 191 | 0 192 | 1 193 | -------------------------------------------------------------------------------- /source/map/qam_sim.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | vlog QAM16_MAP.v 4 | vlog QAM16_MAP_tb.v 5 | vsim QAM16_MAP_tb 6 | 7 | 8 | 9 | add wave -label qam_clk /QAM16_MAP_tb/qam_clk 10 | add wave -label qam_rst_n /QAM16_MAP_tb/qam_rst_n 11 | add wave -label din_valid /QAM16_MAP_tb/din_valid 12 | add wave -label din_mem /QAM16_MAP_tb/i1/din_mem 13 | add wave -radix unsigned -label div_cnt /QAM16_MAP_tb/i1/div_cnt 14 | add wave -label map_en /QAM16_MAP_tb/i1/map_en 15 | add wave -radix unsigned -label qam_dout_real_mem /QAM16_MAP_tb/i1/qam_dout_real_mem 16 | add wave -radix unsigned -label qam_dout_imag_mem /QAM16_MAP_tb/i1/qam_dout_imag_mem 17 | add wave -radix unsigned -label qam_dout_real /QAM16_MAP_tb/qam_dout_real 18 | add wave -radix unsigned -label qam_dout_imag /QAM16_MAP_tb/qam_dout_imag 19 | add wave -label dout_en /QAM16_MAP_tb/i1/dout_en 20 | add wave -radix unsigned -label dout_cnt /QAM16_MAP_tb/i1/dout_cnt 21 | add wave -radix unsigned -label dout_index /QAM16_MAP_tb/dout_index 22 | add wave -label dout_valid /QAM16_MAP_tb/dout_valid 23 | 24 | run -all; -------------------------------------------------------------------------------- /source/map/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/map/vsim.wlf -------------------------------------------------------------------------------- /source/pilot/Insert_Pilot.v: -------------------------------------------------------------------------------- 1 | //功能插入导频 2 | //数据符号(Symbol)个数：48 3 | //导频符号个数：4 4 | //FFT点数：64 5 | //数据位宽：16 6 | module Insert_Pilot #(parameter DATAWIDTH = 16)( 7 | input pilot_clk, //时钟信号 8 | input pilot_rst_n, //复位信号，低有效 9 | input [5:0] index, //输入数据计数，index = 0~47 10 | 11 | input din_valid, //输入数据有效 12 | input [DATAWIDTH-1:0] pilot_real_din, //数据实部输入 13 | input [DATAWIDTH-1:0] pilot_imag_din, //数据虚部输入 14 | 15 | output reg [5:0] dout_index, 16 | output reg [DATAWIDTH-1:0] pilot_real_dout, //数据实部输出 17 | output reg [DATAWIDTH-1:0] pilot_imag_dout, //数据虚部输出 18 | output reg dout_valid ); //数据输出有效 19 | 20 | 21 | reg [DATAWIDTH-1:0] re_din_buf; //输入数据实部缓存 22 | reg [DATAWIDTH-1:0] im_din_buf; //输入数据虚部缓存 23 | 24 | 25 | reg din_en; //输入使能 26 | reg [5:0] index_reg; //输入数据标号 27 | reg dout_en; //数据输出使能 28 | 29 | 30 | reg read_en; //双口RAM读使能 31 | reg write_en; //双口RAM写使能 32 | reg wac; //双口RAM写地址控制 33 | reg rac; 34 | reg [6:0] write_addr; //双口RAM写地址 35 | reg [6:0] read_addr; //双口RAM读地址 36 | reg [DATAWIDTH-1:0] ram_real_din; //双口RAM实部输入缓存 37 | reg [DATAWIDTH-1:0] ram_imag_din; //双口RAM虚部输入缓存 38 | wire [DATAWIDTH-1:0] ram_real_dout; //双口RAM实部输出 39 | wire [DATAWIDTH-1:0] ram_imag_dout; //双口RAM虚部输出 40 | 41 | 42 | //为保证模块所有输入信号同步，在模块输入端口为所有信号加1级缓存 43 | always@(posedge pilot_clk) begin 44 | if(!pilot_rst_n) begin 45 | re_din_buf <= 0; 46 | im_din_buf <= 0; 47 | din_en <= 1'b0; 48 | index_reg <= 6'd0; 49 | end 50 | else begin 51 | if(din_valid) begin 52 | re_din_buf <= pilot_real_din; 53 | im_din_buf <= pilot_imag_din; 54 | din_en <= din_valid; 55 | index_reg <= index; 56 | end 57 | else begin 58 | re_din_buf <= 0; 59 | im_din_buf <= 0; 60 | din_en <= 1'b0; 61 | index_reg <= 6'd0; 62 | end 63 | end 64 | end 65 | //写数据模块 66 | always@(posedge pilot_clk) begin 67 | if(!pilot_rst_n) begin 68 | write_addr[6:0] <= 0; 69 | write_en <= 1'b0; 70 | ram_real_din <= 0; 71 | ram_imag_din <= 0; 72 | wac <= 1'b0; 73 | end 74 | else begin 75 | if(din_en) begin 76 | write_addr[6] <= wac; //将wac信号作为RAM写地址缓存的最高位以控制数据写入RAM的不同部分 77 | 78 | /* if(index_reg <= 6'd4) //wac为0时写入RAM的低64bytes，反之，写入RAM的高64bytes 79 | write_addr[5:0] <= index_reg + 6'd38; 80 | else if(index_reg <= 6'd17) 81 | write_addr[5:0] <= index_reg + 6'd39; 82 | else if(index_reg <= 6'd23) 83 | write_addr[5:0] <= index_reg + 6'd40; 84 | else if(index_reg <= 6'd29) 85 | write_addr[5:0] <= index_reg - 6'd23; 86 | else if(index_reg <= 6'd42) 87 | write_addr[5:0] <= index_reg - 6'd22; 88 | else if(index_reg <= 6'd47) 89 | write_addr[5:0] <= index_reg - 6'd21; 90 | else 91 | write_addr[5:0] <= 0; */ 92 | 93 | case(index_reg) 94 | 0,1,2,3,4: 95 | write_addr[5:0] <= index_reg + 6'd38; 96 | 5,6,7,8,9,10,11,12,13,14,15,16,17: 97 | write_addr[5:0] <= index_reg + 6'd39; 98 | 18,19,20,21,22,23: 99 | write_addr[5:0] <= index_reg + 6'd40; 100 | 24,25,26,27,28,29: 101 | write_addr[5:0] <= index_reg - 6'd23; 102 | 30,31,32,33,34,35,36,37,38,39,40,41,42: 103 | write_addr[5:0] <= index_reg - 6'd22; 104 | 43,44,45,46,47: 105 | write_addr[5:0] <= index_reg - 6'd21; 106 | default: 107 | write_addr[5:0] <= 6'd0; 108 | endcase 109 | 110 | write_en <= 1'b1; 111 | ram_real_din <= re_din_buf; 112 | ram_imag_din <= im_din_buf; 113 | 114 | if(index_reg==47) begin 115 | //read_en <= 1'b1; 116 | wac <= ~wac; 117 | end 118 | else ; 119 | 120 | end 121 | else begin 122 | write_en <= 1'b0; 123 | write_addr[5:0] <= 0; 124 | ram_real_din <= 0; 125 | ram_imag_din <= 0; 126 | end 127 | end 128 | end 129 | 130 | //读数据模块 131 | always@(posedge pilot_clk) begin 132 | if(!pilot_rst_n) begin 133 | read_en <= 1'b0; 134 | dout_en <= 1'b0; 135 | //rac <= 1'b0; 136 | end 137 | else begin 138 | if(index_reg==24) begin 139 | read_en <= 1'b1; 140 | //wac <= ~wac; 141 | //dout_en <= 1'b1; 142 | end 143 | else ; 144 | 145 | if(read_addr == 63 || read_addr == 127) begin 146 | //if( read_addr == 127) 147 | read_en <= 1'b0; 148 | //dout_en <= 1'b0; 149 | //rac <= ~rac; 150 | end 151 | else ; 152 | 153 | if(read_en) 154 | dout_en <= 1'b1; 155 | else 156 | dout_en <= 1'b0; 157 | end 158 | end 159 | 160 | //计数器单元，输出计数信号作为双口RAM的读地址信号 161 | always@(posedge pilot_clk) begin 162 | if(!pilot_rst_n) begin 163 | //read_addr[6] <= 1; 164 | read_addr <= 0; 165 | end 166 | else begin 167 | if(read_en) begin 168 | //read_addr[6] <= rac; 169 | read_addr[6:0] <= read_addr[6:0] + 1'b1; 170 | end 171 | else ; 172 | end 173 | end 174 | 175 | //数据输出模块 176 | always@(posedge pilot_clk) begin 177 | if(!pilot_rst_n) begin 178 | pilot_real_dout <= 0; 179 | pilot_imag_dout <= 0; 180 | dout_valid <= 1'b0; 181 | end 182 | else begin 183 | if(dout_en) begin 184 | pilot_real_dout <= ram_real_dout; 185 | pilot_imag_dout <= ram_imag_dout; 186 | dout_valid <= 1'b1; 187 | end 188 | else begin 189 | pilot_real_dout <= 0; 190 | pilot_imag_dout <= 0; 191 | dout_valid <= 1'b0; 192 | end 193 | end 194 | end 195 | 196 | //输出计数模块0-63 197 | always@(posedge pilot_clk) begin 198 | if(!pilot_rst_n) begin 199 | dout_index <= 0; 200 | end 201 | else begin 202 | if(dout_valid) begin 203 | dout_index <= dout_index + 1'b1; 204 | end 205 | else begin 206 | dout_index <= 0; 207 | end 208 | end 209 | end 210 | 211 | //调用双口RAM 212 | pilot_ram2port pilot_ram2port_re ( 213 | .data ( ram_real_din ), 214 | .rdaddress ( read_addr ), 215 | .rdclock ( pilot_clk ), 216 | .rden ( read_en ), 217 | .wraddress ( write_addr ), 218 | .wrclock ( pilot_clk ), 219 | .wren ( write_en ), 220 | .q ( ram_real_dout ) 221 | ); 222 | 223 | pilot_ram2port pilot_ram2port_im ( 224 | .data ( ram_imag_din ), 225 | .rdaddress ( read_addr ), 226 | .rdclock ( pilot_clk ), 227 | .rden ( read_en ), 228 | .wraddress ( write_addr ), 229 | .wrclock ( pilot_clk ), 230 | .wren ( write_en ), 231 | .q ( ram_imag_dout ) 232 | ); 233 | endmodule -------------------------------------------------------------------------------- /source/pilot/Insert_Pilot_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns/ 1 ns 3 | module Insert_Pilot_tb(); 4 | 5 | reg din_valid; 6 | reg [5:0] index; 7 | reg pilot_clk; 8 | reg [15:0] pilot_imag_din; 9 | reg [15:0] pilot_real_din; 10 | reg pilot_rst_n; 11 | // wires 12 | wire dout_valid; 13 | wire [15:0] pilot_imag_dout; 14 | wire [15:0] pilot_real_dout; 15 | 16 | integer data_re, data_im; 17 | 18 | Insert_Pilot i1 ( 19 | 20 | .din_valid(din_valid), 21 | .dout_valid(dout_valid), 22 | .index(index), 23 | .pilot_clk(pilot_clk), 24 | .pilot_imag_din(pilot_imag_din), 25 | .pilot_imag_dout(pilot_imag_dout), 26 | .pilot_real_din(pilot_real_din), 27 | .pilot_real_dout(pilot_real_dout), 28 | .pilot_rst_n(pilot_rst_n) 29 | ); 30 | initial 31 | begin 32 | data_re = $fopen("C:/Users/Administrator/Desktop/code/data/re_data.txt","r"); 33 | data_im = $fopen("C:/Users/Administrator/Desktop/code/data/im_data.txt","r"); 34 | pilot_clk = 0; 35 | pilot_rst_n = 0; 36 | //din_ready = 0; 37 | din_valid = 0; 38 | #120; 39 | pilot_rst_n = 1; 40 | din_valid = 1; 41 | #1920; //48*40 42 | din_valid = 0; 43 | #1280; //32*40 44 | din_valid = 1; 45 | #1920; //48*40 46 | din_valid = 0; 47 | #1280; //32*40 48 | din_valid = 1; 49 | #1920; //48*40 50 | $stop; 51 | end 52 | always #20 pilot_clk = ~pilot_clk; //25M 53 | 54 | always@(posedge pilot_clk) begin 55 | if(!pilot_rst_n) 56 | index <= 0; 57 | else begin 58 | if(din_valid) begin 59 | if(index == 47) 60 | index <= 0; 61 | else 62 | index <= index + 1'b1; 63 | end 64 | else; 65 | end 66 | end 67 | 68 | 69 | integer rc_x,ic_x,data_real_in_int,data_imag_in_int; 70 | 71 | always@(negedge pilot_clk) begin 72 | if(!pilot_rst_n) begin 73 | pilot_real_din <= 0; 74 | pilot_imag_din <= 0; 75 | end 76 | else begin 77 | if(din_valid) begin 78 | //data_re = $fopen("C:/Users/Administrator/Desktop/code/data/re_data.txt","r"); 79 | //data_im = $fopen("C:/Users/Administrator/Desktop/code/data/im_data.txt","r"); 80 | rc_x = $fscanf(data_re,"%d",data_real_in_int); 81 | pilot_real_din <= data_real_in_int; 82 | ic_x = $fscanf(data_im,"%d",data_imag_in_int); 83 | pilot_imag_din <= data_imag_in_int; 84 | end 85 | end 86 | end 87 | endmodule 88 | -------------------------------------------------------------------------------- /source/pilot/Readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/pilot/Readme.txt -------------------------------------------------------------------------------- /source/pilot/create_inidata.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/pilot/create_inidata.m -------------------------------------------------------------------------------- /source/pilot/data/im_data.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 101 50 | 102 51 | 103 52 | 104 53 | 105 54 | 106 55 | 107 56 | 108 57 | 109 58 | 110 59 | 111 60 | 112 61 | 113 62 | 114 63 | 115 64 | 116 65 | 117 66 | 118 67 | 119 68 | 120 69 | 121 70 | 122 71 | 123 72 | 124 73 | 125 74 | 126 75 | 127 76 | 128 77 | 129 78 | 130 79 | 131 80 | 132 81 | 133 82 | 134 83 | 135 84 | 136 85 | 137 86 | 138 87 | 139 88 | 140 89 | 141 90 | 142 91 | 143 92 | 144 93 | 145 94 | 146 95 | 147 96 | 148 97 | -------------------------------------------------------------------------------- /source/pilot/data/pilot_data.mif: -------------------------------------------------------------------------------- 1 | WIDTH=16; 2 | DEPTH=128; 3 | 4 | ADDRESS_RADIX=UNS; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 0 : 0; 9 | 1 : 0; 10 | 2 : 0; 11 | 3 : 0; 12 | 4 : 0; 13 | 5 : 0; 14 | 6 : 0; 15 | 7 : 4000; 16 | 8 : 0; 17 | 9 : 0; 18 | 10 : 0; 19 | 11 : 0; 20 | 12 : 0; 21 | 13 : 0; 22 | 14 : 0; 23 | 15 : 0; 24 | 16 : 0; 25 | 17 : 0; 26 | 18 : 0; 27 | 19 : 0; 28 | 20 : 0; 29 | 21 : C000; 30 | 22 : 0; 31 | 23 : 0; 32 | 24 : 0; 33 | 25 : 0; 34 | 26 : 0; 35 | 27 : 0; 36 | 28 : 0; 37 | 29 : 0; 38 | 30 : 0; 39 | 31 : 0; 40 | 32 : 0; 41 | 33 : 0; 42 | 34 : 0; 43 | 35 : 0; 44 | 36 : 0; 45 | 37 : 0; 46 | 38 : 0; 47 | 39 : 0; 48 | 40 : 0; 49 | 41 : 0; 50 | 42 : 0; 51 | 43 : 4000; 52 | 44 : 0; 53 | 45 : 0; 54 | 46 : 0; 55 | 47 : 0; 56 | 48 : 0; 57 | 49 : 0; 58 | 50 : 0; 59 | 51 : 0; 60 | 52 : 0; 61 | 53 : 0; 62 | 54 : 0; 63 | 55 : 0; 64 | 56 : 0; 65 | 57 : 4000; 66 | 58 : 0; 67 | 59 : 0; 68 | 60 : 0; 69 | 61 : 0; 70 | 62 : 0; 71 | 63 : 0; 72 | 64 : 0; 73 | 65 : 0; 74 | 66 : 0; 75 | 67 : 0; 76 | 68 : 0; 77 | 69 : 0; 78 | 70 : 0; 79 | 71 : 4000; 80 | 72 : 0; 81 | 73 : 0; 82 | 74 : 0; 83 | 75 : 0; 84 | 76 : 0; 85 | 77 : 0; 86 | 78 : 0; 87 | 79 : 0; 88 | 80 : 0; 89 | 81 : 0; 90 | 82 : 0; 91 | 83 : 0; 92 | 84 : 0; 93 | 85 : C000; 94 | 86 : 0; 95 | 87 : 0; 96 | 88 : 0; 97 | 89 : 0; 98 | 90 : 0; 99 | 91 : 0; 100 | 92 : 0; 101 | 93 : 0; 102 | 94 : 0; 103 | 95 : 0; 104 | 96 : 0; 105 | 97 : 0; 106 | 98 : 0; 107 | 99 : 0; 108 | 100 : 0; 109 | 101 : 0; 110 | 102 : 0; 111 | 103 : 0; 112 | 104 : 0; 113 | 105 : 0; 114 | 106 : 0; 115 | 107 : 4000; 116 | 108 : 0; 117 | 109 : 0; 118 | 110 : 0; 119 | 111 : 0; 120 | 112 : 0; 121 | 113 : 0; 122 | 114 : 0; 123 | 115 : 0; 124 | 116 : 0; 125 | 117 : 0; 126 | 118 : 0; 127 | 119 : 0; 128 | 120 : 0; 129 | 121 : 4000; 130 | 122 : 0; 131 | 123 : 0; 132 | 124 : 0; 133 | 125 : 0; 134 | 126 : 0; 135 | 127 : 0; 136 | 137 | END; 138 | -------------------------------------------------------------------------------- /source/pilot/data/re_data.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 101 50 | 102 51 | 103 52 | 104 53 | 105 54 | 106 55 | 107 56 | 108 57 | 109 58 | 110 59 | 111 60 | 112 61 | 113 62 | 114 63 | 115 64 | 116 65 | 117 66 | 118 67 | 119 68 | 120 69 | 121 70 | 122 71 | 123 72 | 124 73 | 125 74 | 126 75 | 127 76 | 128 77 | 129 78 | 130 79 | 131 80 | 132 81 | 133 82 | 134 83 | 135 84 | 136 85 | 137 86 | 138 87 | 139 88 | 140 89 | 141 90 | 142 91 | 143 92 | 144 93 | 145 94 | 146 95 | 147 96 | 148 97 | -------------------------------------------------------------------------------- /source/pilot/pilot_data.mif: -------------------------------------------------------------------------------- 1 | WIDTH=16; 2 | DEPTH=128; 3 | 4 | ADDRESS_RADIX=UNS; 5 | DATA_RADIX=HEX; 6 | 7 | CONTENT BEGIN 8 | 0 : 0; 9 | 1 : 0; 10 | 2 : 0; 11 | 3 : 0; 12 | 4 : 0; 13 | 5 : 0; 14 | 6 : 0; 15 | 7 : 4000; 16 | 8 : 0; 17 | 9 : 0; 18 | 10 : 0; 19 | 11 : 0; 20 | 12 : 0; 21 | 13 : 0; 22 | 14 : 0; 23 | 15 : 0; 24 | 16 : 0; 25 | 17 : 0; 26 | 18 : 0; 27 | 19 : 0; 28 | 20 : 0; 29 | 21 : C000; 30 | 22 : 0; 31 | 23 : 0; 32 | 24 : 0; 33 | 25 : 0; 34 | 26 : 0; 35 | 27 : 0; 36 | 28 : 0; 37 | 29 : 0; 38 | 30 : 0; 39 | 31 : 0; 40 | 32 : 0; 41 | 33 : 0; 42 | 34 : 0; 43 | 35 : 0; 44 | 36 : 0; 45 | 37 : 0; 46 | 38 : 0; 47 | 39 : 0; 48 | 40 : 0; 49 | 41 : 0; 50 | 42 : 0; 51 | 43 : 4000; 52 | 44 : 0; 53 | 45 : 0; 54 | 46 : 0; 55 | 47 : 0; 56 | 48 : 0; 57 | 49 : 0; 58 | 50 : 0; 59 | 51 : 0; 60 | 52 : 0; 61 | 53 : 0; 62 | 54 : 0; 63 | 55 : 0; 64 | 56 : 0; 65 | 57 : 4000; 66 | 58 : 0; 67 | 59 : 0; 68 | 60 : 0; 69 | 61 : 0; 70 | 62 : 0; 71 | 63 : 0; 72 | 64 : 0; 73 | 65 : 0; 74 | 66 : 0; 75 | 67 : 0; 76 | 68 : 0; 77 | 69 : 0; 78 | 70 : 0; 79 | 71 : 4000; 80 | 72 : 0; 81 | 73 : 0; 82 | 74 : 0; 83 | 75 : 0; 84 | 76 : 0; 85 | 77 : 0; 86 | 78 : 0; 87 | 79 : 0; 88 | 80 : 0; 89 | 81 : 0; 90 | 82 : 0; 91 | 83 : 0; 92 | 84 : 0; 93 | 85 : C000; 94 | 86 : 0; 95 | 87 : 0; 96 | 88 : 0; 97 | 89 : 0; 98 | 90 : 0; 99 | 91 : 0; 100 | 92 : 0; 101 | 93 : 0; 102 | 94 : 0; 103 | 95 : 0; 104 | 96 : 0; 105 | 97 : 0; 106 | 98 : 0; 107 | 99 : 0; 108 | 100 : 0; 109 | 101 : 0; 110 | 102 : 0; 111 | 103 : 0; 112 | 104 : 0; 113 | 105 : 0; 114 | 106 : 0; 115 | 107 : 4000; 116 | 108 : 0; 117 | 109 : 0; 118 | 110 : 0; 119 | 111 : 0; 120 | 112 : 0; 121 | 113 : 0; 122 | 114 : 0; 123 | 115 : 0; 124 | 116 : 0; 125 | 117 : 0; 126 | 118 : 0; 127 | 119 : 0; 128 | 120 : 0; 129 | 121 : 4000; 130 | 122 : 0; 131 | 123 : 0; 132 | 124 : 0; 133 | 125 : 0; 134 | 126 : 0; 135 | 127 : 0; 136 | 137 | END; 138 | -------------------------------------------------------------------------------- /source/pilot/pilot_ram2port.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pilot_ram2port.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pilot_ram2port_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pilot_ram2port_bb.v"] 6 | -------------------------------------------------------------------------------- /source/pilot/pilot_sim.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | vlog C:/Users/Administrator/Desktop/code/sim_lib/altera_mf.v 4 | vlog Insert_Pilot.v 5 | vlog pilot_ram2port.v 6 | vlog Insert_Pilot_tb.v 7 | vsim Insert_Pilot_tb 8 | 9 | 10 | add wave -label pilot_clk /Insert_Pilot_tb/pilot_clk 11 | add wave -label pilot_rst_n /Insert_Pilot_tb/pilot_rst_n 12 | add wave -color Yellow -label din_valid /Insert_Pilot_tb/din_valid 13 | add wave -color Yellow -label din_en /Insert_Pilot_tb/i1/din_en 14 | add wave -radix unsigned -label pilot_real_din /Insert_Pilot_tb/pilot_real_din 15 | add wave -radix unsigned -label pilot_imag_din /Insert_Pilot_tb/pilot_imag_din 16 | add wave -radix unsigned -label re_din_buf /Insert_Pilot_tb/i1/re_din_buf 17 | add wave -radix unsigned -label im_din_buf /Insert_Pilot_tb/i1/im_din_buf 18 | add wave -color Yellow -radix unsigned -label ram_imag_din /Insert_Pilot_tb/i1/ram_imag_din 19 | add wave -color Yellow -radix unsigned -label ram_real_din /Insert_Pilot_tb/i1/ram_real_din 20 | 21 | add wave -radix unsigned -label index /Insert_Pilot_tb/index 22 | add wave -radix unsigned -label index_reg /Insert_Pilot_tb/i1/index_reg 23 | 24 | add wave -color Yellow -radix unsigned -label write_addr /Insert_Pilot_tb/i1/write_addr 25 | add wave -color Yellow -label write_en /Insert_Pilot_tb/i1/write_en 26 | add wave -color Cyan -label read_en /Insert_Pilot_tb/i1/read_en 27 | add wave -color Cyan -radix unsigned -label read_addr /Insert_Pilot_tb/i1/read_addr 28 | add wave -color Cyan -label dout_en /Insert_Pilot_tb/i1/dout_en 29 | add wave -color Magenta -radix unsigned -label pilot_imag_dout /Insert_Pilot_tb/pilot_imag_dout 30 | add wave -color Magenta -radix unsigned -label pilot_real_dout /Insert_Pilot_tb/pilot_real_dout 31 | add wave -color Magenta -radix unsigned -label dout_valid /Insert_Pilot_tb/dout_valid 32 | ##add wave -color Magenta -radix unsigned -label /Insert_Pilot_tb/i1/ram_imag_dout 33 | ##add wave -color Magenta -radix unsigned -label /Insert_Pilot_tb/i1/ram_real_dout 34 | 35 | ##add wave -noupdate -color Magenta -format Literal -radix unsigned 36 | run -all; -------------------------------------------------------------------------------- /source/pilot/sim_lib/altera_mf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/pilot/sim_lib/altera_mf.v -------------------------------------------------------------------------------- /source/pilot/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/pilot/vsim.wlf -------------------------------------------------------------------------------- /source/prbs/prbs15.v: -------------------------------------------------------------------------------- 1 | // 移位寄存器长度: 15 2 | // 移位方向: 右移 3 | // LFSR结构: Fibonacci(external XOR gates) 4 | // 反馈回路门类型: NOR 5 | // 初始值(seed): 15'h7fff 6 | // Taps系数 : 15 14 1 7 | 8 | module prbs15( 9 | input prbs_clk, 10 | input prbs_rst_n, 11 | input trig_en, 12 | output reg dout_valid, 13 | output reg prbs_out); 14 | 15 | reg [14:0] prbs_mem; 16 | //reg dout_en; 17 | always @(posedge prbs_clk) begin 18 | if(!prbs_rst_n) 19 | prbs_mem[14:0] <= 15'h7fff; 20 | else begin 21 | if(trig_en) begin 22 | prbs_mem[0] <= prbs_mem[13] ^ prbs_mem[14]; 23 | prbs_mem[14:1] <= prbs_mem[13:0]; 24 | end 25 | else ; 26 | end 27 | end 28 | 29 | always@(posedge prbs_clk) begin 30 | if(!prbs_rst_n) begin 31 | prbs_out <= 1'bx; 32 | dout_valid <= 1'b0; 33 | end 34 | else begin 35 | if(trig_en) begin 36 | prbs_out <= prbs_mem[14]; 37 | dout_valid <= 1'b1; 38 | end 39 | else begin 40 | prbs_out <= 1'bx; 41 | dout_valid <= 1'b0; 42 | end 43 | end 44 | end 45 | 46 | //assign prbs_out = prbs_mem[14]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /source/prbs/prbs15_sim.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | vlog prbs15.v 4 | vlog prbs15_tb.v 5 | vsim prbs15_tb 6 | 7 | 8 | add wave -label prbs_clk /prbs15_tb/prbs_clk 9 | add wave -label prbs_rst_n /prbs15_tb/prbs_rst_n 10 | add wave -label trig_en /prbs15_tb/trig_en 11 | ##add wave -radix unsigned -label cycles /prbs15_tb/cycles 12 | add wave -label prbs_mem /prbs15_tb/ins/prbs_mem 13 | add wave -label dout_valid /prbs15_tb/dout_valid 14 | add wave -label prbs_out /prbs15_tb/prbs_out 15 | 16 | 17 | run -all; -------------------------------------------------------------------------------- /source/prbs/prbs15_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | module prbs15_tb(); 4 | reg prbs_clk; 5 | reg prbs_rst_n; 6 | reg trig_en; 7 | wire prbs_out; 8 | wire dout_valid; 9 | 10 | integer cycles; 11 | integer data; 12 | parameter LENGTH = 15; 13 | 14 | prbs15 ins( .prbs_clk(prbs_clk), 15 | .prbs_rst_n(prbs_rst_n), 16 | .trig_en(trig_en), 17 | .dout_valid(dout_valid), 18 | .prbs_out(prbs_out)); 19 | 20 | 21 | initial begin 22 | data = $fopen("prbs_output.txt"); 23 | prbs_clk = 0; 24 | prbs_rst_n = 0; 25 | trig_en = 0; 26 | cycles = 0; 27 | @(posedge prbs_clk); 28 | prbs_rst_n = 1; 29 | trig_en = 1; 30 | #150; 31 | trig_en = 0; 32 | #20; 33 | trig_en = 1; 34 | #50; 35 | $stop(); 36 | end 37 | 38 | always@(posedge prbs_clk) begin 39 | //cycles = cycles + 1; 40 | //if(trig_en) 41 | $fdisplay(data,"%b", prbs_out); 42 | //if(cycles == (1 << LENGTH)) begin 43 | // $display($time," value = %d \n", cycles); 44 | // $stop(); 45 | //end 46 | end 47 | 48 | always #5 prbs_clk = ~ prbs_clk; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /source/prbs/rom/prbs_data.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "13.0" 3 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "prbs_data.v"] 4 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "prbs_data_inst.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "prbs_data_bb.v"] 6 | -------------------------------------------------------------------------------- /source/prbs/rom/prbs_data_inst.v: -------------------------------------------------------------------------------- 1 | prbs_data prbs_data_inst ( 2 | .address ( address_sig ), 3 | .clock ( clock_sig ), 4 | .q ( q_sig ) 5 | ); 6 | -------------------------------------------------------------------------------- /source/prbs/rom/prbs_gen_data.m: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yugithub/OFDM-baseband/54e7110eb50489d5bb5a810cc6adbe8f4f82b03d/source/prbs/rom/prbs_gen_data.m -------------------------------------------------------------------------------- /source/scale_clip/data/exp.txt: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000111100 2 | 00000000000000000000000000111100 3 | 00000000000000000000000000111100 4 | 00000000000000000000000000111100 5 | 00000000000000000000000000111100 6 | 00000000000000000000000000111100 7 | 00000000000000000000000000111100 8 | 00000000000000000000000000111100 9 | 00000000000000000000000000111100 10 | 00000000000000000000000000111100 11 | 00000000000000000000000000111100 12 | 00000000000000000000000000111100 13 | 00000000000000000000000000111100 14 | 00000000000000000000000000111100 15 | 00000000000000000000000000111100 16 | 00000000000000000000000000111100 17 | 00000000000000000000000000111100 18 | 00000000000000000000000000111100 19 | 00000000000000000000000000111100 20 | 00000000000000000000000000111100 21 | 00000000000000000000000000111100 22 | 00000000000000000000000000111100 23 | 00000000000000000000000000111100 24 | 00000000000000000000000000111100 25 | 00000000000000000000000000111100 26 | 00000000000000000000000000111100 27 | 00000000000000000000000000111100 28 | 00000000000000000000000000111100 29 | 00000000000000000000000000111100 30 | 00000000000000000000000000111100 31 | 00000000000000000000000000111100 32 | 00000000000000000000000000111100 33 | 00000000000000000000000000111100 34 | 00000000000000000000000000111100 35 | 00000000000000000000000000111100 36 | 00000000000000000000000000111100 37 | 00000000000000000000000000111100 38 | 00000000000000000000000000111100 39 | 00000000000000000000000000111100 40 | 00000000000000000000000000111100 41 | 00000000000000000000000000111100 42 | 00000000000000000000000000111100 43 | 00000000000000000000000000111100 44 | 00000000000000000000000000111100 45 | 00000000000000000000000000111100 46 | 00000000000000000000000000111100 47 | 00000000000000000000000000111100 48 | 00000000000000000000000000111100 49 | 00000000000000000000000000111100 50 | 00000000000000000000000000111100 51 | 00000000000000000000000000111100 52 | 00000000000000000000000000111100 53 | 00000000000000000000000000111100 54 | 00000000000000000000000000111100 55 | 00000000000000000000000000111100 56 | 00000000000000000000000000111100 57 | 00000000000000000000000000111100 58 | 00000000000000000000000000111100 59 | 00000000000000000000000000111100 60 | 00000000000000000000000000111100 61 | 00000000000000000000000000111100 62 | 00000000000000000000000000111100 63 | 00000000000000000000000000111100 64 | 00000000000000000000000000111100 65 | 00000000000000000000000000111100 66 | 00000000000000000000000000111100 67 | 00000000000000000000000000111100 68 | 00000000000000000000000000111100 69 | 00000000000000000000000000111100 70 | 00000000000000000000000000111100 71 | 00000000000000000000000000111100 72 | 00000000000000000000000000111100 73 | 00000000000000000000000000111100 74 | 00000000000000000000000000111100 75 | 00000000000000000000000000111100 76 | 00000000000000000000000000111100 77 | 00000000000000000000000000111100 78 | 00000000000000000000000000111100 79 | 00000000000000000000000000111100 80 | 00000000000000000000000000111100 81 | 00000000000000000000000000111100 82 | 00000000000000000000000000111100 83 | 00000000000000000000000000111100 84 | 00000000000000000000000000111100 85 | 00000000000000000000000000111100 86 | 00000000000000000000000000111100 87 | 00000000000000000000000000111100 88 | 00000000000000000000000000111100 89 | 00000000000000000000000000111100 90 | 00000000000000000000000000111100 91 | 00000000000000000000000000111100 92 | 00000000000000000000000000111100 93 | 00000000000000000000000000111100 94 | 00000000000000000000000000111100 95 | 00000000000000000000000000111100 96 | 00000000000000000000000000111100 97 | 00000000000000000000000000111100 98 | 00000000000000000000000000111100 99 | 00000000000000000000000000111100 100 | 00000000000000000000000000111100 101 | 00000000000000000000000000111100 102 | 00000000000000000000000000111100 103 | 00000000000000000000000000111100 104 | 00000000000000000000000000111100 105 | 00000000000000000000000000111100 106 | 00000000000000000000000000111100 107 | 00000000000000000000000000111100 108 | 00000000000000000000000000111100 109 | 00000000000000000000000000111100 110 | 00000000000000000000000000111100 111 | 00000000000000000000000000111100 112 | 00000000000000000000000000111100 113 | 00000000000000000000000000111100 114 | 00000000000000000000000000111100 115 | 00000000000000000000000000111100 116 | 00000000000000000000000000111100 117 | 00000000000000000000000000111100 118 | 00000000000000000000000000111100 119 | 00000000000000000000000000111100 120 | 00000000000000000000000000111100 121 | 00000000000000000000000000111100 122 | 00000000000000000000000000111100 123 | 00000000000000000000000000111100 124 | 00000000000000000000000000111100 125 | 00000000000000000000000000111100 126 | 00000000000000000000000000111100 127 | 00000000000000000000000000111100 128 | 00000000000000000000000000111100 129 | -------------------------------------------------------------------------------- /source/scale_clip/data/im_din.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | 1 66 | 2 67 | 3 68 | 4 69 | 5 70 | 6 71 | 7 72 | 8 73 | 9 74 | 10 75 | 11 76 | 12 77 | 13 78 | 14 79 | 15 80 | 16 81 | 17 82 | 18 83 | 19 84 | 20 85 | 21 86 | 22 87 | 23 88 | 24 89 | 25 90 | 26 91 | 27 92 | 28 93 | 29 94 | 30 95 | 31 96 | 32 97 | 33 98 | 34 99 | 35 100 | 36 101 | 37 102 | 38 103 | 39 104 | 40 105 | 41 106 | 42 107 | 43 108 | 44 109 | 45 110 | 46 111 | 47 112 | 48 113 | 49 114 | 50 115 | 51 116 | 52 117 | 53 118 | 54 119 | 55 120 | 56 121 | 57 122 | 58 123 | 59 124 | 60 125 | 61 126 | 62 127 | 63 128 | 64 -------------------------------------------------------------------------------- /source/scale_clip/data/im_dout.txt: -------------------------------------------------------------------------------- 1 | 00000000000000000000000010000100 2 | 00000000000000001111111111010101 3 | 00000000000000001111111111101001 4 | 00000000000000001111111111110001 5 | 00000000000000001111111111110100 6 | 00000000000000001111111111110110 7 | 00000000000000001111111111110110 8 | 00000000000000001111111111111010 9 | 00000000000000001111111111111001 10 | 00000000000000001111111111111001 11 | 00000000000000001111111111111011 12 | 00000000000000001111111111111010 13 | 00000000000000001111111111111011 14 | 00000000000000001111111111111011 15 | 00000000000000001111111111111100 16 | 00000000000000001111111111111100 17 | 00000000000000001111111111111100 18 | 00000000000000001111111111111101 19 | 00000000000000001111111111111100 20 | 00000000000000001111111111111100 21 | 00000000000000001111111111111100 22 | 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00000000000000000000000000001000 126 | 00000000000000000000000000001100 127 | 00000000000000000000000000010011 128 | 00000000000000000000000000100111 129 | -------------------------------------------------------------------------------- /source/scale_clip/data/re_din.txt: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | 5 6 | 6 7 | 7 8 | 8 9 | 9 10 | 10 11 | 11 12 | 12 13 | 13 14 | 14 15 | 15 16 | 16 17 | 17 18 | 18 19 | 19 20 | 20 21 | 21 22 | 22 23 | 23 24 | 24 25 | 25 26 | 26 27 | 27 28 | 28 29 | 29 30 | 30 31 | 31 32 | 32 33 | 33 34 | 34 35 | 35 36 | 36 37 | 37 38 | 38 39 | 39 40 | 40 41 | 41 42 | 42 43 | 43 44 | 44 45 | 45 46 | 46 47 | 47 48 | 48 49 | 49 50 | 50 51 | 51 52 | 52 53 | 53 54 | 54 55 | 55 56 | 56 57 | 57 58 | 58 59 | 59 60 | 60 61 | 61 62 | 62 63 | 63 64 | 64 65 | 1 66 | 2 67 | 3 68 | 4 69 | 5 70 | 6 71 | 7 72 | 8 73 | 9 74 | 10 75 | 11 76 | 12 77 | 13 78 | 14 79 | 15 80 | 16 81 | 17 82 | 18 83 | 19 84 | 20 85 | 21 86 | 22 87 | 23 88 | 24 89 | 25 90 | 26 91 | 27 92 | 28 93 | 29 94 | 30 95 | 31 96 | 32 97 | 33 98 | 34 99 | 35 100 | 36 101 | 37 102 | 38 103 | 39 104 | 40 105 | 41 106 | 42 107 | 43 108 | 44 109 | 45 110 | 46 111 | 47 112 | 48 113 | 49 114 | 50 115 | 51 116 | 52 117 | 53 118 | 54 119 | 55 120 | 56 121 | 57 122 | 58 123 | 59 124 | 60 125 | 61 126 | 62 127 | 63 128 | 64 -------------------------------------------------------------------------------- /source/scale_clip/data/re_dout.txt: -------------------------------------------------------------------------------- 1 | 00000000000000000000000010000100 2 | 00000000000000000000000000100111 3 | 00000000000000000000000000010011 4 | 00000000000000000000000000001011 5 | 00000000000000000000000000001000 6 | 00000000000000000000000000000110 7 | 00000000000000000000000000000110 8 | 00000000000000000000000000000010 9 | 00000000000000000000000000000011 10 | 00000000000000000000000000000011 11 | 00000000000000000000000000000001 12 | 00000000000000000000000000000010 13 | 00000000000000000000000000000001 14 | 00000000000000000000000000000001 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000001111111111111111 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000001111111111111111 22 | 00000000000000001111111111111110 23 | 00000000000000001111111111111111 24 | 00000000000000001111111111111111 25 | 00000000000000001111111111111111 26 | 00000000000000000000000000000000 27 | 00000000000000001111111111111110 28 | 00000000000000001111111111111111 29 | 00000000000000001111111111111110 30 | 00000000000000001111111111111110 31 | 00000000000000001111111111111110 32 | 00000000000000001111111111111110 33 | 00000000000000000000000000000000 34 | 00000000000000001111111111111110 35 | 00000000000000001111111111111101 36 | 00000000000000001111111111111110 37 | 00000000000000001111111111111101 38 | 00000000000000001111111111111101 39 | 00000000000000001111111111111100 40 | 00000000000000001111111111111101 41 | 00000000000000001111111111111101 42 | 00000000000000001111111111111100 43 | 00000000000000001111111111111101 44 | 00000000000000001111111111111101 45 | 00000000000000001111111111111100 46 | 00000000000000001111111111111100 47 | 00000000000000001111111111111100 48 | 00000000000000001111111111111101 49 | 00000000000000001111111111111100 50 | 00000000000000001111111111111100 51 | 00000000000000001111111111111100 52 | 00000000000000001111111111111011 53 | 00000000000000001111111111111011 54 | 00000000000000001111111111111010 55 | 00000000000000001111111111111010 56 | 00000000000000001111111111111010 57 | 00000000000000001111111111111001 58 | 00000000000000001111111111111001 59 | 00000000000000001111111111110111 60 | 00000000000000001111111111110110 61 | 00000000000000001111111111110100 62 | 00000000000000001111111111110000 63 | 00000000000000001111111111101001 64 | 00000000000000001111111111010101 65 | 00000000000000000000000010000100 66 | 00000000000000000000000000100111 67 | 00000000000000000000000000010011 68 | 00000000000000000000000000001011 69 | 00000000000000000000000000001000 70 | 00000000000000000000000000000110 71 | 00000000000000000000000000000110 72 | 00000000000000000000000000000010 73 | 00000000000000000000000000000011 74 | 00000000000000000000000000000011 75 | 00000000000000000000000000000001 76 | 00000000000000000000000000000010 77 | 00000000000000000000000000000001 78 | 00000000000000000000000000000001 79 | 00000000000000000000000000000000 80 | 00000000000000000000000000000000 81 | 00000000000000000000000000000000 82 | 00000000000000001111111111111111 83 | 00000000000000000000000000000000 84 | 00000000000000000000000000000000 85 | 00000000000000001111111111111111 86 | 00000000000000001111111111111110 87 | 00000000000000001111111111111111 88 | 00000000000000001111111111111111 89 | 00000000000000001111111111111111 90 | 00000000000000000000000000000000 91 | 00000000000000001111111111111110 92 | 00000000000000001111111111111111 93 | 00000000000000001111111111111110 94 | 00000000000000001111111111111110 95 | 00000000000000001111111111111110 96 | 00000000000000001111111111111110 97 | 00000000000000000000000000000000 98 | 00000000000000001111111111111110 99 | 00000000000000001111111111111101 100 | 00000000000000001111111111111110 101 | 00000000000000001111111111111101 102 | 00000000000000001111111111111101 103 | 00000000000000001111111111111100 104 | 00000000000000001111111111111101 105 | 00000000000000001111111111111101 106 | 00000000000000001111111111111100 107 | 00000000000000001111111111111101 108 | 00000000000000001111111111111101 109 | 00000000000000001111111111111100 110 | 00000000000000001111111111111100 111 | 00000000000000001111111111111100 112 | 00000000000000001111111111111101 113 | 00000000000000001111111111111100 114 | 00000000000000001111111111111100 115 | 00000000000000001111111111111100 116 | 00000000000000001111111111111011 117 | 00000000000000001111111111111011 118 | 00000000000000001111111111111010 119 | 00000000000000001111111111111010 120 | 00000000000000001111111111111010 121 | 00000000000000001111111111111001 122 | 00000000000000001111111111111001 123 | 00000000000000001111111111110111 124 | 00000000000000001111111111110110 125 | 00000000000000001111111111110100 126 | 00000000000000001111111111110000 127 | 00000000000000001111111111101001 128 | 00000000000000001111111111010101 129 | -------------------------------------------------------------------------------- /source/scale_clip/sc_sim.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vmap work work 3 | 4 | vlog scale_clip.v 5 | vlog scale_clip_tb.v 6 | vsim scale_clip_tb 7 | 8 | 9 | add wave -label clk /scale_clip_tb/clk 10 | 11 | 12 | add wave -radix dec -label sc_real_din /scale_clip_tb/sc_real_din 13 | add wave -radix dec -label sc_imag_din /scale_clip_tb/sc_imag_din 14 | add wave -radix dec -label exp /scale_clip_tb/ins/exp 15 | add wave -radix dec -label full_range_real_out /scale_clip_tb/ins/full_range_real_out 16 | add wave -radix dec -label full_range_imag_out /scale_clip_tb/ins/full_range_imag_out 17 | add wave -color Magenta -radix dec -label sc_real_dout /scale_clip_tb/sc_real_dout 18 | add wave -color Magenta -radix dec -label sc_imag_dout /scale_clip_tb/sc_imag_dout 19 | 20 | run -all; -------------------------------------------------------------------------------- /source/scale_clip/scale_clip.v: -------------------------------------------------------------------------------- 1 | //功能：数据位宽扩展与裁剪 2 | 3 | module scale_clip( 4 | input [15:0] sc_real_din, 5 | input [15:0] sc_imag_din, 6 | input [5:0] exp, 7 | output [17:0] sc_real_dout, //16+8-6=18 8 | output [17:0] sc_imag_dout); 9 | 10 | reg [23:0] full_range_real_out; //根据数据手册，N=64,Quad Output Engine,Exponent Scaling Values ,Max=-8,Min=-4 11 | reg [23:0] full_range_imag_out; //IFFT real_value = data*2^(-exp)/N. 12 | 13 | assign sc_real_dout = full_range_real_out[23:6]; 14 | assign sc_imag_dout = full_range_imag_out[23:6]; 15 | //数据为扩展，data*2^(-exp) 16 | always@(*) begin 17 | case (exp) 18 | 6'b111000 : //-8 19 | begin 20 | full_range_real_out[23:0] <= {sc_real_din[15:0],8'b0}; 21 | full_range_imag_out[23:0] <= {sc_imag_din[15:0],8'b0}; 22 | end 23 | 6'b111001 : //-7 24 | begin 25 | full_range_real_out[23] <= {sc_real_din[15]}; 26 | full_range_real_out[22:0] <= {sc_real_din[15:0],7'b0}; 27 | full_range_imag_out[23] <= {sc_imag_din[15]}; 28 | full_range_imag_out[22:0] <= {sc_imag_din[15:0],7'b0}; 29 | end 30 | 6'b111010 : //-6 31 | begin 32 | full_range_real_out[23:22] <= {sc_real_din[15],sc_real_din[15]}; 33 | full_range_real_out[21:0] <= {sc_real_din[15:0],6'b0}; 34 | full_range_imag_out[23:22] <= {sc_imag_din[15],sc_imag_din[15]}; 35 | full_range_imag_out[21:0] <= {sc_imag_din[15:0],6'b0}; 36 | end 37 | 6'b111011 : //-5 38 | begin 39 | full_range_real_out[23:21] <= {3{sc_real_din[15]}}; 40 | full_range_real_out[20:0] <= {sc_real_din[15:0],5'b0}; 41 | full_range_imag_out[23:21] <= {3{sc_imag_din[15]}}; 42 | full_range_imag_out[20:0] <= {sc_imag_din[15:0],5'b0}; 43 | end 44 | 6'b111100 : //-4 45 | begin 46 | full_range_real_out[23:20] <= {4{sc_real_din[15]}}; 47 | full_range_real_out[19:0] <= {sc_real_din[15:0],4'b0}; 48 | full_range_imag_out[23:20] <= {4{sc_imag_din[15]}}; 49 | full_range_imag_out[19:0] <= {sc_imag_din[15:0],4'b0}; 50 | end 51 | endcase 52 | end 53 | endmodule 54 | -------------------------------------------------------------------------------- /source/scale_clip/scale_clip_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module scale_clip_tb(); 3 | reg [15:0] sc_real_din; 4 | reg [15:0] sc_imag_din; 5 | reg [5:0] exp; 6 | wire [17:0] sc_real_dout; 7 | wire [17:0] sc_imag_dout; 8 | 9 | reg clk; 10 | integer expf; 11 | integer data_re,data_im; 12 | 13 | initial begin 14 | data_re = $fopen("C:/Users/Administrator/Desktop/code/data/re_dout.txt","r"); 15 | data_im = $fopen("C:/Users/Administrator/Desktop/code/data/im_dout.txt","r"); 16 | expf = $fopen("C:/Users/Administrator/Desktop/code/data/exp.txt","r"); 17 | clk = 0; 18 | #2560; //64*40 19 | $stop(); 20 | end 21 | 22 | always #20 clk = ~clk; 23 | 24 | integer rc_x,ic_x,data_real_in_int,data_imag_in_int,exp_in,exp_in_int; 25 | always@(negedge clk) begin 26 | rc_x = $fscanf(data_re,"%b",data_real_in_int); 27 | sc_real_din <= data_real_in_int; 28 | ic_x = $fscanf(data_im,"%b",data_imag_in_int); 29 | sc_imag_din <= data_imag_in_int; 30 | exp_in = $fscanf(expf,"%b",exp_in_int); 31 | exp <= exp_in_int; 32 | end 33 | 34 | scale_clip ins( 35 | .sc_real_din(sc_real_din), 36 | .sc_imag_din(sc_imag_din), 37 | .exp(exp), 38 | .sc_real_dout(sc_real_dout), 39 | .sc_imag_dout(sc_imag_dout)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /source/tx_top.v: -------------------------------------------------------------------------------- 1 | module tx_top #(parameter WIDTH = 16)( 2 | input clk, //系统时钟100M 3 | input rst_n, 4 | output dout_valid, 5 | output [18-1:0] cp_real_dout, //输出数据的虚部 6 | output [18-1:0] cp_imag_dout); //输出数据的实部 7 | 8 | reg trig_en; 9 | reg [8:0] tx_cnt; 10 | 11 | 12 | 13 | wire clk_20; 14 | wire clk_80; 15 | wire rx_data; 16 | wire map_pilot_valid; 17 | wire prbs_map_valid; 18 | wire pilot_her_valid; 19 | wire her_ifft_valid; 20 | wire ifft_cp_valid; 21 | 22 | wire [5:0] exp; 23 | wire [5:0] map_pilot_index; 24 | wire [5:0] ifft_cp_index; 25 | wire [5:0] pilot_her_index; 26 | wire [WIDTH-1:0] map_pilot_real; 27 | wire [WIDTH-1:0] map_pilot_imag; 28 | wire [WIDTH-1:0] pilot_her_real; 29 | wire [WIDTH-1:0] pilot_her_imag; 30 | wire [WIDTH-1:0] her_ifft_real; 31 | wire [WIDTH-1:0] her_ifft_imag; 32 | wire [WIDTH-1:0] ifft_sc_real; 33 | wire [WIDTH-1:0] ifft_sc_imag; 34 | wire [18-1:0] sc_cp_real; 35 | wire [18-1:0] sc_cp_imag; 36 | 37 | 38 | always@(posedge clk_80) begin 39 | if(!rst_n) begin 40 | tx_cnt <= 1'b0; 41 | end 42 | else begin 43 | if(tx_cnt == 319) begin 44 | tx_cnt <= 1'b0; 45 | end 46 | else begin 47 | tx_cnt <= tx_cnt + 1'b1; 48 | end 49 | end 50 | end 51 | 52 | always@(*) begin 53 | //if(!rst_n) begin 54 | // en <= 1'b0; 55 | //end 56 | //else begin 57 | if(tx_cnt < 192) 58 | trig_en = 1'b1; 59 | else 60 | trig_en = 1'b0; 61 | //end 62 | end 63 | //always@(negedge clk_25) begin 64 | // if(!rst_n) begin 65 | // ifft_rst_n <= 0; 66 | // end 67 | // else begin 68 | // if(pilot_her_valid) begin 69 | // ifft_rst_n <= 1'b1; 70 | // end 71 | // else begin 72 | // // ifft_rst_n <= 0; 73 | // end 74 | // end 75 | //end 76 | 77 | clk_pll clk_div ( 78 | .refclk ( clk ), 79 | .rst(), 80 | .outclk_0 ( clk_20 ), 81 | .outclk_1 ( clk_80 )); 82 | 83 | 84 | prbs15 prbs( 85 | .prbs_clk(clk_80), 86 | .prbs_rst_n(rst_n), 87 | .trig_en(trig_en), 88 | .prbs_out(rx_data), 89 | .dout_valid(prbs_map_valid)); 90 | 91 | QAM16_MAP map( 92 | .qam_clk(clk_80), 93 | .din_valid(prbs_map_valid), 94 | .qam_din(rx_data), 95 | .dout_valid(map_pilot_valid), 96 | .qam_dout_imag(map_pilot_imag), 97 | .qam_dout_real(map_pilot_real), 98 | .qam_rst_n(rst_n), 99 | .dout_index(map_pilot_index)); 100 | 101 | Insert_Pilot pilot ( 102 | .pilot_clk(clk_20), 103 | .pilot_rst_n(rst_n), 104 | .din_valid(map_pilot_valid), 105 | .index(map_pilot_index), 106 | .pilot_imag_din(map_pilot_imag), 107 | .pilot_real_din(map_pilot_real), 108 | .pilot_imag_dout(pilot_her_imag), 109 | .pilot_real_dout(pilot_her_real), 110 | .dout_valid(pilot_her_valid), 111 | .dout_index(pilot_her_index)); 112 | 113 | hermitian her_ins( 114 | .her_clk(clk_20), 115 | .her_rst_n(rst_n), 116 | .din_valid(pilot_her_valid), 117 | .din_index(pilot_her_index), 118 | .her_real_din(pilot_her_real), 119 | .her_imag_din(pilot_her_imag), 120 | .her_real_dout(her_ifft_real), 121 | .her_imag_dout(her_ifft_imag), 122 | .dout_valid(her_ifft_valid)); 123 | 124 | ifft_clac ifft( 125 | .ifft_clk(clk_20), 126 | .ifft_rst_n(rst_n), 127 | .din_valid(her_ifft_valid), 128 | .ifft_real_din(her_ifft_real), 129 | .ifft_imag_din(her_ifft_imag), 130 | .dout_valid(ifft_cp_valid), 131 | .ifft_real_dout(ifft_sc_real), 132 | .ifft_imag_dout(ifft_sc_imag), 133 | .dout_exp(exp), 134 | .dout_index(ifft_cp_index)); 135 | 136 | scale_clip sc_ins( 137 | .sc_real_din(ifft_sc_real), 138 | .sc_imag_din(ifft_sc_imag), 139 | .exp(exp), 140 | .sc_real_dout(sc_cp_real), 141 | .sc_imag_dout(sc_cp_imag)); 142 | 143 | add_cyclic_prefix #(18) cp( 144 | .cp_clk(clk_20), 145 | .cp_rst_n(rst_n), 146 | .din_valid(ifft_cp_valid), 147 | .cp_real_din(sc_cp_real), 148 | .cp_imag_din(sc_cp_imag), 149 | .din_index(ifft_cp_index), 150 | .dout_valid(dout_valid), 151 | .cp_real_dout(cp_real_dout), 152 | .cp_imag_dout(cp_imag_dout)); 153 | 154 | endmodule 155 | -------------------------------------------------------------------------------- /tb/tx_top_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module tx_top_tb(); 4 | reg clk; 5 | reg rst_n; 6 | 7 | wire [17:0] cp_real_dout; 8 | wire [17:0] cp_imag_dout; 9 | wire dout_valid; 10 | 11 | wire clk_20; 12 | wire clk_80; 13 | 14 | integer cp_real_out_int,cp_imag_out_int; 15 | integer cp_rf, cp_if; 16 | 17 | tx_top tx_top_ins(.clk(clk), 18 | .rst_n(rst_n), 19 | .cp_real_dout(cp_real_dout), 20 | .cp_imag_dout(cp_imag_dout), 21 | .dout_valid(dout_valid)); 22 | 23 | 24 | 25 | clk_pll clk_divv ( 26 | .refclk ( clk ), 27 | .rst(), 28 | .outclk_0 ( clk_20 ), 29 | .outclk_1 ( clk_80 )); 30 | 31 | initial begin 32 | cp_rf = $fopen("cp_real_output.txt"); 33 | cp_if = $fopen("cp_imag_output.txt"); 34 | clk = 0; 35 | rst_n = 0; 36 | #200; 37 | rst_n = 1; 38 | 39 | end 40 | 41 | always #10 clk = ~clk; 42 | 43 | parameter MAXVAL_c = 2**(18 -1); 44 | parameter OFFSET_c = 2**(18); 45 | 46 | always @ (posedge clk_20) begin 47 | if(dout_valid) begin 48 | cp_real_out_int = cp_real_dout; 49 | cp_imag_out_int = cp_imag_dout; 50 | $fdisplay(cp_rf, "%d", (cp_real_out_int < MAXVAL_c) ? cp_real_out_int : cp_real_out_int - OFFSET_c); 51 | $fdisplay(cp_if, "%d", (cp_imag_out_int < MAXVAL_c) ? cp_imag_out_int : cp_imag_out_int - OFFSET_c); 52 | 53 | end 54 | end 55 | 56 | endmodule 57 | 58 | 59 | 60 | 61 | --------------------------------------------------------------------------------