├── .gitattributes ├── .gitignore ├── README.md ├── images ├── 0.jpg └── 1.jpg ├── overlay └── pynquser │ ├── dac_contest.bit │ └── dac_contest.tcl ├── pynquser ├── dac_contest.ipynb ├── libraries │ ├── xxx.py │ └── xxx.so ├── params │ └── xxx.bin └── preprocessing.py └── result ├── coordinate └── pynquser │ └── xxx.txt ├── time └── pynquser.txt └── xml └── pynquser ├── 0.xml └── 1.xml /.gitattributes: -------------------------------------------------------------------------------- 1 | # Per default everything gets normalized and gets LF line endings on checkout. 2 | * text eol=lf 3 | 4 | # These will always have CRLF line endings on checkout. 5 | *.vcxproj text eol=crlf 6 | *.props text eol=crlf 7 | *.project text eol=crlf 8 | *.cproject text eol=crlf 9 | 10 | # These are binary so should never be modified by git. 11 | *.png binary 12 | *.jpg binary 13 | *.jpe binary 14 | *.jpeg binary 15 | *.JPG binary 16 | *.PNG binary 17 | *.ttf binary 18 | *.eot binary 19 | *.woff binary 20 | *.inv binary 21 | *.dxf binary 22 | *.mp4 binary 23 | *.wav binary -crlf 24 | *.mp3 binary 25 | *.hdf binary 26 | *.bat binary 27 | *.pdm binary 28 | *.doctree binary 29 | *.elf binary -crlf 30 | *.bin binary -crlf 31 | *.bit binary -crlf 32 | *.a binary -crlf 33 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Compiled Sources 2 | ################### 3 | *.o 4 | *.map 5 | *.hex 6 | *.dis 7 | *.exe 8 | 9 | # Packages 10 | ############ 11 | 12 | # Windows Thumbnail 13 | ###################### 14 | Thumbs.db 15 | thumbs.db 16 | 17 | # Logs and Databases 18 | ###################### 19 | *.log 20 | 21 | # VIM Swap Files 22 | ###################### 23 | *.swp 24 | 25 | # Build directory 26 | ###################### 27 | build/ 28 | sdcard/ 29 | 30 | # Test failure outputs 31 | ###################### 32 | tests/*.exp 33 | tests/*.out 34 | 35 | # Python cache files 36 | ###################### 37 | __pycache__/ 38 | 39 | # Customized Makefile/project overrides 40 | ###################### 41 | GNUmakefile 42 | user.props 43 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # DAC 2018 Design Contest 2 | 3 | For general questions regarding this contest, please contact Xinyi Zhang . 4 | 5 | ## Usage 6 | The get started, users have to run the following command on PYNQ-Z1 board: 7 | 8 | ```shell 9 | cd /home/xilinx/jupyter_notebooks 10 | sudo git clone https://github.com/yunqu/dac_2018.git 11 | ``` 12 | Remember the user name and password are both `xilinx` for super user. 13 | 14 | After the above step is completed successfully, you will see a folder `dac_2018` under your 15 | jupyter notebook dashboard. 16 | 17 | 18 | ## Folder Structure 19 | 20 | 1. overlay: This folder stores the overlay needed for the design. Usually it includes .bit and .tcl. 21 | 22 | 2. images: All the test images are stored in this folder. 23 | 24 | 3. python: This folder contains the python classes needed for the design, as well as the example notebook(s). 25 | 26 | 4. result: The results includes the coordinates of the resized pictures and the frame rate of each picture. 27 | 28 | ## 12/06/2017 update 29 | 30 | Redundant variables in DACSDC.py were moved. 31 | 32 | Function "storeResultsToXML" in DACSDC.py is revised. 33 | 34 | Please ignore object "boat9" and "group4" in the training dataset. They will be deleted from the latest training dataset. 35 | 36 | ## 01/05/2018 update 37 | 38 | Revised python classes and polished notebooks. 39 | 40 | ## 01/18/2018 update 41 | 42 | Updated the overlay: (1) changed to use HP port for DMA transfer, (2) enlarged the FIFO depth, (3) updated the 43 | DDR memory parameters, and (4) updated DMA configuration parameters. 44 | 45 | -------------------------------------------------------------------------------- /images/0.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yunqu/dac_2018/4d016db025f5c26b9a277010c933f386672c1a48/images/0.jpg -------------------------------------------------------------------------------- /images/1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yunqu/dac_2018/4d016db025f5c26b9a277010c933f386672c1a48/images/1.jpg -------------------------------------------------------------------------------- /overlay/pynquser/dac_contest.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yunqu/dac_2018/4d016db025f5c26b9a277010c933f386672c1a48/overlay/pynquser/dac_contest.bit -------------------------------------------------------------------------------- /overlay/pynquser/dac_contest.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: dac_contest 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | namespace eval _tcl { 11 | proc get_script_folder {} { 12 | set script_path [file normalize [info script]] 13 | set script_folder [file dirname $script_path] 14 | return $script_folder 15 | } 16 | } 17 | variable script_folder 18 | set script_folder [_tcl::get_script_folder] 19 | 20 | ################################################################ 21 | # Check if script is running in correct Vivado version. 22 | ################################################################ 23 | set scripts_vivado_version 2016.1 24 | set current_vivado_version [version -short] 25 | 26 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 27 | puts "" 28 | catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 29 | 30 | return 1 31 | } 32 | 33 | ################################################################ 34 | # START 35 | ################################################################ 36 | 37 | # To test this script, run the following commands from Vivado Tcl console: 38 | # source dac_contest_script.tcl 39 | 40 | # If there is no project opened, this script will create a 41 | # project, but make sure you do not have an existing project 42 | # <./myproj/project_1.xpr> in the current working folder. 43 | 44 | set list_projs [get_projects -quiet] 45 | if { $list_projs eq "" } { 46 | create_project project_1 myproj -part xc7z020clg400-1 47 | } 48 | 49 | 50 | # CHANGE DESIGN NAME HERE 51 | set design_name dac_contest 52 | 53 | # This script was generated for a remote BD. To create a non-remote design, 54 | # change the variable to <0>. 55 | 56 | set run_remote_bd_flow 1 57 | if { $run_remote_bd_flow == 1 } { 58 | set str_bd_folder . 59 | set str_bd_filepath ${str_bd_folder}/${design_name}.bd 60 | 61 | # Check if remote design exists on disk 62 | if { [file exists $str_bd_filepath ] == 1 } { 63 | catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"} 64 | common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable to <0>." 65 | common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project." 66 | 67 | return 1 68 | } 69 | 70 | # Check if design exists in memory 71 | set list_existing_designs [get_bd_designs -quiet $design_name] 72 | if { $list_existing_designs ne "" } { 73 | catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."} 74 | 75 | common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable to <0> or please set a different value to variable ." 76 | 77 | return 1 78 | } 79 | 80 | # Check if design exists on disk within project 81 | set list_existing_designs [get_files */${design_name}.bd] 82 | if { $list_existing_designs ne "" } { 83 | catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location: 84 | $list_existing_designs"} 85 | catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."} 86 | 87 | common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable to <0> or please set a different value to variable ." 88 | 89 | return 1 90 | } 91 | 92 | # Now can create the remote BD 93 | create_bd_design -dir $str_bd_folder $design_name 94 | } else { 95 | 96 | # Create regular design 97 | if { [catch {create_bd_design $design_name} errmsg] } { 98 | common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable ." 99 | 100 | return 1 101 | } 102 | } 103 | 104 | current_bd_design $design_name 105 | 106 | ################################################################## 107 | # DESIGN PROCs 108 | ################################################################## 109 | 110 | 111 | 112 | # Procedure to create entire design; Provide argument to make 113 | # procedure reusable. If parentCell is "", will use root. 114 | proc create_root_design { parentCell } { 115 | 116 | variable script_folder 117 | 118 | if { $parentCell eq "" } { 119 | set parentCell [get_bd_cells /] 120 | } 121 | 122 | # Get object for parentCell 123 | set parentObj [get_bd_cells $parentCell] 124 | if { $parentObj == "" } { 125 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 126 | return 127 | } 128 | 129 | # Make sure parentObj is hier blk 130 | set parentType [get_property TYPE $parentObj] 131 | if { $parentType ne "hier" } { 132 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 133 | return 134 | } 135 | 136 | # Save current instance; Restore later 137 | set oldCurInst [current_bd_instance .] 138 | 139 | # Set parent object as current 140 | current_bd_instance $parentObj 141 | 142 | 143 | # Create interface ports 144 | set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] 145 | set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] 146 | 147 | # Create ports 148 | 149 | # Create instance: axi_dma_0, and set properties 150 | set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] 151 | set_property -dict [ list \ 152 | CONFIG.c_include_mm2s_dre {0} \ 153 | CONFIG.c_include_s2mm_dre {0} \ 154 | CONFIG.c_include_sg {0} \ 155 | CONFIG.c_mm2s_burst_size {256} \ 156 | CONFIG.c_s2mm_burst_size {256} \ 157 | CONFIG.c_sg_include_stscntrl_strm {0} \ 158 | CONFIG.c_sg_length_width {23} \ 159 | ] $axi_dma_0 160 | 161 | # Create instance: axi_interconnect_0, and set properties 162 | set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] 163 | set_property -dict [ list \ 164 | CONFIG.NUM_MI {1} \ 165 | CONFIG.NUM_SI {2} \ 166 | ] $axi_interconnect_0 167 | 168 | # Create instance: axi_interconnect_1, and set properties 169 | set axi_interconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1 ] 170 | set_property -dict [ list \ 171 | CONFIG.NUM_MI {1} \ 172 | ] $axi_interconnect_1 173 | 174 | # Create instance: axis_data_fifo_0, and set properties 175 | set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] 176 | set_property -dict [ list \ 177 | CONFIG.FIFO_DEPTH {32768} \ 178 | ] $axis_data_fifo_0 179 | 180 | # Create instance: proc_sys_reset_0, and set properties 181 | set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] 182 | 183 | # Create instance: processing_system7_0, and set properties 184 | set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] 185 | set_property -dict [ list \ 186 | CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ 187 | CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ 188 | CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ 189 | CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \ 190 | CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ 191 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 192 | CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ 193 | CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ 194 | CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ 195 | CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ 196 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ 197 | CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \ 198 | CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ 199 | CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ 200 | CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ 201 | CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 202 | CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 203 | CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 204 | CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 205 | CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 206 | CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 207 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \ 208 | CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ 209 | CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ 210 | CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ 211 | CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ 212 | CONFIG.PCW_CAN0_CAN0_IO {} \ 215 | CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ 216 | CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ 217 | CONFIG.PCW_CAN1_CAN1_IO {} \ 220 | CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ 221 | CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ 222 | CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ 223 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ 224 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ 225 | CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ 226 | CONFIG.PCW_CLK0_FREQ {100000000} \ 227 | CONFIG.PCW_CLK1_FREQ {10000000} \ 228 | CONFIG.PCW_CLK2_FREQ {10000000} \ 229 | CONFIG.PCW_CLK3_FREQ {10000000} \ 230 | CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ 231 | CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ 232 | CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ 233 | CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ 234 | CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ 235 | CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ 236 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ 237 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ 238 | CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ 239 | CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ 240 | CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ 241 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 242 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 243 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 244 | CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ 245 | CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ 246 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 247 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 248 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 249 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 250 | CONFIG.PCW_DDR_PRIORITY_READPORT_0 {} \ 252 | CONFIG.PCW_DDR_PRIORITY_READPORT_2 {} \ 254 | CONFIG.PCW_DDR_PRIORITY_WRITEPORT_0 {} \ 256 | CONFIG.PCW_DDR_PRIORITY_WRITEPORT_2 {} \ 258 | CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ 259 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 260 | CONFIG.PCW_ENET0_ENET0_IO {} \ 263 | CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ 264 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ 265 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ 266 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ 267 | CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ 268 | CONFIG.PCW_ENET0_RESET_ENABLE {0} \ 269 | CONFIG.PCW_ENET0_RESET_IO {} \ 271 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 272 | CONFIG.PCW_ENET1_GRP_MDIO_IO {} \ 280 | CONFIG.PCW_ENET_RESET_ENABLE {0} \ 281 | CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ 282 | CONFIG.PCW_ENET_RESET_SELECT {} \ 305 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ 306 | CONFIG.PCW_GPIO_MIO_GPIO_IO {} \ 310 | CONFIG.PCW_I2C0_I2C0_IO {} \ 314 | CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \ 315 | CONFIG.PCW_I2C1_GRP_INT_IO {} \ 317 | CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \ 318 | CONFIG.PCW_I2C1_RESET_ENABLE {0} \ 319 | CONFIG.PCW_I2C1_RESET_IO {} \ 324 | CONFIG.PCW_IOPLL_CTRL_FBDIV {32} \ 325 | CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \ 326 | CONFIG.PCW_MIO_0_DIRECTION {} \ 328 | CONFIG.PCW_MIO_0_PULLUP {} \ 330 | CONFIG.PCW_MIO_10_DIRECTION {} \ 332 | CONFIG.PCW_MIO_10_PULLUP {} \ 334 | CONFIG.PCW_MIO_11_DIRECTION {} \ 336 | CONFIG.PCW_MIO_11_PULLUP {} \ 338 | CONFIG.PCW_MIO_12_DIRECTION {} \ 340 | CONFIG.PCW_MIO_12_PULLUP {} \ 342 | CONFIG.PCW_MIO_13_DIRECTION {} \ 344 | CONFIG.PCW_MIO_13_PULLUP {} \ 346 | CONFIG.PCW_MIO_14_DIRECTION {} \ 348 | CONFIG.PCW_MIO_14_PULLUP {} \ 350 | CONFIG.PCW_MIO_15_DIRECTION {} \ 352 | CONFIG.PCW_MIO_15_PULLUP {} \ 354 | CONFIG.PCW_MIO_16_DIRECTION {} \ 356 | CONFIG.PCW_MIO_16_PULLUP {} \ 358 | CONFIG.PCW_MIO_17_DIRECTION {} \ 360 | CONFIG.PCW_MIO_17_PULLUP {} \ 362 | CONFIG.PCW_MIO_18_DIRECTION {} \ 364 | CONFIG.PCW_MIO_18_PULLUP {} \ 366 | CONFIG.PCW_MIO_19_DIRECTION {} \ 368 | CONFIG.PCW_MIO_19_PULLUP {} \ 370 | CONFIG.PCW_MIO_1_DIRECTION {} \ 372 | CONFIG.PCW_MIO_1_PULLUP {} \ 374 | CONFIG.PCW_MIO_20_DIRECTION {} \ 376 | CONFIG.PCW_MIO_20_PULLUP {} \ 378 | CONFIG.PCW_MIO_21_DIRECTION {} \ 380 | CONFIG.PCW_MIO_21_PULLUP {} \ 382 | CONFIG.PCW_MIO_22_DIRECTION {} \ 384 | CONFIG.PCW_MIO_22_PULLUP {} \ 386 | CONFIG.PCW_MIO_23_DIRECTION {} \ 388 | CONFIG.PCW_MIO_23_PULLUP {} \ 390 | CONFIG.PCW_MIO_24_DIRECTION {} \ 392 | CONFIG.PCW_MIO_24_PULLUP {} \ 394 | CONFIG.PCW_MIO_25_DIRECTION {} \ 396 | CONFIG.PCW_MIO_25_PULLUP {} \ 398 | CONFIG.PCW_MIO_26_DIRECTION {} \ 400 | CONFIG.PCW_MIO_26_PULLUP {} \ 402 | CONFIG.PCW_MIO_27_DIRECTION {} \ 404 | CONFIG.PCW_MIO_27_PULLUP {} \ 406 | CONFIG.PCW_MIO_28_DIRECTION {} \ 408 | CONFIG.PCW_MIO_28_PULLUP {} \ 410 | CONFIG.PCW_MIO_29_DIRECTION {} \ 412 | CONFIG.PCW_MIO_29_PULLUP {} \ 414 | CONFIG.PCW_MIO_2_DIRECTION {} \ 416 | CONFIG.PCW_MIO_2_PULLUP {} \ 418 | CONFIG.PCW_MIO_30_DIRECTION {} \ 420 | CONFIG.PCW_MIO_30_PULLUP {} \ 422 | CONFIG.PCW_MIO_31_DIRECTION {} \ 424 | CONFIG.PCW_MIO_31_PULLUP {} \ 426 | CONFIG.PCW_MIO_32_DIRECTION {} \ 428 | CONFIG.PCW_MIO_32_PULLUP {} \ 430 | CONFIG.PCW_MIO_33_DIRECTION {} \ 432 | CONFIG.PCW_MIO_33_PULLUP {} \ 434 | CONFIG.PCW_MIO_34_DIRECTION {} \ 436 | CONFIG.PCW_MIO_34_PULLUP {} \ 438 | CONFIG.PCW_MIO_35_DIRECTION {} \ 440 | CONFIG.PCW_MIO_35_PULLUP {} \ 442 | CONFIG.PCW_MIO_36_DIRECTION {} \ 444 | CONFIG.PCW_MIO_36_PULLUP {} \ 446 | CONFIG.PCW_MIO_37_DIRECTION {} \ 448 | CONFIG.PCW_MIO_37_PULLUP {} \ 450 | CONFIG.PCW_MIO_38_DIRECTION {} \ 452 | CONFIG.PCW_MIO_38_PULLUP {} \ 454 | CONFIG.PCW_MIO_39_DIRECTION {} \ 456 | CONFIG.PCW_MIO_39_PULLUP {} \ 458 | CONFIG.PCW_MIO_3_DIRECTION {} \ 460 | CONFIG.PCW_MIO_3_PULLUP {} \ 462 | CONFIG.PCW_MIO_40_DIRECTION {} \ 464 | CONFIG.PCW_MIO_40_PULLUP {} \ 466 | CONFIG.PCW_MIO_41_DIRECTION {} \ 468 | CONFIG.PCW_MIO_41_PULLUP {} \ 470 | CONFIG.PCW_MIO_42_DIRECTION {} \ 472 | CONFIG.PCW_MIO_42_PULLUP {} \ 474 | CONFIG.PCW_MIO_43_DIRECTION {} \ 476 | CONFIG.PCW_MIO_43_PULLUP {} \ 478 | CONFIG.PCW_MIO_44_DIRECTION {} \ 480 | CONFIG.PCW_MIO_44_PULLUP {} \ 482 | CONFIG.PCW_MIO_45_DIRECTION {} \ 484 | CONFIG.PCW_MIO_45_PULLUP {} \ 486 | CONFIG.PCW_MIO_46_DIRECTION {} \ 488 | CONFIG.PCW_MIO_46_PULLUP {} \ 490 | CONFIG.PCW_MIO_47_DIRECTION {} \ 492 | CONFIG.PCW_MIO_47_PULLUP {} \ 494 | CONFIG.PCW_MIO_48_DIRECTION {} \ 496 | CONFIG.PCW_MIO_48_PULLUP {} \ 498 | CONFIG.PCW_MIO_49_DIRECTION {} \ 500 | CONFIG.PCW_MIO_49_PULLUP {} \ 502 | CONFIG.PCW_MIO_4_DIRECTION {} \ 504 | CONFIG.PCW_MIO_4_PULLUP {} \ 506 | CONFIG.PCW_MIO_50_DIRECTION {} \ 508 | CONFIG.PCW_MIO_50_PULLUP {} \ 510 | CONFIG.PCW_MIO_51_DIRECTION {} \ 512 | CONFIG.PCW_MIO_51_PULLUP {} \ 514 | CONFIG.PCW_MIO_52_DIRECTION {} \ 516 | CONFIG.PCW_MIO_52_PULLUP {} \ 518 | CONFIG.PCW_MIO_53_DIRECTION {} \ 520 | CONFIG.PCW_MIO_53_PULLUP {} \ 522 | CONFIG.PCW_MIO_5_DIRECTION {} \ 524 | CONFIG.PCW_MIO_5_PULLUP {} \ 526 | CONFIG.PCW_MIO_6_DIRECTION {} \ 528 | CONFIG.PCW_MIO_6_PULLUP {} \ 530 | CONFIG.PCW_MIO_7_DIRECTION {} \ 532 | CONFIG.PCW_MIO_7_PULLUP {} \ 534 | CONFIG.PCW_MIO_8_DIRECTION {} \ 536 | CONFIG.PCW_MIO_8_PULLUP {} \ 538 | CONFIG.PCW_MIO_9_DIRECTION {} \ 540 | CONFIG.PCW_MIO_9_PULLUP {} \ 542 | CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \ 543 | CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \ 544 | CONFIG.PCW_NAND_CYCLES_T_AR {1} \ 545 | CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ 546 | CONFIG.PCW_NAND_CYCLES_T_RC {11} \ 547 | CONFIG.PCW_NAND_CYCLES_T_REA {1} \ 548 | CONFIG.PCW_NAND_CYCLES_T_RR {1} \ 549 | CONFIG.PCW_NAND_CYCLES_T_WC {11} \ 550 | CONFIG.PCW_NAND_CYCLES_T_WP {1} \ 551 | CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ 552 | CONFIG.PCW_NAND_GRP_D8_IO {} \ 554 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 555 | CONFIG.PCW_NOR_CS0_T_CEOE {1} \ 556 | CONFIG.PCW_NOR_CS0_T_PC {1} \ 557 | CONFIG.PCW_NOR_CS0_T_RC {11} \ 558 | CONFIG.PCW_NOR_CS0_T_TR {1} \ 559 | CONFIG.PCW_NOR_CS0_T_WC {11} \ 560 | CONFIG.PCW_NOR_CS0_T_WP {1} \ 561 | CONFIG.PCW_NOR_CS0_WE_TIME {0} \ 562 | CONFIG.PCW_NOR_CS1_T_CEOE {1} \ 563 | CONFIG.PCW_NOR_CS1_T_PC {1} \ 564 | CONFIG.PCW_NOR_CS1_T_RC {11} \ 565 | CONFIG.PCW_NOR_CS1_T_TR {1} \ 566 | CONFIG.PCW_NOR_CS1_T_WC {11} \ 567 | CONFIG.PCW_NOR_CS1_T_WP {1} \ 568 | CONFIG.PCW_NOR_CS1_WE_TIME {0} \ 569 | CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ 570 | CONFIG.PCW_NOR_GRP_A25_IO {} \ 573 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 574 | CONFIG.PCW_NOR_GRP_CS1_IO {} \ 577 | CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ 578 | CONFIG.PCW_NOR_GRP_SRAM_CS1_IO {} \ 581 | CONFIG.PCW_NOR_NOR_IO {} \ 611 | CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ 612 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 613 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 3.3V} \ 614 | CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \ 615 | CONFIG.PCW_QSPI_GRP_FBCLK_IO {} \ 618 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ 619 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {} \ 622 | CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ 623 | CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ 624 | CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {0} \ 625 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ 626 | CONFIG.PCW_QSPI_QSPI_IO {} \ 629 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 630 | CONFIG.PCW_SD0_GRP_POW_IO {} \ 633 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0} \ 634 | CONFIG.PCW_SD0_SD0_IO {} \ 637 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 638 | CONFIG.PCW_SD1_GRP_POW_IO {} \ 641 | CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ 642 | CONFIG.PCW_SD1_SD1_IO {} \ 651 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 652 | CONFIG.PCW_SPI0_GRP_SS1_IO {} \ 655 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 656 | CONFIG.PCW_SPI0_SPI0_IO {} \ 659 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 660 | CONFIG.PCW_SPI1_GRP_SS1_IO {} \ 663 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 664 | CONFIG.PCW_SPI1_SPI1_IO {} \ 677 | CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \ 678 | CONFIG.PCW_TRACE_GRP_2BIT_IO {} \ 681 | CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \ 682 | CONFIG.PCW_TRACE_GRP_4BIT_IO {} \ 685 | CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \ 686 | CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \ 687 | CONFIG.PCW_TRACE_TRACE_IO {} \ 699 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 700 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ 701 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 702 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 703 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ 704 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 705 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 706 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ 707 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 708 | CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \ 709 | CONFIG.PCW_TTC1_TTC1_IO {} \ 714 | CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \ 715 | CONFIG.PCW_UART0_UART0_IO {} \ 719 | CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ 720 | CONFIG.PCW_UART1_UART1_IO {} \ 801 | CONFIG.PCW_USB0_USB0_IO {} \ 806 | CONFIG.PCW_USB1_USB1_IO {} \ 810 | CONFIG.PCW_USE_CROSS_TRIGGER {0} \ 811 | CONFIG.PCW_USE_S_AXI_GP0 {0} \ 812 | CONFIG.PCW_USE_S_AXI_GP1 {0} \ 813 | CONFIG.PCW_USE_S_AXI_HP0 {1} \ 814 | CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ 815 | CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ 816 | CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \ 817 | CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ 818 | CONFIG.PCW_WDT_WDT_IO {