├── CA.drawio ├── Lab1 ├── .gitignore ├── figures │ ├── 1.png │ └── CA.pdf ├── main.pdf ├── main.tex └── ref.bib ├── Lab2 ├── .gitignore ├── Lab2 │ ├── Lab2.cache │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── Lab2.hw │ │ └── Lab2.lpr │ ├── Lab2.ip_user_files │ │ └── README.txt │ ├── Lab2.srcs │ │ ├── sim_1 │ │ │ └── imports │ │ │ │ └── Simulation │ │ │ │ └── testBench.v │ │ └── sources_1 │ │ │ ├── imports │ │ │ └── SourceCode │ │ │ │ ├── ALU.v │ │ │ │ ├── BranchDecision.v │ │ │ │ ├── Cache │ │ │ │ ├── DataCache.v │ │ │ │ └── InstructionCache.v │ │ │ │ ├── ControllerDecoder.v │ │ │ │ ├── DataExtend.v │ │ │ │ ├── ExMemSegReg │ │ │ │ ├── AddrMem.v │ │ │ │ ├── CtrlMem.v │ │ │ │ ├── Reg2Mem.v │ │ │ │ └── Result.v │ │ │ │ ├── GeneralRegister.v │ │ │ │ ├── Hazard.v │ │ │ │ ├── IdExSegReg │ │ │ │ ├── AddrEx.v │ │ │ │ ├── BrTarget.v │ │ │ │ ├── CtrlEx.v │ │ │ │ ├── Op1.v │ │ │ │ ├── PcEx.v │ │ │ │ └── Reg2Ex.v │ │ │ │ ├── IfIdSegReg │ │ │ │ ├── IR.v │ │ │ │ └── PcId.v │ │ │ │ ├── ImmExtend.v │ │ │ │ ├── MemWbSegReg │ │ │ │ ├── AddrWb.v │ │ │ │ ├── CtrlWb.v │ │ │ │ └── WbData.v │ │ │ │ ├── NPCGenerator.v │ │ │ │ ├── PC.v │ │ │ │ ├── Parameters.v │ │ │ │ └── RV32ICore.v │ │ │ └── new │ │ │ ├── CSR_EX.v │ │ │ ├── CSR_Regfile.v │ │ │ └── Imm.v │ └── Lab2.xpr ├── Test │ ├── cache-dump │ │ ├── DataCacheContent.txt │ │ └── InstCacheContent.txt │ └── test-data │ │ ├── 1testAll.data │ │ ├── 1testAll.inst │ │ ├── 1testAll.txt │ │ ├── 2testAll.data │ │ ├── 2testAll.inst │ │ ├── 2testAll.txt │ │ ├── 3testAll.data │ │ ├── 3testAll.inst │ │ ├── 3testAll.txt │ │ ├── CSRtest.data │ │ ├── CSRtest.inst │ │ └── CSRtest.txt └── report │ ├── assets │ ├── image-20200508211758092.png │ └── image-20200508212232179.png │ └── report.md ├── Lab3 ├── .gitignore ├── ASM-Benchmark │ ├── generate_data │ │ ├── generate_mem_for_matmul.py │ │ ├── generate_mem_for_quicksort.py │ │ ├── matmul16.sv │ │ ├── matmul8.sv │ │ ├── qsort256.sv │ │ └── qsort512.sv │ └── generate_inst │ │ ├── MatMul16.S │ │ ├── MatMul16.v │ │ ├── MatMul8.S │ │ ├── MatMul8.v │ │ ├── MatMul_check.S │ │ ├── MatMul_check.v │ │ ├── QuickSort256.S │ │ ├── QuickSort256.v │ │ ├── QuickSort512.S │ │ ├── QuickSort512.v │ │ ├── QuickSort_check.S │ │ ├── QuickSort_check.v │ │ ├── asm2verilogrom.py │ │ ├── bht.S │ │ ├── bht.v │ │ ├── btb.S │ │ └── btb.v ├── Lab3-with-CPU │ ├── Lab3-with-CPU.cache │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── Lab3-with-CPU.hw │ │ └── Lab3-with-CPU.lpr │ ├── Lab3-with-CPU.ip_user_files │ │ └── README.txt │ ├── Lab3-with-CPU.runs │ │ └── .jobs │ │ │ └── vrs_config_1.xml │ ├── Lab3-with-CPU.srcs │ │ ├── sim_1 │ │ │ └── imports │ │ │ │ └── Lab3 │ │ │ │ └── cpu_tb.v │ │ └── sources_1 │ │ │ └── imports │ │ │ ├── CacheSrcCode │ │ │ ├── cache.sv │ │ │ ├── main_mem.sv │ │ │ └── mem.sv │ │ │ ├── SourceCode │ │ │ ├── ALU.v │ │ │ ├── BranchDecision.v │ │ │ ├── Cache │ │ │ │ └── InstructionCache.v │ │ │ ├── ControllerDecoder.v │ │ │ ├── DataExtend.v │ │ │ ├── ExMemSegReg │ │ │ │ ├── AddrMem.v │ │ │ │ ├── CtrlMem.v │ │ │ │ ├── Reg2Mem.v │ │ │ │ └── Result.v │ │ │ ├── GeneralRegister.v │ │ │ ├── Hazard.v │ │ │ ├── IdExSegReg │ │ │ │ ├── AddrEx.v │ │ │ │ ├── BrTarget.v │ │ │ │ ├── CtrlEx.v │ │ │ │ ├── Op1.v │ │ │ │ ├── PcEx.v │ │ │ │ └── Reg2Ex.v │ │ │ ├── IfIdSegReg │ │ │ │ ├── IR.v │ │ │ │ └── PcId.v │ │ │ ├── ImmExtend.v │ │ │ ├── MemWbSegReg │ │ │ │ ├── AddrWb.v │ │ │ │ ├── CtrlWb.v │ │ │ │ └── WbData.v │ │ │ ├── NPCGenerator.v │ │ │ ├── PC.v │ │ │ ├── Parameters.v │ │ │ └── RV32ICore.v │ │ │ └── new │ │ │ ├── CSR_EX.v │ │ │ ├── CSR_Regfile.v │ │ │ └── Imm.v │ └── Lab3-with-CPU.xpr ├── Lab3 │ ├── Lab3.cache │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── Lab3.hw │ │ └── Lab3.lpr │ ├── Lab3.ip_user_files │ │ └── README.txt │ ├── Lab3.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_11.xml │ │ │ ├── vrs_config_12.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_8.xml │ │ │ └── vrs_config_9.xml │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── cache.dcp │ │ │ ├── cache.tcl │ │ │ ├── cache.vds │ │ │ ├── cache_utilization_synth.pb │ │ │ ├── cache_utilization_synth.rpt │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── project.wdf │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.sh │ │ │ └── vivado.pb │ ├── Lab3.sim │ │ └── sim_1 │ │ │ └── behav │ │ │ └── xsim │ │ │ ├── cache_tb.tcl │ │ │ ├── cache_tb_behav.wdb │ │ │ ├── cache_tb_vlog.prj │ │ │ ├── compile.bat │ │ │ ├── elaborate.bat │ │ │ ├── glbl.v │ │ │ ├── simulate.bat │ │ │ ├── xelab.pb │ │ │ ├── xsim.dir │ │ │ ├── cache_tb_behav │ │ │ │ ├── Compile_Options.txt │ │ │ │ ├── TempBreakPointFile.txt │ │ │ │ ├── obj │ │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ │ ├── xsim_1.c │ │ │ │ │ └── xsim_1.win64.obj │ │ │ │ ├── webtalk │ │ │ │ │ ├── .xsim_webtallk.info │ │ │ │ │ ├── usage_statistics_ext_xsim.html │ │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ │ ├── usage_statistics_ext_xsim.xml │ │ │ │ │ └── xsim_webtalk.tcl │ │ │ │ ├── xsim.dbg │ │ │ │ ├── xsim.mem │ │ │ │ ├── xsim.reloc │ │ │ │ ├── xsim.rlx │ │ │ │ ├── xsim.rtti │ │ │ │ ├── xsim.svtype │ │ │ │ ├── xsim.type │ │ │ │ ├── xsim.xdbg │ │ │ │ └── xsimSettings.ini │ │ │ ├── xil_defaultlib │ │ │ │ ├── cache.sdb │ │ │ │ ├── cache_tb.sdb │ │ │ │ ├── glbl.sdb │ │ │ │ ├── main_mem.sdb │ │ │ │ ├── mem.sdb │ │ │ │ └── xil_defaultlib.rlx │ │ │ └── xsim.svtype │ │ │ ├── xsim.ini │ │ │ └── xvlog.pb │ ├── Lab3.srcs │ │ ├── sim_1 │ │ │ └── imports │ │ │ │ └── CacheSrcCode │ │ │ │ └── cache_tb.sv │ │ └── sources_1 │ │ │ └── imports │ │ │ └── CacheSrcCode │ │ │ ├── cache.sv │ │ │ ├── main_mem.sv │ │ │ └── mem.sv │ └── Lab3.xpr └── report │ └── report.md ├── Lab4 ├── ASM-Benchmark │ ├── generate_data │ │ ├── generate_mem_for_matmul.py │ │ ├── generate_mem_for_quicksort.py │ │ ├── matmul16.sv │ │ ├── matmul8.sv │ │ ├── qsort256.sv │ │ └── qsort512.sv │ └── generate_inst │ │ ├── MatMul16.S │ │ ├── MatMul16.v │ │ ├── MatMul8.S │ │ ├── MatMul8.v │ │ ├── MatMul_check.S │ │ ├── MatMul_check.v │ │ ├── QuickSort256.S │ │ ├── QuickSort256.v │ │ ├── QuickSort512.S │ │ ├── QuickSort512.v │ │ ├── QuickSort_check.S │ │ ├── QuickSort_check.v │ │ ├── asm2verilogrom.py │ │ ├── bht.S │ │ ├── bht.v │ │ ├── btb.S │ │ └── btb.v ├── Lab4 │ ├── Lab4.cache │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── webtalk_pa.xml │ │ │ └── xsim.wdf │ ├── Lab4.hw │ │ └── Lab4.lpr │ ├── Lab4.ip_user_files │ │ └── README.txt │ ├── Lab4.srcs │ │ ├── sim_1 │ │ │ └── imports │ │ │ │ └── USTC-ComputerArchitecture-2020S │ │ │ │ └── cpu_tb.v │ │ └── sources_1 │ │ │ ├── imports │ │ │ └── SourceCode │ │ │ │ ├── ALU.v │ │ │ │ ├── BranchDecision.v │ │ │ │ ├── CSR_EX.v │ │ │ │ ├── CSR_Regfile.v │ │ │ │ ├── Cache │ │ │ │ └── InstructionCache.v │ │ │ │ ├── ControllerDecoder.v │ │ │ │ ├── DataExtend.v │ │ │ │ ├── ExMemSegReg │ │ │ │ ├── AddrMem.v │ │ │ │ ├── CtrlMem.v │ │ │ │ ├── Reg2Mem.v │ │ │ │ └── Result.v │ │ │ │ ├── GeneralRegister.v │ │ │ │ ├── Hazard.v │ │ │ │ ├── IdExSegReg │ │ │ │ ├── AddrEx.v │ │ │ │ ├── BrTarget.v │ │ │ │ ├── CtrlEx.v │ │ │ │ ├── Op1.v │ │ │ │ ├── PcEx.v │ │ │ │ └── Reg2Ex.v │ │ │ │ ├── IfIdSegReg │ │ │ │ ├── IR.v │ │ │ │ └── PcId.v │ │ │ │ ├── Imm.v │ │ │ │ ├── ImmExtend.v │ │ │ │ ├── MemWbSegReg │ │ │ │ ├── AddrWb.v │ │ │ │ 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