├── README.md ├── libcpu ├── arm │ ├── common │ │ ├── div0.c │ │ ├── showmem.c │ │ └── backtrace.c │ └── arm926 │ │ ├── cache.h │ │ ├── cache_gcc.S │ │ ├── mmu.h │ │ ├── stack.c │ │ ├── context_gcc.s │ │ ├── cpuport.c │ │ ├── trap.c │ │ ├── start_gcc.s │ │ └── mmu.c └── SConscript ├── Drivers ├── board.c ├── board.h ├── nuc97x_conf.h ├── nuc97x_gpio.c ├── nuc97x_gpio.h ├── nuc97x_i2c.h ├── nuc97x_i2s.h ├── nuc97x_lcd.h ├── nuc97x_spi.h ├── nuc97x_sys.c ├── nuc97x_sys.h ├── nuc97x_uart.c ├── nuc97x_uart.h ├── nuc97x_etimer.c ├── nuc97x_etimer.h ├── nuc97x_timer.c ├── nuc97x_timer.h ├── nuc97x_ethernet.h ├── nuc97x_interrupt.c ├── nuc97x_interrupt.h └── SConscript ├── Applications ├── task_blink.c ├── tcpserver.c ├── SConscript └── main.c ├── components ├── emWin │ ├── README.md │ ├── emWin_Demo │ │ └── README.md │ ├── emWin_Config │ │ └── README.md │ ├── emWin_header │ │ └── README.md │ └── emWin_library │ │ └── README.md └── SConscript ├── Platform ├── rt_low_level_init.c ├── SConscript └── rt_low_level_gcc.inc ├── SConscript ├── KConfig ├── Makefile ├── SConstruct ├── rtconfig.py ├── nuc970_ram.ld ├── .config └── rtconfig.h /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/README.md -------------------------------------------------------------------------------- /libcpu/arm/common/div0.c: -------------------------------------------------------------------------------- 1 | void __div0 (void) 2 | { 3 | while (1) ; 4 | } 5 | -------------------------------------------------------------------------------- /Drivers/board.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/board.c -------------------------------------------------------------------------------- /Drivers/board.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/board.h -------------------------------------------------------------------------------- /Drivers/nuc97x_conf.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_conf.h -------------------------------------------------------------------------------- /Drivers/nuc97x_gpio.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_gpio.c -------------------------------------------------------------------------------- /Drivers/nuc97x_gpio.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_gpio.h -------------------------------------------------------------------------------- /Drivers/nuc97x_i2c.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_i2c.h -------------------------------------------------------------------------------- /Drivers/nuc97x_i2s.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_i2s.h -------------------------------------------------------------------------------- /Drivers/nuc97x_lcd.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_lcd.h -------------------------------------------------------------------------------- /Drivers/nuc97x_spi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_spi.h -------------------------------------------------------------------------------- /Drivers/nuc97x_sys.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_sys.c -------------------------------------------------------------------------------- /Drivers/nuc97x_sys.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_sys.h -------------------------------------------------------------------------------- /Drivers/nuc97x_uart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_uart.c -------------------------------------------------------------------------------- /Drivers/nuc97x_uart.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_uart.h -------------------------------------------------------------------------------- /Drivers/nuc97x_etimer.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_etimer.c -------------------------------------------------------------------------------- /Drivers/nuc97x_etimer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_etimer.h -------------------------------------------------------------------------------- /Drivers/nuc97x_timer.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_timer.c -------------------------------------------------------------------------------- /Drivers/nuc97x_timer.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_timer.h -------------------------------------------------------------------------------- /Applications/task_blink.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Applications/task_blink.c -------------------------------------------------------------------------------- /Applications/tcpserver.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Applications/tcpserver.c -------------------------------------------------------------------------------- /Drivers/nuc97x_ethernet.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_ethernet.h -------------------------------------------------------------------------------- /Drivers/nuc97x_interrupt.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_interrupt.c -------------------------------------------------------------------------------- /Drivers/nuc97x_interrupt.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Drivers/nuc97x_interrupt.h -------------------------------------------------------------------------------- /components/emWin/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/components/emWin/README.md -------------------------------------------------------------------------------- /libcpu/arm/arm926/cache.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/libcpu/arm/arm926/cache.h -------------------------------------------------------------------------------- /Platform/rt_low_level_init.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/Platform/rt_low_level_init.c -------------------------------------------------------------------------------- /libcpu/arm/arm926/cache_gcc.S: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/libcpu/arm/arm926/cache_gcc.S -------------------------------------------------------------------------------- /components/emWin/emWin_Demo/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/components/emWin/emWin_Demo/README.md -------------------------------------------------------------------------------- /components/emWin/emWin_Config/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/components/emWin/emWin_Config/README.md -------------------------------------------------------------------------------- /components/emWin/emWin_header/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/components/emWin/emWin_header/README.md -------------------------------------------------------------------------------- /components/emWin/emWin_library/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/yygg/nuc972_rtthread/HEAD/components/emWin/emWin_library/README.md -------------------------------------------------------------------------------- /Platform/SConscript: -------------------------------------------------------------------------------- 1 | Import('RTT_ROOT') 2 | Import('rtconfig') 3 | from building import * 4 | 5 | cwd = GetCurrentDir() 6 | src = Glob('*.c') + Glob('*.cpp') 7 | CPPPATH = cwd 8 | 9 | group = DefineGroup('Platform', src, depend = [''], CPPPATH = CPPPATH) 10 | 11 | Return('group') 12 | -------------------------------------------------------------------------------- /Applications/SConscript: -------------------------------------------------------------------------------- 1 | from building import * 2 | 3 | cwd = GetCurrentDir() 4 | src = Glob('*.c') + Glob('*.cpp') 5 | 6 | if not GetDepend('RT_USING_LWIP'): 7 | SrcRemove(src,'tcpserver.c') 8 | 9 | CPPPATH = [cwd, str(Dir('#'))] 10 | 11 | group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) 12 | 13 | Return('group') 14 | -------------------------------------------------------------------------------- /Drivers/SConscript: -------------------------------------------------------------------------------- 1 | from building import * 2 | 3 | cwd = GetCurrentDir() 4 | src = Glob('*.c') + Glob('*.cpp') 5 | 6 | if not GetDepend('RT_USING_LWIP'): 7 | SrcRemove(src,'nuc97x_ethernet.c') 8 | 9 | 10 | CPPPATH = [cwd, str(Dir('#'))] 11 | 12 | group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) 13 | 14 | Return('group') 15 | -------------------------------------------------------------------------------- /components/SConscript: -------------------------------------------------------------------------------- 1 | import os 2 | from building import * 3 | 4 | cwd = GetCurrentDir() 5 | objs = [] 6 | list = os.listdir(cwd) 7 | 8 | for d in list: 9 | path = os.path.join(cwd, d) 10 | if os.path.isfile(os.path.join(path, 'SConscript')): 11 | objs = objs + SConscript(os.path.join(d, 'SConscript')) 12 | 13 | Return('objs') 14 | -------------------------------------------------------------------------------- /SConscript: -------------------------------------------------------------------------------- 1 | # for module compiling 2 | import os 3 | from building import * 4 | 5 | cwd = GetCurrentDir() 6 | objs = [] 7 | list = os.listdir(cwd) 8 | 9 | for d in list: 10 | path = os.path.join(cwd, d) 11 | if os.path.isfile(os.path.join(path, 'SConscript')): 12 | objs = objs + SConscript(os.path.join(d, 'SConscript')) 13 | 14 | Return('objs') 15 | -------------------------------------------------------------------------------- /KConfig: -------------------------------------------------------------------------------- 1 | mainmenu "RT-Thread Configuration" 2 | 3 | config $BSP_DIR 4 | string 5 | option env="BSP_ROOT" 6 | default "." 7 | 8 | config $RTT_DIR 9 | string 10 | option env="RTT_ROOT" 11 | default "rt-thread" 12 | 13 | config $PKGS_DIR 14 | string 15 | option env="PKGS_ROOT" 16 | default "packages" 17 | 18 | source "$RTT_DIR/KConfig" 19 | source "$PKGS_DIR/KConfig" 20 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | export RTT_EXEC_PATH=E:\embTools\arm-2014.05\bin 2 | #export RTT_ROOT=E:\embTools\rt-thread-v2.1.x 3 | #export RTT_ROOT=E:\embTools\rt-thread-fork 4 | 5 | scons:=python ${SCONS}\scons.py 6 | 7 | all: 8 | @$(scons) -j4 9 | 10 | copy: 11 | @$(scons) --copy -s 12 | 13 | clean: 14 | @$(scons) -j4 -c 15 | 16 | buildlib: 17 | @$(scons) --buildlib=SPIFFS 18 | cleanlib: 19 | @$(scons) --cleanlib 20 | -------------------------------------------------------------------------------- /Applications/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : main.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, RT-Thread Development Team 5 | * 6 | * The license and distribution terms for this file may be 7 | * found in the file LICENSE in this distribution or at 8 | * http://www.rt-thread.org/license/LICENSE 9 | * 10 | * Change Logs: 11 | * Date Author Notes 12 | */ 13 | 14 | #include 15 | 16 | #include 17 | 18 | #include 19 | #include 20 | #include 21 | 22 | 23 | 24 | int main(void *parameter) 25 | { 26 | printf("Hello RT-Thread !!!\n"); 27 | #ifdef RT_USING_EMWIN 28 | { 29 | extern int gui_task_start(void); 30 | gui_task_start(); 31 | } 32 | #endif 33 | return 0; 34 | } 35 | 36 | 37 | /*@}*/ 38 | -------------------------------------------------------------------------------- /libcpu/arm/common/showmem.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : showmem.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team 5 | * 6 | * The license and distribution terms for this file may be 7 | * found in the file LICENSE in this distribution or at 8 | * http://openlab.rt-thread.com/license/LICENSE 9 | * 10 | * Change Logs: 11 | * Date Author Notes 12 | * 2008-07-29 Bernard first version from QiuYi implementation 13 | */ 14 | 15 | #include 16 | 17 | void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) 18 | { 19 | int i = 0, j =0; 20 | 21 | RT_ASSERT(addr); 22 | 23 | addr = addr & ~0xF; 24 | size = 4*((size + 3)/4); 25 | 26 | while(i < size) 27 | { 28 | rt_kprintf("0x%08x: ", addr ); 29 | 30 | for(j=0; j<4; j++) 31 | { 32 | rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); 33 | 34 | addr += 4; 35 | i++; 36 | } 37 | 38 | rt_kprintf("\n"); 39 | } 40 | 41 | return; 42 | } 43 | -------------------------------------------------------------------------------- /libcpu/SConscript: -------------------------------------------------------------------------------- 1 | Import('RTT_ROOT') 2 | Import('rtconfig') 3 | from building import * 4 | 5 | cwd = GetCurrentDir() 6 | comm = rtconfig.ARCH + '/common' 7 | path = rtconfig.ARCH + '/' + rtconfig.CPU 8 | 9 | # The set of source files associated with this SConscript file. 10 | if rtconfig.PLATFORM == 'armcc': 11 | src = Glob(path + '/*.c') + Glob(path + '/*_rvds.S') + Glob(comm + '/*.c') 12 | 13 | if rtconfig.PLATFORM == 'gcc': 14 | src = Glob(path + '/*.c') + Glob(path + '/*_gcc.S') + Glob(comm + '/*.c') + Glob(path + '/*_init.S') 15 | 16 | if rtconfig.PLATFORM == 'iar': 17 | src = Glob(path + '/*.c') + Glob(path + '/*_iar.S') + Glob(comm + '/*.c') 18 | 19 | if rtconfig.PLATFORM == 'cl': 20 | src = Glob(path + '/*.c') 21 | 22 | if rtconfig.PLATFORM == 'mingw': 23 | src = Glob(path + '/*.c') 24 | 25 | CPPPATH = [cwd + '/' + rtconfig.ARCH + '/' + rtconfig.CPU, cwd + '/' + rtconfig.ARCH + '/common'] 26 | group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH) 27 | 28 | Return('group') 29 | -------------------------------------------------------------------------------- /SConstruct: -------------------------------------------------------------------------------- 1 | import os 2 | import sys 3 | import rtconfig 4 | 5 | if os.getenv('RTT_ROOT'): 6 | RTT_ROOT = os.getenv('RTT_ROOT') 7 | else: 8 | RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread') 9 | 10 | sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] 11 | from building import * 12 | 13 | TARGET = 'rtthread-nuc970.' + rtconfig.TARGET_EXT 14 | 15 | env = Environment(tools = ['mingw'], 16 | AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, 17 | CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, 18 | CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, 19 | AR = rtconfig.AR, ARFLAGS = '-rc', 20 | LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) 21 | env.PrependENVPath('PATH', rtconfig.EXEC_PATH) 22 | 23 | # add --start-group and --end-group for GNU GCC 24 | if rtconfig.PLATFORM == 'gcc': 25 | env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group' 26 | 27 | Export('RTT_ROOT') 28 | Export('rtconfig') 29 | 30 | # prepare building environment 31 | objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True) 32 | 33 | # make a building 34 | DoBuilding(TARGET, objs) 35 | -------------------------------------------------------------------------------- /Platform/rt_low_level_gcc.inc: -------------------------------------------------------------------------------- 1 | /* 2 | * File : rt_low_level_gcc.inc 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | * 2015-04-14 ArdaFu first version 23 | */ 24 | 25 | /*--------- Stack size of CPU modes ------------------------------------------*/ 26 | .equ UND_STK_SIZE, 2048 27 | .equ SVC_STK_SIZE, 4096 28 | .equ ABT_STK_SIZE, 2048 29 | .equ IRQ_STK_SIZE, 4096 30 | .equ FIQ_STK_SIZE, 4096 31 | .equ SYS_STK_SIZE, 2048 32 | -------------------------------------------------------------------------------- /libcpu/arm/common/backtrace.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : backtrace.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team 5 | * 6 | * The license and distribution terms for this file may be 7 | * found in the file LICENSE in this distribution or at 8 | * http://openlab.rt-thread.com/license/LICENSE 9 | * 10 | * Change Logs: 11 | * Date Author Notes 12 | * 2008-07-29 Bernard first version from QiuYi implementation 13 | */ 14 | 15 | #include 16 | 17 | #ifdef __GNUC__ 18 | /* 19 | -->High Address,Stack Top 20 | PC<-----| 21 | LR | 22 | IP | 23 | FP | 24 | ...... | 25 | PC<-| | 26 | LR | | 27 | IP | | 28 | FP---|-- | 29 | ...... | 30 | PC | 31 | LR | 32 | IP | 33 | FP--- 34 | -->Low Address,Stack Bottom 35 | */ 36 | void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) 37 | { 38 | rt_uint32_t i, pc, func_entry; 39 | 40 | pc = *fp; 41 | rt_kprintf("[0x%x]\n", pc-0xC); 42 | 43 | for(i=0; i<10; i++) 44 | { 45 | fp = (rt_uint32_t *)*(fp - 3); 46 | pc = *fp ; 47 | 48 | func_entry = pc - 0xC; 49 | 50 | if(func_entry <= 0x30000000) break; 51 | 52 | if((func_entry == thread_entry)) 53 | { 54 | rt_kprintf("EntryPoint:0x%x\n", func_entry); 55 | 56 | break; 57 | } 58 | 59 | rt_kprintf("[0x%x]\n", func_entry); 60 | } 61 | } 62 | #else 63 | void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) 64 | { 65 | /* old compiler implementation */ 66 | } 67 | #endif 68 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/mmu.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File : mmu.h 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, RT-Thread Development Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | */ 23 | 24 | #ifndef __MMU_H__ 25 | #define __MMU_H__ 26 | 27 | #include 28 | 29 | #define CACHE_LINE_SIZE 32 30 | 31 | #define DESC_SEC (0x2|(1<<4)) 32 | #define CB (3<<2) //cache_on, write_back 33 | #define CNB (2<<2) //cache_on, write_through 34 | #define NCB (1<<2) //cache_off,WR_BUF on 35 | #define NCNB (0<<2) //cache_off,WR_BUF off 36 | #define AP_RW (3<<10) //supervisor=RW, user=RW 37 | #define AP_RO (2<<10) //supervisor=RW, user=RO 38 | 39 | #define DOMAIN_FAULT (0x0) 40 | #define DOMAIN_CHK (0x1) 41 | #define DOMAIN_NOTCHK (0x3) 42 | #define DOMAIN0 (0x0<<5) 43 | #define DOMAIN1 (0x1<<5) 44 | 45 | #define DOMAIN0_ATTR (DOMAIN_CHK<<0) 46 | #define DOMAIN1_ATTR (DOMAIN_FAULT<<2) 47 | 48 | #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ 49 | #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ 50 | #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 51 | #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 52 | 53 | struct mem_desc 54 | { 55 | rt_uint32_t vaddr_start; 56 | rt_uint32_t vaddr_end; 57 | rt_uint32_t paddr_start; 58 | rt_uint32_t attr; 59 | }; 60 | 61 | void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); 62 | 63 | #endif 64 | -------------------------------------------------------------------------------- /rtconfig.py: -------------------------------------------------------------------------------- 1 | import os 2 | 3 | # toolchains options 4 | ARCH ='arm' 5 | CPU ='arm926' 6 | CROSS_TOOL ='gcc' 7 | 8 | TextBase = '0x00000000' 9 | 10 | if os.getenv('RTT_CC'): 11 | CROSS_TOOL = os.getenv('RTT_CC') 12 | 13 | if CROSS_TOOL == 'gcc': 14 | PLATFORM = 'gcc' 15 | EXEC_PATH = r'E:/embStudio/tools/arm-2015.q3/bin' 16 | 17 | if os.getenv('RTT_EXEC_PATH'): 18 | EXEC_PATH = os.getenv('RTT_EXEC_PATH') 19 | elif CROSS_TOOL == 'keil': 20 | PLATFORM = 'armcc' 21 | EXEC_PATH = r'd:/Keil' 22 | else: 23 | print ('================ERROR============================') 24 | print ('unknown platform!') 25 | print ('=================================================') 26 | exit(0) 27 | 28 | BUILD = 'debug' 29 | MAP_FILE = 'rtthread_nuc970.map' 30 | LINK_FILE = 'nuc970_ram' 31 | TARGET_NAME = 'rtthread.bin' 32 | 33 | if PLATFORM == 'gcc': 34 | # toolchains 35 | PREFIX = 'arm-none-eabi-' 36 | CC = PREFIX + 'gcc' 37 | CXX = PREFIX + 'g++' 38 | AS = PREFIX + 'gcc' 39 | AR = PREFIX + 'ar' 40 | LINK = PREFIX + 'g++' 41 | TARGET_EXT = 'elf' 42 | SIZE = PREFIX + 'size' 43 | OBJDUMP = PREFIX + 'objdump' 44 | OBJCPY = PREFIX + 'objcopy' 45 | 46 | DEVICE = ' -mcpu=arm926ej-s' 47 | #CFLAGS = DEVICE 48 | CFLAGS = DEVICE + ' -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fno-omit-frame-pointer' 49 | AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' 50 | AFLAGS += ' -IPlatform' 51 | LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_nuc970.map,-cref,-u,Reset_Handler -T nuc970_ram.ld' + ' -Ttext ' + TextBase 52 | 53 | if BUILD == 'debug': 54 | CFLAGS += ' -O0 -gdwarf-2' 55 | AFLAGS += ' -gdwarf-2' 56 | else: 57 | CFLAGS += ' -O2' 58 | 59 | CXXFLAGS = CFLAGS 60 | 61 | POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' 62 | #------- Keil settings --------------------------------------------------------- 63 | elif PLATFORM == 'armcc': 64 | # toolchains 65 | CC = 'armcc' 66 | AS = 'armasm' 67 | AR = 'armar' 68 | LINK = 'armlink' 69 | TARGET_EXT = 'elf' 70 | EXEC_PATH += '/arm/armcc/bin/' 71 | 72 | DEVICE = ' --cpu ARM926EJ-S' 73 | CFLAGS = DEVICE + ' --c99 --apcs=interwork --diag_suppress=870' 74 | AFLAGS = DEVICE + ' -Iplatform' 75 | LFLAGS = DEVICE + ' --strict' 76 | LFLAGS += ' --info sizes --info totals --info unused --info veneers' 77 | LFLAGS += ' --list ' + MAP_FILE 78 | LFLAGS += ' --scatter ' + LINK_FILE + '.scat' 79 | 80 | if BUILD == 'debug': 81 | CFLAGS += ' -g -O0' 82 | AFLAGS += ' -g' 83 | else: 84 | CFLAGS += ' -O2' 85 | 86 | POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n' 87 | POST_ACTION += 'fromelf -z $TARGET\n' 88 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/stack.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : stack.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, RT-Thread Development Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | * 2011-01-13 weety copy from mini2440 23 | */ 24 | #include 25 | 26 | /*****************************/ 27 | /* CPU Mode */ 28 | /*****************************/ 29 | #define USERMODE 0x10 30 | #define FIQMODE 0x11 31 | #define IRQMODE 0x12 32 | #define SVCMODE 0x13 33 | #define ABORTMODE 0x17 34 | #define UNDEFMODE 0x1b 35 | #define MODEMASK 0x1f 36 | #define NOINT 0xc0 37 | 38 | /** 39 | * This function will initialize thread stack 40 | * 41 | * @param tentry the entry of thread 42 | * @param parameter the parameter of entry 43 | * @param stack_addr the beginning stack address 44 | * @param texit the function will be called when thread exit 45 | * 46 | * @return stack address 47 | */ 48 | rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, 49 | rt_uint8_t *stack_addr, void *texit) 50 | { 51 | rt_uint32_t *stk; 52 | 53 | //stk = (rt_uint32_t*)stack_addr; 54 | stack_addr += sizeof(rt_uint32_t); 55 | stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); 56 | stk = (rt_uint32_t *)stack_addr; 57 | 58 | *(--stk) = (rt_uint32_t)tentry; /* entry point */ 59 | *(--stk) = (rt_uint32_t)texit; /* lr */ 60 | *(--stk) = 0xdeadbeef; /* r12 */ 61 | *(--stk) = 0xdeadbeef; /* r11 */ 62 | *(--stk) = 0xdeadbeef; /* r10 */ 63 | *(--stk) = 0xdeadbeef; /* r9 */ 64 | *(--stk) = 0xdeadbeef; /* r8 */ 65 | *(--stk) = 0xdeadbeef; /* r7 */ 66 | *(--stk) = 0xdeadbeef; /* r6 */ 67 | *(--stk) = 0xdeadbeef; /* r5 */ 68 | *(--stk) = 0xdeadbeef; /* r4 */ 69 | *(--stk) = 0xdeadbeef; /* r3 */ 70 | *(--stk) = 0xdeadbeef; /* r2 */ 71 | *(--stk) = 0xdeadbeef; /* r1 */ 72 | *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ 73 | /* cpsr */ 74 | if ((rt_uint32_t)tentry & 0x01) 75 | *(--stk) = SVCMODE | 0x20; /* thumb mode */ 76 | else 77 | *(--stk) = SVCMODE; /* arm mode */ 78 | 79 | /* return task's current stack address */ 80 | return (rt_uint8_t *)stk; 81 | } 82 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/context_gcc.s: -------------------------------------------------------------------------------- 1 | ;/* 2 | ; * File : context_iar.S 3 | ; * This file is part of RT-Thread RTOS 4 | ; * COPYRIGHT (C) 2006, RT-Thread Development Team 5 | ; * 6 | ; * This program is free software; you can redistribute it and/or modify 7 | ; * it under the terms of the GNU General Public License as published by 8 | ; * the Free Software Foundation; either version 2 of the License, or 9 | ; * (at your option) any later version. 10 | ; * 11 | ; * This program is distributed in the hope that it will be useful, 12 | ; * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | ; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | ; * GNU General Public License for more details. 15 | ; * 16 | ; * You should have received a copy of the GNU General Public License along 17 | ; * with this program; if not, write to the Free Software Foundation, Inc., 18 | ; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | ; * 20 | ; * Change Logs: 21 | ; * Date Author Notes 22 | ; * 2011-08-14 weety copy from mini2440 23 | ; */ 24 | 25 | #define NOINT 0xC0 26 | 27 | ;/* 28 | ; * rt_base_t rt_hw_interrupt_disable(); 29 | ; */ 30 | .globl rt_hw_interrupt_disable 31 | rt_hw_interrupt_disable: 32 | MRS R0, CPSR 33 | ORR R1, R0, #NOINT 34 | MSR CPSR_c, R1 35 | BX LR 36 | 37 | /* 38 | * void rt_hw_interrupt_enable(rt_base_t level); 39 | */ 40 | .globl rt_hw_interrupt_enable 41 | rt_hw_interrupt_enable: 42 | MSR CPSR, R0 43 | BX LR 44 | 45 | /* 46 | * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); 47 | * r0 --> from 48 | * r1 --> to 49 | */ 50 | .globl rt_hw_context_switch 51 | rt_hw_context_switch: 52 | STMFD SP!, {LR} @; push pc (lr should be pushed in place of pc) 53 | STMFD SP!, {R0-R12, LR} @; push lr & register file 54 | MRS R4, CPSR 55 | STMFD SP!, {R4} @; push cpsr 56 | STR SP, [R0] @; store sp in preempted tasks tcb 57 | LDR SP, [R1] @; get new task stack pointer 58 | LDMFD SP!, {R4} @; pop new task spsr 59 | MSR SPSR_cxsf, R4 60 | LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc 61 | 62 | /* 63 | * void rt_hw_context_switch_to(rt_uint32 to); 64 | * r0 --> to 65 | */ 66 | .globl rt_hw_context_switch_to 67 | rt_hw_context_switch_to: 68 | LDR SP, [R0] @; get new task stack pointer 69 | LDMFD SP!, {R4} @; pop new task cpsr 70 | MSR SPSR_cxsf, R4 71 | LDMFD SP!, {R0-R12, LR, PC}^ @; pop new task r0-r12, lr & pc 72 | 73 | /* 74 | * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); 75 | */ 76 | .globl rt_thread_switch_interrupt_flag 77 | .globl rt_interrupt_from_thread 78 | .globl rt_interrupt_to_thread 79 | .globl rt_hw_context_switch_interrupt 80 | rt_hw_context_switch_interrupt: 81 | LDR R2, =rt_thread_switch_interrupt_flag 82 | LDR R3, [R2] 83 | CMP R3, #1 84 | BEQ _reswitch 85 | MOV R3, #1 @; set flag to 1 86 | STR R3, [R2] 87 | LDR R2, =rt_interrupt_from_thread @; set rt_interrupt_from_thread 88 | STR R0, [R2] 89 | _reswitch: 90 | LDR R2, =rt_interrupt_to_thread @; set rt_interrupt_to_thread 91 | STR R1, [R2] 92 | BX LR 93 | -------------------------------------------------------------------------------- /nuc970_ram.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 2 | OUTPUT_ARCH(arm) 3 | ENTRY(start) 4 | 5 | /* Program Entry, set to mark it as "used" and avoid gc */ 6 | MEMORY 7 | { 8 | SDRAM (rx) : ORIGIN = 0x00000000, LENGTH = 0x03C00000 /* base code section 60M */ 9 | NETRAM (rx) : ORIGIN = 0x03C00000, LENGTH = 0x00400000 /* base code section 4M */ 10 | } 11 | SECTIONS 12 | { 13 | . = ALIGN(4); 14 | .text : 15 | { 16 | *(.init) 17 | *(.text) 18 | *(.gnu.linkonce.t*) 19 | 20 | /* section information for finsh shell */ 21 | . = ALIGN(4); 22 | __fsymtab_start = .; 23 | KEEP(*(FSymTab)) 24 | __fsymtab_end = .; 25 | . = ALIGN(4); 26 | __vsymtab_start = .; 27 | KEEP(*(VSymTab)) 28 | __vsymtab_end = .; 29 | . = ALIGN(4); 30 | 31 | /* section information for modules */ 32 | . = ALIGN(4); 33 | __rtmsymtab_start = .; 34 | KEEP(*(RTMSymTab)) 35 | __rtmsymtab_end = .; 36 | 37 | /* section information for initialization */ 38 | . = ALIGN(4); 39 | __rt_init_start = .; 40 | KEEP(*(SORT(.rti_fn*))) 41 | __rt_init_end = .; 42 | } > SDRAM=0 43 | 44 | . = ALIGN(4); 45 | .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }> SDRAM 46 | 47 | . = ALIGN(4); 48 | .ctors : 49 | { 50 | PROVIDE(__ctors_start__ = .); 51 | KEEP(*(SORT(.ctors.*))) 52 | KEEP(*(.ctors)) 53 | PROVIDE(__ctors_end__ = .); 54 | }> SDRAM 55 | 56 | .dtors : 57 | { 58 | PROVIDE(__dtors_start__ = .); 59 | KEEP(*(SORT(.dtors.*))) 60 | KEEP(*(.dtors)) 61 | PROVIDE(__dtors_end__ = .); 62 | }> SDRAM 63 | 64 | . = ALIGN(4); 65 | .data : 66 | { 67 | *(.data) 68 | *(.data.*) 69 | *(.gnu.linkonce.d*) 70 | }> SDRAM 71 | 72 | . = ALIGN(4); 73 | .nobss : { *(.nobss) }> SDRAM 74 | 75 | . = ALIGN(4); 76 | __bss_start__ = .; 77 | .bss : 78 | { 79 | *(.bss) 80 | *(.bss.*) 81 | }> SDRAM 82 | __bss_end__ = .; 83 | 84 | /* stabs debugging sections. */ 85 | .stab 0 : { *(.stab) } 86 | .stabstr 0 : { *(.stabstr) } 87 | .stab.excl 0 : { *(.stab.excl) } 88 | .stab.exclstr 0 : { *(.stab.exclstr) } 89 | .stab.index 0 : { *(.stab.index) } 90 | .stab.indexstr 0 : { *(.stab.indexstr) } 91 | .comment 0 : { *(.comment) } 92 | /* DWARF debug sections. 93 | * Symbols in the DWARF debugging sections are relative to the beginning 94 | * of the section so we begin them at 0. */ 95 | /* DWARF 1 */ 96 | .debug 0 : { *(.debug) } 97 | .line 0 : { *(.line) } 98 | /* GNU DWARF 1 extensions */ 99 | .debug_srcinfo 0 : { *(.debug_srcinfo) } 100 | .debug_sfnames 0 : { *(.debug_sfnames) } 101 | /* DWARF 1.1 and DWARF 2 */ 102 | .debug_aranges 0 : { *(.debug_aranges) } 103 | .debug_pubnames 0 : { *(.debug_pubnames) } 104 | /* DWARF 2 */ 105 | .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } 106 | .debug_abbrev 0 : { *(.debug_abbrev) } 107 | .debug_line 0 : { *(.debug_line) } 108 | .debug_frame 0 : { *(.debug_frame) } 109 | .debug_str 0 : { *(.debug_str) } 110 | .debug_loc 0 : { *(.debug_loc) } 111 | .debug_macinfo 0 : { *(.debug_macinfo) } 112 | /* SGI/MIPS DWARF 2 extensions */ 113 | .debug_weaknames 0 : { *(.debug_weaknames) } 114 | .debug_funcnames 0 : { *(.debug_funcnames) } 115 | .debug_typenames 0 : { *(.debug_typenames) } 116 | .debug_varnames 0 : { *(.debug_varnames) } 117 | 118 | _end = .; 119 | } 120 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/cpuport.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : cpu.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, RT-Thread Develop Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | * 2011-01-13 weety modified from mini2440 23 | * 2015-04-15 ArdaFu Add code for IAR 24 | */ 25 | 26 | #include 27 | #include 28 | 29 | #define ICACHE_MASK (rt_uint32_t)(1 << 12) 30 | #define DCACHE_MASK (rt_uint32_t)(1 << 2) 31 | 32 | RT_WEAK void machine_reset(void) 33 | { 34 | 35 | } 36 | RT_WEAK void machine_shutdown(void) 37 | { 38 | 39 | } 40 | 41 | #if defined(__GNUC__) || defined(__ICCARM__) 42 | rt_inline rt_uint32_t cp15_rd(void) 43 | { 44 | rt_uint32_t i; 45 | 46 | __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); 47 | return i; 48 | } 49 | 50 | rt_inline void cache_enable(rt_uint32_t bit) 51 | { 52 | __asm volatile(\ 53 | "mrc p15,0,r0,c1,c0,0\n\t" \ 54 | "orr r0,r0,%0\n\t" \ 55 | "mcr p15,0,r0,c1,c0,0" \ 56 | : \ 57 | :"r" (bit) \ 58 | :"memory"); 59 | } 60 | 61 | rt_inline void cache_disable(rt_uint32_t bit) 62 | { 63 | __asm volatile(\ 64 | "mrc p15,0,r0,c1,c0,0\n\t" \ 65 | "bic r0,r0,%0\n\t" \ 66 | "mcr p15,0,r0,c1,c0,0" \ 67 | : \ 68 | :"r" (bit) \ 69 | :"memory"); 70 | } 71 | #endif 72 | 73 | #if defined(__CC_ARM) 74 | rt_inline rt_uint32_t cp15_rd(void) 75 | { 76 | rt_uint32_t i; 77 | 78 | __asm volatile 79 | { 80 | mrc p15, 0, i, c1, c0, 0 81 | } 82 | 83 | return i; 84 | } 85 | 86 | rt_inline void cache_enable(rt_uint32_t bit) 87 | { 88 | rt_uint32_t value; 89 | 90 | __asm volatile 91 | { 92 | mrc p15, 0, value, c1, c0, 0 93 | orr value, value, bit 94 | mcr p15, 0, value, c1, c0, 0 95 | } 96 | } 97 | 98 | rt_inline void cache_disable(rt_uint32_t bit) 99 | { 100 | rt_uint32_t value; 101 | 102 | __asm volatile 103 | { 104 | mrc p15, 0, value, c1, c0, 0 105 | bic value, value, bit 106 | mcr p15, 0, value, c1, c0, 0 107 | } 108 | } 109 | #endif 110 | 111 | /** 112 | * enable I-Cache 113 | * 114 | */ 115 | void rt_hw_cpu_icache_enable() 116 | { 117 | cache_enable(ICACHE_MASK); 118 | } 119 | 120 | /** 121 | * disable I-Cache 122 | * 123 | */ 124 | void rt_hw_cpu_icache_disable() 125 | { 126 | cache_disable(ICACHE_MASK); 127 | } 128 | 129 | /** 130 | * return the status of I-Cache 131 | * 132 | */ 133 | rt_base_t rt_hw_cpu_icache_status() 134 | { 135 | return (cp15_rd() & ICACHE_MASK); 136 | } 137 | 138 | /** 139 | * enable D-Cache 140 | * 141 | */ 142 | void rt_hw_cpu_dcache_enable() 143 | { 144 | cache_enable(DCACHE_MASK); 145 | } 146 | 147 | /** 148 | * disable D-Cache 149 | * 150 | */ 151 | void rt_hw_cpu_dcache_disable() 152 | { 153 | cache_disable(DCACHE_MASK); 154 | } 155 | 156 | /** 157 | * return the status of D-Cache 158 | * 159 | */ 160 | rt_base_t rt_hw_cpu_dcache_status() 161 | { 162 | return (cp15_rd() & DCACHE_MASK); 163 | } 164 | 165 | /** 166 | * reset cpu by dog's time-out 167 | * 168 | */ 169 | 170 | void rt_hw_cpu_reset() 171 | { 172 | 173 | rt_kprintf("Restarting system...\n"); 174 | machine_reset(); 175 | 176 | while(1); /* loop forever and wait for reset to happen */ 177 | 178 | /* NEVER REACHED */ 179 | } 180 | 181 | /** 182 | * shutdown CPU 183 | * 184 | */ 185 | void rt_hw_cpu_shutdown() 186 | { 187 | rt_uint32_t level; 188 | rt_kprintf("shutdown...\n"); 189 | 190 | level = rt_hw_interrupt_disable(); 191 | machine_shutdown(); 192 | while (level) 193 | { 194 | RT_ASSERT(0); 195 | } 196 | } 197 | 198 | #ifdef RT_USING_CPU_FFS 199 | /** 200 | * This function finds the first bit set (beginning with the least significant bit) 201 | * in value and return the index of that bit. 202 | * 203 | * Bits are numbered starting at 1 (the least significant bit). A return value of 204 | * zero from any of these functions means that the argument was zero. 205 | * 206 | * @return return the index of the first bit set. If value is 0, then this function 207 | * shall return 0. 208 | */ 209 | #if defined(__CC_ARM) 210 | int __rt_ffs(int value) 211 | { 212 | register rt_uint32_t x; 213 | 214 | if (value == 0) 215 | return value; 216 | 217 | __asm 218 | { 219 | rsb x, value, #0 220 | and x, x, value 221 | clz x, x 222 | rsb x, x, #32 223 | } 224 | 225 | return x; 226 | } 227 | #elif defined(__GNUC__) || defined(__ICCARM__) 228 | int __rt_ffs(int value) 229 | { 230 | register rt_uint32_t x; 231 | 232 | if (value == 0) 233 | return value; 234 | 235 | __asm 236 | ( 237 | "rsb %[temp], %[val], #0\n" 238 | "and %[temp], %[temp], %[val]\n" 239 | "clz %[temp], %[temp]\n" 240 | "rsb %[temp], %[temp], #32\n" 241 | :[temp] "=r"(x) 242 | :[val] "r"(value) 243 | ); 244 | return x; 245 | } 246 | #endif 247 | 248 | #endif 249 | 250 | 251 | /*@}*/ 252 | -------------------------------------------------------------------------------- /.config: -------------------------------------------------------------------------------- 1 | # 2 | # Automatically generated file; DO NOT EDIT. 3 | # RT-Thread Configuration 4 | # 5 | 6 | # 7 | # RT-Thread Kernel 8 | # 9 | CONFIG_RT_NAME_MAX=8 10 | CONFIG_RT_ALIGN_SIZE=8 11 | CONFIG_RT_THREAD_PRIORITY_MAX=256 12 | CONFIG_RT_TICK_PER_SECOND=100 13 | CONFIG_RT_DEBUG=y 14 | CONFIG_RT_USING_OVERFLOW_CHECK=y 15 | CONFIG_RT_DEBUG_INIT=1 16 | CONFIG_RT_DEBUG_THREAD=y 17 | CONFIG_RT_USING_HOOK=y 18 | CONFIG_IDLE_THREAD_STACK_SIZE=512 19 | CONFIG_RT_USING_TIMER_SOFT=y 20 | CONFIG_RT_TIMER_THREAD_PRIO=4 21 | CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 22 | 23 | # 24 | # Inter-Thread communication 25 | # 26 | CONFIG_RT_USING_SEMAPHORE=y 27 | CONFIG_RT_USING_MUTEX=y 28 | CONFIG_RT_USING_EVENT=y 29 | CONFIG_RT_USING_MAILBOX=y 30 | CONFIG_RT_USING_MESSAGEQUEUE=y 31 | 32 | # 33 | # Memory Management 34 | # 35 | CONFIG_RT_USING_MEMPOOL=y 36 | CONFIG_RT_USING_MEMHEAP=y 37 | CONFIG_RT_USING_HEAP=y 38 | # CONFIG_RT_USING_SMALL_MEM is not set 39 | CONFIG_RT_USING_SLAB=y 40 | 41 | # 42 | # Kernel Device Object 43 | # 44 | CONFIG_RT_USING_DEVICE=y 45 | CONFIG_RT_USING_CONSOLE=y 46 | CONFIG_RT_CONSOLEBUF_SIZE=512 47 | CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" 48 | # CONFIG_RT_USING_MODULE is not set 49 | 50 | # 51 | # RT-Thread Components 52 | # 53 | CONFIG_RT_USING_COMPONENTS_INIT=y 54 | CONFIG_RT_USING_USER_MAIN=y 55 | 56 | # 57 | # C++ features 58 | # 59 | CONFIG_RT_USING_CPLUSPLUS=y 60 | 61 | # 62 | # Command shell 63 | # 64 | CONFIG_RT_USING_FINSH=y 65 | CONFIG_FINSH_USING_SYMTAB=y 66 | CONFIG_FINSH_USING_DESCRIPTION=y 67 | CONFIG_FINSH_THREAD_STACK_SIZE=4096 68 | # CONFIG_FINSH_USING_AUTH is not set 69 | CONFIG_FINSH_DEFAULT_PASSWORD="rtthread" 70 | CONFIG_FINSH_USING_MSH=y 71 | CONFIG_FINSH_USING_MSH_DEFAULT=y 72 | CONFIG_FINSH_USING_MSH_ONLY=y 73 | 74 | # 75 | # Device virtual file system 76 | # 77 | CONFIG_RT_USING_DFS=y 78 | CONFIG_DFS_USING_WORKDIR=y 79 | CONFIG_DFS_FILESYSTEMS_MAX=4 80 | CONFIG_DFS_FD_MAX=4 81 | CONFIG_RT_USING_DFS_ELMFAT=y 82 | CONFIG_RT_DFS_ELM_CODE_PAGE=437 83 | CONFIG_RT_DFS_ELM_WORD_ACCESS=y 84 | CONFIG_RT_DFS_ELM_USE_LFN_0=y 85 | # CONFIG_RT_DFS_ELM_USE_LFN_1 is not set 86 | # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set 87 | # CONFIG_RT_DFS_ELM_USE_LFN_3 is not set 88 | CONFIG_RT_DFS_ELM_USE_LFN=0 89 | CONFIG_RT_DFS_ELM_MAX_LFN=256 90 | CONFIG_RT_DFS_ELM_DRIVES=4 91 | CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 92 | # CONFIG_RT_DFS_ELM_USE_ERASE is not set 93 | CONFIG_RT_DFS_ELM_REENTRANT=y 94 | CONFIG_RT_USING_DFS_DEVFS=y 95 | # CONFIG_RT_USING_DFS_NET is not set 96 | # CONFIG_RT_USING_DFS_NFS is not set 97 | 98 | # 99 | # Network stack 100 | # 101 | 102 | # 103 | # light weight TCP/IP stack 104 | # 105 | CONFIG_RT_USING_LWIP=y 106 | # CONFIG_RT_USING_LWIP141 is not set 107 | # CONFIG_RT_USING_LWIP200 is not set 108 | CONFIG_RT_USING_LWIP202=y 109 | CONFIG_RT_LWIP_IGMP=y 110 | CONFIG_RT_LWIP_ICMP=y 111 | # CONFIG_RT_LWIP_SNMP is not set 112 | CONFIG_RT_LWIP_DNS=y 113 | CONFIG_RT_LWIP_DHCP=y 114 | CONFIG_IP_SOF_BROADCAST=1 115 | CONFIG_IP_SOF_BROADCAST_RECV=1 116 | CONFIG_LWIP_USING_DHCPD=y 117 | CONFIG_RT_LWIP_UDP=y 118 | CONFIG_RT_LWIP_TCP=y 119 | # CONFIG_RT_LWIP_RAW is not set 120 | # CONFIG_RT_LWIP_PPP is not set 121 | # CONFIG_RT_LWIP_PPPOE is not set 122 | # CONFIG_RT_LWIP_PPPOS is not set 123 | CONFIG_RT_LWIP_PBUF_NUM=64 124 | CONFIG_RT_LWIP_RAW_PCB_NUM=32 125 | CONFIG_RT_LWIP_UDP_PCB_NUM=16 126 | CONFIG_RT_LWIP_TCP_PCB_NUM=16 127 | CONFIG_RT_LWIP_TCP_SEG_NUM=40 128 | CONFIG_RT_LWIP_TCP_SND_BUF=32768 129 | CONFIG_RT_LWIP_TCP_WND=32768 130 | CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 131 | CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 132 | CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096 133 | CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 134 | CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 135 | CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 136 | # CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set 137 | CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 138 | CONFIG_SO_REUSE=1 139 | CONFIG_LWIP_SO_RCVTIMEO=1 140 | CONFIG_LWIP_SO_SNDTIMEO=1 141 | CONFIG_LWIP_SO_RCVBUF=1 142 | 143 | # 144 | # Modbus master and slave stack 145 | # 146 | CONFIG_RT_USING_MODBUS=y 147 | # CONFIG_RT_MODBUS_MASTER_RTU is not set 148 | CONFIG_RT_MODBUS_SLAVE_RTU=y 149 | CONFIG_RT_USING_NETUTILS=y 150 | 151 | # 152 | # Device Drivers 153 | # 154 | CONFIG_RT_USING_DEVICE_IPC=y 155 | CONFIG_RT_USING_SERIAL=y 156 | # CONFIG_RT_USING_CAN is not set 157 | # CONFIG_RT_USING_HWTIMER is not set 158 | CONFIG_RT_USING_I2C=y 159 | CONFIG_RT_USING_I2C_BITOPS=y 160 | CONFIG_RT_USING_PIN=y 161 | CONFIG_RT_USING_MTD_NOR=y 162 | CONFIG_RT_USING_MTD_NAND=y 163 | CONFIG_RT_MTD_NAND_DEBUG=y 164 | CONFIG_RT_USING_RTC=y 165 | CONFIG_RT_USING_SDIO=y 166 | CONFIG_RT_USING_SPI=y 167 | CONFIG_RT_USING_SFUD=y 168 | CONFIG_RT_SFUD_USING_SFDP=y 169 | CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y 170 | CONFIG_RT_SFUD_DEBUG=y 171 | CONFIG_RT_USING_W25QXX=y 172 | # CONFIG_RT_USING_GD is not set 173 | # CONFIG_RT_USING_ENC28J60 is not set 174 | # CONFIG_RT_USING_SPI_WIFI is not set 175 | CONFIG_RT_USING_WDT=y 176 | # CONFIG_RT_USING_USB_HOST is not set 177 | CONFIG_RT_USING_USB_DEVICE=y 178 | CONFIG_RT_USB_DEVICE_CDC=y 179 | CONFIG_RT_USB_DEVICE_MSTORAGE=y 180 | 181 | # 182 | # RT-Thread UI Engine 183 | # 184 | # CONFIG_RT_USING_GUIENGINE is not set 185 | 186 | # 187 | # libc 188 | # 189 | CONFIG_RT_USING_LIBC=y 190 | # CONFIG_RT_USING_PTHREADS is not set 191 | 192 | # 193 | # RT-Thread online packages 194 | # 195 | 196 | # 197 | # system packages 198 | # 199 | # CONFIG_PKG_USING_PARTITION is not set 200 | # CONFIG_PKG_USING_SQLITE is not set 201 | 202 | # 203 | # IoT - internet of things 204 | # 205 | # CONFIG_PKG_USING_PAHOMQTT is not set 206 | # CONFIG_PKG_USING_WEBCLIENT is not set 207 | # CONFIG_PKG_USING_MONGOOSE is not set 208 | # CONFIG_PKG_USING_WEBTERMINAL is not set 209 | # CONFIG_PKG_USING_CJSON is not set 210 | # CONFIG_PKG_USING_EZXML is not set 211 | 212 | # 213 | # Marvell WiFi 214 | # 215 | # CONFIG_PKG_USING_MARVELLWIFI is not set 216 | 217 | # 218 | # security packages 219 | # 220 | # CONFIG_PKG_USING_MBEDTLS is not set 221 | 222 | # 223 | # language packages 224 | # 225 | # CONFIG_PKG_USING_JERRYSCRIPT is not set 226 | 227 | # 228 | # multimedia packages 229 | # 230 | # CONFIG_PKG_USING_FASTLZ is not set 231 | 232 | # 233 | # tools packages 234 | # 235 | # CONFIG_PKG_USING_CMBACKTRACE is not set 236 | # CONFIG_PKG_USING_EASYLOGGER is not set 237 | 238 | # 239 | # miscellaneous packages 240 | # 241 | # CONFIG_PKG_USING_HELLO is not set 242 | -------------------------------------------------------------------------------- /rtconfig.h: -------------------------------------------------------------------------------- 1 | #ifndef RT_CONFIG_H__ 2 | #define RT_CONFIG_H__ 3 | 4 | /* Automatically generated file; DO NOT EDIT. */ 5 | /* RT-Thread Configuration */ 6 | 7 | /* RT-Thread Kernel */ 8 | 9 | #define RT_NAME_MAX 8 10 | #define RT_ALIGN_SIZE 8 11 | #define RT_THREAD_PRIORITY_MAX 32 12 | #define RT_TICK_PER_SECOND 100 13 | #define RT_DEBUG 14 | #define RT_USING_OVERFLOW_CHECK 15 | #define RT_DEBUG_INIT 1 16 | #define RT_DEBUG_THREAD 0 17 | //#define RT_USING_HOOK 18 | #define IDLE_THREAD_STACK_SIZE 512 19 | #define RT_USING_TIMER_SOFT 20 | #define RT_TIMER_THREAD_PRIO 4 21 | #define RT_TIMER_THREAD_STACK_SIZE 512 22 | 23 | /* Inter-Thread communication */ 24 | 25 | #define RT_USING_SEMAPHORE 26 | #define RT_USING_MUTEX 27 | #define RT_USING_EVENT 28 | #define RT_USING_MAILBOX 29 | #define RT_USING_MESSAGEQUEUE 30 | 31 | /* Memory Management */ 32 | 33 | #define RT_USING_MEMPOOL 34 | #define RT_USING_MEMHEAP 35 | #define RT_USING_HEAP 36 | /* RT_USING_SMALL_MEM is not set */ 37 | #define RT_USING_SLAB 38 | 39 | /* Kernel Device Object */ 40 | 41 | #define RT_USING_DEVICE 42 | #define RT_USING_CONSOLE 43 | #define RT_CONSOLEBUF_SIZE 512 44 | #define RT_CONSOLE_DEVICE_NAME "uart0" 45 | /* RT_USING_MODULE is not set */ 46 | 47 | /* RT-Thread Components */ 48 | 49 | #define RT_USING_COMPONENTS_INIT 50 | #define RT_USING_USER_MAIN 51 | 52 | /* C++ features */ 53 | 54 | #define RT_USING_CPLUSPLUS 55 | 56 | /* Command shell */ 57 | 58 | #define RT_USING_FINSH 59 | #define FINSH_USING_SYMTAB 60 | #define FINSH_USING_DESCRIPTION 61 | #define FINSH_THREAD_STACK_SIZE 4096 62 | /* FINSH_USING_AUTH is not set */ 63 | #define FINSH_DEFAULT_PASSWORD "rtthread" 64 | #define FINSH_USING_MSH 65 | #define FINSH_USING_MSH_DEFAULT 66 | #define FINSH_USING_MSH_ONLY 67 | 68 | /* Device virtual file system */ 69 | 70 | #define RT_USING_DFS 71 | #define DFS_USING_WORKDIR 72 | #define DFS_FILESYSTEMS_MAX 4 73 | #define DFS_FD_MAX 4 74 | #define RT_USING_DFS_ELMFAT 75 | #define RT_DFS_ELM_CODE_PAGE 437 76 | #define RT_DFS_ELM_WORD_ACCESS 77 | #define RT_DFS_ELM_USE_LFN_0 78 | /* RT_DFS_ELM_USE_LFN_1 is not set */ 79 | /* RT_DFS_ELM_USE_LFN_2 is not set */ 80 | /* RT_DFS_ELM_USE_LFN_3 is not set */ 81 | #define RT_DFS_ELM_USE_LFN 0 82 | #define RT_DFS_ELM_MAX_LFN 256 83 | #define RT_DFS_ELM_DRIVES 4 84 | #define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 85 | /* RT_DFS_ELM_USE_ERASE is not set */ 86 | #define RT_DFS_ELM_REENTRANT 87 | #define RT_USING_DFS_DEVFS 88 | /* RT_USING_DFS_NET is not set */ 89 | /* RT_USING_DFS_NFS is not set */ 90 | 91 | /* Network stack */ 92 | 93 | /* light weight TCP/IP stack */ 94 | 95 | #define RT_USING_LWIP 96 | /* RT_USING_LWIP141 is not set */ 97 | /* RT_USING_LWIP200 is not set */ 98 | #define RT_USING_LWIP202 99 | #define RT_LWIP_IGMP 100 | #define RT_LWIP_ICMP 101 | /* RT_LWIP_SNMP is not set */ 102 | #define RT_LWIP_DNS 103 | //#define RT_LWIP_DHCP 104 | #define IP_SOF_BROADCAST 1 105 | #define IP_SOF_BROADCAST_RECV 1 106 | #define LWIP_USING_DHCPD 107 | #define RT_LWIP_UDP 108 | #define RT_LWIP_TCP 109 | /* RT_LWIP_RAW is not set */ 110 | /* RT_LWIP_PPP is not set */ 111 | /* RT_LWIP_PPPOE is not set */ 112 | /* RT_LWIP_PPPOS is not set */ 113 | #define RT_LWIP_PBUF_NUM 64 114 | #define RT_LWIP_RAW_PCB_NUM 32 115 | #define RT_LWIP_UDP_PCB_NUM 16 116 | #define RT_LWIP_TCP_PCB_NUM 16 117 | #define RT_LWIP_TCP_SEG_NUM 32 118 | #define RT_LWIP_TCP_SND_BUF (8 * 1024) 119 | #define RT_LWIP_TCP_WND 32768 120 | #define RT_LWIP_TCPTHREAD_PRIORITY 10 121 | #define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 122 | #define RT_LWIP_TCPTHREAD_STACKSIZE 4096 123 | #define RT_LWIP_ETHTHREAD_PRIORITY 12 124 | #define RT_LWIP_ETHTHREAD_STACKSIZE 1024 125 | #define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 126 | /* RT_LWIP_REASSEMBLY_FRAG is not set */ 127 | #define LWIP_NETIF_STATUS_CALLBACK 1 128 | #define SO_REUSE 1 129 | #define LWIP_SO_RCVTIMEO 1 130 | #define LWIP_SO_SNDTIMEO 1 131 | #define LWIP_SO_RCVBUF 1 132 | 133 | #ifndef RT_LWIP_DHCP 134 | # define RT_LWIP_IPADDR "192.168.1.101" 135 | # define RT_LWIP_GWADDR "192.168.1.1" 136 | # define RT_LWIP_MSKADDR "255.255.255.0" 137 | #endif 138 | 139 | /* Modbus master and slave stack */ 140 | 141 | //#define RT_USING_MODBUS 142 | /* RT_MODBUS_MASTER_RTU is not set */ 143 | #define RT_MODBUS_SLAVE_RTU 144 | #define RT_USING_NETUTILS 145 | 146 | /* Device Drivers */ 147 | 148 | #define RT_USING_DEVICE_IPC 149 | #define RT_USING_SERIAL 150 | /* RT_USING_CAN is not set */ 151 | /* RT_USING_HWTIMER is not set */ 152 | #define RT_USING_I2C 153 | #define RT_USING_I2C_BITOPS 154 | #define RT_USING_PIN 155 | #define RT_USING_MTD_NOR 156 | #define RT_USING_MTD_NAND 157 | #define RT_MTD_NAND_DEBUG 158 | #define RT_USING_RTC 159 | #define RT_USING_SDIO 160 | #define RT_USING_SPI 161 | #define RT_USING_SFUD 162 | #define RT_SFUD_USING_SFDP 163 | #define RT_SFUD_USING_FLASH_INFO_TABLE 164 | #define RT_SFUD_DEBUG 165 | #define RT_USING_W25QXX 166 | /* RT_USING_GD is not set */ 167 | /* RT_USING_ENC28J60 is not set */ 168 | /* RT_USING_SPI_WIFI is not set */ 169 | #define RT_USING_WDT 170 | /* RT_USING_USB_HOST is not set */ 171 | //#define RT_USING_USB_DEVICE 172 | #define RT_USB_DEVICE_CDC 173 | #define RT_USB_DEVICE_MSTORAGE 174 | 175 | /* RT-Thread UI Engine */ 176 | 177 | /* RT_USING_GUIENGINE is not set */ 178 | 179 | /* libc */ 180 | 181 | #define RT_USING_LIBC 182 | /* RT_USING_PTHREADS is not set */ 183 | 184 | /* RT-Thread online packages */ 185 | 186 | /* system packages */ 187 | 188 | /* PKG_USING_PARTITION is not set */ 189 | /* PKG_USING_SQLITE is not set */ 190 | 191 | /* IoT - internet of things */ 192 | 193 | /* PKG_USING_PAHOMQTT is not set */ 194 | /* PKG_USING_WEBCLIENT is not set */ 195 | /* PKG_USING_MONGOOSE is not set */ 196 | /* PKG_USING_WEBTERMINAL is not set */ 197 | /* PKG_USING_CJSON is not set */ 198 | /* PKG_USING_EZXML is not set */ 199 | 200 | /* Marvell WiFi */ 201 | 202 | /* PKG_USING_MARVELLWIFI is not set */ 203 | 204 | /* security packages */ 205 | 206 | /* PKG_USING_MBEDTLS is not set */ 207 | 208 | /* language packages */ 209 | 210 | /* PKG_USING_JERRYSCRIPT is not set */ 211 | 212 | /* multimedia packages */ 213 | 214 | /* PKG_USING_FASTLZ is not set */ 215 | 216 | /* tools packages */ 217 | 218 | /* PKG_USING_CMBACKTRACE is not set */ 219 | /* PKG_USING_EASYLOGGER is not set */ 220 | 221 | /* miscellaneous packages */ 222 | 223 | /* PKG_USING_HELLO is not set */ 224 | 225 | /* EMWIN config */ 226 | //#define RT_USING_EMWIN 227 | 228 | #endif 229 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/trap.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : trap.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | * 2011-01-13 weety modified from mini2440 23 | * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP 24 | */ 25 | 26 | #include 27 | #include 28 | 29 | #define INT_IRQ 0x00 30 | #define INT_FIQ 0x01 31 | 32 | extern struct rt_thread *rt_current_thread; 33 | #ifdef RT_USING_FINSH 34 | extern long list_thread(void); 35 | #endif 36 | 37 | struct rt_hw_register 38 | { 39 | rt_uint32_t r0; 40 | rt_uint32_t r1; 41 | rt_uint32_t r2; 42 | rt_uint32_t r3; 43 | rt_uint32_t r4; 44 | rt_uint32_t r5; 45 | rt_uint32_t r6; 46 | rt_uint32_t r7; 47 | rt_uint32_t r8; 48 | rt_uint32_t r9; 49 | rt_uint32_t r10; 50 | rt_uint32_t fp; 51 | rt_uint32_t ip; 52 | rt_uint32_t sp; 53 | rt_uint32_t lr; 54 | rt_uint32_t pc; 55 | rt_uint32_t cpsr; 56 | rt_uint32_t ORIG_r0; 57 | }; 58 | 59 | /** 60 | * this function will show registers of CPU 61 | * 62 | * @param regs the registers point 63 | */ 64 | 65 | void rt_hw_show_register (struct rt_hw_register *regs) 66 | { 67 | rt_kprintf("Execption:\n"); 68 | rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", 69 | regs->r0, regs->r1, regs->r2, regs->r3); 70 | rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", 71 | regs->r4, regs->r5, regs->r6, regs->r7); 72 | rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", 73 | regs->r8, regs->r9, regs->r10); 74 | rt_kprintf("fp :0x%08x ip :0x%08x\n", 75 | regs->fp, regs->ip); 76 | rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", 77 | regs->sp, regs->lr, regs->pc); 78 | rt_kprintf("cpsr:0x%08x\n", regs->cpsr); 79 | } 80 | 81 | /** 82 | * When ARM7TDMI comes across an instruction which it cannot handle, 83 | * it takes the undefined instruction trap. 84 | * 85 | * @param regs system registers 86 | * 87 | * @note never invoke this function in application 88 | */ 89 | void rt_hw_trap_udef(struct rt_hw_register *regs) 90 | { 91 | rt_hw_show_register(regs); 92 | 93 | rt_kprintf("undefined instruction\n"); 94 | rt_kprintf("thread - %s stack:\n", rt_current_thread->name); 95 | 96 | #ifdef RT_USING_FINSH 97 | list_thread(); 98 | #endif 99 | rt_hw_cpu_shutdown(); 100 | } 101 | 102 | /** 103 | * The software interrupt instruction (SWI) is used for entering 104 | * Supervisor mode, usually to request a particular supervisor 105 | * function. 106 | * 107 | * @param regs system registers 108 | * 109 | * @note never invoke this function in application 110 | */ 111 | void rt_hw_trap_swi(struct rt_hw_register *regs) 112 | { 113 | rt_hw_show_register(regs); 114 | 115 | rt_kprintf("software interrupt\n"); 116 | rt_hw_cpu_shutdown(); 117 | } 118 | 119 | /** 120 | * An abort indicates that the current memory access cannot be completed, 121 | * which occurs during an instruction prefetch. 122 | * 123 | * @param regs system registers 124 | * 125 | * @note never invoke this function in application 126 | */ 127 | void rt_hw_trap_pabt(struct rt_hw_register *regs) 128 | { 129 | rt_hw_show_register(regs); 130 | 131 | rt_kprintf("prefetch abort\n"); 132 | rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name); 133 | 134 | #ifdef RT_USING_FINSH 135 | list_thread(); 136 | #endif 137 | rt_hw_cpu_shutdown(); 138 | } 139 | 140 | /** 141 | * An abort indicates that the current memory access cannot be completed, 142 | * which occurs during a data access. 143 | * 144 | * @param regs system registers 145 | * 146 | * @note never invoke this function in application 147 | */ 148 | void rt_hw_trap_dabt(struct rt_hw_register *regs) 149 | { 150 | rt_hw_show_register(regs); 151 | 152 | rt_kprintf("data abort\n"); 153 | rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name); 154 | 155 | #ifdef RT_USING_FINSH 156 | list_thread(); 157 | #endif 158 | rt_hw_cpu_shutdown(); 159 | } 160 | 161 | /** 162 | * Normally, system will never reach here 163 | * 164 | * @param regs system registers 165 | * 166 | * @note never invoke this function in application 167 | */ 168 | void rt_hw_trap_resv(struct rt_hw_register *regs) 169 | { 170 | rt_kprintf("not used\n"); 171 | rt_hw_show_register(regs); 172 | rt_hw_cpu_shutdown(); 173 | } 174 | extern struct rt_irq_desc irq_desc[]; 175 | extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq); 176 | extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id); 177 | 178 | void rt_hw_trap_irq() 179 | { 180 | rt_isr_handler_t isr_func; 181 | rt_uint32_t irq; 182 | void *param; 183 | 184 | /* get irq number */ 185 | irq = rt_hw_interrupt_get_active(INT_IRQ); 186 | 187 | /* get interrupt service routine */ 188 | isr_func = irq_desc[irq].handler; 189 | param = irq_desc[irq].param; 190 | 191 | /* turn to interrupt service routine */ 192 | isr_func(irq, param); 193 | 194 | rt_hw_interrupt_ack(INT_IRQ, irq); 195 | #ifdef RT_USING_INTERRUPT_INFO 196 | irq_desc[irq].counter ++; 197 | #endif 198 | } 199 | 200 | void rt_hw_trap_fiq() 201 | { 202 | rt_isr_handler_t isr_func; 203 | rt_uint32_t irq; 204 | void *param; 205 | 206 | /* get irq number */ 207 | irq = rt_hw_interrupt_get_active(INT_FIQ); 208 | 209 | /* get interrupt service routine */ 210 | isr_func = irq_desc[irq].handler; 211 | param = irq_desc[irq].param; 212 | 213 | /* turn to interrupt service routine */ 214 | isr_func(irq, param); 215 | 216 | rt_hw_interrupt_ack(INT_FIQ, irq); 217 | #ifdef RT_USING_INTERRUPT_INFO 218 | irq_desc[irq].counter ++; 219 | #endif 220 | } 221 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/start_gcc.s: -------------------------------------------------------------------------------- 1 | /* 2 | * File : start_gcc.S 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | * 2011-01-13 weety first version 23 | * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP 24 | * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table 25 | * 2015-06-04 aozima Align stack address to 8 byte. 26 | */ 27 | 28 | #define S_FRAME_SIZE (18*4) //72 29 | 30 | @#define S_SPSR (17*4) //SPSR 31 | @#define S_CPSR (16*4) //CPSR 32 | #define S_PC (15*4) //R15 33 | @#define S_LR (14*4) //R14 34 | @#define S_SP (13*4) //R13 35 | 36 | @#define S_IP (12*4) //R12 37 | @#define S_FP (11*4) //R11 38 | @#define S_R10 (10*4) 39 | @#define S_R9 (9*4) 40 | @#define S_R8 (8*4) 41 | @#define S_R7 (7*4) 42 | @#define S_R6 (6*4) 43 | @#define S_R5 (5*4) 44 | @#define S_R4 (4*4) 45 | @#define S_R3 (3*4) 46 | @#define S_R2 (2*4) 47 | @#define S_R1 (1*4) 48 | @#define S_R0 (0*4) 49 | 50 | #define MODE_SYS 0x1F 51 | #define MODE_FIQ 0x11 52 | #define MODE_IRQ 0x12 53 | #define MODE_SVC 0x13 54 | #define MODE_ABT 0x17 55 | #define MODE_UND 0x1B 56 | #define MODEMASK 0x1F 57 | #define NOINT 0xC0 58 | 59 | .include "rt_low_level_gcc.inc" 60 | 61 | @;----------------------- Stack and Heap Definitions --------------------------- 62 | .section .nobss, "w" 63 | 64 | .space UND_STK_SIZE 65 | .align 3 66 | .global UND_STACK_START 67 | UND_STACK_START: 68 | 69 | .space ABT_STK_SIZE 70 | .align 3 71 | .global ABT_STACK_START 72 | ABT_STACK_START: 73 | 74 | .space FIQ_STK_SIZE 75 | .align 3 76 | .global FIQ_STACK_START 77 | FIQ_STACK_START: 78 | 79 | .space IRQ_STK_SIZE 80 | .align 3 81 | .global IRQ_STACK_START 82 | IRQ_STACK_START: 83 | 84 | .skip SYS_STK_SIZE 85 | .align 3 86 | .global SYS_STACK_START 87 | SYS_STACK_START: 88 | 89 | .space SVC_STK_SIZE 90 | .align 3 91 | .global SVC_STACK_START 92 | SVC_STACK_START: 93 | 94 | @;--------------Jump vector table----------------------------------------------- 95 | .section .init, "ax" 96 | .arm 97 | 98 | .global start 99 | start: 100 | LDR PC, vector_reset 101 | LDR PC, vector_undef 102 | LDR PC, vector_swi 103 | LDR PC, vector_pabt 104 | LDR PC, vector_dabt 105 | LDR PC, vector_resv 106 | LDR PC, vector_irq 107 | LDR PC, vector_fiq 108 | 109 | vector_reset: 110 | .word Reset_Handler 111 | vector_undef: 112 | .word Undef_Handler 113 | vector_swi: 114 | .word SWI_Handler 115 | vector_pabt: 116 | .word PAbt_Handler 117 | vector_dabt: 118 | .word DAbt_Handler 119 | vector_resv: 120 | .word Resv_Handler 121 | vector_irq: 122 | .word IRQ_Handler 123 | vector_fiq: 124 | .word FIQ_Handler 125 | 126 | .balignl 16,0xdeadbeef 127 | 128 | @;----------------- Reset Handler --------------------------------------------- 129 | .global rt_low_level_init 130 | .global main 131 | .global Reset_Handler 132 | Reset_Handler: 133 | @; Set the cpu to SVC32 mode 134 | MRS R0, CPSR 135 | BIC R0, R0, #MODEMASK 136 | ORR R0, R0, #MODE_SVC|NOINT 137 | MSR CPSR_cxsf, R0 138 | 139 | @; Set CO-Processor 140 | @; little-end，disbale I/D Cache MMU, vector table is 0x00000000 141 | MRC P15, 0, R0, C1, C0, 0 @; Read CP15 142 | LDR R1, =0x00003085 @; set clear bits 143 | BIC R0, R0, R1 144 | MCR P15, 0, R0, C1, C0, 0 @; Write CP15 145 | 146 | @; Call low level init function, 147 | @; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. 148 | LDR SP, =SVC_STACK_START 149 | LDR R0, =rt_low_level_init 150 | BLX R0 151 | 152 | Setup_Stack: 153 | @; Setup Stack for each mode 154 | MRS R0, CPSR 155 | BIC R0, R0, #MODEMASK 156 | 157 | ORR R1, R0, #MODE_UND|NOINT 158 | MSR CPSR_cxsf, R1 @; Undef mode 159 | LDR SP, =UND_STACK_START 160 | 161 | ORR R1, R0, #MODE_ABT|NOINT 162 | MSR CPSR_cxsf, R1 @; Abort mode 163 | LDR SP, =ABT_STACK_START 164 | 165 | ORR R1, R0, #MODE_IRQ|NOINT 166 | MSR CPSR_cxsf, R1 @; IRQ mode 167 | LDR SP, =IRQ_STACK_START 168 | 169 | ORR R1, R0, #MODE_FIQ|NOINT 170 | MSR CPSR_cxsf, R1 @; FIQ mode 171 | LDR SP, =FIQ_STACK_START 172 | 173 | ORR R1, R0, #MODE_SYS|NOINT 174 | MSR CPSR_cxsf,R1 @; SYS/User mode 175 | LDR SP, =SYS_STACK_START 176 | 177 | ORR R1, R0, #MODE_SVC|NOINT 178 | MSR CPSR_cxsf, R1 @; SVC mode 179 | LDR SP, =SVC_STACK_START 180 | 181 | @; clear .bss 182 | MOV R0, #0 @; get a zero 183 | LDR R1, =__bss_start__ @; bss start 184 | LDR R2, =__bss_end__ @; bss end 185 | 186 | bss_clear_loop: 187 | CMP R1, R2 @; check if data to clear 188 | STRLO R0, [R1], #4 @; clear 4 bytes 189 | BLO bss_clear_loop @; loop until done 190 | 191 | @; call C++ constructors of global objects 192 | LDR R0, =__ctors_start__ 193 | LDR R1, =__ctors_end__ 194 | 195 | ctor_loop: 196 | CMP R0, R1 197 | BEQ ctor_end 198 | LDR R2, [R0], #4 199 | STMFD SP!, {R0-R1} 200 | MOV LR, PC 201 | BX R2 202 | LDMFD SP!, {R0-R1} 203 | B ctor_loop 204 | ctor_end: 205 | 206 | @; Enter the C code 207 | LDR R0, =rtthread_startup 208 | BLX R0 209 | 210 | @;----------------- Exception Handler ----------------------------------------- 211 | .global rt_hw_trap_udef 212 | .global rt_hw_trap_swi 213 | .global rt_hw_trap_pabt 214 | .global rt_hw_trap_dabt 215 | .global rt_hw_trap_resv 216 | .global rt_hw_trap_irq 217 | .global rt_hw_trap_fiq 218 | 219 | .global rt_interrupt_enter 220 | .global rt_interrupt_leave 221 | .global rt_thread_switch_interrupt_flag 222 | .global rt_interrupt_from_thread 223 | .global rt_interrupt_to_thread 224 | 225 | .align 5 226 | Undef_Handler: 227 | SUB SP, SP, #S_FRAME_SIZE 228 | STMIA SP, {R0 - R12} @; Calling R0-R12 229 | ADD R8, SP, #S_PC 230 | STMDB R8, {SP, LR} @; Calling SP, LR 231 | STR LR, [R8, #0] @; Save calling PC 232 | MRS R6, SPSR 233 | STR R6, [R8, #4] @; Save CPSR 234 | STR R0, [R8, #8] @; Save SPSR 235 | MOV R0, SP 236 | BL rt_hw_trap_udef 237 | 238 | .align 5 239 | SWI_Handler: 240 | BL rt_hw_trap_swi 241 | 242 | .align 5 243 | PAbt_Handler: 244 | BL rt_hw_trap_pabt 245 | 246 | .align 5 247 | DAbt_Handler: 248 | SUB SP, SP, #S_FRAME_SIZE 249 | STMIA SP, {R0 - R12} @; Calling R0-R12 250 | ADD R8, SP, #S_PC 251 | STMDB R8, {SP, LR} @; Calling SP, LR 252 | STR LR, [R8, #0] @; Save calling PC 253 | MRS R6, SPSR 254 | STR R6, [R8, #4] @; Save CPSR 255 | STR R0, [R8, #8] @; Save SPSR 256 | MOV R0, SP 257 | BL rt_hw_trap_dabt 258 | 259 | .align 5 260 | Resv_Handler: 261 | BL rt_hw_trap_resv 262 | 263 | .align 5 264 | FIQ_Handler: 265 | STMFD SP!, {R0-R7,LR} 266 | BL rt_hw_trap_fiq 267 | LDMFD SP!, {R0-R7,LR} 268 | SUBS PC, LR, #4 269 | 270 | .align 5 271 | IRQ_Handler: 272 | STMFD SP!, {R0-R12,LR} 273 | BL rt_interrupt_enter 274 | BL rt_hw_trap_irq 275 | BL rt_interrupt_leave 276 | 277 | @; If rt_thread_switch_interrupt_flag set, 278 | @; jump to rt_hw_context_switch_interrupt_do and don't return 279 | LDR R0, =rt_thread_switch_interrupt_flag 280 | LDR R1, [R0] 281 | CMP R1, #1 282 | BEQ rt_hw_context_switch_interrupt_do 283 | 284 | LDMFD SP!, {R0-R12,LR} 285 | SUBS PC, LR, #4 286 | 287 | @;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- 288 | rt_hw_context_switch_interrupt_do: 289 | MOV R1, #0 @; Clear flag 290 | STR R1, [R0] @; Save to flag variable 291 | 292 | LDMFD SP!, {R0-R12,LR} @; Reload saved registers 293 | STMFD SP, {R0-R2} @; Save R0-R2 294 | SUB R1, SP, #4*3 @; Save old task's SP to R1 295 | SUB R2, LR, #4 @; Save old task's PC to R2 296 | 297 | MRS R0, SPSR @; Get CPSR of interrupt thread 298 | 299 | MSR CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt 300 | 301 | STMFD SP!, {R2} @; Push old task's PC 302 | STMFD SP!, {R3-R12,LR} @; Push old task's LR,R12-R3 303 | LDMFD R1, {R1-R3} 304 | STMFD SP!, {R1-R3} @; Push old task's R2-R0 305 | STMFD SP!, {R0} @; Push old task's CPSR 306 | 307 | LDR R4, =rt_interrupt_from_thread 308 | LDR R5, [R4] @; R5 = stack ptr in old tasks's TCB 309 | STR SP, [R5] @; Store SP in preempted tasks's TCB 310 | 311 | LDR R6, =rt_interrupt_to_thread 312 | LDR R6, [R6] @; R6 = stack ptr in new tasks's TCB 313 | LDR SP, [R6] @; Get new task's stack pointer 314 | 315 | LDMFD SP!, {R4} @; Pop new task's SPSR 316 | MSR SPSR_cxsf, R4 317 | 318 | LDMFD SP!, {R0-R12,LR,PC}^ @; pop new task's R0-R12,LR & PC SPSR 2 CPSR 319 | -------------------------------------------------------------------------------- /libcpu/arm/arm926/mmu.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File : mmu.c 3 | * This file is part of RT-Thread RTOS 4 | * COPYRIGHT (C) 2006, RT-Thread Development Team 5 | * 6 | * This program is free software; you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation; either version 2 of the License, or 9 | * (at your option) any later version. 10 | * 11 | * This program is distributed in the hope that it will be useful, 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | * GNU General Public License for more details. 15 | * 16 | * You should have received a copy of the GNU General Public License along 17 | * with this program; if not, write to the Free Software Foundation, Inc., 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 | * 20 | * Change Logs: 21 | * Date Author Notes 22 | * 2015-04-15 ArdaFu Add code for IAR 23 | */ 24 | 25 | #include "mmu.h" 26 | 27 | /*----- Keil -----------------------------------------------------------------*/ 28 | #ifdef __CC_ARM 29 | void mmu_setttbase(rt_uint32_t i) 30 | { 31 | register rt_uint32_t value; 32 | 33 | /* Invalidates all TLBs.Domain access is selected as 34 | * client by configuring domain access register, 35 | * in that case access controlled by permission value 36 | * set by page table entry 37 | */ 38 | value = 0; 39 | __asm volatile{ mcr p15, 0, value, c8, c7, 0 } 40 | value = 0x55555555; 41 | __asm volatile { mcr p15, 0, value, c3, c0, 0 } 42 | __asm volatile { mcr p15, 0, i, c2, c0, 0 } 43 | } 44 | 45 | void mmu_set_domain(rt_uint32_t i) 46 | { 47 | __asm volatile { mcr p15, 0, i, c3, c0, 0 } 48 | } 49 | 50 | void mmu_enable() 51 | { 52 | register rt_uint32_t value; 53 | 54 | __asm volatile 55 | { 56 | mrc p15, 0, value, c1, c0, 0 57 | orr value, value, #0x01 58 | mcr p15, 0, value, c1, c0, 0 59 | } 60 | } 61 | 62 | void mmu_disable() 63 | { 64 | register rt_uint32_t value; 65 | 66 | __asm volatile 67 | { 68 | mrc p15, 0, value, c1, c0, 0 69 | bic value, value, #0x01 70 | mcr p15, 0, value, c1, c0, 0 71 | } 72 | } 73 | 74 | void mmu_enable_icache() 75 | { 76 | register rt_uint32_t value; 77 | 78 | __asm volatile 79 | { 80 | mrc p15, 0, value, c1, c0, 0 81 | orr value, value, #0x1000 82 | mcr p15, 0, value, c1, c0, 0 83 | } 84 | } 85 | 86 | void mmu_enable_dcache() 87 | { 88 | register rt_uint32_t value; 89 | 90 | __asm volatile 91 | { 92 | mrc p15, 0, value, c1, c0, 0 93 | orr value, value, #0x04 94 | mcr p15, 0, value, c1, c0, 0 95 | } 96 | } 97 | 98 | void mmu_disable_icache() 99 | { 100 | register rt_uint32_t value; 101 | 102 | __asm volatile 103 | { 104 | mrc p15, 0, value, c1, c0, 0 105 | bic value, value, #0x1000 106 | mcr p15, 0, value, c1, c0, 0 107 | } 108 | } 109 | 110 | void mmu_disable_dcache() 111 | { 112 | register rt_uint32_t value; 113 | 114 | __asm volatile 115 | { 116 | mrc p15, 0, value, c1, c0, 0 117 | bic value, value, #0x04 118 | mcr p15, 0, value, c1, c0, 0 119 | } 120 | } 121 | 122 | void mmu_enable_alignfault() 123 | { 124 | register rt_uint32_t value; 125 | 126 | __asm volatile 127 | { 128 | mrc p15, 0, value, c1, c0, 0 129 | orr value, value, #0x02 130 | mcr p15, 0, value, c1, c0, 0 131 | } 132 | } 133 | 134 | void mmu_disable_alignfault() 135 | { 136 | register rt_uint32_t value; 137 | 138 | __asm volatile 139 | { 140 | mrc p15, 0, value, c1, c0, 0 141 | bic value, value, #0x02 142 | mcr p15, 0, value, c1, c0, 0 143 | } 144 | } 145 | 146 | void mmu_clean_invalidated_cache_index(int index) 147 | { 148 | __asm volatile { mcr p15, 0, index, c7, c14, 2 } 149 | } 150 | 151 | void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) 152 | { 153 | unsigned int ptr; 154 | 155 | ptr = buffer & ~(CACHE_LINE_SIZE - 1); 156 | 157 | while(ptr < buffer + size) 158 | { 159 | __asm volatile { MCR p15, 0, ptr, c7, c14, 1 } 160 | ptr += CACHE_LINE_SIZE; 161 | } 162 | } 163 | 164 | void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) 165 | { 166 | unsigned int ptr; 167 | 168 | ptr = buffer & ~(CACHE_LINE_SIZE - 1); 169 | 170 | while (ptr < buffer + size) 171 | { 172 | __asm volatile { MCR p15, 0, ptr, c7, c10, 1 } 173 | ptr += CACHE_LINE_SIZE; 174 | } 175 | } 176 | 177 | void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) 178 | { 179 | unsigned int ptr; 180 | 181 | ptr = buffer & ~(CACHE_LINE_SIZE - 1); 182 | 183 | while (ptr < buffer + size) 184 | { 185 | __asm volatile { MCR p15, 0, ptr, c7, c6, 1 } 186 | ptr += CACHE_LINE_SIZE; 187 | } 188 | } 189 | 190 | void mmu_invalidate_tlb() 191 | { 192 | register rt_uint32_t value; 193 | 194 | value = 0; 195 | __asm volatile { mcr p15, 0, value, c8, c7, 0 } 196 | } 197 | 198 | void mmu_invalidate_icache() 199 | { 200 | register rt_uint32_t value; 201 | 202 | value = 0; 203 | 204 | __asm volatile { mcr p15, 0, value, c7, c5, 0 } 205 | } 206 | 207 | 208 | void mmu_invalidate_dcache_all() 209 | { 210 | register rt_uint32_t value; 211 | 212 | value = 0; 213 | 214 | __asm volatile { mcr p15, 0, value, c7, c6, 0 } 215 | } 216 | /*----- GNU ------------------------------------------------------------------*/ 217 | #elif defined(__GNUC__) || defined(__ICCARM__) 218 | void mmu_setttbase(register rt_uint32_t i) 219 | { 220 | register rt_uint32_t value; 221 | 222 | /* Invalidates all TLBs.Domain access is selected as 223 | * client by configuring domain access register, 224 | * in that case access controlled by permission value 225 | * set by page table entry 226 | */ 227 | value = 0; 228 | asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); 229 | 230 | value = 0x55555555; 231 | asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); 232 | 233 | asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); 234 | 235 | } 236 | 237 | void mmu_set_domain(register rt_uint32_t i) 238 | { 239 | asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); 240 | } 241 | 242 | void mmu_enable() 243 | { 244 | asm volatile 245 | ( 246 | "mrc p15, 0, r0, c1, c0, 0 \n" 247 | "orr r0, r0, #0x1 \n" 248 | "mcr p15, 0, r0, c1, c0, 0 \n" 249 | :::"r0" 250 | ); 251 | } 252 | 253 | void mmu_disable() 254 | { 255 | asm volatile 256 | ( 257 | "mrc p15, 0, r0, c1, c0, 0 \n" 258 | "bic r0, r0, #0x1 \n" 259 | "mcr p15, 0, r0, c1, c0, 0 \n" 260 | :::"r0" 261 | ); 262 | 263 | } 264 | 265 | void mmu_enable_icache() 266 | { 267 | asm volatile 268 | ( 269 | "mrc p15, 0, r0, c1, c0, 0 \n" 270 | "orr r0, r0, #(1<<12) \n" 271 | "mcr p15, 0, r0, c1, c0, 0 \n" 272 | :::"r0" 273 | ); 274 | } 275 | 276 | void mmu_enable_dcache() 277 | { 278 | asm volatile 279 | ( 280 | "mrc p15, 0, r0, c1, c0, 0 \n" 281 | "orr r0, r0, #(1<<2) \n" 282 | "mcr p15, 0, r0, c1, c0, 0 \n" 283 | :::"r0" 284 | ); 285 | 286 | } 287 | 288 | void mmu_disable_icache() 289 | { 290 | asm volatile 291 | ( 292 | "mrc p15, 0, r0, c1, c0, 0 \n" 293 | "bic r0, r0, #(1<<12) \n" 294 | "mcr p15, 0, r0, c1, c0, 0 \n" 295 | :::"r0" 296 | ); 297 | 298 | } 299 | 300 | void mmu_disable_dcache() 301 | { 302 | asm volatile 303 | ( 304 | "mrc p15, 0, r0, c1, c0, 0 \n" 305 | "bic r0, r0, #(1<<2) \n" 306 | "mcr p15, 0, r0, c1, c0, 0 \n" 307 | :::"r0" 308 | ); 309 | 310 | } 311 | 312 | void mmu_enable_alignfault() 313 | { 314 | asm volatile 315 | ( 316 | "mrc p15, 0, r0, c1, c0, 0 \n" 317 | "orr r0, r0, #1 \n" 318 | "mcr p15, 0, r0, c1, c0, 0 \n" 319 | :::"r0" 320 | ); 321 | 322 | } 323 | 324 | void mmu_disable_alignfault() 325 | { 326 | asm volatile 327 | ( 328 | "mrc p15, 0, r0, c1, c0, 0 \n" 329 | "bic r0, r0, #1 \n" 330 | "mcr p15, 0, r0, c1, c0, 0 \n" 331 | :::"r0" 332 | ); 333 | 334 | } 335 | 336 | void mmu_clean_invalidated_cache_index(int index) 337 | { 338 | asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); 339 | } 340 | 341 | void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) 342 | { 343 | unsigned int ptr; 344 | 345 | ptr = buffer & ~(CACHE_LINE_SIZE - 1); 346 | 347 | while(ptr < buffer + size) 348 | { 349 | asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); 350 | 351 | ptr += CACHE_LINE_SIZE; 352 | } 353 | } 354 | 355 | 356 | void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) 357 | { 358 | unsigned int ptr; 359 | 360 | ptr = buffer & ~(CACHE_LINE_SIZE - 1); 361 | 362 | while (ptr < buffer + size) 363 | { 364 | asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); 365 | 366 | ptr += CACHE_LINE_SIZE; 367 | } 368 | } 369 | 370 | void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) 371 | { 372 | unsigned int ptr; 373 | 374 | ptr = buffer & ~(CACHE_LINE_SIZE - 1); 375 | 376 | while (ptr < buffer + size) 377 | { 378 | asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); 379 | 380 | ptr += CACHE_LINE_SIZE; 381 | } 382 | } 383 | 384 | void mmu_invalidate_tlb() 385 | { 386 | asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); 387 | 388 | } 389 | 390 | void mmu_invalidate_icache() 391 | { 392 | asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); 393 | 394 | } 395 | 396 | void mmu_invalidate_dcache_all() 397 | { 398 | asm volatile ("mcr p15, 0, %0, c7, c10, 4": :"r" (0)); 399 | 400 | } 401 | #endif 402 | 403 | /* level1 page table */ 404 | #if defined(__ICCARM__) 405 | #pragma data_alignment=(16*1024) 406 | static volatile rt_uint32_t _page_table[4*1024]; 407 | #else 408 | static volatile rt_uint32_t _page_table[4*1024] \ 409 | __attribute__((aligned(16*1024))); 410 | #endif 411 | 412 | void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, 413 | rt_uint32_t paddrStart, rt_uint32_t attr) 414 | { 415 | volatile rt_uint32_t *pTT; 416 | volatile int nSec; 417 | int i = 0; 418 | pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20); 419 | nSec=(vaddrEnd>>20)-(vaddrStart>>20); 420 | for(i=0; i<=nSec; i++) 421 | { 422 | *pTT = attr |(((paddrStart>>20)+i)<<20); 423 | pTT++; 424 | } 425 | } 426 | 427 | void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) 428 | { 429 | /* disable I/D cache */ 430 | mmu_disable_dcache(); 431 | mmu_disable_icache(); 432 | mmu_disable(); 433 | mmu_invalidate_tlb(); 434 | 435 | /* set page table */ 436 | for (; size > 0; size--) 437 | { 438 | mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, 439 | mdesc->paddr_start, mdesc->attr); 440 | mdesc++; 441 | } 442 | 443 | /* set MMU table address */ 444 | mmu_setttbase((rt_uint32_t)_page_table); 445 | 446 | /* enables MMU */ 447 | mmu_enable(); 448 | 449 | /* enable Instruction Cache */ 450 | mmu_enable_icache(); 451 | 452 | /* enable Data Cache */ 453 | mmu_enable_dcache(); 454 | 455 | mmu_invalidate_icache(); 456 | mmu_invalidate_dcache_all(); 457 | } 458 | --------------------------------------------------------------------------------