├── Makefile ├── README.md ├── firmware ├── Makefile ├── MicoSleepHelper.S ├── crt0ram-smu.S ├── delay.h ├── makefirmware.sh ├── memcpy.c ├── ops.h ├── servicereq.c ├── servicereq.h ├── smu.c ├── smu.h └── smu.ld ├── header.bin ├── signsmu.py ├── smudump.c ├── smutool.c └── swap.py /Makefile: -------------------------------------------------------------------------------- 1 | CC= gcc 2 | CFLAGS= -Wall -O0 -g 3 | LIBS= -lpci 4 | 5 | INCLUDES= -I. 6 | 7 | SRCS1= smutool.c 8 | SRCS2= smudump.c 9 | 10 | OBJS1 = $(SRCS1:.c=.o) 11 | OBJS2 = $(SRCS2:.c=.o) 12 | 13 | TARGET1= smutool 14 | TARGET2= smudump 15 | 16 | 17 | .PHONY: depend clean 18 | 19 | all: $(TARGET1) $(TARGET2) 20 | 21 | $(TARGET1): $(OBJS1) $(SRCS1) 22 | $(CC) $(CFLAGS) $(INCLUDES) -o $(TARGET1) $(OBJS1) $(LIBS) 23 | $(TARGET2): $(OBJS2) $(SRCS2) 24 | $(CC) $(CFLAGS) $(INCLUDES) -o $(TARGET2) $(OBJS2) $(LIBS) 25 | 26 | .c.o: 27 | $(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@ 28 | 29 | clean: 30 | rm $(TARGET1) $(TARGET2) *.o 31 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | smutool 2 | ======= 3 | 4 | This tool aids in the reverse engineering of AMD SMU. 5 | The SMU is a LatticeMico32 co-processor residing in the mainboard 6 | for controlling thermal management, clocks, and fans etc. 7 | 8 | The purpose of this project is to collaborate with others to 9 | create a free alternative firmware SMU stack that interoperates with coreboot. 10 | 11 | Compiling 12 | ========= 13 | You need libpci-dev 14 | ``` 15 | make 16 | ``` 17 | 18 | RAM dumping 19 | =========== 20 | ``` 21 | sudo ./smudump > ram 22 | ``` 23 | 24 | ROM dumping 25 | =========== 26 | (Code needs tweaking on different machines): 27 | ``` 28 | sudo ./smutool > rom 29 | ``` 30 | 31 | User firmware signing 32 | ===================== 33 | ``` 34 | python signsmu.py myfirmware 35 | ``` 36 | 37 | License 38 | ======= 39 | This project is released under GPLv3 40 | -------------------------------------------------------------------------------- /firmware/Makefile: -------------------------------------------------------------------------------- 1 | # Free/Libre SMU firmware 2 | # Copyright (C) 2015 Damien Zammit 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # See .- 14 | # 15 | 16 | CC = lm32-elf-gcc 17 | LD = lm32-elf-ld 18 | OC = lm32-elf-objcopy 19 | 20 | LIBS=-L/opt/lm32/lib/gcc/lm32-elf/4.5.4 21 | SRCS=servicereq.c memcpy.c smu.c 22 | ASMS=MicoSleepHelper.S crt0ram-smu.S 23 | OBJS=$(SRCS:.c=.o) 24 | OBJS2=$(ASMS:.S=.o) 25 | TARGET=smu.elf 26 | OPT=-Os 27 | 28 | all: $(TARGET) 29 | 30 | $(TARGET): $(OBJS) $(OBJS2) 31 | $(LD) $(LIBS) $(OBJS) $(OBJS2) -static -M -T smu.ld -o $(TARGET) >/dev/null 32 | $(OC) -S -I elf32-lm32 -O binary $(TARGET) smu.rom 33 | bash ./makefirmware.sh smu.rom > GnbSmuFirmwareTN.h 34 | 35 | .c.o: 36 | $(CC) $(LIBS) $(OPT) -Wall -ffreestanding -c $< -o $@ 37 | 38 | .S.o: 39 | $(CC) $(LIBS) $(OPT) -Wall -ffreestanding -c $< -o $@ 40 | 41 | clean: 42 | rm -f *.o *~ $(TARGET) smu.rom 43 | -------------------------------------------------------------------------------- /firmware/MicoSleepHelper.S: -------------------------------------------------------------------------------- 1 | /* 2 | * Disclaimer: 3 | * 4 | * This source code is intended as a design reference 5 | * which illustrates how these types of functions can be implemented. 6 | * It is the user's responsibility to verify their design for 7 | * consistency and functionality through the use of formal 8 | * verification methods. Lattice Semiconductor provides no warranty 9 | * regarding the use or functionality of this code. 10 | * 11 | * -------------------------------------------------------------------- 12 | * 13 | * Lattice Semiconductor Corporation 14 | * 5555 NE Moore Court 15 | * Hillsboro, OR 97214 16 | * U.S.A 17 | * 18 | * TEL: 1-800-Lattice (USA and Canada) 19 | * 408-826-6000 (other locations) 20 | * 21 | * web: http://www.latticesemi.com/ 22 | * email: techsupport@latticesemi.com 23 | * 24 | * -------------------------------------------------------------------- 25 | * 26 | * Project: LatticeMico32 27 | * File: MicoSleepHelper.S 28 | * Description: C Source code implementation for MicoSleepHelper 29 | * called by MicoSleepMilliSecs and MicoSleepMicroSecs 30 | * 31 | *---------------------------------------------------------------------------- 32 | * Change History 33 | * 34 | * Vers Date Change 35 | * --------------------------------------------------------------------------- 36 | * 3.0 Mar-25-2008: Sync'd version to 3.0 for MSB 7.1 release 37 | * 38 | * 1.1 Mar-19-2008: Updated function implementation to correct for 39 | * branch-prediction. branch-prediction no longer 40 | * results in 5 cycles for 1 add and one taken-bne 41 | * hence breaking the function. The inner loop 42 | * now approximates 11 cycles. 43 | * 44 | *---------------------------------------------------------------------------- 45 | */ 46 | .section .text 47 | .align 4 48 | .global MicoSleepHelper 49 | .type MicoSleepHelper, @function 50 | MicoSleepHelper: 51 | .LM1: 52 | or r3, r0, r2 53 | /* .LM2 to .LM3 consists the inner loop; 54 | * because of branch prediction, be and bi 55 | * don't take the exact ticks specified in the 56 | * processor user guide; so to nullify their 57 | * effect, add a bunch of addi (1-cycle) 58 | * to reduce the uncertainty (in lieu of 59 | * simulating it in RTL) 60 | */ 61 | .LM2: 62 | be r3, r0, .LM3 63 | addi r3, r3,-1 64 | addi r3, r3, 1 65 | addi r3, r3,-1 66 | addi r3, r3, 1 67 | addi r3, r3,-1 68 | addi r3, r3, 1 69 | addi r3, r3,-1 70 | addi r3, r3, 0 71 | bi .LM2 72 | .LM3: 73 | addi r1, r1, -1 74 | bne r1, r0, .LM1 75 | .LM4: 76 | ret 77 | .size MicoSleepHelper, .-MicoSleepHelper 78 | 79 | -------------------------------------------------------------------------------- /firmware/crt0ram-smu.S: -------------------------------------------------------------------------------- 1 | /* 2 | * LatticeMico32 C startup code. 3 | * 4 | * Redistribution and use in source and binary forms, with or without 5 | * modification, are permitted provided that the following conditions 6 | * are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 | * SUCH DAMAGE. 24 | * 25 | * Modified for AMD SMU by Damien Zammit 26 | * 27 | */ 28 | 29 | /* From include/sys/signal.h */ 30 | #define SIGINT 2 /* interrupt */ 31 | #define SIGTRAP 5 /* trace trap */ 32 | #define SIGFPE 8 /* arithmetic exception */ 33 | #define SIGSEGV 11 /* segmentation violation */ 34 | 35 | #define SYSEXIT 1 36 | 37 | /* Exception handlers - Must be 32 bytes long. */ 38 | .section .boot, "ax", @progbits 39 | 40 | .global _start 41 | _start: 42 | 43 | .global _reset_handler 44 | .type _reset_handler, @function 45 | _reset_handler: 46 | xor r0, r0, r0 47 | xor r0, r0, r0 48 | wcsr IE, r0 49 | mvhi r1, hi(_reset_handler) 50 | ori r1, r1, lo(_reset_handler) 51 | wcsr EBA, r1 52 | wcsr DEBA, r1 53 | calli _crt0 54 | .size _reset_handler, .-_reset_handler 55 | 56 | .global _breakpoint_handler 57 | .type _breakpoint_handler, @function 58 | _breakpoint_handler: 59 | rcsr r7, DEBA 60 | addi r7, r7, 32 61 | b r7 62 | nop 63 | nop 64 | nop 65 | nop 66 | nop 67 | .size _breakpoint_handler, .-_breakpoint_handler 68 | 69 | .global _instruction_bus_error_handler 70 | .type _instruction_bus_error_handler, @function 71 | _instruction_bus_error_handler: 72 | rcsr r7, DEBA 73 | addi r7, r7, 64 74 | b r7 75 | nop 76 | nop 77 | nop 78 | nop 79 | nop 80 | .size _instruction_bus_error_handler, .-_instruction_bus_error_handler 81 | 82 | .global _watchpoint_handler 83 | .type _watchpoint_handler, @function 84 | _watchpoint_handler: 85 | rcsr r7, DEBA 86 | addi r7, r7, 96 87 | b r7 88 | nop 89 | nop 90 | nop 91 | nop 92 | nop 93 | .size _watchpoint_handler, .-_watchpoint_handler 94 | 95 | .global _data_bus_error_handler 96 | .type _data_bus_error_handler, @function 97 | _data_bus_error_handler: 98 | rcsr r7, DEBA 99 | addi r7, r7, 128 100 | b r7 101 | nop 102 | nop 103 | nop 104 | nop 105 | nop 106 | .size _data_bus_error_handler, .-_data_bus_error_handler 107 | 108 | .global _divide_by_zero_handler 109 | .type _divide_by_zero_handler, @function 110 | _divide_by_zero_handler: 111 | rcsr r7, DEBA 112 | addi r7, r7, 160 113 | b r7 114 | nop 115 | nop 116 | nop 117 | nop 118 | nop 119 | .size _divide_by_zero_handler, .-_divide_by_zero_handler 120 | 121 | .global _interrupt_handler 122 | .type _interrupt_handler, @function 123 | _interrupt_handler: 124 | sw (sp+0), ra 125 | calli _save_all 126 | mvi r1, SIGINT 127 | mvhi r1, hi(MicoISRHandler) 128 | ori r1, r1, lo(MicoISRHandler) 129 | call r1 130 | bi _restore_all_and_return 131 | nop 132 | .size _interrupt_handler, .-_interrupt_handler 133 | 134 | .global _system_call_handler 135 | .type _system_call_handler, @function 136 | _system_call_handler: 137 | rcsr r7, DEBA 138 | addi r7, r7, 224 139 | b r7 140 | nop 141 | nop 142 | nop 143 | nop 144 | nop 145 | .size _system_call_handler, .-_system_call_handler 146 | 147 | .global _crt0 148 | .type _crt0, @function 149 | _crt0: 150 | /* Clear r0 */ 151 | xor r0, r0, r0 152 | /* Setup stack and global pointer */ 153 | mvhi sp, hi(_fstack) 154 | ori sp, sp, lo(_fstack) 155 | mvhi gp, hi(_gp) 156 | ori gp, gp, lo(_gp) 157 | 158 | /* Relocate text */ 159 | mvhi r1, hi(_ftext) 160 | ori r1, r1, lo(_ftext) 161 | mvhi r2, hi(_ftext_rom) 162 | ori r2, r2, lo(_ftext_rom) 163 | be r1, r2, .L_done_text_relocation 164 | mvhi r3, (_etext) 165 | ori r3, r3, (_etext) 166 | calli _relocate_text 167 | .L_done_text_relocation: 168 | 169 | /* Relocate read-only data */ 170 | mvhi r1, hi(_frodata) 171 | ori r1, r1, lo(_frodata) 172 | mvhi r2, hi(_frodata_rom) 173 | ori r2, r2, lo(_frodata_rom) 174 | be r1, r2, .L_done_rodata_relocation 175 | mvhi r3, hi(_erodata) 176 | ori r3, r3, lo(_erodata) 177 | be r1, r3, .L_done_rodata_relocation 178 | sub r3, r3, r1 179 | mvhi r4, hi(memcpy) 180 | ori r4, r4, lo(memcpy) 181 | call r4 182 | .L_done_rodata_relocation: 183 | 184 | /* Relocate data */ 185 | mvhi r1, hi(_fdata) 186 | ori r1, r1, lo(_fdata) 187 | mvhi r2, hi(_fdata_rom) 188 | ori r2, r2, lo(_fdata_rom) 189 | be r1, r2, .L_done_data_relocation 190 | mvhi r3, hi(_edata) 191 | ori r3, r3, lo(_edata) 192 | be r1, r3, .L_done_data_relocation 193 | sub r3, r3, r1 194 | mvhi r4, hi(memcpy) 195 | ori r4, r4, lo(memcpy) 196 | call r4 197 | .L_done_data_relocation: 198 | 199 | /* Clear BSS */ 200 | mvhi r1, hi(_fbss) 201 | ori r1, r1, lo(_fbss) 202 | mvhi r3, hi(_ebss) 203 | ori r3, r3, lo(_ebss) 204 | .size _crt0, .-_crt0 205 | 206 | .global .ClearBSS 207 | .type .ClearBSS, @function 208 | .ClearBSS: 209 | be r1, r3, .CallConstructor 210 | sw (r1+0), r0 211 | addi r1, r1, 4 212 | bi .ClearBSS 213 | .size .ClearBSS, .-.ClearBSS 214 | 215 | .global .CallConstructor 216 | .type .CallConstructor, @function 217 | .CallConstructor: 218 | /* Call C++ constructors */ 219 | calli _init 220 | /* Call main program */ 221 | mvi r1, 0 222 | mvi r2, 0 223 | mvi r3, 0 224 | calli main 225 | /* Call exit, which doesn't return, to perform any clean up */ 226 | calli _fini 227 | calli _exit 228 | /* Save all registers onto the stack */ 229 | .size .CallConstructor, .-.CallConstructor 230 | 231 | .global _relocate_text 232 | .type _relocate_text, @function 233 | _relocate_text: 234 | lb r4, (r2+0) 235 | addi r2, r2, 1 236 | sb (r1+0), r4 237 | addi r1, r1, 1 238 | bne r1, r3, _relocate_text 239 | ret 240 | .size _relocate_text, .-_relocate_text 241 | 242 | .global _save_all 243 | .type _save_all, @function 244 | _save_all: 245 | addi sp, sp, -128 246 | sw (sp+4), r1 247 | sw (sp+8), r2 248 | sw (sp+12), r3 249 | sw (sp+16), r4 250 | sw (sp+20), r5 251 | sw (sp+24), r6 252 | sw (sp+28), r7 253 | sw (sp+32), r8 254 | sw (sp+36), r9 255 | sw (sp+40), r10 256 | sw (sp+44), r11 257 | sw (sp+48), r12 258 | sw (sp+52), r13 259 | sw (sp+56), r14 260 | sw (sp+60), r15 261 | sw (sp+64), r16 262 | sw (sp+68), r17 263 | sw (sp+72), r18 264 | sw (sp+76), r19 265 | sw (sp+80), r20 266 | sw (sp+84), r21 267 | sw (sp+88), r22 268 | sw (sp+92), r23 269 | sw (sp+96), r24 270 | sw (sp+100), r25 271 | sw (sp+104), r26 272 | sw (sp+108), r27 273 | sw (sp+120), ea 274 | sw (sp+124), ba 275 | /* ra and sp need special handling, as they have been modified */ 276 | lw r1, (sp+128) 277 | sw (sp+116), r1 278 | mv r1, sp 279 | addi r1, r1, 128 280 | sw (sp+112), r1 281 | xor r1, r1, r1 282 | wcsr ie, r1 283 | ret 284 | .size _save_all, .-_save_all 285 | 286 | .global _restore_all_and_return 287 | .type _restore_all_and_return, @function 288 | /* Restore all registers and return from exception */ 289 | _restore_all_and_return: 290 | addi r1, r0, 2 291 | wcsr ie, r1 292 | lw r1, (sp+4) 293 | lw r2, (sp+8) 294 | lw r3, (sp+12) 295 | lw r4, (sp+16) 296 | lw r5, (sp+20) 297 | lw r6, (sp+24) 298 | lw r7, (sp+28) 299 | lw r8, (sp+32) 300 | lw r9, (sp+36) 301 | lw r10, (sp+40) 302 | lw r11, (sp+44) 303 | lw r12, (sp+48) 304 | lw r13, (sp+52) 305 | lw r14, (sp+56) 306 | lw r15, (sp+60) 307 | lw r16, (sp+64) 308 | lw r17, (sp+68) 309 | lw r18, (sp+72) 310 | lw r19, (sp+76) 311 | lw r20, (sp+80) 312 | lw r21, (sp+84) 313 | lw r22, (sp+88) 314 | lw r23, (sp+92) 315 | lw r24, (sp+96) 316 | lw r25, (sp+100) 317 | lw r26, (sp+104) 318 | lw r27, (sp+108) 319 | lw ra, (sp+116) 320 | lw ea, (sp+120) 321 | lw ba, (sp+124) 322 | /* Stack pointer must be restored last, in case it has been updated */ 323 | lw sp, (sp+112) 324 | nop 325 | eret 326 | .size _restore_all_and_return, .-_restore_all_and_return 327 | 328 | .global _exit 329 | _exit: 330 | mvi r8, SYSEXIT 331 | scall 332 | .size _exit, .-_exit 333 | -------------------------------------------------------------------------------- /firmware/delay.h: -------------------------------------------------------------------------------- 1 | /* Free/Libre SMU firmware 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See .- 14 | */ 15 | 16 | extern void MicoSleepHelper(int tick, int clock); 17 | 18 | void mdelay(int ms) 19 | { 20 | MicoSleepHelper(ms, MICO_SLEEP_MILLISEC); 21 | } 22 | 23 | void udelay(int us) 24 | { 25 | MicoSleepHelper(us, MICO_SLEEP_MICROSEC); 26 | } 27 | 28 | -------------------------------------------------------------------------------- /firmware/makefirmware.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # 3 | # makefirmware.sh 4 | # Copyright (C) 2016 Damien Zammit 5 | # 6 | # This program is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # (at your option) any later version. 10 | # 11 | # This program is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | 17 | FIRMWARE=$1 18 | 19 | LINES=$(od -t x4 -w4 -v -An --endian=big $FIRMWARE|wc -l) 20 | FWLEN=$(printf "0x%08x," $LINES) 21 | FWHEX=$(od -t x4 -w4 -v -An --endian=big $FIRMWARE|awk '{print "0x"$1","}') 22 | SHA1HASH=$(python ../signsmu.py $1 | awk '{print $1","}') 23 | 24 | echo " 25 | /* 26 | * SMU FIRMWARE (Autogenerated by makefirmware.sh) 27 | * This firmware for SMU was compiled from source 28 | * available in 'smutool' by Damien Zammit (2016) 29 | */ 30 | 31 | #ifndef _SMUFIRMWARE_H 32 | #define _SMUFIRMWARE_H 33 | 34 | UINT32 FirmwareTNHeader[] = { 35 | 0x554D535F, 36 | 0x554D535F, 37 | 0x0000F030, 38 | 0x00002000, 39 | 0x00010000, 40 | 0x7E26E3A5, 41 | 0x00004E54, 42 | 0x00000000, 43 | 0x00000000, 44 | 0x00000000, 45 | 0x00000000, 46 | 0x00000000, 47 | }; 48 | 49 | UINT32 FirmwareTN[] = { 50 | 0x000a00cb, 51 | 0x00000040," 52 | echo "$FWLEN" 53 | echo " 0x00010100," 54 | echo "$SHA1HASH" 55 | echo " 0x00010100, //0x0001d97c, 56 | 0x00010100, //0x0001da8c, 57 | 0x00000000, 58 | 0x00010100, //0x0001daad, 59 | 0x00010100, //0x0001dabc, 60 | 0x00010100, //0x0001d9d0, 61 | 0x00010100, //0x0001dbf4, 62 | 0x00000000, 63 | 0x00000000, 64 | 0x00000000, 65 | 0x00000000, 66 | 0x00000000, 67 | 0x00000000, 68 | 0x00000000, 69 | 0x00000000, 70 | 0x00000000, 71 | 0x00000000, 72 | 0x00000000, 73 | 0x00000000, 74 | 0x00000000, 75 | 0x00000000, 76 | 0x00000000, 77 | 0x00000000, 78 | 0x00000000, 79 | 0x00000000, 80 | 0x00000000, 81 | 0x00000000, 82 | 0x00000000, 83 | 0x00000000, 84 | 0x00000000, 85 | 0x00000000, 86 | 0x00000000, 87 | 0x00000000, 88 | 0x00000000, 89 | 0x00000000, 90 | 0x00000000, 91 | 0x00000000, 92 | 0x00000000, 93 | 0x00000000, 94 | 0x00000000, 95 | 0x00000000, 96 | 0x00000000, 97 | 0x00000000, 98 | 0x00000000, 99 | 0x00000000, 100 | 0x00000000, 101 | 0x00000000, 102 | 0x00000000, 103 | 0x00000000, 104 | 0x00000000, 105 | 0x00000000, 106 | 0x00000000, 107 | 0x00000000, 108 | 0x00000000, 109 | 0xaa55aa55," 110 | echo "$FWHEX" 111 | echo "};" 112 | echo "#endif" 113 | -------------------------------------------------------------------------------- /firmware/memcpy.c: -------------------------------------------------------------------------------- 1 | /* Free/Libre SMU firmware 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | *- 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See .- 14 | */ 15 | 16 | #include 17 | void *memcpy(void *vdest, const void *vsrc, size_t bytes) 18 | { 19 | const char *src = vsrc; 20 | char *dest = vdest; 21 | int i; 22 | 23 | for (i = 0; i < (int)bytes; i++) 24 | dest[i] = src[i]; 25 | 26 | return vdest; 27 | } 28 | -------------------------------------------------------------------------------- /firmware/ops.h: -------------------------------------------------------------------------------- 1 | /* Free/Libre SMU firmware 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | *- 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See .- 14 | */ 15 | 16 | #ifndef _OPS_H 17 | #define _OPS_H 18 | 19 | inline int __mulsi3 (int a, int b) 20 | { 21 | int c; 22 | asm ("mul %0, %1, %2" 23 | :"=r"(c) 24 | :"r"(a),"r"(b) 25 | : 26 | ); 27 | return c; 28 | } 29 | 30 | inline int __lshrsi3 (int a, int b) 31 | { 32 | int c; 33 | asm ("sr %0, %1, %2" 34 | :"=r"(c) 35 | :"r"(a),"r"(b) 36 | : 37 | ); 38 | return c; 39 | } 40 | 41 | inline int __lshlsi3 (int a, int b) 42 | { 43 | int c; 44 | asm ("sl %0, %1, %2" 45 | :"=r"(c) 46 | :"r"(a),"r"(b) 47 | : 48 | ); 49 | return c; 50 | } 51 | 52 | inline int __ashrsi3 (int a, int b) 53 | { 54 | int c; 55 | asm ("sr %0, %1, %2" 56 | :"=r"(c) 57 | :"r"(a),"r"(b) 58 | : 59 | ); 60 | return c; 61 | } 62 | 63 | inline int __ashlsi3 (int a, int b) 64 | { 65 | int c; 66 | asm ("sl %0, %1, %2" 67 | :"=r"(c) 68 | :"r"(a),"r"(b) 69 | : 70 | ); 71 | return c; 72 | } 73 | 74 | inline unsigned int __udivsi3 (unsigned int a, unsigned int b) 75 | { 76 | unsigned int c; 77 | asm ("divu %0, %1, %2" 78 | :"=r"(c) 79 | :"r"(a),"r"(b) 80 | : 81 | ); 82 | return c; 83 | } 84 | 85 | inline int __divsi3 (int a, int b) 86 | { 87 | unsigned int c; 88 | asm ("divu %0, %1, %2" 89 | :"=r"(c) 90 | :"r"(a),"r"(b) 91 | : 92 | ); 93 | return c; 94 | } 95 | #endif 96 | -------------------------------------------------------------------------------- /firmware/servicereq.h: -------------------------------------------------------------------------------- 1 | /* Free/Libre SMU firmware 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | *- 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See .- 14 | */ 15 | 16 | typedef void(*ISRCallback)(unsigned int, void *); 17 | 18 | typedef struct ISREntry{ 19 | ISRCallback Callback; 20 | void *Context; 21 | } ISREntry_t; 22 | 23 | static ISREntry_t ISREntryTable[32]; 24 | 25 | void MicoISRHandler(void); 26 | void smu_service_request(unsigned int); 27 | -------------------------------------------------------------------------------- /firmware/smu.c: -------------------------------------------------------------------------------- 1 | /* Free/Libre SMU firmware 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | *- 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | */ 14 | 15 | #include "smu.h" 16 | #include "delay.h" 17 | #include "servicereq.h" 18 | 19 | void main(void) 20 | { 21 | int i; 22 | int ie; 23 | int e3; 24 | 25 | /* disable interrupts */ 26 | asm volatile ("rcsr %0,ie":"=r"(ie)); 27 | ie &= (~0x1); 28 | asm volatile ("wcsr ie, %0"::"r"(ie)); 29 | 30 | for (i = 0; i < 32; i++) { 31 | ISREntryTable[i].Callback = 0; 32 | ISREntryTable[i].Context = 0; 33 | } 34 | 35 | /* clear all pending interrupts */ 36 | asm volatile ("wcsr ip, %0"::"r"(0xffffffff)); 37 | 38 | /* tell x86 that interrupts are ready */ 39 | write32(0xe0003004, INTACK | INTDONE); 40 | write32(0x1f380, 1); 41 | 42 | SMU_POST(0xcb); 43 | 44 | while (1) { 45 | e3 = read32(0xe0003000); 46 | if ((e3 & ~1)) { 47 | write32(0xe0003004, INTACK); 48 | smu_service_request(e3); 49 | write32(0xe0003004, INTACK | INTDONE); 50 | } 51 | 52 | mdelay(30); 53 | } 54 | } 55 | -------------------------------------------------------------------------------- /firmware/smu.h: -------------------------------------------------------------------------------- 1 | /* Free/Libre SMU firmware 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | *- 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See .- 14 | */ 15 | 16 | #ifndef _SMU_H 17 | #define _SMU_H 18 | 19 | typedef unsigned char u8; 20 | typedef unsigned short u16; 21 | typedef unsigned int u32; 22 | 23 | #define SMU_POST(x) write32(0xe0003024, (x & 0xff)) 24 | 25 | #define SMC_MSG_AUTH 0 26 | #define SMC_MSG_HALT 1 27 | #define SMC_MSG_PHY_LN_OFF 2 28 | #define SMC_MSG_PHY_LN_ON 3 29 | #define SMC_MSG_DDI_PHY_OFF 4 30 | #define SMC_MSG_DDI_PHY_ON 5 31 | #define SMC_MSG_CASCADE_PLL_OFF 6 32 | #define SMC_MSG_CASCADE_PLL_ON 7 33 | #define SMC_MSG_PWR_OFF_x16 8 34 | #define SMC_MSG_CONFIG_LCLK_DPM 9 35 | #define SMC_MSG_FLUSH_DATA_CACHE 10 36 | #define SMC_MSG_FLUSH_INSTRUCTION_CACHE 11 37 | #define SMC_MSG_CONFIG_VPC_ACCUMULATOR 12 38 | #define SMC_MSG_CONFIG_BAPM 13 39 | #define SMC_MSG_CONFIG_TDC_LIMIT 14 40 | #define SMC_MSG_CONFIG_LPMx 15 41 | #define SMC_MSG_CONFIG_HTC_LIMIT 16 42 | #define SMC_MSG_CONFIG_THERMAL_CNTL 17 43 | #define SMC_MSG_CONFIG_VOLTAGE_CNTL 18 44 | #define SMC_MSG_CONFIG_TDP_CNTL 19 45 | #define SMC_MSG_EN_PM_CNTL 20 46 | #define SMC_MSG_DIS_PM_CNTL 21 47 | #define SMC_MSG_CONFIG_NBDPM 22 48 | #define SMC_MSG_CONFIG_LOADLINE 23 49 | #define SMC_MSG_ADJUST_LOADLINE 24 50 | #define SMC_MSG_RECONFIGURE 25 51 | #define SMC_MSG_PCIE_PLLSWITCH 27 52 | #define SMC_MSG_ENABLE_BAPM 32 53 | #define SMC_MSG_DISABLE_BAPM 33 54 | #define SMC_MSG_READ_ROM_HACK 99 55 | 56 | #define MICO32_CPU_CLOCK_MHZ (25000000) 57 | #define MICO_SLEEP_MICROSEC (MICO32_CPU_CLOCK_MHZ/11000000) 58 | #define MICO_SLEEP_MILLISEC (MICO32_CPU_CLOCK_MHZ/11000) 59 | 60 | #define write8(addr, val) (*((volatile u8 *)(addr))) = (val) 61 | #define read8(addr) (*((volatile u8 *)(addr))) 62 | #define write16(addr, val) (*((volatile u16 *)(addr))) = (val) 63 | #define read16(addr) (*((volatile u16 *)(addr))) 64 | #define write32(addr, val) (*((volatile u32 *)(addr))) = (val) 65 | #define read32(addr) (*((volatile u32 *)(addr))) 66 | 67 | #define INTACK 1 68 | #define INTDONE 2 69 | 70 | /// x1F200 71 | typedef union { 72 | struct { 73 | u32 StateValid:1 ; 74 | u32 Reserved_7_1:7 ; 75 | u32 LclkDivider:8 ; 76 | u32 VID:8 ; 77 | u32 LowVoltageReqThreshold:8 ; 78 | } Field; 79 | u32 Value; 80 | } x1F200_t; 81 | 82 | /// x1F208 83 | typedef union { 84 | struct { 85 | u32 HysteresisUp:8 ; 86 | u32 HysteresisDown:8 ; 87 | u32 ResidencyCounter:16; 88 | } Field; 89 | u32 Value; 90 | } x1F208_t; 91 | 92 | /// x1F210 93 | typedef union { 94 | struct { 95 | u32 ActivityThreshold:8 ; 96 | u32 Reserved_31_8:24; 97 | } Field; 98 | u32 Value; 99 | } x1F210_t; 100 | 101 | /// x1F220 102 | typedef union { 103 | struct { 104 | u32 StateValid:1 ; 105 | u32 Reserved_7_1:7 ; 106 | u32 LclkDivider:8 ; 107 | u32 VID:8 ; 108 | u32 LowVoltageReqThreshold:8 ; 109 | } Field; 110 | u32 Value; 111 | } x1F220_t; 112 | 113 | /// x1F228 114 | typedef union { 115 | struct { 116 | u32 HysteresisUp:8 ; 117 | u32 HysteresisDown:8 ; 118 | u32 ResidencyCounter:16; 119 | } Field; 120 | u32 Value; 121 | } x1F228_t; 122 | 123 | /// x1F230 124 | typedef union { 125 | struct { 126 | u32 ActivityThreshold:8 ; 127 | u32 Reserved_31_8:24; 128 | } Field; 129 | u32 Value; 130 | } x1F230_t; 131 | 132 | /// x1F240 133 | typedef union { 134 | struct { 135 | u32 StateValid:1 ; 136 | u32 Reserved_7_1:7 ; 137 | u32 LclkDivider:8 ; 138 | u32 VID:8 ; 139 | u32 LowVoltageReqThreshold:8 ; 140 | } Field; 141 | u32 Value; 142 | } x1F240_t; 143 | 144 | /// x1F248 145 | typedef union { 146 | struct { 147 | u32 HysteresisUp:8 ; 148 | u32 HysteresisDown:8 ; 149 | u32 ResidencyCounter:16; 150 | } Field; 151 | u32 Value; 152 | } x1F248_t; 153 | 154 | /// x1F250 155 | typedef union { 156 | struct { 157 | u32 ActivityThreshold:8 ; 158 | u32 Reserved_31_8:24; 159 | } Field; 160 | u32 Value; 161 | } x1F250_t; 162 | 163 | /// x1F260 164 | typedef union { 165 | struct { 166 | u32 StateValid:1 ; 167 | u32 Reserved_7_1:7 ; 168 | u32 LclkDivider:8 ; 169 | u32 VID:8 ; 170 | u32 LowVoltageReqThreshold:8 ; 171 | } Field; 172 | u32 Value; 173 | } x1F260_t; 174 | 175 | /// x1F268 176 | typedef union { 177 | struct { 178 | u32 HysteresisUp:8 ; 179 | u32 HysteresisDown:8 ; 180 | u32 ResidencyCounter:16; 181 | } Field; 182 | u32 Value; 183 | } x1F268_t; 184 | 185 | /// x1F270 186 | typedef union { 187 | struct { 188 | u32 ActivityThreshold:8 ; 189 | u32 Reserved_31_8:24; 190 | } Field; 191 | u32 Value; 192 | } x1F270_t; 193 | 194 | /// x1F280 195 | typedef union { 196 | struct { 197 | u32 StateValid:1 ; 198 | u32 Reserved_7_1:7 ; 199 | u32 LclkDivider:8 ; 200 | u32 VID:8 ; 201 | u32 LowVoltageReqThreshold:8 ; 202 | } Field; 203 | u32 Value; 204 | } x1F280_t; 205 | 206 | /// x1F288 207 | typedef union { 208 | struct { 209 | u32 HysteresisUp:8 ; 210 | u32 HysteresisDown:8 ; 211 | u32 ResidencyCounter:16; 212 | } Field; 213 | u32 Value; 214 | } x1F288_t; 215 | 216 | /// x1F290 217 | typedef union { 218 | struct { 219 | u32 ActivityThreshold:8 ; 220 | u32 Reserved_31_8:24; 221 | } Field; 222 | u32 Value; 223 | } x1F290_t; 224 | 225 | /// x1F2A0 226 | typedef union { 227 | struct { 228 | u32 StateValid:1 ; 229 | u32 Reserved_7_1:7 ; 230 | u32 LclkDivider:8 ; 231 | u32 VID:8 ; 232 | u32 LowVoltageReqThreshold:8 ; 233 | } Field; 234 | u32 Value; 235 | } x1F2A0_t; 236 | 237 | /// x1F2A8 238 | typedef union { 239 | struct { 240 | u32 HysteresisUp:8 ; 241 | u32 HysteresisDown:8 ; 242 | u32 ResidencyCounter:16; 243 | } Field; 244 | u32 Value; 245 | } x1F2A8_t; 246 | 247 | /// x1F2B0 248 | typedef union { 249 | struct { 250 | u32 ActivityThreshold:8 ; 251 | u32 Reserved_31_8:24; 252 | } Field; 253 | u32 Value; 254 | } x1F2B0_t; 255 | 256 | /// x1F2C0 257 | typedef union { 258 | struct { 259 | u32 StateValid:1 ; 260 | u32 Reserved_7_1:7 ; 261 | u32 LclkDivider:8 ; 262 | u32 VID:8 ; 263 | u32 LowVoltageReqThreshold:8 ; 264 | } Field; 265 | u32 Value; 266 | } x1F2C0_t; 267 | 268 | /// x1F2C8 269 | typedef union { 270 | struct { 271 | u32 HysteresisUp:8 ; 272 | u32 HysteresisDown:8 ; 273 | u32 ResidencyCounter:16; 274 | } Field; 275 | u32 Value; 276 | } x1F2C8_t; 277 | 278 | /// x1F2D0 279 | typedef union { 280 | struct { 281 | u32 ActivityThreshold:8 ; 282 | u32 Reserved_31_8:24; 283 | } Field; 284 | u32 Value; 285 | } x1F2D0_t; 286 | 287 | /// x1F2E0 288 | typedef union { 289 | struct { 290 | u32 StateValid:1 ; 291 | u32 Reserved_7_1:7 ; 292 | u32 LclkDivider:8 ; 293 | u32 VID:8 ; 294 | u32 LowVoltageReqThreshold:8 ; 295 | } Field; 296 | u32 Value; 297 | } x1F2E0_t; 298 | 299 | /// x1F2E8 300 | typedef union { 301 | struct { 302 | u32 HysteresisUp:8 ; 303 | u32 HysteresisDown:8 ; 304 | u32 ResidencyCounter:16; 305 | } Field; 306 | u32 Value; 307 | } x1F2E8_t; 308 | 309 | /// x1F2F0 310 | typedef union { 311 | struct { 312 | u32 ActivityThreshold:8 ; 313 | u32 Reserved_31_8:24; 314 | } Field; 315 | u32 Value; 316 | } x1F2F0_t; 317 | 318 | /// x1F300 319 | typedef union { 320 | struct { 321 | u32 LclkDpmEn:1 ; 322 | u32 Reserved_7_1:7 ; 323 | u32 LclkDpmType:1 ; 324 | u32 Reserved_15_9:7 ; 325 | u32 LclkDpmBootState:8 ; 326 | u32 VoltageChgEn:1 ; 327 | u32 Reserved_31_25:7 ; 328 | } Field; 329 | u32 Value; 330 | } x1F300_t; 331 | 332 | /// x1F308 333 | typedef union { 334 | struct { 335 | u32 LclkThermalThrottlingEn:1 ; 336 | u32 Reserved_7_1:7 ; 337 | u32 TemperatureSel:1 ; 338 | u32 Reserved_15_9:7 ; 339 | u32 LclkTtMode:3 ; 340 | u32 :13; 341 | } Field; 342 | u32 Value; 343 | } x1F308_t; 344 | 345 | /// x1F30C 346 | typedef union { 347 | struct { 348 | u32 LowThreshold:16; 349 | u32 HighThreshold:16; 350 | } Field; 351 | u32 Value; 352 | } x1F30C_t; 353 | 354 | /// x1F380 355 | typedef union { 356 | struct { 357 | u32 InterruptsEnabled:1 ; 358 | u32 Reserved_23_1:23; 359 | u32 TestCount:8 ; 360 | } Field; 361 | u32 Value; 362 | } x1F380_t; 363 | 364 | /// x1F384 365 | typedef union { 366 | struct { 367 | u32 FirmwareVid:8 ; 368 | u32 Reserved_31_8:24; 369 | } Field; 370 | u32 Value; 371 | } x1F384_t; 372 | 373 | /// x1F388 374 | typedef union { 375 | struct { 376 | u32 CsrAddr:6 ; 377 | u32 TcenId:4 ; 378 | u32 Reserved_31_10:22; 379 | } Field; 380 | u32 Value; 381 | } x1F388_t; 382 | 383 | /// x1F39C 384 | typedef union { 385 | struct { 386 | u32 Rx:1 ; 387 | u32 Tx:1 ; 388 | u32 Core:1 ; 389 | u32 SkipPhy:1 ; 390 | u32 SkipCore:1 ; 391 | u32 Reserved_15_5:11; 392 | u32 LowerLaneID:8 ; 393 | u32 UpperLaneID:8 ; 394 | } Field; 395 | u32 Value; 396 | } x1F39C_t; 397 | 398 | /// x1F3D8 399 | typedef union { 400 | struct { 401 | u32 LoadLineTrim3:8 ; 402 | u32 LoadLineTrim2:8 ; 403 | u32 LoadLineTrim1:8 ; 404 | u32 LoadLineTrim0:8 ; 405 | } Field; 406 | u32 Value; 407 | } x1F3D8_t; 408 | 409 | /// x1F3DC 410 | typedef union { 411 | struct { 412 | u32 LoadLineTrim7:8 ; 413 | u32 LoadLineTrim6:8 ; 414 | u32 LoadLineTrim5:8 ; 415 | u32 LoadLineTrim4:8 ; 416 | } Field; 417 | u32 Value; 418 | } x1F3DC_t; 419 | 420 | /// x1F3F8 421 | typedef union { 422 | struct { 423 | u32 SviInitLoadLineVdd:8 ; 424 | u32 SviInitLoadLineVddNB:8 ; 425 | u32 SviTrimValueVdd:8 ; 426 | u32 SviTrimValueVddNB:8 ; 427 | } Field; 428 | u32 Value; 429 | } x1F3F8_t; 430 | 431 | /// x1F3FC 432 | typedef union { 433 | struct { 434 | u32 SviVidStepBase:16; 435 | u32 SviVidStep:16; 436 | } Field; 437 | u32 Value; 438 | } x1F3FC_t; 439 | 440 | /// x1F400 441 | typedef union { 442 | struct { 443 | u32 SviLoadLineOffsetVdd:8 ; 444 | u32 SviLoadLineOffsetVddNB:8 ; 445 | u32 PstateMax:8 ; 446 | u32 Reserved_31_24:8 ; 447 | } Field; 448 | u32 Value; 449 | } x1F400_t; 450 | 451 | /// x1F404 452 | typedef union { 453 | struct { 454 | u32 LoadLineOffset3:8 ; 455 | u32 LoadLineOffset2:8 ; 456 | u32 LoadLineOffset1:8 ; 457 | u32 LoadLineOffset0:8 ; 458 | } Field; 459 | u32 Value; 460 | } x1F404_t; 461 | 462 | /// x1F428 463 | typedef union { 464 | struct { 465 | u32 EnableVpcAccumulators:1 ; 466 | u32 EnableBapm:1 ; 467 | u32 EnableTdcLimit:1 ; 468 | u32 EnableLpmx:1 ; 469 | u32 field_4:1; 470 | u32 EnableNbDpm:1 ; 471 | u32 EnableLoadline:1 ; 472 | u32 Reserved_15_7:9 ; 473 | u32 :1 ; 474 | u32 :1 ; 475 | u32 :1 ; 476 | u32 line180 :1 ; 477 | u32 Reserved_23_20:4 ; 478 | u32 PstateAllCpusIdle:3 ; 479 | u32 NbPstateAllCpusIdle:1 ; 480 | u32 BapmCoeffOverride:1 ; 481 | u32 SviMode:1 ; 482 | u32 Reserved_31_30:2 ; 483 | } Field; 484 | u32 Value; 485 | } x1F428_t; 486 | 487 | /// x1F460 488 | typedef union { 489 | struct { 490 | u32 LclkDpm:8 ; 491 | u32 ThermalCntl:8 ; 492 | u32 VoltageCntl:8 ; 493 | u32 Loadline:8 ; 494 | } Field; 495 | u32 Value; 496 | } x1F460_t; 497 | 498 | /// x1F464 499 | typedef union { 500 | struct { 501 | u32 SclkDpm:8 ; 502 | u32 StaticSimdPgCntl:8 ; 503 | u32 DynSimdPgCntl:8 ; 504 | u32 TdpCntl:8 ; 505 | } Field; 506 | u32 Value; 507 | } x1F464_t; 508 | 509 | /// x1F468 510 | typedef union { 511 | struct { 512 | u32 TimerPeriod:32; 513 | } Field; 514 | u32 Value; 515 | } x1F468_t; 516 | 517 | /// x1F46C 518 | typedef union { 519 | struct { 520 | u32 VpcPeriod:16; 521 | u32 BapmPeriod:8 ; 522 | u32 LpmxPeriod:8 ; 523 | } Field; 524 | u32 Value; 525 | } x1F46C_t; 526 | 527 | /// x1F5F8 528 | typedef union { 529 | struct { 530 | u32 Dpm0PgNbPsLo:2 ; 531 | u32 Dpm0PgNbPsHi:2 ; 532 | u32 DpmXNbPsLo:2 ; 533 | u32 DpmXNbPsHi:2 ; 534 | u32 Hysteresis:8 ; 535 | u32 SkipPG:1 ; 536 | u32 SkipDPM0:1 ; 537 | u32 Reserved_21_18:4 ; 538 | u32 EnableNbPsi1:1 ; 539 | u32 EnableDpmPstatePoll:1 ; 540 | u32 Reserved_31_24:8 ; 541 | } Field; 542 | u32 Value; 543 | } x1F5F8_t; 544 | 545 | /// x1F5FC 546 | typedef union { 547 | struct { 548 | u32 ChangeInProgress:1 ; 549 | u32 CurrentPstatePair:1 ; 550 | u32 Reserved_7_2:6 ; 551 | u32 PSI1Sts:1 ; 552 | u32 Reserved_31_9:23; 553 | } Field; 554 | u32 Value; 555 | } x1F5FC_t; 556 | 557 | /// x1F610 558 | typedef union { 559 | struct { 560 | u32 RESERVED:8 ; 561 | u32 GFXH:8 ; 562 | u32 GFXL:8 ; 563 | u32 GPPSB:8 ; 564 | } Field; 565 | u32 Value; 566 | } x1F610_t; 567 | 568 | /// x1F628 569 | typedef union { 570 | struct { 571 | u32 Reserved_15_0:16; 572 | u32 HtcActivePstateLimit:8; 573 | u32 Reserved_31_24:8; 574 | } Field; 575 | u32 Value; 576 | } x1F628_t; 577 | 578 | /// x1F62C 579 | typedef union { 580 | struct { 581 | u32 Idd:16; 582 | u32 Iddnb:16; 583 | } Field; 584 | u32 Value; 585 | } x1F62C_t; 586 | 587 | /// x1F630 588 | typedef union { 589 | struct { 590 | u32 RECONF_WAIT:8; 591 | u32 RECONF_WRAPPER:8; 592 | u32 Reserved:16; 593 | } Field; 594 | u32 Value; 595 | } x1F630_t; 596 | 597 | /// x1F638 598 | typedef union { 599 | struct { 600 | u32 TdcPeriod:8 ; 601 | u32 HtcPeriod:8 ; 602 | u32 NbdpmPeriod:8 ; 603 | u32 PginterlockPeriod:8 ; 604 | } Field; 605 | u32 Value; 606 | } x1F638_t; 607 | 608 | /// x1F6E4 609 | typedef union { 610 | struct { 611 | u32 DdrVoltFloor:8 ; 612 | u32 BapmDdrVoltFloor:8 ; 613 | u32 Reserved:16; 614 | } Field; 615 | u32 Value; 616 | } x1F6E4_t; 617 | 618 | /// x1F6B4 619 | typedef union { 620 | struct { 621 | u32 TjOffset:8 ; 622 | u32 Reserved:24; 623 | } Field; 624 | u32 Value; 625 | } x1F6B4_t; 626 | 627 | /// x1F840 628 | typedef union { 629 | struct { 630 | u32 IddspikeOCP:16; 631 | u32 IddNbspikeOCP:16; 632 | } Field; 633 | u32 Value; 634 | } x1F840_t; 635 | 636 | /// x1F844 637 | typedef union { 638 | struct { 639 | u32 CsrAddr:6; 640 | u32 TcenId:4; 641 | u32 Reserved_31_10:22; 642 | } Field; 643 | u32 Value; 644 | } x1F844_t; 645 | 646 | /// x1F848 647 | typedef union { 648 | struct { 649 | u32 CsrAddr:6; 650 | u32 TcenId:4; 651 | u32 Reserved_31_10:22; 652 | } Field; 653 | u32 Value; 654 | } x1F848_t; 655 | 656 | /// x1F84C 657 | typedef union { 658 | struct { 659 | u32 CsrAddr:6; 660 | u32 TcenId:4; 661 | u32 Reserved_31_10:22; 662 | } Field; 663 | u32 Value; 664 | } x1F84C_t; 665 | 666 | /// x1F870 667 | typedef union { 668 | struct { 669 | u32 AmbientTempBase:8; 670 | u32 BAPMTI_TjOffset_2:8; 671 | u32 BAPMTI_TjOffset_1:8; 672 | u32 BAPMTI_TjOffset_0:8; 673 | } Field; 674 | u32 Value; 675 | } x1F870_t; 676 | 677 | /// x1F878 678 | typedef union { 679 | struct { 680 | u32 FUSE_DATA:32; 681 | } Field; 682 | u32 Value; 683 | } x1F878_t; 684 | 685 | /// x1F87C 686 | typedef union { 687 | struct { 688 | u32 LL_PCIE_LoadStep:16; 689 | u32 LL_VddNbLoadStepBase:16; 690 | } Field; 691 | u32 Value; 692 | } x1F87C_t; 693 | 694 | /// x1F880 695 | typedef union { 696 | struct { 697 | u32 LL_VCE_LoadStep:16; 698 | u32 LL_UVD_LoadStep:16; 699 | } Field; 700 | u32 Value; 701 | } x1F880_t; 702 | 703 | /// x1F884 704 | typedef union { 705 | struct { 706 | u32 LL_DCE2_LoadStep:16; 707 | u32 LL_DCE_LoadStep:16; 708 | } Field; 709 | u32 Value; 710 | } x1F884_t; 711 | 712 | /// x1F888 713 | typedef union { 714 | struct { 715 | u32 VddNbTdp:16; 716 | u32 LL_GPU_LoadStep:16; 717 | } Field; 718 | u32 Value; 719 | } x1F888_t; 720 | 721 | /// x1F88C 722 | typedef union { 723 | struct { 724 | u32 NbVid_3:8 ; 725 | u32 NbVid_2:8 ; 726 | u32 NbVid_1:8 ; 727 | u32 NbVid_0:8 ; 728 | } Field; 729 | u32 Value; 730 | } x1F88C_t; 731 | 732 | /// x1F890 733 | typedef union { 734 | struct { 735 | u32 CpuVid_3:8 ; 736 | u32 CpuVid_2:8 ; 737 | u32 CpuVid_1:8 ; 738 | u32 CpuVid_0:8 ; 739 | } Field; 740 | u32 Value; 741 | } x1F890_t; 742 | 743 | /// x1F894 744 | typedef union { 745 | struct { 746 | u32 CpuVid_7:8 ; 747 | u32 CpuVid_6:8 ; 748 | u32 CpuVid_5:8 ; 749 | u32 CpuVid_4:8 ; 750 | } Field; 751 | u32 Value; 752 | } x1F894_t; 753 | 754 | /// x1F8D4 755 | typedef union { 756 | struct { 757 | u32 BapmPstateVid_3:8; 758 | u32 BapmPstateVid_2:8; 759 | u32 BapmPstateVid_1:8; 760 | u32 BapmPstateVid_0:8; 761 | } Field; 762 | u32 Value; 763 | } x1F8D4_t; 764 | 765 | /// x1F8D8 766 | typedef union { 767 | struct { 768 | u32 BapmPstateVid_7:8; 769 | u32 BapmPstateVid_6:8; 770 | u32 BapmPstateVid_5:8; 771 | u32 BapmPstateVid_4:8; 772 | } Field; 773 | u32 Value; 774 | } x1F8D8_t; 775 | 776 | /// x1F8DC 777 | typedef union { 778 | struct { 779 | u32 SClkVid3:8; 780 | u32 SClkVid2:8; 781 | u32 SClkVid1:8; 782 | u32 SClkVid0:8; 783 | } Field; 784 | u32 Value; 785 | } x1F8DC_t; 786 | 787 | /// x1F8E0 788 | typedef union { 789 | struct { 790 | u32 BapmSclkVid_2:8; 791 | u32 BapmSclkVid_1:8; 792 | u32 BapmSclkVid_0:8; 793 | u32 DdrVoltFloor:8; 794 | } Field; 795 | u32 Value; 796 | } x1F8E0_t; 797 | 798 | /// x1F8E4 799 | typedef union { 800 | struct { 801 | u32 BapmNbVid_1:8; 802 | u32 BapmNbVid_0:8; 803 | u32 BapmDdrVoltFloor:8; 804 | u32 BapmSclkVid_3:8; 805 | } Field; 806 | u32 Value; 807 | } x1F8E4_t; 808 | 809 | /// x1F8E8 810 | typedef union { 811 | struct { 812 | u32 Reserved_15_0:16; 813 | u32 BapmNbVid_3:8; 814 | u32 BapmNbVid_2:8; 815 | } Field; 816 | u32 Value; 817 | } x1F8E8_t; 818 | 819 | /// x1F85C 820 | typedef union { 821 | struct { 822 | u32 VCETdp:20; 823 | u32 spare8:1; 824 | u32 TdpAgeValue:3; 825 | u32 TdpAgeRate:8; 826 | } Field; 827 | u32 Value; 828 | } x1F85C_t; 829 | 830 | /// x1F860 831 | typedef union { 832 | struct { 833 | u32 BAPMTI_TjHyst_1:8; 834 | u32 BAPMTI_TjMax_1:8; 835 | u32 BAPMTI_TjHyst_0:8; 836 | u32 BAPMTI_TjMax_0:8; 837 | } Field; 838 | u32 Value; 839 | } x1F860_t; 840 | 841 | /// x1F864 842 | typedef union { 843 | struct { 844 | u32 PCIe2PhyOffset:8; 845 | u32 PCIe1PhyOffset:8; 846 | u32 BAPMTI_GpuTjHyst:8; 847 | u32 BAPMTI_GpuTjMax:8; 848 | } Field; 849 | u32 Value; 850 | } x1F864_t; 851 | 852 | /// x1F86C 853 | typedef union { 854 | struct { 855 | u32 Reserved_22_0:23; 856 | u32 BapmLhtcCap:1; 857 | u32 Reserved_31_24:8; 858 | } Field; 859 | u32 Value; 860 | } x1F86C_t; 861 | 862 | /// x1FE00 863 | typedef union { 864 | struct { 865 | u32 Data:32; 866 | } Field; 867 | u32 Value; 868 | } x1FE00_t; 869 | 870 | 871 | /////////////////////////////////////// 872 | // Hardware registers 873 | 874 | /// xE0000004 875 | typedef union { 876 | struct { 877 | u32 RCU_TST_jpc_rep_req:1 ; 878 | u32 RCU_TST_jpc_rep_done:1 ; 879 | u32 drv_rst_mode:1 ; 880 | u32 SMU_DC_efuse_status_invalid:1 ; 881 | u32 Reserved:1 ; 882 | u32 TST_RCU_jpc_DtmSMSCntDone:1 ; 883 | u32 TP_Tester:1 ; 884 | u32 boot_seq_done:1 ; 885 | u32 sclk_deep_sleep_exit:1 ; 886 | u32 BREAK_PT1_ACTIVE:1 ; 887 | u32 BREAK_PT2_ACTIVE:1 ; 888 | u32 FCH_HALT:1 ; 889 | u32 FCH_LOCKDOWN_WRITE_DIS:1 ; 890 | u32 RCU_GIO_fch_lockdown:1 ; 891 | u32 Reserved14_23:10; 892 | u32 lm32_irq31_sel:2 ; 893 | u32 Reserved26_31:6 ; 894 | } Field; 895 | u32 Value; 896 | } xE0000004_t; 897 | 898 | /// xE0000120 899 | typedef union { 900 | struct { 901 | u32 ActivityCntRst:1 ; 902 | u32 PeriodCntRst:1 ; 903 | u32 Reserved_2_2:1 ; 904 | u32 BusyCntSel:2 ; 905 | u32 Reserved_7_5:3 ; 906 | u32 EnBifCnt:1 ; 907 | u32 EnOrbUsCnt:1 ; 908 | u32 EnOrbDsCnt:1 ; 909 | u32 Reserved_31_11:21; 910 | } Field; 911 | u32 Value; 912 | } xE0000120_t; 913 | 914 | /// xE0001008 915 | typedef union { 916 | struct { 917 | u32 SClkVid0:8 ; 918 | u32 SClkVid1:8 ; 919 | u32 SClkVid2:8 ; 920 | u32 SClkVid3:8 ; 921 | } Field; 922 | u32 Value; 923 | } xE0001008_t; 924 | 925 | 926 | // SERVICE REQUESTS 927 | 928 | /// xE0003000 929 | typedef union { 930 | struct { 931 | u32 IntToggle:1 ; 932 | u32 ServiceIndex:16; 933 | u32 Reserved_31_17:15; 934 | } Field; 935 | u32 Value; 936 | } xE0003000_t; 937 | 938 | /// xE0003004 939 | typedef union { 940 | struct { 941 | u32 IntAck:1 ; 942 | u32 IntDone:1 ; 943 | u32 Reserved_31_2:30; 944 | } Field; 945 | u32 Value; 946 | } xE0003004_t; 947 | 948 | /// xE0003024 949 | typedef union { 950 | struct { 951 | u32 SMU_SCRATCH_A:32; 952 | } Field; 953 | u32 Value; 954 | } xE0003024_t; 955 | 956 | /// xE0003034 957 | typedef union { 958 | struct { 959 | u32 PmAllcpusincc6:1 ; 960 | u32 PmNbps:1 ; 961 | u32 PmCommitselfrefr:2 ; 962 | u32 PmPreselfrefresh:1 ; 963 | u32 PmReqnbpstate:1 ; 964 | u32 Reserved_8_6:3 ; 965 | u32 NbNbps:1 ; 966 | u32 NbCommitselfrefr:2 ; 967 | u32 NbPreselfrefresh:1 ; 968 | u32 NbReqnbpstate:1 ; 969 | u32 McNbps:1 ; 970 | u32 GmconCommitselfrefr:2 ; 971 | u32 GmconPreselfrefresh:1 ; 972 | u32 GmconReqnbpstate:1 ; 973 | u32 SysIso:1 ; 974 | u32 CpIso:1 ; 975 | u32 Dc0Iso:1 ; 976 | u32 Dc1Iso:1 ; 977 | u32 DciIso:1 ; 978 | u32 DcipgIso:1 ; 979 | u32 DdiIso:1 ; 980 | u32 GmcIso:1 ; 981 | u32 Reserved_27_27:1 ; 982 | u32 GmcPmSel:2 ; 983 | u32 CpPmSel:2 ; 984 | } Field; 985 | u32 Value; 986 | } xE0003034_t; 987 | 988 | /// xE0003048 989 | typedef union { 990 | struct { 991 | u32 Fracv:12; 992 | u32 Intv:7 ; 993 | u32 Reserved_31_19:13; 994 | } Field; 995 | u32 Value; 996 | } xE0003048_t; 997 | 998 | /// xE0003088 999 | typedef union { 1000 | struct { 1001 | u32 SmuAuthDone:1 ; 1002 | u32 SmuAuthPass:1 ; 1003 | u32 Reserved_31_2:30; 1004 | } Field; 1005 | u32 Value; 1006 | } xE0003088_t; 1007 | 1008 | /// xE00030A4 1009 | typedef union { 1010 | struct { 1011 | u32 Reserved_15_0:16; 1012 | u32 SmuProtectedMode:1 ; 1013 | u32 Reserved_31_17:15; 1014 | } Field; 1015 | u32 Value; 1016 | } xE00030A4_t; 1017 | 1018 | /// xE0104040 1019 | typedef union { 1020 | struct { 1021 | u32 Reserved_6_0:7; 1022 | u32 DeviceID:16 ; 1023 | u32 Reserved_31_23:9; 1024 | } Field; 1025 | u32 Value; 1026 | } xE0104040_t; 1027 | 1028 | /// xE0104168 1029 | typedef union { 1030 | struct { 1031 | u32 GnbLPML15_5_0:6 ; 1032 | u32 MemClkVid0_7_0:8 ; 1033 | u32 MemClkVid1_7_0:8 ; 1034 | u32 MemClkVid2_7_0:8 ; 1035 | u32 MemClkVid3_1_0:2 ; 1036 | } Field; 1037 | u32 Value; 1038 | } xE0104168_t; 1039 | 1040 | /// xE010416C 1041 | typedef union { 1042 | struct { 1043 | u32 MemClkVid3_7_2:6 ; 1044 | u32 MemClkVid4_7_0:8 ; 1045 | u32 MemClkVid5_7_0:8 ; 1046 | u32 MemClkVid6_7_0:8 ; 1047 | u32 MemClkVid7_1_0:2 ; 1048 | } Field; 1049 | u32 Value; 1050 | } xE010416C_t; 1051 | 1052 | /// xE0104170 1053 | typedef union { 1054 | struct { 1055 | u32 MemClkVid7_7_2:6 ; 1056 | u32 MemClkVid8_7_0:8 ; 1057 | u32 AmbientTempBase_7_0:8 ; 1058 | u32 SMU_SPARE31_9_0:10; 1059 | } Field; 1060 | u32 Value; 1061 | } xE0104170_t; 1062 | 1063 | /// xE0300000 1064 | typedef union { 1065 | struct { 1066 | u32 FsmAddr:8 ; 1067 | u32 PowerDown:1 ; 1068 | u32 PowerUp:1 ; 1069 | u32 P1Select:1 ; 1070 | u32 P2Select:1 ; 1071 | u32 WriteOp:1 ; 1072 | u32 ReadOp:1 ; 1073 | u32 Reserved_27_14:14; 1074 | u32 RegAddr:4 ; 1075 | } Field; 1076 | u32 Value; 1077 | } xE0300000_t; 1078 | 1079 | /// xE0300004 1080 | typedef union { 1081 | struct { 1082 | u32 Write_value:32; 1083 | } Field; 1084 | u32 Value; 1085 | } xE0300004_t; 1086 | 1087 | /// xE0300008 1088 | typedef union { 1089 | struct { 1090 | u32 ReadValue:24; 1091 | u32 ReadValid:1 ; 1092 | u32 Reserved_31_25:7 ; 1093 | } Field; 1094 | u32 Value; 1095 | } xE0300008_t; 1096 | 1097 | /// xE030000C 1098 | typedef union { 1099 | struct { 1100 | u32 FsmAddr:8 ; 1101 | u32 PowerDown:1 ; 1102 | u32 PowerUp:1 ; 1103 | u32 P1Select:1 ; 1104 | u32 P2Select:1 ; 1105 | u32 WriteOp:1 ; 1106 | u32 ReadOp:1 ; 1107 | u32 Reserved_27_14:14; 1108 | u32 RegAddr:4 ; 1109 | } Field; 1110 | u32 Value; 1111 | } xE030000C_t; 1112 | 1113 | /// xE0300010 1114 | typedef union { 1115 | struct { 1116 | u32 Write_value:32; 1117 | } Field; 1118 | u32 Value; 1119 | } xE0300010_t; 1120 | 1121 | /// xE0300018 1122 | typedef union { 1123 | struct { 1124 | u32 FsmAddr:8 ; 1125 | u32 PowerDown:1 ; 1126 | u32 PowerUp:1 ; 1127 | u32 P1Select:1 ; 1128 | u32 P2Select:1 ; 1129 | u32 WriteOp:1 ; 1130 | u32 ReadOp:1 ; 1131 | u32 Reserved_27_14:14; 1132 | u32 RegAddr:4 ; 1133 | } Field; 1134 | u32 Value; 1135 | } xE0300018_t; 1136 | 1137 | /// xE030001C 1138 | typedef union { 1139 | struct { 1140 | u32 Write_value:32; 1141 | } Field; 1142 | u32 Value; 1143 | } xE030001C_t; 1144 | 1145 | /// xE0300024 1146 | typedef union { 1147 | struct { 1148 | u32 FsmAddr:8 ; 1149 | u32 PowerDown:1 ; 1150 | u32 PowerUp:1 ; 1151 | u32 P1Select:1 ; 1152 | u32 P2Select:1 ; 1153 | u32 WriteOp:1 ; 1154 | u32 ReadOp:1 ; 1155 | u32 Reserved_27_14:14; 1156 | u32 RegAddr:4 ; 1157 | } Field; 1158 | u32 Value; 1159 | } xE0300024_t; 1160 | 1161 | /// xE0300028 1162 | typedef union { 1163 | struct { 1164 | u32 Write_value:32; 1165 | } Field; 1166 | u32 Value; 1167 | } xE0300028_t; 1168 | 1169 | /// xE0300030 1170 | typedef union { 1171 | struct { 1172 | u32 FsmAddr:8 ; 1173 | u32 PowerDown:1 ; 1174 | u32 PowerUp:1 ; 1175 | u32 P1Select:1 ; 1176 | u32 P2Select:1 ; 1177 | u32 WriteOp:1 ; 1178 | u32 ReadOp:1 ; 1179 | u32 Reserved_27_14:14; 1180 | u32 RegAddr:4 ; 1181 | } Field; 1182 | u32 Value; 1183 | } xE0300030_t; 1184 | 1185 | /// xE0300034 1186 | typedef union { 1187 | struct { 1188 | u32 Write_value:32; 1189 | } Field; 1190 | u32 Value; 1191 | } xE0300034_t; 1192 | 1193 | /// xE030003C 1194 | typedef union { 1195 | struct { 1196 | u32 FsmAddr:8 ; 1197 | u32 PowerDown:1 ; 1198 | u32 PowerUp:1 ; 1199 | u32 P1Select:1 ; 1200 | u32 P2Select:1 ; 1201 | u32 WriteOp:1 ; 1202 | u32 ReadOp:1 ; 1203 | u32 Reserved_27_14:14; 1204 | u32 RegAddr:4 ; 1205 | } Field; 1206 | u32 Value; 1207 | } xE030003C_t; 1208 | 1209 | /// xE0300040 1210 | typedef union { 1211 | struct { 1212 | u32 Write_value:32; 1213 | } Field; 1214 | u32 Value; 1215 | } xE0300040_t; 1216 | 1217 | /// xE0300054 1218 | typedef union { 1219 | struct { 1220 | u32 FsmAddr:8 ; 1221 | u32 PowerDown:1 ; 1222 | u32 PowerUp:1 ; 1223 | u32 P1Select:1 ; 1224 | u32 P2Select:1 ; 1225 | u32 WriteOp:1 ; 1226 | u32 ReadOp:1 ; 1227 | u32 Reserved_27_14:14; 1228 | u32 RegAddr:4 ; 1229 | } Field; 1230 | u32 Value; 1231 | } xE0300054_t; 1232 | 1233 | /// xE0300058 1234 | typedef union { 1235 | struct { 1236 | u32 WriteValue:32; 1237 | } Field; 1238 | u32 Value; 1239 | } xE0300058_t; 1240 | 1241 | /// xE0300070 1242 | typedef union { 1243 | struct { 1244 | u32 FsmAddr:8 ; 1245 | u32 PowerDown:1 ; 1246 | u32 PowerUp:1 ; 1247 | u32 P1Select:1 ; 1248 | u32 P2Select:1 ; 1249 | u32 WriteOp:1 ; 1250 | u32 ReadOp:1 ; 1251 | u32 Reserved_27_14:14; 1252 | u32 RegAddr:4 ; 1253 | } Field; 1254 | u32 Value; 1255 | } xE0300070_t; 1256 | 1257 | /// xE0300074 1258 | typedef union { 1259 | struct { 1260 | u32 WriteValue:32; 1261 | } Field; 1262 | u32 Value; 1263 | } xE0300074_t; 1264 | 1265 | /// xE030008C 1266 | typedef union { 1267 | struct { 1268 | u32 FsmAddr:8 ; 1269 | u32 PowerDown:1 ; 1270 | u32 PowerUp:1 ; 1271 | u32 P1Select:1 ; 1272 | u32 P2Select:1 ; 1273 | u32 WriteOp:1 ; 1274 | u32 ReadOp:1 ; 1275 | u32 Reserved_27_14:14; 1276 | u32 RegAddr:4 ; 1277 | } Field; 1278 | u32 Value; 1279 | } xE030008C_t; 1280 | 1281 | /// xE0300090 1282 | typedef union { 1283 | struct { 1284 | u32 WriteValue:32; 1285 | } Field; 1286 | u32 Value; 1287 | } xE0300090_t; 1288 | 1289 | /// xE03000A8 1290 | typedef union { 1291 | struct { 1292 | u32 FsmAddr:8 ; 1293 | u32 PowerDown:1 ; 1294 | u32 PowerUp:1 ; 1295 | u32 P1Select:1 ; 1296 | u32 P2Select:1 ; 1297 | u32 WriteOp:1 ; 1298 | u32 ReadOp:1 ; 1299 | u32 Reserved_27_14:14; 1300 | u32 RegAddr:4 ; 1301 | } Field; 1302 | u32 Value; 1303 | } xE03000A8_t; 1304 | 1305 | /// xE03000AC 1306 | typedef union { 1307 | struct { 1308 | u32 WriteValue:32; 1309 | } Field; 1310 | u32 Value; 1311 | } xE03000AC_t; 1312 | 1313 | /// xE03000C4 1314 | typedef union { 1315 | struct { 1316 | u32 FsmAddr:8 ; 1317 | u32 PowerDown:1 ; 1318 | u32 PowerUp:1 ; 1319 | u32 P1Select:1 ; 1320 | u32 P2Select:1 ; 1321 | u32 WriteOp:1 ; 1322 | u32 ReadOp:1 ; 1323 | u32 Reserved_27_14:14; 1324 | u32 RegAddr:4 ; 1325 | } Field; 1326 | u32 Value; 1327 | } xE03000C4_t; 1328 | 1329 | /// xE03000C8 1330 | typedef union { 1331 | struct { 1332 | u32 WriteValue:32; 1333 | } Field; 1334 | u32 Value; 1335 | } xE03000C8_t; 1336 | 1337 | /// xE03000E0 1338 | typedef union { 1339 | struct { 1340 | u32 FsmAddr:8 ; 1341 | u32 PowerDown:1 ; 1342 | u32 PowerUp:1 ; 1343 | u32 P1Select:1 ; 1344 | u32 P2Select:1 ; 1345 | u32 WriteOp:1 ; 1346 | u32 ReadOp:1 ; 1347 | u32 Reserved_27_14:14; 1348 | u32 RegAddr:4 ; 1349 | } Field; 1350 | u32 Value; 1351 | } xE03000E0_t; 1352 | 1353 | /// xE03000E4 1354 | typedef union { 1355 | struct { 1356 | u32 WriteValue:32; 1357 | } Field; 1358 | u32 Value; 1359 | } xE03000E4_t; 1360 | 1361 | /// xE03000FC 1362 | typedef union { 1363 | struct { 1364 | u32 FsmAddr:8 ; 1365 | u32 PowerDown:1 ; 1366 | u32 PowerUp:1 ; 1367 | u32 P1Select:1 ; 1368 | u32 P2Select:1 ; 1369 | u32 WriteOp:1 ; 1370 | u32 ReadOp:1 ; 1371 | u32 Reserved_27_14:14; 1372 | u32 RegAddr:4 ; 1373 | } Field; 1374 | u32 Value; 1375 | } xE03000FC_t; 1376 | 1377 | /// xE0300100 1378 | typedef union { 1379 | struct { 1380 | u32 WriteValue:32; 1381 | } Field; 1382 | u32 Value; 1383 | } xE0300100_t; 1384 | 1385 | /// xE0300200 1386 | typedef union { 1387 | struct { 1388 | u32 Reserved_9_0:10; 1389 | u32 P1IsoN:1 ; 1390 | u32 Reserved_31_11:21; 1391 | } Field; 1392 | u32 Value; 1393 | } xE0300200_t; 1394 | 1395 | /// xE0300208 1396 | typedef union { 1397 | struct { 1398 | u32 Reserved_9_0:10; 1399 | u32 P1IsoN:1 ; 1400 | u32 Reserved_12_11:2 ; 1401 | u32 :1 ; 1402 | u32 Reserved_31_14:18; 1403 | } Field; 1404 | u32 Value; 1405 | } xE0300208_t; 1406 | 1407 | /// xE030020C 1408 | typedef union { 1409 | struct { 1410 | u32 Reserved_9_0:10; 1411 | u32 P1IsoN:1 ; 1412 | u32 Reserved_31_11:21; 1413 | } Field; 1414 | u32 Value; 1415 | } xE030020C_t; 1416 | 1417 | /// xE0300210 1418 | typedef union { 1419 | struct { 1420 | u32 Reserved_9_0:10; 1421 | u32 P1IsoN:1 ; 1422 | u32 Reserved_12_11:2 ; 1423 | u32 :1 ; 1424 | u32 Reserved_31_14:18; 1425 | } Field; 1426 | u32 Value; 1427 | } xE0300210_t; 1428 | 1429 | /// xE0300218 1430 | typedef union { 1431 | struct { 1432 | u32 Reserved_9_0:10; 1433 | u32 P1IsoN:1 ; 1434 | u32 Reserved_31_11:21; 1435 | } Field; 1436 | u32 Value; 1437 | } xE0300218_t; 1438 | 1439 | /// xE03002DC 1440 | typedef union { 1441 | struct { 1442 | u32 DC2_PGFSM_CONTROL:1 ; 1443 | u32 Reserved:31; 1444 | } Field; 1445 | u32 Value; 1446 | } xE03002DC_t; 1447 | 1448 | /// xE03002E4 1449 | typedef union { 1450 | struct { 1451 | u32 SmuCb0PsoDaug:1 ; 1452 | u32 SmuCb1PsoDaug:1 ; 1453 | u32 SmuDb0PsoDaug:1 ; 1454 | u32 SmuDb1PsoDaug:1 ; 1455 | u32 SmuPaPsoDaug:1 ; 1456 | u32 SmuSpmPsoDaug:1 ; 1457 | u32 SmuSpsPsoDaug:1 ; 1458 | u32 SmuSqbPsoDaug:1 ; 1459 | u32 SmuSxmPsoDaug:1 ; 1460 | u32 SmuSxs0PsoDaug:1 ; 1461 | u32 SmuSxs1PsoDaug:1 ; 1462 | u32 SmuXbrPsoDaug:1 ; 1463 | u32 SmuGdsPsoDaug:1 ; 1464 | u32 SmuVgtPsoDaug:1 ; 1465 | u32 SmuSqaPsoDaug:1 ; 1466 | u32 SmuSqcPsoDaug:1 ; 1467 | u32 SmuTcPsoDaug:1 ; 1468 | u32 SmuScPsoDaug:1 ; 1469 | u32 Reserved_31_18:14; 1470 | } Field; 1471 | u32 Value; 1472 | } xE03002E4_t; 1473 | 1474 | /// xE03002F0 1475 | typedef union { 1476 | struct { 1477 | u32 SmuTatd0P1IsoN:1 ; 1478 | u32 SmuSp000P1IsoN:1 ; 1479 | u32 SmuSp002P1IsoN:1 ; 1480 | u32 SmuLds0P1IsoN:1 ; 1481 | u32 SmuTcp0P1IsoN:1 ; 1482 | u32 SmuTatd1P1IsoN:1 ; 1483 | u32 SmuSp010P1IsoN:1 ; 1484 | u32 SmuSp012P1IsoN:1 ; 1485 | u32 SmuLds1P1IsoN:1 ; 1486 | u32 SmuTcp1P1IsoN:1 ; 1487 | u32 SmuTatd2P1IsoN:1 ; 1488 | u32 SmuSp020P1IsoN:1 ; 1489 | u32 SmuSp022P1IsoN:1 ; 1490 | u32 SmuLds2P1IsoN:1 ; 1491 | u32 SmuTcp2P1IsoN:1 ; 1492 | u32 SmuTatd3P1IsoN:1 ; 1493 | u32 SmuSp030P1IsoN:1 ; 1494 | u32 SmuSp032P1IsoN:1 ; 1495 | u32 SmuLds3P1IsoN:1 ; 1496 | u32 SmuTcp3P1IsoN:1 ; 1497 | u32 SmuTatd4P1IsoN:1 ; 1498 | u32 SmuSp040P1IsoN:1 ; 1499 | u32 SmuSp042P1IsoN:1 ; 1500 | u32 SmuLds4P1IsoN:1 ; 1501 | u32 SmuTcp4P1IsoN:1 ; 1502 | u32 SmuTatd5P1IsoN:1 ; 1503 | u32 SmuSp050P1IsoN:1 ; 1504 | u32 SmuSp052P1IsoN:1 ; 1505 | u32 SmuLds5P1IsoN:1 ; 1506 | u32 SmuTcp5P1IsoN:1 ; 1507 | u32 Reserved_31_30:2 ; 1508 | } Field; 1509 | u32 Value; 1510 | } xE03002F0_t; 1511 | 1512 | /// xE03002F4 1513 | typedef union { 1514 | struct { 1515 | u32 SmuCb0IsoN:1 ; 1516 | u32 SmuCb1IsoN:1 ; 1517 | u32 SmuDb0IsoN:1 ; 1518 | u32 SmuDb1IsoN:1 ; 1519 | u32 SmuPaIsoN:1 ; 1520 | u32 SmuSpmIsoN:1 ; 1521 | u32 SmuSpsIsoN:1 ; 1522 | u32 SmuSqbIsoN:1 ; 1523 | u32 SmuSxmIsoN:1 ; 1524 | u32 SmuSxs0IsoN:1 ; 1525 | u32 SmuSxs1IsoN:1 ; 1526 | u32 SmuXbrIsoN:1 ; 1527 | u32 SmuGdsIsoN:1 ; 1528 | u32 SmuVgtIsoN:1 ; 1529 | u32 SmuSqaIsoN:1 ; 1530 | u32 SmuSqcIsoN:1 ; 1531 | u32 SmuTcIsoN:1 ; 1532 | u32 SmuScIsoN:1 ; 1533 | u32 Reserved_31_18:14; 1534 | } Field; 1535 | u32 Value; 1536 | } xE03002F4_t; 1537 | 1538 | /// xE03002F8 1539 | typedef union { 1540 | struct { 1541 | u32 SmuTatd0P2IsoN:1 ; 1542 | u32 SmuSp000P2IsoN:1 ; 1543 | u32 SmuSp002P2IsoN:1 ; 1544 | u32 SmuLds0P2IsoN:1 ; 1545 | u32 SmuTcp0P2IsoN:1 ; 1546 | u32 SmuTatd1P2IsoN:1 ; 1547 | u32 SmuSp010P2IsoN:1 ; 1548 | u32 SmuSp012P2IsoN:1 ; 1549 | u32 SmuLds1P2IsoN:1 ; 1550 | u32 SmuTcp1P2IsoN:1 ; 1551 | u32 SmuTatd2P2IsoN:1 ; 1552 | u32 SmuSp020P2IsoN:1 ; 1553 | u32 SmuSp022P2IsoN:1 ; 1554 | u32 SmuLds2P2IsoN:1 ; 1555 | u32 SmuTcp2P2IsoN:1 ; 1556 | u32 SmuTatd3P2IsoN:1 ; 1557 | u32 SmuSp030P2IsoN:1 ; 1558 | u32 SmuSp032P2IsoN:1 ; 1559 | u32 SmuLds3P2IsoN:1 ; 1560 | u32 SmuTcp3P2IsoN:1 ; 1561 | u32 SmuTatd4P2IsoN:1 ; 1562 | u32 SmuSp040P2IsoN:1 ; 1563 | u32 SmuSp042P2IsoN:1 ; 1564 | u32 SmuLds4P2IsoN:1 ; 1565 | u32 SmuTcp4P2IsoN:1 ; 1566 | u32 SmuTatd5P2IsoN:1 ; 1567 | u32 SmuSp050P2IsoN:1 ; 1568 | u32 SmuSp052P2IsoN:1 ; 1569 | u32 SmuLds5P2IsoN:1 ; 1570 | u32 SmuTcp5P2IsoN:1 ; 1571 | u32 Reserved_31_30:2 ; 1572 | } Field; 1573 | u32 Value; 1574 | } xE03002F8_t; 1575 | 1576 | /// xE03002FC 1577 | typedef union { 1578 | struct { 1579 | u32 SmuTatd0P2PsoDaug:1 ; 1580 | u32 SmuSp000P2PsoDaug:1 ; 1581 | u32 SmuSp002P2PsoDaug:1 ; 1582 | u32 SmuLds0P2PsoDaug:1 ; 1583 | u32 SmuTcp0P2PsoDaug:1 ; 1584 | u32 SmuTatd1P2PsoDaug:1 ; 1585 | u32 SmuSp010P2PsoDaug:1 ; 1586 | u32 SmuSp012P2PsoDaug:1 ; 1587 | u32 SmuLds1P2PsoDaug:1 ; 1588 | u32 SmuTcp1P2PsoDaug:1 ; 1589 | u32 SmuTatd2P2PsoDaug:1 ; 1590 | u32 SmuSp020P2PsoDaug:1 ; 1591 | u32 SmuSp022P2PsoDaug:1 ; 1592 | u32 SmuLds2P2PsoDaug:1 ; 1593 | u32 SmuTcp2P2PsoDaug:1 ; 1594 | u32 SmuTatd3P2PsoDaug:1 ; 1595 | u32 SmuSp030P2PsoDaug:1 ; 1596 | u32 SmuSp032P2PsoDaug:1 ; 1597 | u32 SmuLds3P2PsoDaug:1 ; 1598 | u32 SmuTcp3P2PsoDaug:1 ; 1599 | u32 SmuTatd4P2PsoDaug:1 ; 1600 | u32 SmuSp040P2PsoDaug:1 ; 1601 | u32 SmuSp042P2PsoDaug:1 ; 1602 | u32 SmuLds4P2PsoDaug:1 ; 1603 | u32 SmuTcp4P2PsoDaug:1 ; 1604 | u32 SmuTatd5P2PsoDaug:1 ; 1605 | u32 SmuSp050P2PsoDaug:1 ; 1606 | u32 SmuSp052P2PsoDaug:1 ; 1607 | u32 SmuLds5P2PsoDaug:1 ; 1608 | u32 SmuTcp5P2PsoDaug:1 ; 1609 | u32 Reserved_31_30:2 ; 1610 | } Field; 1611 | u32 Value; 1612 | } xE03002FC_t; 1613 | 1614 | /// xE0300320 1615 | typedef union { 1616 | struct { 1617 | u32 PgdPgfsmClockEn:1 ; 1618 | u32 IommuPgfsmClockEn:1 ; 1619 | u32 Reserved_31_2:30; 1620 | } Field; 1621 | u32 Value; 1622 | } xE0300320_t; 1623 | 1624 | /// xE0300324 1625 | typedef union { 1626 | struct { 1627 | u32 VcePgfsmClockEn:1 ; 1628 | u32 UvdPgfsmClockEn:1 ; 1629 | u32 Dc2PgfsmClockEn:1 ; 1630 | u32 Reserved_31_3:29; 1631 | } Field; 1632 | u32 Value; 1633 | } xE0300324_t; 1634 | 1635 | /// xFF000000 1636 | typedef union { 1637 | struct { 1638 | u32 GckFuseProg:1 ; 1639 | u32 MainPllOpFreqIdStartup:6 ; 1640 | u32 MainPllOpFreqIdMax:6 ; 1641 | u32 MainPllRefAdj:5 ; 1642 | u32 PllMiscFuseCtl:4 ; 1643 | u32 Reserved_31_22:10; 1644 | } Field; 1645 | u32 Value; 1646 | } xFF000000_t; 1647 | 1648 | /// xE010703C 1649 | typedef union { 1650 | struct { 1651 | u32 Reserved_2_0:3 ; 1652 | u32 NbPstateHi:2 ; 1653 | u32 NbPstateLo:2 ; 1654 | u32 Reserved_31_7:25; 1655 | } Field; 1656 | u32 Value; 1657 | } xE010703C_t; 1658 | 1659 | /// xE01040A8 1660 | typedef union { 1661 | struct { 1662 | u32 Reserved0_14:15; 1663 | u32 SviLoadLineVdd:7 ; 1664 | u32 SviLoadLineVddNb:7 ; 1665 | u32 Reserved29_31:3 ; 1666 | } Field; 1667 | u32 Value; 1668 | } xE01040A8_t; 1669 | 1670 | /// xE0104158 1671 | typedef union { 1672 | struct { 1673 | u32 Reserved0_9:10; 1674 | u32 EClkDid0:7 ; 1675 | u32 EClkDid1:7 ; 1676 | u32 EClkDid2:7 ; 1677 | u32 Reserved31_31:1 ; 1678 | } Field; 1679 | u32 Value; 1680 | } xE0104158_t; 1681 | 1682 | /// xE010415B 1683 | typedef union { 1684 | struct { 1685 | u32 Reserved0_6:7 ; 1686 | u32 EClkDid3:7 ; 1687 | u32 Reserved14_31:18; 1688 | } Field; 1689 | u32 Value; 1690 | } xE010415B_t; 1691 | 1692 | /// xE0104184 1693 | typedef union { 1694 | struct { 1695 | u32 SviLoadLineTrimVdd:3 ; 1696 | u32 SviLoadLineTrimVddNb:3 ; 1697 | u32 SviLoadLineOffsetVdd:2 ; 1698 | u32 SviLoadLineOffsetVddNb:2 ; 1699 | u32 VCEFlag0:8 ; 1700 | u32 VCEFlag1:8 ; 1701 | u32 Reserved26_31:6 ; 1702 | } Field; 1703 | u32 Value; 1704 | } xE0104184_t; 1705 | 1706 | /// xE0104187 1707 | typedef union { 1708 | struct { 1709 | u32 Reserved0_1:2 ; 1710 | u32 VCEFlag2:8 ; 1711 | u32 Reserved10_31:22; 1712 | } Field; 1713 | u32 Value; 1714 | } xE0104187_t; 1715 | 1716 | /// xE0104188 1717 | typedef union { 1718 | struct { 1719 | u32 Reserved0_1:2 ; 1720 | u32 VCEFlag3:8 ; 1721 | u32 ReqSclkSel0:3 ; 1722 | u32 ReqSclkSel1:3 ; 1723 | u32 ReqSclkSel2:3 ; 1724 | u32 ReqSclkSel3:3 ; 1725 | u32 VCEMclk:4 ; 1726 | u32 LhtcPstateLimit:3 ; 1727 | u32 BapmMeasuredTemp:1 ; 1728 | u32 BapmDisable:1 ; 1729 | u32 Reserved31_31:1 ; 1730 | } Field; 1731 | u32 Value; 1732 | } xE0104188_t; 1733 | 1734 | /// xE0106020 1735 | typedef union { 1736 | struct { 1737 | u32 Reserved0_24:25; 1738 | u32 PowerplayDClkVClkSel0:2 ; 1739 | u32 PowerplayDClkVClkSel1:2 ; 1740 | u32 PowerplayDClkVClkSel2:2 ; 1741 | u32 Reserved31_31:1 ; 1742 | } Field; 1743 | u32 Value; 1744 | } xE0106020_t; 1745 | 1746 | /// xE0106023 1747 | typedef union { 1748 | struct { 1749 | u32 Reserved0_6:7 ; 1750 | u32 PowerplayDClkVClkSel3:2 ; 1751 | u32 Reserved9_31:23; 1752 | } Field; 1753 | u32 Value; 1754 | } xE0106023_t; 1755 | 1756 | /// xE0106024 1757 | typedef union { 1758 | struct { 1759 | u32 Reserved0_0:1 ; 1760 | u32 PowerplayDClkVClkSel4:2 ; 1761 | u32 PowerplayDClkVClkSel5:2 ; 1762 | u32 Reserved5_31:27; 1763 | } Field; 1764 | u32 Value; 1765 | } xE0106024_t; 1766 | 1767 | /// xE010705C 1768 | typedef union { 1769 | struct { 1770 | u32 Reserved0_17:18; 1771 | u32 PowerplayTableRev:4 ; 1772 | u32 SClkThermDid:7 ; 1773 | u32 PcieGen2Vid:2 ; 1774 | u32 Reserved31_31:1 ; 1775 | } Field; 1776 | u32 Value; 1777 | } xE010705C_t; 1778 | 1779 | /// xE010705F 1780 | typedef union { 1781 | struct { 1782 | u32 Reserved0_6:7 ; 1783 | u32 SClkDpmVid0:2 ; 1784 | u32 Reserved9_31:23; 1785 | } Field; 1786 | u32 Value; 1787 | } xE010705F_t; 1788 | 1789 | /// xE0107060 1790 | typedef union { 1791 | struct { 1792 | u32 Reserved0_0:1 ; 1793 | u32 SClkDpmVid1:2 ; 1794 | u32 SClkDpmVid2:2 ; 1795 | u32 SClkDpmVid3:2 ; 1796 | u32 SClkDpmVid4:2 ; 1797 | u32 SClkDpmDid0:7 ; 1798 | u32 SClkDpmDid1:7 ; 1799 | u32 SClkDpmDid2:7 ; 1800 | u32 Reserved30_31:2 ; 1801 | } Field; 1802 | u32 Value; 1803 | } xE0107060_t; 1804 | 1805 | /// xE0107063 1806 | typedef union { 1807 | struct { 1808 | u32 Reserved0_5:6 ; 1809 | u32 SClkDpmDid3:7 ; 1810 | u32 Reserved13_31:19; 1811 | } Field; 1812 | u32 Value; 1813 | } xE0107063_t; 1814 | 1815 | /// xE0107064 1816 | typedef union { 1817 | struct { 1818 | u32 Reserved0_4:5 ; 1819 | u32 SClkDpmDid4:7 ; 1820 | u32 Reserved12_31:20; 1821 | } Field; 1822 | u32 Value; 1823 | } xE0107064_t; 1824 | 1825 | /// xE0107067 1826 | typedef union { 1827 | struct { 1828 | u32 Reserved0_3:4 ; 1829 | u32 DispClkDid0:7 ; 1830 | u32 Reserved11_31:21; 1831 | } Field; 1832 | u32 Value; 1833 | } xE0107067_t; 1834 | 1835 | /// xE0107068 1836 | typedef union { 1837 | struct { 1838 | u32 Reserved0_2:3 ; 1839 | u32 DispClkDid1:7 ; 1840 | u32 DispClkDid2:7 ; 1841 | u32 DispClkDid3:7 ; 1842 | u32 LClkDpmDid0:7 ; 1843 | u32 Reserved31_31:1 ; 1844 | } Field; 1845 | u32 Value; 1846 | } xE0107068_t; 1847 | 1848 | /// xE010706B 1849 | typedef union { 1850 | struct { 1851 | u32 Reserved0_6:7 ; 1852 | u32 LClkDpmDid1:7 ; 1853 | u32 Reserved14_31:18; 1854 | } Field; 1855 | u32 Value; 1856 | } xE010706B_t; 1857 | 1858 | /// xE010706C 1859 | typedef union { 1860 | struct { 1861 | u32 Reserved0_5:6 ; 1862 | u32 LClkDpmDid2:7 ; 1863 | u32 LClkDpmDid3:7 ; 1864 | u32 LClkDpmValid:4 ; 1865 | u32 DClkDid0:7 ; 1866 | u32 Reserved31_31:1 ; 1867 | } Field; 1868 | u32 Value; 1869 | } xE010706C_t; 1870 | 1871 | /// xE010706F 1872 | typedef union { 1873 | struct { 1874 | u32 Reserved0_6:7 ; 1875 | u32 DClkDid1:7 ; 1876 | u32 Reserved14_31:18; 1877 | } Field; 1878 | u32 Value; 1879 | } xE010706F_t; 1880 | 1881 | /// xE0107070 1882 | typedef union { 1883 | struct { 1884 | u32 Reserved0_5:6 ; 1885 | u32 DClkDid2:7 ; 1886 | u32 DClkDid3:7 ; 1887 | u32 VClkDid0:7 ; 1888 | u32 Reserved27_31:5 ; 1889 | } Field; 1890 | u32 Value; 1891 | } xE0107070_t; 1892 | 1893 | /// xE0107073 1894 | typedef union { 1895 | struct { 1896 | u32 Reserved0_2:3 ; 1897 | u32 VClkDid1:7 ; 1898 | u32 Reserved10_31:22; 1899 | } Field; 1900 | u32 Value; 1901 | } xE0107073_t; 1902 | 1903 | /// xE0107074 1904 | typedef union { 1905 | struct { 1906 | u32 Reserved0_1:2 ; 1907 | u32 VClkDid2:7 ; 1908 | u32 VClkDid3:7 ; 1909 | u32 PowerplaySclkDpmValid0:5 ; 1910 | u32 PowerplaySclkDpmValid1:5 ; 1911 | u32 PowerplaySclkDpmValid2:5 ; 1912 | u32 Reserved31_31:1 ; 1913 | } Field; 1914 | u32 Value; 1915 | } xE0107074_t; 1916 | 1917 | /// xE0107077 1918 | typedef union { 1919 | struct { 1920 | u32 Reserved0_6:7 ; 1921 | u32 PowerplaySclkDpmValid3:5 ; 1922 | u32 Reserved12_31:20; 1923 | } Field; 1924 | u32 Value; 1925 | } xE0107077_t; 1926 | 1927 | /// xE0107078 1928 | typedef union { 1929 | struct { 1930 | u32 Reserved0_3:4 ; 1931 | u32 PowerplaySclkDpmValid4:5 ; 1932 | u32 PowerplaySclkDpmValid5:5 ; 1933 | u32 PowerplayPolicyLabel0:2 ; 1934 | u32 PowerplayPolicyLabel1:2 ; 1935 | u32 PowerplayPolicyLabel2:2 ; 1936 | u32 PowerplayPolicyLabel3:2 ; 1937 | u32 PowerplayPolicyLabel4:2 ; 1938 | u32 PowerplayPolicyLabel5:2 ; 1939 | u32 Reserved26_31:6 ; 1940 | } Field; 1941 | u32 Value; 1942 | } xE0107078_t; 1943 | 1944 | /// xE010707B 1945 | typedef union { 1946 | struct { 1947 | u32 Reserved0_1:2 ; 1948 | u32 PowerplayStateFlag0:7 ; 1949 | u32 Reserved9_31:23; 1950 | } Field; 1951 | u32 Value; 1952 | } xE010707B_t; 1953 | 1954 | /// xE010707C 1955 | typedef union { 1956 | struct { 1957 | u32 Reserved0_0:1 ; 1958 | u32 PowerplayStateFlag1:7 ; 1959 | u32 PowerplayStateFlag2:7 ; 1960 | u32 PowerplayStateFlag3:7 ; 1961 | u32 PowerplayStateFlag4:7 ; 1962 | u32 Reserved29_31:3 ; 1963 | } Field; 1964 | u32 Value; 1965 | } xE010707C_t; 1966 | 1967 | /// xE010707F 1968 | typedef union { 1969 | struct { 1970 | u32 Reserved0_4:5 ; 1971 | u32 PowerplayStateFlag5:7 ; 1972 | u32 Reserved12_31:20; 1973 | } Field; 1974 | u32 Value; 1975 | } xE010707F_t; 1976 | 1977 | #endif 1978 | -------------------------------------------------------------------------------- /firmware/smu.ld: -------------------------------------------------------------------------------- 1 | /* 2 | * Link script for LatticeMico32 programs. 3 | * 4 | * Redistribution and use in source and binary forms, with or without 5 | * modification, are permitted provided that the following conditions 6 | * are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 | * SUCH DAMAGE. 24 | * 25 | * Modified for SMU by Damien Zammit 26 | * 27 | */ 28 | 29 | OUTPUT_FORMAT("elf32-lm32") 30 | ENTRY(_start) 31 | INPUT(crti.o crtbegin.o crtend.o crtn.o) 32 | 33 | MEMORY 34 | { 35 | rom : ORIGIN = 0x0, LENGTH = 0x10000 36 | header : ORIGIN = 0x00010000, LENGTH = 0x100 37 | ram : ORIGIN = 0x00010100, LENGTH = 0xcf00 38 | regs : ORIGIN = 0x0001d000, LENGTH = 0x3000 39 | } 40 | 41 | SECTIONS 42 | { 43 | /* code */ 44 | .boot : { *(.boot) } > ram 45 | .text : 46 | { 47 | . = ALIGN(4); 48 | _ftext = .; 49 | _ftext_rom = .; 50 | *(.text .stub .text.* .gnu.linkonce.t.*) 51 | *(.gnu.warning) 52 | KEEP (*(.init)) 53 | KEEP (*(.fini)) 54 | 55 | /* Exception handlers */ 56 | *(.eh_frame_hdr) 57 | KEEP (*(.eh_frame)) 58 | *(.gcc_except_table) 59 | 60 | /* Constructors and destructors */ 61 | KEEP (*crtbegin*.o(.ctors)) 62 | KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) 63 | KEEP (*(SORT(.ctors.*))) 64 | KEEP (*(.ctors)) 65 | KEEP (*crtbegin*.o(.dtors)) 66 | KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) 67 | KEEP (*(SORT(.dtors.*))) 68 | KEEP (*(.dtors)) 69 | KEEP (*(.jcr)) 70 | _etext = .; 71 | } > ram =0 72 | 73 | /* read-only data */ 74 | .rodata : 75 | { 76 | . = ALIGN(4); 77 | _frodata = .; 78 | _frodata_rom = LOADADDR(.rodata); 79 | *(.rodata .rodata.* .gnu.linkonce.r.*) 80 | *(.rodata1) 81 | _erodata = .; 82 | } > ram 83 | 84 | /* read/write data */ 85 | .data : 86 | { 87 | . = ALIGN(4); 88 | _fdata = .; 89 | _fdata_rom = .; 90 | *(.data .data.* .gnu.linkonce.d.*) 91 | *(.data1) 92 | SORT(CONSTRUCTORS) 93 | _gp = ALIGN(16) + 0x7ff0; 94 | *(.sdata .sdata.* .gnu.linkonce.s.*) 95 | _edata = .; 96 | } > ram 97 | 98 | .sreg : 99 | { 100 | . = ABSOLUTE(0x9a4); 101 | thermal_params = .; 102 | LONG(0x3178); /* VPC */ 103 | LONG(0x0000); 104 | LONG(0x3171); /* BAPM */ 105 | LONG(0x0000); 106 | LONG(0x3172); /* BAPM */ 107 | LONG(0x0000); 108 | LONG(0x7103); /* BAPM */ 109 | LONG(0x0000); /* BAPM */ 110 | LONG(0x7116); /* BAPM */ 111 | LONG(0x0000); /* BAPM */ 112 | LONG(0x317d); /* VPC */ 113 | LONG(0x0000); 114 | LONG(0x7103); /* VPC */ 115 | LONG(0x0000); /* VPC */ 116 | LONG(0x712e); 117 | LONG(0x0000); 118 | LONG(0x710f); /* TDC/HTC */ 119 | LONG(0x0000); /* TDC/HTC */ 120 | LONG(0x7110); /* LPMx */ 121 | LONG(0x0000); /* LPMx */ 122 | LONG(0x7111); /* LPMx */ 123 | LONG(0x0000); /* LPMx */ 124 | LONG(0x7112); /* LPMx */ 125 | LONG(0x0000); /* LPMx */ 126 | LONG(0x7113); /* LPMx */ 127 | LONG(0x0000); /* LPMx */ 128 | LONG(0x715c); /* VPC/BAPM */ 129 | LONG(0x0000); /* VPC/BAPM */ 130 | LONG(0x715d); /* VPC */ 131 | LONG(0x0000); 132 | LONG(0x7162); /* LOADLINE */ 133 | LONG(0x0000); /* LOADLINE */ 134 | LONG(0x7117); /* BAPM */ 135 | LONG(0x0000); /* BAPM */ 136 | LONG(0x7157); 137 | LONG(0x0000); 138 | LONG(0x7106); /* BAPM */ 139 | LONG(0x0000); /* BAPM */ 140 | } > regs =0 141 | 142 | /* bss */ 143 | .bss : 144 | { 145 | . = ALIGN(4); 146 | _fbss = .; 147 | *(.dynsbss) 148 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 149 | *(.scommon) 150 | *(.dynbss) 151 | *(.bss .bss.* .gnu.linkonce.b.*) 152 | *(COMMON) 153 | . = ALIGN(4); 154 | _ebss = .; 155 | _end = .; 156 | PROVIDE (end = .); 157 | } > ram 158 | 159 | /* first location in stack is highest address in ram */ 160 | PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4); 161 | 162 | /* stabs debugging sections. */ 163 | .stab 0 : { *(.stab) } 164 | .stabstr 0 : { *(.stabstr) } 165 | .stab.excl 0 : { *(.stab.excl) } 166 | .stab.exclstr 0 : { *(.stab.exclstr) } 167 | .stab.index 0 : { *(.stab.index) } 168 | .stab.indexstr 0 : { *(.stab.indexstr) } 169 | .comment 0 : { *(.comment) } 170 | } 171 | -------------------------------------------------------------------------------- /header.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zamaudio/smutool/59e4001aa06c1db46ffe44da5bc1b254e9b636c0/header.bin -------------------------------------------------------------------------------- /signsmu.py: -------------------------------------------------------------------------------- 1 | # smutool Tool for SMU 2 | # Copyright (C) 2015 Damien Zammit 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # See . 14 | # 15 | 16 | import sys 17 | import struct, hashlib, hmac 18 | 19 | args=sys.argv 20 | if len(sys.argv) == 1: 21 | print "Usage: python signsmu.py " 22 | sys.exit() 23 | 24 | def reverse(strs): 25 | return ''.join([strs[i] for i in xrange(len(strs)-1, -1, -1)]) 26 | 27 | key1 = "\x77\x33\xbf\x25\x5c\x07\x03\x78\x1f\xb7\xc1\x3b\x7f\x4b\x92\xaf" 28 | 29 | f = open(args[1], "rb") 30 | firmware = bytearray() 31 | try: 32 | firmware = bytearray(f.read()) 33 | finally: 34 | f.close() 35 | 36 | h = hmac.new(key1, firmware, hashlib.sha1) 37 | mhash = h.digest() 38 | print hex(struct.unpack(">5I", mhash)[0]) 39 | print hex(struct.unpack(">5I", mhash)[1]) 40 | print hex(struct.unpack(">5I", mhash)[2]) 41 | print hex(struct.unpack(">5I", mhash)[3]) 42 | print hex(struct.unpack(">5I", mhash)[4]) 43 | 44 | -------------------------------------------------------------------------------- /smudump.c: -------------------------------------------------------------------------------- 1 | /* smutool Tool for SMU 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See . 14 | */ 15 | 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | 25 | #define SIZE 0x40000 26 | 27 | int main(int argc, char* argv[]) 28 | { 29 | uint32_t fd_mem; 30 | struct pci_access *pacc; 31 | struct pci_dev *nb; 32 | if (iopl(3)) { 33 | perror("iopl"); 34 | fprintf(stderr, "You need to be root\n"); 35 | exit(1); 36 | } 37 | 38 | if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { 39 | perror("Can not open /dev/mem"); 40 | exit(1); 41 | } 42 | 43 | pacc = pci_alloc(); 44 | pacc->method = PCI_ACCESS_I386_TYPE1; 45 | pci_init(pacc); 46 | pci_scan_bus(pacc); 47 | nb = pci_get_dev(pacc, 0, 0, 0x0, 0); 48 | pci_fill_info(nb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); 49 | 50 | fprintf(stderr, "Reading SMU RAM...\n"); 51 | uint32_t data[SIZE], i; 52 | for (i = 0; i < SIZE; i+=4) { 53 | pci_write_long(nb, 0xb8, i); 54 | data[i/4] = pci_read_long(nb, 0xbc); 55 | printf("%c%c%c%c", 56 | data[i/4] >> 24, 57 | data[i/4] >> 16, 58 | data[i/4] >> 8, 59 | data[i/4]); 60 | } 61 | 62 | fprintf(stderr, "exiting\n"); 63 | pci_cleanup(pacc); 64 | return 0; 65 | } 66 | -------------------------------------------------------------------------------- /smutool.c: -------------------------------------------------------------------------------- 1 | /* smutool Tool for SMU 2 | * Copyright (C) 2015 Damien Zammit 3 | * 4 | * This program is free software: you can redistribute it and/or modify 5 | * it under the terms of the GNU General Public License as published by 6 | * the Free Software Foundation, either version 3 of the License, or 7 | * (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * See . 14 | */ 15 | 16 | #include 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | 25 | #define SIZE 0x10000 26 | 27 | int main(int argc, char* argv[]) 28 | { 29 | uint32_t fd_mem; 30 | struct pci_access *pacc; 31 | struct pci_dev *nb; 32 | if (iopl(3)) { 33 | perror("iopl"); 34 | fprintf(stderr, "You need to be root\n"); 35 | exit(1); 36 | } 37 | 38 | if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { 39 | perror("Can not open /dev/mem"); 40 | exit(1); 41 | } 42 | 43 | pacc = pci_alloc(); 44 | pacc->method = PCI_ACCESS_I386_TYPE1; 45 | pci_init(pacc); 46 | pci_scan_bus(pacc); 47 | nb = pci_get_dev(pacc, 0, 0, 0x0, 0); 48 | pci_fill_info(nb, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_SIZES | PCI_FILL_CLASS); 49 | 50 | 51 | /* lm32 instructions, load at 0x1ff80, read peek at 0x1fff0 52 | 1ff80: 37 9c ff f0 addi sp,sp,-16 53 | 1ff84: 5b 9b 00 08 sw (sp+8),fp 54 | 1ff88: 5b 9d 00 04 sw (sp+4),ra 55 | 1ff8c: 34 1b 00 10 mvi fp,16 56 | 1ff90: b7 7c d8 00 add fp,fp,sp 57 | 1ff94: 78 01 ab cd mvhi r1,0xabcd 58 | 1ff98: 38 21 ef 00 ori r1,r1,0xef00 59 | 1ff9c: 5b 61 00 00 sw (fp+0),r1 60 | 1ffa0: 78 01 00 01 mvhi r1,0x1 61 | 1ffa4: 38 21 ff f0 ori r1,r1,0xfff0 62 | 1ffa8: 5b 61 ff fc sw (fp+-4),r1 63 | 1ffac: 2b 61 ff fc lw r1,(fp+-4) 64 | 1ffb0: 2b 62 00 00 lw r2,(fp+0) 65 | 1ffb4: 28 42 00 00 lw r2,(r2+0) 66 | 1ffb8: 58 22 00 00 sw (r1+0),r2 67 | 1ffbc: 2b 9b 00 08 lw fp,(sp+8) 68 | 1ffc0: 2b 9d 00 04 lw ra,(sp+4) 69 | 1ffc4: 37 9c 00 10 addi sp,sp,16 70 | 1ffc8: c3 a0 00 00 ret 71 | */ 72 | // Fill peek location with 1s so we can tell if anything changed 73 | pci_write_long(nb, 0xb8, 0x1fff0); 74 | pci_write_long(nb, 0xbc, 0x11223344); 75 | 76 | // Enable interrupts on SMU 77 | pci_write_long(nb, 0xb8, 0x1f380); 78 | pci_write_long(nb, 0xbc, 79 | pci_read_long(nb, 0xbc) & ~1); 80 | pci_write_long(nb, 0xb8, 0x1f380); 81 | pci_write_long(nb, 0xbc, 82 | pci_read_long(nb, 0xbc) | 1); 83 | 84 | uint32_t peek; 85 | for (peek = 0; peek < SIZE; peek += 4) { 86 | uint16_t peeklo = peek & 0xffff; 87 | uint16_t peekhi = (peek >> 16) & 0xffff; 88 | pci_write_long(nb, 0xb8, 0x1ff80); 89 | pci_write_long(nb, 0xbc, (0x379cfff0)); 90 | pci_write_long(nb, 0xb8, 0x1ff84); 91 | pci_write_long(nb, 0xbc, (0x5b9b0008)); 92 | pci_write_long(nb, 0xb8, 0x1ff88); 93 | pci_write_long(nb, 0xbc, (0x5b9d0004)); 94 | pci_write_long(nb, 0xb8, 0x1ff8c); 95 | pci_write_long(nb, 0xbc, (0x341b0010)); 96 | pci_write_long(nb, 0xb8, 0x1ff90); 97 | pci_write_long(nb, 0xbc, (0xb77cd800)); 98 | pci_write_long(nb, 0xb8, 0x1ff94); 99 | pci_write_long(nb, 0xbc, (0x78010000 | (peekhi))); 100 | pci_write_long(nb, 0xb8, 0x1ff98); 101 | pci_write_long(nb, 0xbc, (0x38210000 | (peeklo))); 102 | pci_write_long(nb, 0xb8, 0x1ff9c); 103 | pci_write_long(nb, 0xbc, (0x5b610000)); 104 | pci_write_long(nb, 0xb8, 0x1ffa0); 105 | pci_write_long(nb, 0xbc, (0x78010001)); 106 | pci_write_long(nb, 0xb8, 0x1ffa4); 107 | pci_write_long(nb, 0xbc, (0x3821fff0)); 108 | pci_write_long(nb, 0xb8, 0x1ffa8); 109 | pci_write_long(nb, 0xbc, (0x5b61fffc)); 110 | pci_write_long(nb, 0xb8, 0x1ffac); 111 | pci_write_long(nb, 0xbc, (0x2b61fffc)); 112 | pci_write_long(nb, 0xb8, 0x1ffb0); 113 | pci_write_long(nb, 0xbc, (0x2b620000)); 114 | pci_write_long(nb, 0xb8, 0x1ffb4); 115 | pci_write_long(nb, 0xbc, (0x28420000)); 116 | pci_write_long(nb, 0xb8, 0x1ffb8); 117 | pci_write_long(nb, 0xbc, (0x58220000)); 118 | pci_write_long(nb, 0xb8, 0x1ffbc); 119 | pci_write_long(nb, 0xbc, (0x2b9b0008)); 120 | pci_write_long(nb, 0xb8, 0x1ffc0); 121 | pci_write_long(nb, 0xbc, (0x2b9d0004)); 122 | pci_write_long(nb, 0xb8, 0x1ffc4); 123 | pci_write_long(nb, 0xbc, (0x379c0010)); 124 | pci_write_long(nb, 0xb8, 0x1ffc8); 125 | pci_write_long(nb, 0xbc, (0xc3a00000)); // ret 126 | 127 | // add new service request 128 | uint32_t addr; 129 | for (addr = 0x1dbe0; addr < 0x1dbec; addr+=4) { 130 | pci_write_long(nb, 0xb8, addr); 131 | pci_write_long(nb, 0xbc, 0x1ff80); 132 | } 133 | 134 | uint8_t ack = 0; 135 | while ((ack & 0x3) == 0) { // 0x4 136 | pci_write_long(nb, 0xb8, 0xe0003004); 137 | ack = pci_read_long(nb, 0xbc); 138 | } 139 | pci_write_long(nb, 0xb8, 0xe0003000); 140 | ack = pci_read_long(nb, 0xbc); 141 | ack ^= 1; 142 | ack |= (106 << 1); 143 | pci_write_long(nb, 0xb8, 0xe0003000); 144 | pci_write_long(nb, 0xbc, ack); 145 | 146 | do { 147 | pci_write_long(nb, 0xb8, 0xe0003004); 148 | ack = pci_read_long(nb, 0xbc); 149 | } while ((ack & 0x1) == 0); 150 | 151 | do { 152 | pci_write_long(nb, 0xb8, 0xe0003004); 153 | ack = pci_read_long(nb, 0xbc); 154 | } while ((ack & 0x2) == 0); 155 | 156 | usleep(10000); 157 | uint32_t roml; 158 | pci_write_long(nb, 0xb8, 0x1fff0); 159 | roml = pci_read_long(nb, 0xbc); 160 | printf("%c%c%c%c", 161 | (roml >> 24) & 0xff, 162 | (roml >> 16) & 0xff, 163 | (roml >> 8) & 0xff, 164 | (roml & 0xff)); 165 | 166 | fflush(stdout); 167 | } // end loop 168 | 169 | fprintf(stderr, "exiting\n"); 170 | pci_cleanup(pacc); 171 | return 0; 172 | } 173 | -------------------------------------------------------------------------------- /swap.py: -------------------------------------------------------------------------------- 1 | # smutool Tool for SMU 2 | # Copyright (C) 2015 Damien Zammit 3 | # 4 | # This program is free software: you can redistribute it and/or modify 5 | # it under the terms of the GNU General Public License as published by 6 | # the Free Software Foundation, either version 3 of the License, or 7 | # (at your option) any later version. 8 | # 9 | # This program is distributed in the hope that it will be useful, 10 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | # GNU General Public License for more details. 13 | # See . 14 | # 15 | 16 | import sys 17 | 18 | args=sys.argv 19 | if len(sys.argv) == 1: 20 | print "Usage: python signsmu.py " 21 | sys.exit() 22 | 23 | def reverse(strs): 24 | return ''.join([strs[i] for i in xrange(len(strs)-1, -1, -1)]) 25 | 26 | f = open(args[1], "rb") 27 | firmware = bytearray() 28 | try: 29 | firmware = bytearray(f.read()) 30 | finally: 31 | f.close() 32 | 33 | for wcnt in range(0,len(firmware)/4): 34 | tmp = firmware[wcnt*4] 35 | firmware[wcnt*4] = firmware[wcnt*4+3] 36 | firmware[wcnt*4+3] = tmp 37 | tmp = firmware[wcnt*4+1] 38 | firmware[wcnt*4+1] = firmware[wcnt*4+2] 39 | firmware[wcnt*4+2] = tmp 40 | 41 | sys.stdout.write(firmware) 42 | --------------------------------------------------------------------------------