├── README.md └── project_caches ├── cache_project_handout.pdf ├── clog2.v ├── d_cache.v ├── d_cache_tb ├── Makefile ├── d_cache.vvp ├── d_cache_tb.v └── d_mem_data.txt ├── hardware ├── dec_2_to_1.v ├── dec_4_to_2.v ├── mux_2_to_1.v └── mux_4_to_1.v ├── i_cache.v ├── i_cache_tb ├── Makefile ├── i_cache.vvp ├── i_cache_tb.v └── i_mem_data.txt ├── mem.v ├── old └── notes.txt └── report_part_A.pdf /README.md: -------------------------------------------------------------------------------- 1 | # Processor-Cache 2 | A Verilog implementation of a data and instruction processor cache, created as part of a final project for Computer Architecture (EENG 467) at Yale. Auxillary modules such as memory and testbench initialization were created by Jakub Szefer. 3 | 4 | The data cache implements a 32 KiB, 4-way set associative, 2-word block cache with 32 bit words. The instruction cache implements a 16 KiB, 2-way set associative, 1-word block cache with 32 bit words. Both are write-back, write-allocate caches with an LRU replacement policy. 5 | -------------------------------------------------------------------------------- /project_caches/cache_project_handout.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zebmehring/Processor-Cache/898f61b0a6eb9db44bf947c09baacdcad66799b8/project_caches/cache_project_handout.pdf -------------------------------------------------------------------------------- /project_caches/clog2.v: -------------------------------------------------------------------------------- 1 | 2 | `define CLOG2(x) ( \ 3 | (x <= 2) ? 1 : \ 4 | (x <= 4) ? 2 : \ 5 | (x <= 8) ? 3 : \ 6 | (x <= 16) ? 4 : \ 7 | (x <= 32) ? 5 : \ 8 | (x <= 64) ? 6 : \ 9 | (x <= 128) ? 7 : \ 10 | (x <= 256) ? 8 : \ 11 | (x <= 512) ? 9 : \ 12 | (x <= 1024) ? 10 : \ 13 | (x <= 2048) ? 11 : \ 14 | (x <= 4096) ? 12 : \ 15 | (x <= 8192) ? 13 : \ 16 | (x <= 16384) ? 14 : \ 17 | (x <= 32768) ? 15 : \ 18 | (x <= 65536) ? 16 : \ 19 | (x <= 131072) ? 17 : \ 20 | (x <= 262144) ? 18 : \ 21 | (x <= 524288) ? 19 : \ 22 | (x <= 1048576) ? 20 : \ 23 | (x <= 2097152) ? 21 : \ 24 | (x <= 4194304) ? 22 : \ 25 | (x <= 8388608) ? 23 : \ 26 | (x <= 16777216) ? 24 : \ 27 | (x <= 33554432) ? 25 : \ 28 | (x <= 67108864) ? 26 : \ 29 | (x <= 134217728) ? 27 : \ 30 | (x <= 268435456) ? 28 : \ 31 | (x <= 536870912) ? 29 : \ 32 | (x <= 1073741824) ? 30 : \ 33 | -1) 34 | 35 | -------------------------------------------------------------------------------- /project_caches/d_cache.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * 4 | * A data cache module 5 | * 6 | */ 7 | 8 | `define TAG 31:13 // position of tag in address 9 | `define INDEX 12:3 // position of index in address 10 | `define OFFSET 2:0 // position of offset in address 11 | 12 | module d_cache 13 | #( 14 | // Cache parameters 15 | parameter SIZE = 32*1024*8, 16 | parameter NWAYS = 4, 17 | parameter NSETS = 1024, 18 | parameter BLOCK_SIZE = 64, 19 | parameter WIDTH = 32, 20 | // Memory related paramter, make sure it matches memory module 21 | parameter MWIDTH = 64, // same as block size 22 | // More cache related parameters 23 | parameter INDEX_WIDTH = 10, 24 | parameter TAG_WIDTH = 19, 25 | parameter OFFSET_WIDTH = 3, 26 | parameter WORD1 = 3, 27 | parameter WORD2 = 7 28 | ) 29 | ( 30 | input wire clock, 31 | input wire [WIDTH-1:0] address, // address form CPU 32 | input wire [WIDTH-1:0] din, // data from CPU (if st inst) 33 | input wire rden, // 1 if ld instruction 34 | input wire wren, // 1 if st instruction 35 | output wire hit_miss, // 1 if hit, 0 while handling miss 36 | output wire [WIDTH-1:0] q, // data from cache to CPU 37 | output wire [MWIDTH-1:0] mdout, // data from cache to memory 38 | output wire [WIDTH-1:0] mrdaddress, // memory read address 39 | output wire mrden, // read enable, 1 if reading from memory 40 | output wire [WIDTH-1:0] mwraddress, // memory write address 41 | output wire mwren, // write enable, 1 if writing to memory 42 | input wire [MWIDTH-1:0] mq // data coming from memory 43 | ); 44 | 45 | /******************************************************************* 46 | * Global Parameters and Initializations 47 | *******************************************************************/ 48 | 49 | // WAY 1 cache data 50 | reg valid1 [0:NSETS-1]; 51 | reg dirty1 [0:NSETS-1]; 52 | reg [1:0] lru1 [0:NSETS-1]; 53 | reg [TAG_WIDTH-1:0] tag1 [0:NSETS-1]; 54 | reg [MWIDTH-1:0] mem1 [0:NSETS-1] /* synthesis ramstyle = "M20K" */; 55 | 56 | // WAY 2 cache data 57 | reg valid2 [0:NSETS-1]; 58 | reg dirty2 [0:NSETS-1]; 59 | reg [1:0] lru2 [0:NSETS-1]; 60 | reg [TAG_WIDTH-1:0] tag2 [0:NSETS-1]; 61 | reg [MWIDTH-1:0] mem2 [0:NSETS-1] /* synthesis ramstyle = "M20K" */; 62 | 63 | // WAY 3 cache data 64 | reg valid3 [0:NSETS-1]; 65 | reg dirty3 [0:NSETS-1]; 66 | reg [1:0] lru3 [0:NSETS-1]; 67 | reg [TAG_WIDTH-1:0] tag3 [0:NSETS-1]; 68 | reg [MWIDTH-1:0] mem3 [0:NSETS-1] /* synthesis ramstyle = "M20K" */; 69 | 70 | // WAY 4 cache data 71 | reg valid4 [0:NSETS-1]; 72 | reg dirty4 [0:NSETS-1]; 73 | reg [1:0] lru4 [0:NSETS-1]; 74 | reg [TAG_WIDTH-1:0] tag4 [0:NSETS-1]; 75 | reg [MWIDTH-1:0] mem4 [0:NSETS-1] /* synthesis ramstyle = "M20K" */; 76 | 77 | // initialize the cache to zero 78 | integer k; 79 | initial 80 | begin 81 | for(k = 0; k < NSETS; k = k +1) 82 | begin 83 | valid1[k] = 0; 84 | valid2[k] = 0; 85 | valid3[k] = 0; 86 | valid4[k] = 0; 87 | dirty1[k] = 0; 88 | dirty2[k] = 0; 89 | dirty3[k] = 0; 90 | dirty4[k] = 0; 91 | lru1[k] = 2'b00; 92 | lru2[k] = 2'b00; 93 | lru3[k] = 2'b00; 94 | lru4[k] = 2'b00; 95 | end 96 | end 97 | 98 | // internal registers 99 | reg _hit_miss = 1'b0; 100 | reg [WIDTH-1:0] _q = {WIDTH{1'b0}}; 101 | reg [MWIDTH-1:0] _mdout = {MWIDTH{1'b0}}; 102 | reg [WIDTH-1:0] _mwraddress = {WIDTH{1'b0}}; 103 | reg _mwren = 1'b0; 104 | 105 | // output assignments of internal registers 106 | assign hit_miss = _hit_miss; 107 | assign mrden = !((valid1[address[`INDEX]] && (tag1[address[`INDEX]] == address[`TAG])) 108 | || (valid2[address[`INDEX]] && (tag2[address[`INDEX]] == address[`TAG])) 109 | || (valid3[address[`INDEX]] && (tag3[address[`INDEX]] == address[`TAG])) 110 | || (valid4[address[`INDEX]] && (tag4[address[`INDEX]] == address[`TAG]))); 111 | assign mwren = _mwren; 112 | assign mdout = _mdout; 113 | assign mrdaddress = {address[`TAG],address[`INDEX]}; 114 | assign mwraddress = _mwraddress; 115 | assign q = _q; 116 | 117 | // state parameters 118 | parameter idle = 1'b0; // receive requests from CPU 119 | parameter miss = 1'b1; // write back dirty block and put in new data 120 | 121 | // state register 122 | reg currentState = idle; 123 | 124 | /******************************************************************* 125 | * State Machine 126 | *******************************************************************/ 127 | 128 | always @(posedge clock) 129 | begin 130 | case (currentState) 131 | idle: begin 132 | // reset write enable, if it was turned on 133 | _mwren <= 0; 134 | // set _hit_miss register 135 | _hit_miss <= ((valid1[address[`INDEX]] && (tag1[address[`INDEX]] == address[`TAG])) 136 | || (valid2[address[`INDEX]] && (tag2[address[`INDEX]] == address[`TAG])) 137 | || (valid3[address[`INDEX]] && (tag3[address[`INDEX]] == address[`TAG])) 138 | || (valid4[address[`INDEX]] && (tag4[address[`INDEX]] == address[`TAG]))); 139 | 140 | // do nothing on a null request 141 | if(~rden && ~wren) currentState <= idle; 142 | 143 | // check way 1 144 | else if(valid1[address[`INDEX]] && (tag1[address[`INDEX]] == address[`TAG])) 145 | begin 146 | // read hit 147 | if(rden) _q <= (address[`OFFSET] <= WORD1) ? mem1[address[`INDEX]][WIDTH-1:0] : mem1[address[`INDEX]][2*WIDTH-1:WIDTH]; 148 | // write hit 149 | else if(wren) 150 | begin 151 | _q = {WIDTH{1'b0}}; 152 | dirty1[address[`INDEX]] <= 1; 153 | if(address[`OFFSET] <= WORD1) mem1[address[`INDEX]][WIDTH-1:0] <= din; 154 | else mem1[address[`INDEX]][2*WIDTH-1:WIDTH] <= din; 155 | end 156 | // update LRU data 157 | if(lru2[address[`INDEX]] <= lru1[address[`INDEX]]) lru2[address[`INDEX]] <= lru2[address[`INDEX]] + 1; 158 | if(lru3[address[`INDEX]] <= lru1[address[`INDEX]]) lru3[address[`INDEX]] <= lru3[address[`INDEX]] + 1; 159 | if(lru4[address[`INDEX]] <= lru1[address[`INDEX]]) lru4[address[`INDEX]] <= lru4[address[`INDEX]] + 1; 160 | lru1[address[`INDEX]] <= 0; 161 | end 162 | 163 | // check way 2 164 | else if(valid2[address[`INDEX]] && (tag2[address[`INDEX]] == address[`TAG])) 165 | begin 166 | // read hit 167 | if(rden) _q <= (address[`OFFSET] <= WORD1) ? mem2[address[`INDEX]][WIDTH-1:0] : mem2[address[`INDEX]][2*WIDTH-1:WIDTH]; 168 | // write hit 169 | else if(wren) 170 | begin 171 | _q = {WIDTH{1'b0}}; 172 | dirty2[address[`INDEX]] <= 1; 173 | if(address[`OFFSET] <= WORD1) mem2[address[`INDEX]][WIDTH-1:0] <= din; 174 | else mem2[address[`INDEX]][2*WIDTH-1:WIDTH] <= din; 175 | end 176 | // update LRU data 177 | if(lru1[address[`INDEX]] <= lru2[address[`INDEX]]) lru1[address[`INDEX]] <= lru1[address[`INDEX]] + 1; 178 | if(lru3[address[`INDEX]] <= lru2[address[`INDEX]]) lru3[address[`INDEX]] <= lru3[address[`INDEX]] + 1; 179 | if(lru4[address[`INDEX]] <= lru2[address[`INDEX]]) lru4[address[`INDEX]] <= lru4[address[`INDEX]] + 1; 180 | lru2[address[`INDEX]] <= 0; 181 | end 182 | 183 | // check way 3 184 | else if(valid3[address[`INDEX]] && (tag3[address[`INDEX]] == address[`TAG])) 185 | begin 186 | // read hit 187 | if(rden) _q <= (address[`OFFSET] <= WORD1) ? mem3[address[`INDEX]][WIDTH-1:0] : mem3[address[`INDEX]][2*WIDTH-1:WIDTH]; 188 | // write hit 189 | else if(wren) 190 | begin 191 | _q = {WIDTH{1'b0}}; 192 | dirty3[address[`INDEX]] <= 1; 193 | if(address[`OFFSET] <= WORD1) mem3[address[`INDEX]][WIDTH-1:0] <= din; 194 | else mem3[address[`INDEX]][2*WIDTH-1:WIDTH] <= din; 195 | end 196 | // update LRU data 197 | if(lru1[address[`INDEX]] <= lru3[address[`INDEX]]) lru1[address[`INDEX]] <= lru1[address[`INDEX]] + 1; 198 | if(lru2[address[`INDEX]] <= lru3[address[`INDEX]]) lru2[address[`INDEX]] <= lru2[address[`INDEX]] + 1; 199 | if(lru4[address[`INDEX]] <= lru3[address[`INDEX]]) lru4[address[`INDEX]] <= lru4[address[`INDEX]] + 1; 200 | lru3[address[`INDEX]] <= 0; 201 | end 202 | 203 | // check way 4 204 | else if(valid4[address[`INDEX]] && (tag4[address[`INDEX]] == address[`TAG])) 205 | begin 206 | // read hit 207 | if(rden) _q <= (address[`OFFSET] <= WORD1) ? mem4[address[`INDEX]][WIDTH-1:0] : mem4[address[`INDEX]][2*WIDTH-1:WIDTH]; 208 | // write hit 209 | else if(wren) 210 | begin 211 | _q = {WIDTH{1'b0}}; 212 | dirty4[address[`INDEX]] <= 1; 213 | if(address[`OFFSET] <= WORD1) mem4[address[`INDEX]][WIDTH-1:0] <= din; 214 | else mem4[address[`INDEX]][2*WIDTH-1:WIDTH] <= din; 215 | end 216 | // update LRU data 217 | if(lru1[address[`INDEX]] <= lru4[address[`INDEX]]) lru1[address[`INDEX]] <= lru1[address[`INDEX]] + 1; 218 | if(lru2[address[`INDEX]] <= lru4[address[`INDEX]]) lru2[address[`INDEX]] <= lru2[address[`INDEX]] + 1; 219 | if(lru3[address[`INDEX]] <= lru4[address[`INDEX]]) lru3[address[`INDEX]] <= lru3[address[`INDEX]] + 1; 220 | lru4[address[`INDEX]] <= 0; 221 | end 222 | 223 | // miss 224 | else currentState <= miss; 225 | end 226 | 227 | miss: begin 228 | // one of the ways is invalid -- no need to evict 229 | if(~valid1[address[`INDEX]]) 230 | begin 231 | mem1[address[`INDEX]] <= mq; 232 | tag1[address[`INDEX]] <= address[`TAG]; 233 | dirty1[address[`INDEX]] <= 0; 234 | valid1[address[`INDEX]] <= 1; 235 | end 236 | 237 | else if(~valid2[address[`INDEX]]) 238 | begin 239 | mem2[address[`INDEX]] <= mq; 240 | tag2[address[`INDEX]] <= address[`TAG]; 241 | dirty2[address[`INDEX]] <= 0; 242 | valid2[address[`INDEX]] <= 1; 243 | end 244 | 245 | else if(~valid3[address[`INDEX]]) 246 | begin 247 | mem3[address[`INDEX]] <= mq; 248 | tag3[address[`INDEX]] <= address[`TAG]; 249 | dirty3[address[`INDEX]] <= 0; 250 | valid3[address[`INDEX]] <= 1; 251 | end 252 | 253 | else if(~valid4[address[`INDEX]]) 254 | begin 255 | mem4[address[`INDEX]] <= mq; 256 | tag4[address[`INDEX]] <= address[`TAG]; 257 | dirty4[address[`INDEX]] <= 0; 258 | valid4[address[`INDEX]] <= 1; 259 | end 260 | 261 | // way 1 is LRU 262 | else if(lru1[address[`INDEX]] == 3) 263 | begin 264 | // dirty block writeback 265 | if(dirty1[address[`INDEX]] == 1) 266 | begin 267 | _mwraddress <= {tag1[address[`INDEX]],address[`INDEX]}; 268 | _mwren <= 1; 269 | _mdout <= mem1[address[`INDEX]]; 270 | end 271 | mem1[address[`INDEX]] <= mq; 272 | tag1[address[`INDEX]] <= address[`TAG]; 273 | dirty1[address[`INDEX]] <= 0; 274 | valid1[address[`INDEX]] <= 1; 275 | end 276 | 277 | // way 2 is LRU 278 | else if(lru2[address[`INDEX]] == 3) 279 | begin 280 | // dirty block writeback 281 | if(dirty2[address[`INDEX]] == 1) 282 | begin 283 | _mwraddress <= {tag2[address[`INDEX]],address[`INDEX]}; 284 | _mwren <= 1; 285 | _mdout <= mem2[address[`INDEX]]; 286 | end 287 | mem2[address[`INDEX]] <= mq; 288 | tag2[address[`INDEX]] <= address[`TAG]; 289 | dirty2[address[`INDEX]] <= 0; 290 | valid2[address[`INDEX]] <= 1; 291 | end 292 | 293 | // way 3 is LRU 294 | else if(lru3[address[`INDEX]] == 3) 295 | begin 296 | // dirty block writeback 297 | if(dirty3[address[`INDEX]] == 1) 298 | begin 299 | _mwraddress <= {tag3[address[`INDEX]],address[`INDEX]}; 300 | _mwren <= 1; 301 | _mdout <= mem3[address[`INDEX]]; 302 | end 303 | mem3[address[`INDEX]] <= mq; 304 | tag3[address[`INDEX]] <= address[`TAG]; 305 | dirty3[address[`INDEX]] <= 0; 306 | valid3[address[`INDEX]] <= 1; 307 | end 308 | 309 | // way 4 is LRU 310 | else if(lru4[address[`INDEX]] == 3) 311 | begin 312 | // dirty block writeback 313 | if(dirty4[address[`INDEX]] == 1) 314 | begin 315 | _mwraddress <= {tag4[address[`INDEX]],address[`INDEX]}; 316 | _mwren <= 1; 317 | _mdout <= mem4[address[`INDEX]]; 318 | end 319 | mem4[address[`INDEX]] <= mq; 320 | tag4[address[`INDEX]] <= address[`TAG]; 321 | dirty4[address[`INDEX]] <= 0; 322 | valid4[address[`INDEX]] <= 1; 323 | end 324 | 325 | currentState <= idle; 326 | end 327 | 328 | default: currentState <= idle; 329 | 330 | endcase 331 | 332 | end 333 | 334 | endmodule 335 | 336 | -------------------------------------------------------------------------------- /project_caches/d_cache_tb/Makefile: -------------------------------------------------------------------------------- 1 | SHELL := /bin/bash 2 | 3 | all: run 4 | 5 | d_cache.vvp: ../d_cache.v ../clog2.v ../mem.v d_cache_tb.v 6 | @echo "Building..." 7 | iverilog -Wall -Wno-timescale -o d_cache.vvp ../d_cache.v ../clog2.v ../mem.v d_cache_tb.v 8 | @echo "Done building." 9 | 10 | run: d_cache.vvp 11 | @echo "Simulating..." 12 | @./d_cache.vvp 13 | @echo "Done simulating." 14 | 15 | clean: 16 | rm -f d_cache.vvp 17 | 18 | -------------------------------------------------------------------------------- /project_caches/d_cache_tb/d_cache.vvp: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "0.9.7 " "(v0_9_7)"; 3 | :vpi_time_precision - 12; 4 | :vpi_module "system"; 5 | :vpi_module "v2005_math"; 6 | :vpi_module "va_math"; 7 | S_0x26f8000 .scope module, "d_cache_test" "d_cache_test" 2 4; 8 | .timescale -9 -12; 9 | v0x277bcd0_0 .var "clk", 0 0; 10 | v0x277bd50_0 .var "d_cache_addr", 31 0; 11 | v0x277bdd0_0 .var "d_cache_din", 31 0; 12 | v0x277be50_0 .net "d_cache_hit_miss", 0 0, v0x2778c70_0; 1 drivers 13 | v0x277bed0_0 .net "d_cache_q", 31 0, v0x2778ed0_0; 1 drivers 14 | v0x277bf50_0 .var "d_cache_rden", 0 0; 15 | v0x277bfd0_0 .var "d_cache_wren", 0 0; 16 | v0x277c080_0 .net "data_in", 63 0, v0x2778d10_0; 1 drivers 17 | v0x277c1a0_0 .net "data_out", 63 0, v0x2778080_0; 1 drivers 18 | v0x277c270_0 .net "rd_addr", 31 0, L_0x277e640; 1 drivers 19 | v0x277c320_0 .net "rd_en", 0 0, L_0x277e390; 1 drivers 20 | v0x277c3a0_0 .net "wr_addr", 31 0, v0x2778db0_0; 1 drivers 21 | v0x277c420_0 .net "wr_en", 0 0, v0x2778e50_0; 1 drivers 22 | L_0x277eb50 .part L_0x277e640, 0, 7; 23 | L_0x277ebf0 .part v0x2778db0_0, 0, 7; 24 | S_0x2778440 .scope module, "DUT_CACHE" "d_cache" 2 21, 3 12, S_0x26f8000; 25 | .timescale 0 0; 26 | P_0x2778538 .param/l "BLOCK_SIZE" 3 18, +C4<01000000>; 27 | P_0x2778560 .param/l "INDEX_WIDTH" 3 23, +C4<01010>; 28 | P_0x2778588 .param/l "MWIDTH" 3 21, +C4<01000000>; 29 | P_0x27785b0 .param/l "NSETS" 3 17, +C4<010000000000>; 30 | P_0x27785d8 .param/l "NWAYS" 3 16, +C4<0100>; 31 | P_0x2778600 .param/l "OFFSET_WIDTH" 3 25, +C4<011>; 32 | P_0x2778628 .param/l "SIZE" 3 15, +C4<01000000000000000000>; 33 | P_0x2778650 .param/l "TAG_WIDTH" 3 24, +C4<010011>; 34 | P_0x2778678 .param/l "WIDTH" 3 19, +C4<0100000>; 35 | P_0x27786a0 .param/l "WORD1" 3 26, +C4<011>; 36 | P_0x27786c8 .param/l "WORD2" 3 27, +C4<0111>; 37 | P_0x27786f0 .param/l "idle" 3 118, C4<0>; 38 | P_0x2778718 .param/l "miss" 3 119, C4<1>; 39 | L_0x277cb30 .functor AND 1, L_0x277c540, L_0x277ca10, C4<1>, C4<1>; 40 | L_0x277cfa0 .functor AND 1, L_0x277cc30, L_0x277d0a0, C4<1>, C4<1>; 41 | L_0x277d2a0 .functor OR 1, L_0x277cb30, L_0x277cfa0, C4<0>, C4<0>; 42 | L_0x277c980 .functor AND 1, L_0x277d3a0, L_0x277d870, C4<1>, C4<1>; 43 | L_0x277daf0 .functor OR 1, L_0x277d2a0, L_0x277c980, C4<0>, C4<0>; 44 | L_0x277df20 .functor AND 1, L_0x277dbf0, L_0x277dfe0, C4<1>, C4<1>; 45 | L_0x277e240 .functor OR 1, L_0x277daf0, L_0x277df20, C4<0>, C4<0>; 46 | v0x2778c70_0 .var "_hit_miss", 0 0; 47 | v0x2778d10_0 .var "_mdout", 63 0; 48 | v0x2778db0_0 .var "_mwraddress", 31 0; 49 | v0x2778e50_0 .var "_mwren", 0 0; 50 | v0x2778ed0_0 .var "_q", 31 0; 51 | v0x2778f70_0 .net *"_s11", 18 0, L_0x277c8b0; 1 drivers 52 | v0x2779050_0 .net *"_s12", 0 0, L_0x277ca10; 1 drivers 53 | v0x27790f0_0 .net *"_s14", 0 0, L_0x277cb30; 1 drivers 54 | v0x27791e0_0 .net *"_s16", 0 0, L_0x277cc30; 1 drivers 55 | v0x2779280_0 .net *"_s19", 9 0, L_0x277ccd0; 1 drivers 56 | v0x2779320_0 .net *"_s2", 0 0, L_0x277c540; 1 drivers 57 | v0x27793c0_0 .net *"_s20", 18 0, L_0x277ce10; 1 drivers 58 | v0x27794d0_0 .net *"_s23", 9 0, L_0x277ceb0; 1 drivers 59 | v0x2779570_0 .net *"_s25", 18 0, L_0x277d000; 1 drivers 60 | v0x2779690_0 .net *"_s26", 0 0, L_0x277d0a0; 1 drivers 61 | v0x2779730_0 .net *"_s28", 0 0, L_0x277cfa0; 1 drivers 62 | v0x27795f0_0 .net *"_s30", 0 0, L_0x277d2a0; 1 drivers 63 | v0x2779880_0 .net *"_s32", 0 0, L_0x277d3a0; 1 drivers 64 | v0x27799a0_0 .net *"_s35", 9 0, L_0x277d440; 1 drivers 65 | v0x2779a20_0 .net *"_s36", 18 0, L_0x277d640; 1 drivers 66 | v0x2779900_0 .net *"_s39", 9 0, L_0x277d6e0; 1 drivers 67 | v0x2779b50_0 .net *"_s41", 18 0, L_0x277d7d0; 1 drivers 68 | v0x2779aa0_0 .net *"_s42", 0 0, L_0x277d870; 1 drivers 69 | v0x2779c90_0 .net *"_s44", 0 0, L_0x277c980; 1 drivers 70 | v0x2779bf0_0 .net *"_s46", 0 0, L_0x277daf0; 1 drivers 71 | v0x2779de0_0 .net *"_s48", 0 0, L_0x277dbf0; 1 drivers 72 | v0x2779d30_0 .net *"_s5", 9 0, L_0x277c5e0; 1 drivers 73 | v0x2779f40_0 .net *"_s51", 9 0, L_0x277dc90; 1 drivers 74 | v0x2779e80_0 .net *"_s52", 18 0, L_0x277d9b0; 1 drivers 75 | v0x277a0b0_0 .net *"_s55", 9 0, L_0x277de30; 1 drivers 76 | v0x2779fc0_0 .net *"_s57", 18 0, L_0x277dd80; 1 drivers 77 | v0x277a230_0 .net *"_s58", 0 0, L_0x277dfe0; 1 drivers 78 | v0x277a130_0 .net *"_s6", 18 0, L_0x277c720; 1 drivers 79 | v0x277a3c0_0 .net *"_s60", 0 0, L_0x277df20; 1 drivers 80 | v0x277a2b0_0 .net *"_s62", 0 0, L_0x277e240; 1 drivers 81 | v0x277a560_0 .net *"_s71", 18 0, L_0x277e5a0; 1 drivers 82 | v0x277a440_0 .net *"_s73", 9 0, L_0x277e120; 1 drivers 83 | v0x277a4e0_0 .net *"_s74", 28 0, L_0x277e720; 1 drivers 84 | v0x277a720_0 .net *"_s79", 2 0, C4<000>; 1 drivers 85 | v0x277a7a0_0 .net *"_s9", 9 0, L_0x277c7c0; 1 drivers 86 | v0x277a5e0_0 .net "address", 31 0, v0x277bd50_0; 1 drivers 87 | v0x277a680_0 .net "clock", 0 0, v0x277bcd0_0; 1 drivers 88 | v0x277a980_0 .var "currentState", 0 0; 89 | v0x277aa00_0 .net "din", 31 0, v0x277bdd0_0; 1 drivers 90 | v0x277a820 .array "dirty1", 1023 0, 0 0; 91 | v0x277a8a0 .array "dirty2", 1023 0, 0 0; 92 | v0x277ac00 .array "dirty3", 1023 0, 0 0; 93 | v0x277ac80 .array "dirty4", 1023 0, 0 0; 94 | v0x277aa80_0 .alias "hit_miss", 0 0, v0x277be50_0; 95 | v0x277ab20_0 .var/i "k", 31 0; 96 | v0x277aea0 .array "lru1", 1023 0, 1 0; 97 | v0x277af20 .array "lru2", 1023 0, 1 0; 98 | v0x277ad00 .array "lru3", 1023 0, 1 0; 99 | v0x277ad80 .array "lru4", 1023 0, 1 0; 100 | v0x277ae00_0 .alias "mdout", 63 0, v0x277c080_0; 101 | v0x277b160 .array "mem1", 1023 0, 63 0; 102 | v0x277afa0 .array "mem2", 1023 0, 63 0; 103 | v0x277b020 .array "mem3", 1023 0, 63 0; 104 | v0x277b0a0 .array "mem4", 1023 0, 63 0; 105 | v0x277b3c0_0 .alias "mq", 63 0, v0x277c1a0_0; 106 | v0x277b1e0_0 .alias "mrdaddress", 31 0, v0x277c270_0; 107 | v0x277b260_0 .alias "mrden", 0 0, v0x277c320_0; 108 | v0x277b310_0 .alias "mwraddress", 31 0, v0x277c3a0_0; 109 | v0x277b640_0 .alias "mwren", 0 0, v0x277c420_0; 110 | v0x277b440_0 .alias "q", 31 0, v0x277bed0_0; 111 | v0x277b4c0_0 .net "rden", 0 0, v0x277bf50_0; 1 drivers 112 | v0x277b540 .array "tag1", 1023 0, 18 0; 113 | v0x277b5c0 .array "tag2", 1023 0, 18 0; 114 | v0x277b8f0 .array "tag3", 1023 0, 18 0; 115 | v0x277b970 .array "tag4", 1023 0, 18 0; 116 | v0x277b6c0 .array "valid1", 1023 0, 0 0; 117 | v0x277b740 .array "valid2", 1023 0, 0 0; 118 | v0x277b7c0 .array "valid3", 1023 0, 0 0; 119 | v0x277b840 .array "valid4", 1023 0, 0 0; 120 | v0x277bc50_0 .net "wren", 0 0, v0x277bfd0_0; 1 drivers 121 | L_0x277c540 .array/port v0x277b6c0, L_0x277c5e0; 122 | L_0x277c5e0 .part v0x277bd50_0, 3, 10; 123 | L_0x277c720 .array/port v0x277b540, L_0x277c7c0; 124 | L_0x277c7c0 .part v0x277bd50_0, 3, 10; 125 | L_0x277c8b0 .part v0x277bd50_0, 13, 19; 126 | L_0x277ca10 .cmp/eq 19, L_0x277c720, L_0x277c8b0; 127 | L_0x277cc30 .array/port v0x277b740, L_0x277ccd0; 128 | L_0x277ccd0 .part v0x277bd50_0, 3, 10; 129 | L_0x277ce10 .array/port v0x277b5c0, L_0x277ceb0; 130 | L_0x277ceb0 .part v0x277bd50_0, 3, 10; 131 | L_0x277d000 .part v0x277bd50_0, 13, 19; 132 | L_0x277d0a0 .cmp/eq 19, L_0x277ce10, L_0x277d000; 133 | L_0x277d3a0 .array/port v0x277b7c0, L_0x277d440; 134 | L_0x277d440 .part v0x277bd50_0, 3, 10; 135 | L_0x277d640 .array/port v0x277b8f0, L_0x277d6e0; 136 | L_0x277d6e0 .part v0x277bd50_0, 3, 10; 137 | L_0x277d7d0 .part v0x277bd50_0, 13, 19; 138 | L_0x277d870 .cmp/eq 19, L_0x277d640, L_0x277d7d0; 139 | L_0x277dbf0 .array/port v0x277b840, L_0x277dc90; 140 | L_0x277dc90 .part v0x277bd50_0, 3, 10; 141 | L_0x277d9b0 .array/port v0x277b970, L_0x277de30; 142 | L_0x277de30 .part v0x277bd50_0, 3, 10; 143 | L_0x277dd80 .part v0x277bd50_0, 13, 19; 144 | L_0x277dfe0 .cmp/eq 19, L_0x277d9b0, L_0x277dd80; 145 | L_0x277e390 .reduce/nor L_0x277e240; 146 | L_0x277e5a0 .part v0x277bd50_0, 13, 19; 147 | L_0x277e120 .part v0x277bd50_0, 3, 10; 148 | L_0x277e720 .concat [ 10 19 0 0], L_0x277e120, L_0x277e5a0; 149 | L_0x277e640 .concat [ 29 3 0 0], L_0x277e720, C4<000>; 150 | S_0x26f7d70 .scope module, "DUT_MEM" "mem" 2 44, 4 9, S_0x26f8000; 151 | .timescale 0 0; 152 | P_0x2753338 .param/l "DEPTH" 4 12, +C4<010000000>; 153 | P_0x2753360 .param/str "FILE" 4 13, "d_mem_data.txt"; 154 | P_0x2753388 .param/l "INIT" 4 14, +C4<0>; 155 | P_0x27533b0 .param/l "WIDTH" 4 11, +C4<01000000>; 156 | v0x2735dc0_0 .alias "clock", 0 0, v0x277a680_0; 157 | v0x2777f60_0 .alias "data", 63 0, v0x277c080_0; 158 | v0x2778000 .array "mem", 127 0, 63 0; 159 | v0x2778080_0 .var "q", 63 0; 160 | v0x2778130_0 .net "rdaddress", 6 0, L_0x277eb50; 1 drivers 161 | v0x27781d0_0 .alias "rden", 0 0, v0x277c320_0; 162 | v0x27782b0_0 .net "wraddress", 6 0, L_0x277ebf0; 1 drivers 163 | v0x2778350_0 .alias "wren", 0 0, v0x277c420_0; 164 | E_0x2759140 .event posedge, v0x2735dc0_0; 165 | .scope S_0x2778440; 166 | T_0 ; 167 | %set/v v0x277ab20_0, 0, 32; 168 | T_0.0 ; 169 | %load/v 8, v0x277ab20_0, 32; 170 | %cmpi/s 8, 1024, 32; 171 | %jmp/0xz T_0.1, 5; 172 | %ix/getv/s 3, v0x277ab20_0; 173 | %jmp/1 t_0, 4; 174 | %ix/load 1, 0, 0; 175 | %set/av v0x277b6c0, 0, 1; 176 | t_0 ; 177 | %ix/getv/s 3, v0x277ab20_0; 178 | %jmp/1 t_1, 4; 179 | %ix/load 1, 0, 0; 180 | %set/av v0x277b740, 0, 1; 181 | t_1 ; 182 | %ix/getv/s 3, v0x277ab20_0; 183 | %jmp/1 t_2, 4; 184 | %ix/load 1, 0, 0; 185 | %set/av v0x277b7c0, 0, 1; 186 | t_2 ; 187 | %ix/getv/s 3, v0x277ab20_0; 188 | %jmp/1 t_3, 4; 189 | %ix/load 1, 0, 0; 190 | %set/av v0x277b840, 0, 1; 191 | t_3 ; 192 | %ix/getv/s 3, v0x277ab20_0; 193 | %jmp/1 t_4, 4; 194 | %ix/load 1, 0, 0; 195 | %set/av v0x277a820, 0, 1; 196 | t_4 ; 197 | %ix/getv/s 3, v0x277ab20_0; 198 | %jmp/1 t_5, 4; 199 | %ix/load 1, 0, 0; 200 | %set/av v0x277a8a0, 0, 1; 201 | t_5 ; 202 | %ix/getv/s 3, v0x277ab20_0; 203 | %jmp/1 t_6, 4; 204 | %ix/load 1, 0, 0; 205 | %set/av v0x277ac00, 0, 1; 206 | t_6 ; 207 | %ix/getv/s 3, v0x277ab20_0; 208 | %jmp/1 t_7, 4; 209 | %ix/load 1, 0, 0; 210 | %set/av v0x277ac80, 0, 1; 211 | t_7 ; 212 | %ix/getv/s 3, v0x277ab20_0; 213 | %jmp/1 t_8, 4; 214 | %ix/load 1, 0, 0; 215 | %set/av v0x277aea0, 0, 2; 216 | t_8 ; 217 | %ix/getv/s 3, v0x277ab20_0; 218 | %jmp/1 t_9, 4; 219 | %ix/load 1, 0, 0; 220 | %set/av v0x277af20, 0, 2; 221 | t_9 ; 222 | %ix/getv/s 3, v0x277ab20_0; 223 | %jmp/1 t_10, 4; 224 | %ix/load 1, 0, 0; 225 | %set/av v0x277ad00, 0, 2; 226 | t_10 ; 227 | %ix/getv/s 3, v0x277ab20_0; 228 | %jmp/1 t_11, 4; 229 | %ix/load 1, 0, 0; 230 | %set/av v0x277ad80, 0, 2; 231 | t_11 ; 232 | %ix/load 0, 1, 0; 233 | %load/vp0/s 8, v0x277ab20_0, 32; 234 | %set/v v0x277ab20_0, 8, 32; 235 | %jmp T_0.0; 236 | T_0.1 ; 237 | %end; 238 | .thread T_0; 239 | .scope S_0x2778440; 240 | T_1 ; 241 | %set/v v0x2778c70_0, 0, 1; 242 | %end; 243 | .thread T_1; 244 | .scope S_0x2778440; 245 | T_2 ; 246 | %set/v v0x2778ed0_0, 0, 32; 247 | %end; 248 | .thread T_2; 249 | .scope S_0x2778440; 250 | T_3 ; 251 | %set/v v0x2778d10_0, 0, 64; 252 | %end; 253 | .thread T_3; 254 | .scope S_0x2778440; 255 | T_4 ; 256 | %set/v v0x2778db0_0, 0, 32; 257 | %end; 258 | .thread T_4; 259 | .scope S_0x2778440; 260 | T_5 ; 261 | %set/v v0x2778e50_0, 0, 1; 262 | %end; 263 | .thread T_5; 264 | .scope S_0x2778440; 265 | T_6 ; 266 | %set/v v0x277a980_0, 0, 1; 267 | %end; 268 | .thread T_6; 269 | .scope S_0x2778440; 270 | T_7 ; 271 | %wait E_0x2759140; 272 | %load/v 8, v0x277a980_0, 1; 273 | %cmpi/u 8, 0, 1; 274 | %jmp/1 T_7.0, 6; 275 | %cmpi/u 8, 1, 1; 276 | %jmp/1 T_7.1, 6; 277 | %ix/load 0, 1, 0; 278 | %assign/v0 v0x277a980_0, 0, 0; 279 | %jmp T_7.3; 280 | T_7.0 ; 281 | %ix/load 0, 1, 0; 282 | %assign/v0 v0x2778e50_0, 0, 0; 283 | %ix/load 1, 3, 0; 284 | %mov 4, 0, 1; 285 | %jmp/1 T_7.4, 4; 286 | %load/x1p 9, v0x277a5e0_0, 10; 287 | %jmp T_7.5; 288 | T_7.4 ; 289 | %mov 9, 2, 10; 290 | T_7.5 ; 291 | ; Save base=9 wid=10 in lookaside. 292 | %ix/get 3, 9, 10; 293 | %load/av 8, v0x277b6c0, 1; 294 | %ix/load 1, 3, 0; 295 | %mov 4, 0, 1; 296 | %jmp/1 T_7.6, 4; 297 | %load/x1p 28, v0x277a5e0_0, 10; 298 | %jmp T_7.7; 299 | T_7.6 ; 300 | %mov 28, 2, 10; 301 | T_7.7 ; 302 | ; Save base=28 wid=10 in lookaside. 303 | %ix/get 3, 28, 10; 304 | %load/av 9, v0x277b540, 19; 305 | %ix/load 1, 13, 0; 306 | %mov 4, 0, 1; 307 | %jmp/1 T_7.8, 4; 308 | %load/x1p 28, v0x277a5e0_0, 19; 309 | %jmp T_7.9; 310 | T_7.8 ; 311 | %mov 28, 2, 19; 312 | T_7.9 ; 313 | ; Save base=28 wid=19 in lookaside. 314 | %cmp/u 9, 28, 19; 315 | %mov 9, 4, 1; 316 | %and 8, 9, 1; 317 | %ix/load 1, 3, 0; 318 | %mov 4, 0, 1; 319 | %jmp/1 T_7.10, 4; 320 | %load/x1p 10, v0x277a5e0_0, 10; 321 | %jmp T_7.11; 322 | T_7.10 ; 323 | %mov 10, 2, 10; 324 | T_7.11 ; 325 | ; Save base=10 wid=10 in lookaside. 326 | %ix/get 3, 10, 10; 327 | %load/av 9, v0x277b740, 1; 328 | %ix/load 1, 3, 0; 329 | %mov 4, 0, 1; 330 | %jmp/1 T_7.12, 4; 331 | %load/x1p 29, v0x277a5e0_0, 10; 332 | %jmp T_7.13; 333 | T_7.12 ; 334 | %mov 29, 2, 10; 335 | T_7.13 ; 336 | ; Save base=29 wid=10 in lookaside. 337 | %ix/get 3, 29, 10; 338 | %load/av 10, v0x277b5c0, 19; 339 | %ix/load 1, 13, 0; 340 | %mov 4, 0, 1; 341 | %jmp/1 T_7.14, 4; 342 | %load/x1p 29, v0x277a5e0_0, 19; 343 | %jmp T_7.15; 344 | T_7.14 ; 345 | %mov 29, 2, 19; 346 | T_7.15 ; 347 | ; Save base=29 wid=19 in lookaside. 348 | %cmp/u 10, 29, 19; 349 | %mov 10, 4, 1; 350 | %and 9, 10, 1; 351 | %or 8, 9, 1; 352 | %ix/load 1, 3, 0; 353 | %mov 4, 0, 1; 354 | %jmp/1 T_7.16, 4; 355 | %load/x1p 10, v0x277a5e0_0, 10; 356 | %jmp T_7.17; 357 | T_7.16 ; 358 | %mov 10, 2, 10; 359 | T_7.17 ; 360 | ; Save base=10 wid=10 in lookaside. 361 | %ix/get 3, 10, 10; 362 | %load/av 9, v0x277b7c0, 1; 363 | %ix/load 1, 3, 0; 364 | %mov 4, 0, 1; 365 | %jmp/1 T_7.18, 4; 366 | %load/x1p 29, v0x277a5e0_0, 10; 367 | %jmp T_7.19; 368 | T_7.18 ; 369 | %mov 29, 2, 10; 370 | T_7.19 ; 371 | ; Save base=29 wid=10 in lookaside. 372 | %ix/get 3, 29, 10; 373 | %load/av 10, v0x277b8f0, 19; 374 | %ix/load 1, 13, 0; 375 | %mov 4, 0, 1; 376 | %jmp/1 T_7.20, 4; 377 | %load/x1p 29, v0x277a5e0_0, 19; 378 | %jmp T_7.21; 379 | T_7.20 ; 380 | %mov 29, 2, 19; 381 | T_7.21 ; 382 | ; Save base=29 wid=19 in lookaside. 383 | %cmp/u 10, 29, 19; 384 | %mov 10, 4, 1; 385 | %and 9, 10, 1; 386 | %or 8, 9, 1; 387 | %ix/load 1, 3, 0; 388 | %mov 4, 0, 1; 389 | %jmp/1 T_7.22, 4; 390 | %load/x1p 10, v0x277a5e0_0, 10; 391 | %jmp T_7.23; 392 | T_7.22 ; 393 | %mov 10, 2, 10; 394 | T_7.23 ; 395 | ; Save base=10 wid=10 in lookaside. 396 | %ix/get 3, 10, 10; 397 | %load/av 9, v0x277b840, 1; 398 | %ix/load 1, 3, 0; 399 | %mov 4, 0, 1; 400 | %jmp/1 T_7.24, 4; 401 | %load/x1p 29, v0x277a5e0_0, 10; 402 | %jmp T_7.25; 403 | T_7.24 ; 404 | %mov 29, 2, 10; 405 | T_7.25 ; 406 | ; Save base=29 wid=10 in lookaside. 407 | %ix/get 3, 29, 10; 408 | %load/av 10, v0x277b970, 19; 409 | %ix/load 1, 13, 0; 410 | %mov 4, 0, 1; 411 | %jmp/1 T_7.26, 4; 412 | %load/x1p 29, v0x277a5e0_0, 19; 413 | %jmp T_7.27; 414 | T_7.26 ; 415 | %mov 29, 2, 19; 416 | T_7.27 ; 417 | ; Save base=29 wid=19 in lookaside. 418 | %cmp/u 10, 29, 19; 419 | %mov 10, 4, 1; 420 | %and 9, 10, 1; 421 | %or 8, 9, 1; 422 | %ix/load 0, 1, 0; 423 | %assign/v0 v0x2778c70_0, 0, 8; 424 | %load/v 8, v0x277b4c0_0, 1; 425 | %inv 8, 1; 426 | %load/v 9, v0x277bc50_0, 1; 427 | %inv 9, 1; 428 | %and 8, 9, 1; 429 | %jmp/0xz T_7.28, 8; 430 | %ix/load 0, 1, 0; 431 | %assign/v0 v0x277a980_0, 0, 0; 432 | %jmp T_7.29; 433 | T_7.28 ; 434 | %ix/load 1, 3, 0; 435 | %mov 4, 0, 1; 436 | %jmp/1 T_7.30, 4; 437 | %load/x1p 9, v0x277a5e0_0, 10; 438 | %jmp T_7.31; 439 | T_7.30 ; 440 | %mov 9, 2, 10; 441 | T_7.31 ; 442 | ; Save base=9 wid=10 in lookaside. 443 | %ix/get 3, 9, 10; 444 | %load/av 8, v0x277b6c0, 1; 445 | %ix/load 1, 3, 0; 446 | %mov 4, 0, 1; 447 | %jmp/1 T_7.32, 4; 448 | %load/x1p 28, v0x277a5e0_0, 10; 449 | %jmp T_7.33; 450 | T_7.32 ; 451 | %mov 28, 2, 10; 452 | T_7.33 ; 453 | ; Save base=28 wid=10 in lookaside. 454 | %ix/get 3, 28, 10; 455 | %load/av 9, v0x277b540, 19; 456 | %ix/load 1, 13, 0; 457 | %mov 4, 0, 1; 458 | %jmp/1 T_7.34, 4; 459 | %load/x1p 28, v0x277a5e0_0, 19; 460 | %jmp T_7.35; 461 | T_7.34 ; 462 | %mov 28, 2, 19; 463 | T_7.35 ; 464 | ; Save base=28 wid=19 in lookaside. 465 | %cmp/u 9, 28, 19; 466 | %mov 9, 4, 1; 467 | %and 8, 9, 1; 468 | %jmp/0xz T_7.36, 8; 469 | %load/v 8, v0x277b4c0_0, 1; 470 | %jmp/0xz T_7.38, 8; 471 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 472 | %mov 11, 0, 1; 473 | %cmpi/u 8, 3, 4; 474 | %or 5, 4, 1; 475 | %mov 8, 5, 1; 476 | %jmp/0 T_7.40, 8; 477 | %ix/load 1, 3, 0; 478 | %mov 4, 0, 1; 479 | %jmp/1 T_7.43, 4; 480 | %load/x1p 9, v0x277a5e0_0, 10; 481 | %jmp T_7.44; 482 | T_7.43 ; 483 | %mov 9, 2, 10; 484 | T_7.44 ; 485 | ; Save base=9 wid=10 in lookaside. 486 | %ix/get 3, 9, 10; 487 | %jmp/1 T_7.45, 4; 488 | %ix/get/s 0, 0, 2; 489 | T_7.45 ; 490 | %load/avx.p 9, v0x277b160, 0; 491 | %load/avx.p 10, v0x277b160, 0; 492 | %load/avx.p 11, v0x277b160, 0; 493 | %load/avx.p 12, v0x277b160, 0; 494 | %load/avx.p 13, v0x277b160, 0; 495 | %load/avx.p 14, v0x277b160, 0; 496 | %load/avx.p 15, v0x277b160, 0; 497 | %load/avx.p 16, v0x277b160, 0; 498 | %load/avx.p 17, v0x277b160, 0; 499 | %load/avx.p 18, v0x277b160, 0; 500 | %load/avx.p 19, v0x277b160, 0; 501 | %load/avx.p 20, v0x277b160, 0; 502 | %load/avx.p 21, v0x277b160, 0; 503 | %load/avx.p 22, v0x277b160, 0; 504 | %load/avx.p 23, v0x277b160, 0; 505 | %load/avx.p 24, v0x277b160, 0; 506 | %load/avx.p 25, v0x277b160, 0; 507 | %load/avx.p 26, v0x277b160, 0; 508 | %load/avx.p 27, v0x277b160, 0; 509 | %load/avx.p 28, v0x277b160, 0; 510 | %load/avx.p 29, v0x277b160, 0; 511 | %load/avx.p 30, v0x277b160, 0; 512 | %load/avx.p 31, v0x277b160, 0; 513 | %load/avx.p 32, v0x277b160, 0; 514 | %load/avx.p 33, v0x277b160, 0; 515 | %load/avx.p 34, v0x277b160, 0; 516 | %load/avx.p 35, v0x277b160, 0; 517 | %load/avx.p 36, v0x277b160, 0; 518 | %load/avx.p 37, v0x277b160, 0; 519 | %load/avx.p 38, v0x277b160, 0; 520 | %load/avx.p 39, v0x277b160, 0; 521 | %load/avx.p 40, v0x277b160, 0; 522 | ; Save base=9 wid=32 in lookaside. 523 | %jmp/1 T_7.42, 8; 524 | T_7.40 ; End of true expr. 525 | %movi 41, 32, 7; 526 | %ix/load 1, 3, 0; 527 | %mov 4, 0, 1; 528 | %jmp/1 T_7.46, 4; 529 | %load/x1p 48, v0x277a5e0_0, 10; 530 | %jmp T_7.47; 531 | T_7.46 ; 532 | %mov 48, 2, 10; 533 | T_7.47 ; 534 | ; Save base=48 wid=10 in lookaside. 535 | %ix/get 3, 48, 10; 536 | %jmp/1 T_7.48, 4; 537 | %ix/get/s 0, 41, 7; 538 | T_7.48 ; 539 | %load/avx.p 41, v0x277b160, 0; 540 | %load/avx.p 42, v0x277b160, 0; 541 | %load/avx.p 43, v0x277b160, 0; 542 | %load/avx.p 44, v0x277b160, 0; 543 | %load/avx.p 45, v0x277b160, 0; 544 | %load/avx.p 46, v0x277b160, 0; 545 | %load/avx.p 47, v0x277b160, 0; 546 | %load/avx.p 48, v0x277b160, 0; 547 | %load/avx.p 49, v0x277b160, 0; 548 | %load/avx.p 50, v0x277b160, 0; 549 | %load/avx.p 51, v0x277b160, 0; 550 | %load/avx.p 52, v0x277b160, 0; 551 | %load/avx.p 53, v0x277b160, 0; 552 | %load/avx.p 54, v0x277b160, 0; 553 | %load/avx.p 55, v0x277b160, 0; 554 | %load/avx.p 56, v0x277b160, 0; 555 | %load/avx.p 57, v0x277b160, 0; 556 | %load/avx.p 58, v0x277b160, 0; 557 | %load/avx.p 59, v0x277b160, 0; 558 | %load/avx.p 60, v0x277b160, 0; 559 | %load/avx.p 61, v0x277b160, 0; 560 | %load/avx.p 62, v0x277b160, 0; 561 | %load/avx.p 63, v0x277b160, 0; 562 | %load/avx.p 64, v0x277b160, 0; 563 | %load/avx.p 65, v0x277b160, 0; 564 | %load/avx.p 66, v0x277b160, 0; 565 | %load/avx.p 67, v0x277b160, 0; 566 | %load/avx.p 68, v0x277b160, 0; 567 | %load/avx.p 69, v0x277b160, 0; 568 | %load/avx.p 70, v0x277b160, 0; 569 | %load/avx.p 71, v0x277b160, 0; 570 | %load/avx.p 72, v0x277b160, 0; 571 | ; Save base=41 wid=32 in lookaside. 572 | %jmp/0 T_7.41, 8; 573 | ; End of false expr. 574 | %blend 9, 41, 32; Condition unknown. 575 | %jmp T_7.42; 576 | T_7.41 ; 577 | %mov 9, 41, 32; Return false value 578 | T_7.42 ; 579 | %ix/load 0, 32, 0; 580 | %assign/v0 v0x2778ed0_0, 0, 9; 581 | %jmp T_7.39; 582 | T_7.38 ; 583 | %load/v 8, v0x277bc50_0, 1; 584 | %jmp/0xz T_7.49, 8; 585 | %set/v v0x2778ed0_0, 0, 32; 586 | %ix/load 1, 3, 0; 587 | %mov 4, 0, 1; 588 | %jmp/1 T_7.51, 4; 589 | %load/x1p 8, v0x277a5e0_0, 10; 590 | %jmp T_7.52; 591 | T_7.51 ; 592 | %mov 8, 2, 10; 593 | T_7.52 ; 594 | ; Save base=8 wid=10 in lookaside. 595 | %ix/get 3, 8, 10; 596 | %jmp/1 t_12, 4; 597 | %ix/load 0, 1, 0; word width 598 | %ix/load 1, 0, 0; part off 599 | %assign/av v0x277a820, 0, 1; 600 | t_12 ; 601 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 602 | %mov 11, 0, 1; 603 | %cmpi/u 8, 3, 4; 604 | %or 5, 4, 1; 605 | %jmp/0xz T_7.53, 5; 606 | %load/v 8, v0x277aa00_0, 32; 607 | %ix/load 1, 3, 0; 608 | %mov 4, 0, 1; 609 | %jmp/1 T_7.55, 4; 610 | %load/x1p 40, v0x277a5e0_0, 10; 611 | %jmp T_7.56; 612 | T_7.55 ; 613 | %mov 40, 2, 10; 614 | T_7.56 ; 615 | ; Save base=40 wid=10 in lookaside. 616 | %ix/get 3, 40, 10; 617 | %jmp/1 t_13, 4; 618 | %ix/load 0, 32, 0; word width 619 | %ix/load 1, 0, 0; part off 620 | %assign/av v0x277b160, 0, 8; 621 | t_13 ; 622 | %jmp T_7.54; 623 | T_7.53 ; 624 | %load/v 8, v0x277aa00_0, 32; 625 | %ix/load 1, 3, 0; 626 | %mov 4, 0, 1; 627 | %jmp/1 T_7.57, 4; 628 | %load/x1p 40, v0x277a5e0_0, 10; 629 | %jmp T_7.58; 630 | T_7.57 ; 631 | %mov 40, 2, 10; 632 | T_7.58 ; 633 | ; Save base=40 wid=10 in lookaside. 634 | %ix/get 3, 40, 10; 635 | %jmp/1 t_14, 4; 636 | %ix/load 0, 32, 0; word width 637 | %ix/load 1, 32, 0; part off 638 | %assign/av v0x277b160, 0, 8; 639 | t_14 ; 640 | T_7.54 ; 641 | T_7.49 ; 642 | T_7.39 ; 643 | %ix/load 1, 3, 0; 644 | %mov 4, 0, 1; 645 | %jmp/1 T_7.59, 4; 646 | %load/x1p 10, v0x277a5e0_0, 10; 647 | %jmp T_7.60; 648 | T_7.59 ; 649 | %mov 10, 2, 10; 650 | T_7.60 ; 651 | ; Save base=10 wid=10 in lookaside. 652 | %ix/get 3, 10, 10; 653 | %load/av 8, v0x277af20, 2; 654 | %ix/load 1, 3, 0; 655 | %mov 4, 0, 1; 656 | %jmp/1 T_7.61, 4; 657 | %load/x1p 12, v0x277a5e0_0, 10; 658 | %jmp T_7.62; 659 | T_7.61 ; 660 | %mov 12, 2, 10; 661 | T_7.62 ; 662 | ; Save base=12 wid=10 in lookaside. 663 | %ix/get 3, 12, 10; 664 | %load/av 10, v0x277aea0, 2; 665 | %cmp/u 8, 10, 2; 666 | %or 5, 4, 1; 667 | %jmp/0xz T_7.63, 5; 668 | %ix/load 1, 3, 0; 669 | %mov 4, 0, 1; 670 | %jmp/1 T_7.65, 4; 671 | %load/x1p 40, v0x277a5e0_0, 10; 672 | %jmp T_7.66; 673 | T_7.65 ; 674 | %mov 40, 2, 10; 675 | T_7.66 ; 676 | ; Save base=40 wid=10 in lookaside. 677 | %ix/get 3, 40, 10; 678 | %load/av 8, v0x277af20, 2; 679 | %mov 10, 0, 30; 680 | %addi 8, 1, 32; 681 | %ix/load 1, 3, 0; 682 | %mov 4, 0, 1; 683 | %jmp/1 T_7.67, 4; 684 | %load/x1p 40, v0x277a5e0_0, 10; 685 | %jmp T_7.68; 686 | T_7.67 ; 687 | %mov 40, 2, 10; 688 | T_7.68 ; 689 | ; Save base=40 wid=10 in lookaside. 690 | %ix/get 3, 40, 10; 691 | %jmp/1 t_15, 4; 692 | %ix/load 0, 2, 0; word width 693 | %ix/load 1, 0, 0; part off 694 | %assign/av v0x277af20, 0, 8; 695 | t_15 ; 696 | T_7.63 ; 697 | %ix/load 1, 3, 0; 698 | %mov 4, 0, 1; 699 | %jmp/1 T_7.69, 4; 700 | %load/x1p 10, v0x277a5e0_0, 10; 701 | %jmp T_7.70; 702 | T_7.69 ; 703 | %mov 10, 2, 10; 704 | T_7.70 ; 705 | ; Save base=10 wid=10 in lookaside. 706 | %ix/get 3, 10, 10; 707 | %load/av 8, v0x277ad00, 2; 708 | %ix/load 1, 3, 0; 709 | %mov 4, 0, 1; 710 | %jmp/1 T_7.71, 4; 711 | %load/x1p 12, v0x277a5e0_0, 10; 712 | %jmp T_7.72; 713 | T_7.71 ; 714 | %mov 12, 2, 10; 715 | T_7.72 ; 716 | ; Save base=12 wid=10 in lookaside. 717 | %ix/get 3, 12, 10; 718 | %load/av 10, v0x277aea0, 2; 719 | %cmp/u 8, 10, 2; 720 | %or 5, 4, 1; 721 | %jmp/0xz T_7.73, 5; 722 | %ix/load 1, 3, 0; 723 | %mov 4, 0, 1; 724 | %jmp/1 T_7.75, 4; 725 | %load/x1p 40, v0x277a5e0_0, 10; 726 | %jmp T_7.76; 727 | T_7.75 ; 728 | %mov 40, 2, 10; 729 | T_7.76 ; 730 | ; Save base=40 wid=10 in lookaside. 731 | %ix/get 3, 40, 10; 732 | %load/av 8, v0x277ad00, 2; 733 | %mov 10, 0, 30; 734 | %addi 8, 1, 32; 735 | %ix/load 1, 3, 0; 736 | %mov 4, 0, 1; 737 | %jmp/1 T_7.77, 4; 738 | %load/x1p 40, v0x277a5e0_0, 10; 739 | %jmp T_7.78; 740 | T_7.77 ; 741 | %mov 40, 2, 10; 742 | T_7.78 ; 743 | ; Save base=40 wid=10 in lookaside. 744 | %ix/get 3, 40, 10; 745 | %jmp/1 t_16, 4; 746 | %ix/load 0, 2, 0; word width 747 | %ix/load 1, 0, 0; part off 748 | %assign/av v0x277ad00, 0, 8; 749 | t_16 ; 750 | T_7.73 ; 751 | %ix/load 1, 3, 0; 752 | %mov 4, 0, 1; 753 | %jmp/1 T_7.79, 4; 754 | %load/x1p 10, v0x277a5e0_0, 10; 755 | %jmp T_7.80; 756 | T_7.79 ; 757 | %mov 10, 2, 10; 758 | T_7.80 ; 759 | ; Save base=10 wid=10 in lookaside. 760 | %ix/get 3, 10, 10; 761 | %load/av 8, v0x277ad80, 2; 762 | %ix/load 1, 3, 0; 763 | %mov 4, 0, 1; 764 | %jmp/1 T_7.81, 4; 765 | %load/x1p 12, v0x277a5e0_0, 10; 766 | %jmp T_7.82; 767 | T_7.81 ; 768 | %mov 12, 2, 10; 769 | T_7.82 ; 770 | ; Save base=12 wid=10 in lookaside. 771 | %ix/get 3, 12, 10; 772 | %load/av 10, v0x277aea0, 2; 773 | %cmp/u 8, 10, 2; 774 | %or 5, 4, 1; 775 | %jmp/0xz T_7.83, 5; 776 | %ix/load 1, 3, 0; 777 | %mov 4, 0, 1; 778 | %jmp/1 T_7.85, 4; 779 | %load/x1p 40, v0x277a5e0_0, 10; 780 | %jmp T_7.86; 781 | T_7.85 ; 782 | %mov 40, 2, 10; 783 | T_7.86 ; 784 | ; Save base=40 wid=10 in lookaside. 785 | %ix/get 3, 40, 10; 786 | %load/av 8, v0x277ad80, 2; 787 | %mov 10, 0, 30; 788 | %addi 8, 1, 32; 789 | %ix/load 1, 3, 0; 790 | %mov 4, 0, 1; 791 | %jmp/1 T_7.87, 4; 792 | %load/x1p 40, v0x277a5e0_0, 10; 793 | %jmp T_7.88; 794 | T_7.87 ; 795 | %mov 40, 2, 10; 796 | T_7.88 ; 797 | ; Save base=40 wid=10 in lookaside. 798 | %ix/get 3, 40, 10; 799 | %jmp/1 t_17, 4; 800 | %ix/load 0, 2, 0; word width 801 | %ix/load 1, 0, 0; part off 802 | %assign/av v0x277ad80, 0, 8; 803 | t_17 ; 804 | T_7.83 ; 805 | %ix/load 1, 3, 0; 806 | %mov 4, 0, 1; 807 | %jmp/1 T_7.89, 4; 808 | %load/x1p 8, v0x277a5e0_0, 10; 809 | %jmp T_7.90; 810 | T_7.89 ; 811 | %mov 8, 2, 10; 812 | T_7.90 ; 813 | ; Save base=8 wid=10 in lookaside. 814 | %ix/get 3, 8, 10; 815 | %jmp/1 t_18, 4; 816 | %ix/load 0, 2, 0; word width 817 | %ix/load 1, 0, 0; part off 818 | %assign/av v0x277aea0, 0, 0; 819 | t_18 ; 820 | %jmp T_7.37; 821 | T_7.36 ; 822 | %ix/load 1, 3, 0; 823 | %mov 4, 0, 1; 824 | %jmp/1 T_7.91, 4; 825 | %load/x1p 9, v0x277a5e0_0, 10; 826 | %jmp T_7.92; 827 | T_7.91 ; 828 | %mov 9, 2, 10; 829 | T_7.92 ; 830 | ; Save base=9 wid=10 in lookaside. 831 | %ix/get 3, 9, 10; 832 | %load/av 8, v0x277b740, 1; 833 | %ix/load 1, 3, 0; 834 | %mov 4, 0, 1; 835 | %jmp/1 T_7.93, 4; 836 | %load/x1p 28, v0x277a5e0_0, 10; 837 | %jmp T_7.94; 838 | T_7.93 ; 839 | %mov 28, 2, 10; 840 | T_7.94 ; 841 | ; Save base=28 wid=10 in lookaside. 842 | %ix/get 3, 28, 10; 843 | %load/av 9, v0x277b5c0, 19; 844 | %ix/load 1, 13, 0; 845 | %mov 4, 0, 1; 846 | %jmp/1 T_7.95, 4; 847 | %load/x1p 28, v0x277a5e0_0, 19; 848 | %jmp T_7.96; 849 | T_7.95 ; 850 | %mov 28, 2, 19; 851 | T_7.96 ; 852 | ; Save base=28 wid=19 in lookaside. 853 | %cmp/u 9, 28, 19; 854 | %mov 9, 4, 1; 855 | %and 8, 9, 1; 856 | %jmp/0xz T_7.97, 8; 857 | %load/v 8, v0x277b4c0_0, 1; 858 | %jmp/0xz T_7.99, 8; 859 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 860 | %mov 11, 0, 1; 861 | %cmpi/u 8, 3, 4; 862 | %or 5, 4, 1; 863 | %mov 8, 5, 1; 864 | %jmp/0 T_7.101, 8; 865 | %ix/load 1, 3, 0; 866 | %mov 4, 0, 1; 867 | %jmp/1 T_7.104, 4; 868 | %load/x1p 9, v0x277a5e0_0, 10; 869 | %jmp T_7.105; 870 | T_7.104 ; 871 | %mov 9, 2, 10; 872 | T_7.105 ; 873 | ; Save base=9 wid=10 in lookaside. 874 | %ix/get 3, 9, 10; 875 | %jmp/1 T_7.106, 4; 876 | %ix/get/s 0, 0, 2; 877 | T_7.106 ; 878 | %load/avx.p 9, v0x277afa0, 0; 879 | %load/avx.p 10, v0x277afa0, 0; 880 | %load/avx.p 11, v0x277afa0, 0; 881 | %load/avx.p 12, v0x277afa0, 0; 882 | %load/avx.p 13, v0x277afa0, 0; 883 | %load/avx.p 14, v0x277afa0, 0; 884 | %load/avx.p 15, v0x277afa0, 0; 885 | %load/avx.p 16, v0x277afa0, 0; 886 | %load/avx.p 17, v0x277afa0, 0; 887 | %load/avx.p 18, v0x277afa0, 0; 888 | %load/avx.p 19, v0x277afa0, 0; 889 | %load/avx.p 20, v0x277afa0, 0; 890 | %load/avx.p 21, v0x277afa0, 0; 891 | %load/avx.p 22, v0x277afa0, 0; 892 | %load/avx.p 23, v0x277afa0, 0; 893 | %load/avx.p 24, v0x277afa0, 0; 894 | %load/avx.p 25, v0x277afa0, 0; 895 | %load/avx.p 26, v0x277afa0, 0; 896 | %load/avx.p 27, v0x277afa0, 0; 897 | %load/avx.p 28, v0x277afa0, 0; 898 | %load/avx.p 29, v0x277afa0, 0; 899 | %load/avx.p 30, v0x277afa0, 0; 900 | %load/avx.p 31, v0x277afa0, 0; 901 | %load/avx.p 32, v0x277afa0, 0; 902 | %load/avx.p 33, v0x277afa0, 0; 903 | %load/avx.p 34, v0x277afa0, 0; 904 | %load/avx.p 35, v0x277afa0, 0; 905 | %load/avx.p 36, v0x277afa0, 0; 906 | %load/avx.p 37, v0x277afa0, 0; 907 | %load/avx.p 38, v0x277afa0, 0; 908 | %load/avx.p 39, v0x277afa0, 0; 909 | %load/avx.p 40, v0x277afa0, 0; 910 | ; Save base=9 wid=32 in lookaside. 911 | %jmp/1 T_7.103, 8; 912 | T_7.101 ; End of true expr. 913 | %movi 41, 32, 7; 914 | %ix/load 1, 3, 0; 915 | %mov 4, 0, 1; 916 | %jmp/1 T_7.107, 4; 917 | %load/x1p 48, v0x277a5e0_0, 10; 918 | %jmp T_7.108; 919 | T_7.107 ; 920 | %mov 48, 2, 10; 921 | T_7.108 ; 922 | ; Save base=48 wid=10 in lookaside. 923 | %ix/get 3, 48, 10; 924 | %jmp/1 T_7.109, 4; 925 | %ix/get/s 0, 41, 7; 926 | T_7.109 ; 927 | %load/avx.p 41, v0x277afa0, 0; 928 | %load/avx.p 42, v0x277afa0, 0; 929 | %load/avx.p 43, v0x277afa0, 0; 930 | %load/avx.p 44, v0x277afa0, 0; 931 | %load/avx.p 45, v0x277afa0, 0; 932 | %load/avx.p 46, v0x277afa0, 0; 933 | %load/avx.p 47, v0x277afa0, 0; 934 | %load/avx.p 48, v0x277afa0, 0; 935 | %load/avx.p 49, v0x277afa0, 0; 936 | %load/avx.p 50, v0x277afa0, 0; 937 | %load/avx.p 51, v0x277afa0, 0; 938 | %load/avx.p 52, v0x277afa0, 0; 939 | %load/avx.p 53, v0x277afa0, 0; 940 | %load/avx.p 54, v0x277afa0, 0; 941 | %load/avx.p 55, v0x277afa0, 0; 942 | %load/avx.p 56, v0x277afa0, 0; 943 | %load/avx.p 57, v0x277afa0, 0; 944 | %load/avx.p 58, v0x277afa0, 0; 945 | %load/avx.p 59, v0x277afa0, 0; 946 | %load/avx.p 60, v0x277afa0, 0; 947 | %load/avx.p 61, v0x277afa0, 0; 948 | %load/avx.p 62, v0x277afa0, 0; 949 | %load/avx.p 63, v0x277afa0, 0; 950 | %load/avx.p 64, v0x277afa0, 0; 951 | %load/avx.p 65, v0x277afa0, 0; 952 | %load/avx.p 66, v0x277afa0, 0; 953 | %load/avx.p 67, v0x277afa0, 0; 954 | %load/avx.p 68, v0x277afa0, 0; 955 | %load/avx.p 69, v0x277afa0, 0; 956 | %load/avx.p 70, v0x277afa0, 0; 957 | %load/avx.p 71, v0x277afa0, 0; 958 | %load/avx.p 72, v0x277afa0, 0; 959 | ; Save base=41 wid=32 in lookaside. 960 | %jmp/0 T_7.102, 8; 961 | ; End of false expr. 962 | %blend 9, 41, 32; Condition unknown. 963 | %jmp T_7.103; 964 | T_7.102 ; 965 | %mov 9, 41, 32; Return false value 966 | T_7.103 ; 967 | %ix/load 0, 32, 0; 968 | %assign/v0 v0x2778ed0_0, 0, 9; 969 | %jmp T_7.100; 970 | T_7.99 ; 971 | %load/v 8, v0x277bc50_0, 1; 972 | %jmp/0xz T_7.110, 8; 973 | %set/v v0x2778ed0_0, 0, 32; 974 | %ix/load 1, 3, 0; 975 | %mov 4, 0, 1; 976 | %jmp/1 T_7.112, 4; 977 | %load/x1p 8, v0x277a5e0_0, 10; 978 | %jmp T_7.113; 979 | T_7.112 ; 980 | %mov 8, 2, 10; 981 | T_7.113 ; 982 | ; Save base=8 wid=10 in lookaside. 983 | %ix/get 3, 8, 10; 984 | %jmp/1 t_19, 4; 985 | %ix/load 0, 1, 0; word width 986 | %ix/load 1, 0, 0; part off 987 | %assign/av v0x277a8a0, 0, 1; 988 | t_19 ; 989 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 990 | %mov 11, 0, 1; 991 | %cmpi/u 8, 3, 4; 992 | %or 5, 4, 1; 993 | %jmp/0xz T_7.114, 5; 994 | %load/v 8, v0x277aa00_0, 32; 995 | %ix/load 1, 3, 0; 996 | %mov 4, 0, 1; 997 | %jmp/1 T_7.116, 4; 998 | %load/x1p 40, v0x277a5e0_0, 10; 999 | %jmp T_7.117; 1000 | T_7.116 ; 1001 | %mov 40, 2, 10; 1002 | T_7.117 ; 1003 | ; Save base=40 wid=10 in lookaside. 1004 | %ix/get 3, 40, 10; 1005 | %jmp/1 t_20, 4; 1006 | %ix/load 0, 32, 0; word width 1007 | %ix/load 1, 0, 0; part off 1008 | %assign/av v0x277afa0, 0, 8; 1009 | t_20 ; 1010 | %jmp T_7.115; 1011 | T_7.114 ; 1012 | %load/v 8, v0x277aa00_0, 32; 1013 | %ix/load 1, 3, 0; 1014 | %mov 4, 0, 1; 1015 | %jmp/1 T_7.118, 4; 1016 | %load/x1p 40, v0x277a5e0_0, 10; 1017 | %jmp T_7.119; 1018 | T_7.118 ; 1019 | %mov 40, 2, 10; 1020 | T_7.119 ; 1021 | ; Save base=40 wid=10 in lookaside. 1022 | %ix/get 3, 40, 10; 1023 | %jmp/1 t_21, 4; 1024 | %ix/load 0, 32, 0; word width 1025 | %ix/load 1, 32, 0; part off 1026 | %assign/av v0x277afa0, 0, 8; 1027 | t_21 ; 1028 | T_7.115 ; 1029 | T_7.110 ; 1030 | T_7.100 ; 1031 | %ix/load 1, 3, 0; 1032 | %mov 4, 0, 1; 1033 | %jmp/1 T_7.120, 4; 1034 | %load/x1p 10, v0x277a5e0_0, 10; 1035 | %jmp T_7.121; 1036 | T_7.120 ; 1037 | %mov 10, 2, 10; 1038 | T_7.121 ; 1039 | ; Save base=10 wid=10 in lookaside. 1040 | %ix/get 3, 10, 10; 1041 | %load/av 8, v0x277aea0, 2; 1042 | %ix/load 1, 3, 0; 1043 | %mov 4, 0, 1; 1044 | %jmp/1 T_7.122, 4; 1045 | %load/x1p 12, v0x277a5e0_0, 10; 1046 | %jmp T_7.123; 1047 | T_7.122 ; 1048 | %mov 12, 2, 10; 1049 | T_7.123 ; 1050 | ; Save base=12 wid=10 in lookaside. 1051 | %ix/get 3, 12, 10; 1052 | %load/av 10, v0x277af20, 2; 1053 | %cmp/u 8, 10, 2; 1054 | %or 5, 4, 1; 1055 | %jmp/0xz T_7.124, 5; 1056 | %ix/load 1, 3, 0; 1057 | %mov 4, 0, 1; 1058 | %jmp/1 T_7.126, 4; 1059 | %load/x1p 40, v0x277a5e0_0, 10; 1060 | %jmp T_7.127; 1061 | T_7.126 ; 1062 | %mov 40, 2, 10; 1063 | T_7.127 ; 1064 | ; Save base=40 wid=10 in lookaside. 1065 | %ix/get 3, 40, 10; 1066 | %load/av 8, v0x277aea0, 2; 1067 | %mov 10, 0, 30; 1068 | %addi 8, 1, 32; 1069 | %ix/load 1, 3, 0; 1070 | %mov 4, 0, 1; 1071 | %jmp/1 T_7.128, 4; 1072 | %load/x1p 40, v0x277a5e0_0, 10; 1073 | %jmp T_7.129; 1074 | T_7.128 ; 1075 | %mov 40, 2, 10; 1076 | T_7.129 ; 1077 | ; Save base=40 wid=10 in lookaside. 1078 | %ix/get 3, 40, 10; 1079 | %jmp/1 t_22, 4; 1080 | %ix/load 0, 2, 0; word width 1081 | %ix/load 1, 0, 0; part off 1082 | %assign/av v0x277aea0, 0, 8; 1083 | t_22 ; 1084 | T_7.124 ; 1085 | %ix/load 1, 3, 0; 1086 | %mov 4, 0, 1; 1087 | %jmp/1 T_7.130, 4; 1088 | %load/x1p 10, v0x277a5e0_0, 10; 1089 | %jmp T_7.131; 1090 | T_7.130 ; 1091 | %mov 10, 2, 10; 1092 | T_7.131 ; 1093 | ; Save base=10 wid=10 in lookaside. 1094 | %ix/get 3, 10, 10; 1095 | %load/av 8, v0x277ad00, 2; 1096 | %ix/load 1, 3, 0; 1097 | %mov 4, 0, 1; 1098 | %jmp/1 T_7.132, 4; 1099 | %load/x1p 12, v0x277a5e0_0, 10; 1100 | %jmp T_7.133; 1101 | T_7.132 ; 1102 | %mov 12, 2, 10; 1103 | T_7.133 ; 1104 | ; Save base=12 wid=10 in lookaside. 1105 | %ix/get 3, 12, 10; 1106 | %load/av 10, v0x277af20, 2; 1107 | %cmp/u 8, 10, 2; 1108 | %or 5, 4, 1; 1109 | %jmp/0xz T_7.134, 5; 1110 | %ix/load 1, 3, 0; 1111 | %mov 4, 0, 1; 1112 | %jmp/1 T_7.136, 4; 1113 | %load/x1p 40, v0x277a5e0_0, 10; 1114 | %jmp T_7.137; 1115 | T_7.136 ; 1116 | %mov 40, 2, 10; 1117 | T_7.137 ; 1118 | ; Save base=40 wid=10 in lookaside. 1119 | %ix/get 3, 40, 10; 1120 | %load/av 8, v0x277ad00, 2; 1121 | %mov 10, 0, 30; 1122 | %addi 8, 1, 32; 1123 | %ix/load 1, 3, 0; 1124 | %mov 4, 0, 1; 1125 | %jmp/1 T_7.138, 4; 1126 | %load/x1p 40, v0x277a5e0_0, 10; 1127 | %jmp T_7.139; 1128 | T_7.138 ; 1129 | %mov 40, 2, 10; 1130 | T_7.139 ; 1131 | ; Save base=40 wid=10 in lookaside. 1132 | %ix/get 3, 40, 10; 1133 | %jmp/1 t_23, 4; 1134 | %ix/load 0, 2, 0; word width 1135 | %ix/load 1, 0, 0; part off 1136 | %assign/av v0x277ad00, 0, 8; 1137 | t_23 ; 1138 | T_7.134 ; 1139 | %ix/load 1, 3, 0; 1140 | %mov 4, 0, 1; 1141 | %jmp/1 T_7.140, 4; 1142 | %load/x1p 10, v0x277a5e0_0, 10; 1143 | %jmp T_7.141; 1144 | T_7.140 ; 1145 | %mov 10, 2, 10; 1146 | T_7.141 ; 1147 | ; Save base=10 wid=10 in lookaside. 1148 | %ix/get 3, 10, 10; 1149 | %load/av 8, v0x277ad80, 2; 1150 | %ix/load 1, 3, 0; 1151 | %mov 4, 0, 1; 1152 | %jmp/1 T_7.142, 4; 1153 | %load/x1p 12, v0x277a5e0_0, 10; 1154 | %jmp T_7.143; 1155 | T_7.142 ; 1156 | %mov 12, 2, 10; 1157 | T_7.143 ; 1158 | ; Save base=12 wid=10 in lookaside. 1159 | %ix/get 3, 12, 10; 1160 | %load/av 10, v0x277af20, 2; 1161 | %cmp/u 8, 10, 2; 1162 | %or 5, 4, 1; 1163 | %jmp/0xz T_7.144, 5; 1164 | %ix/load 1, 3, 0; 1165 | %mov 4, 0, 1; 1166 | %jmp/1 T_7.146, 4; 1167 | %load/x1p 40, v0x277a5e0_0, 10; 1168 | %jmp T_7.147; 1169 | T_7.146 ; 1170 | %mov 40, 2, 10; 1171 | T_7.147 ; 1172 | ; Save base=40 wid=10 in lookaside. 1173 | %ix/get 3, 40, 10; 1174 | %load/av 8, v0x277ad80, 2; 1175 | %mov 10, 0, 30; 1176 | %addi 8, 1, 32; 1177 | %ix/load 1, 3, 0; 1178 | %mov 4, 0, 1; 1179 | %jmp/1 T_7.148, 4; 1180 | %load/x1p 40, v0x277a5e0_0, 10; 1181 | %jmp T_7.149; 1182 | T_7.148 ; 1183 | %mov 40, 2, 10; 1184 | T_7.149 ; 1185 | ; Save base=40 wid=10 in lookaside. 1186 | %ix/get 3, 40, 10; 1187 | %jmp/1 t_24, 4; 1188 | %ix/load 0, 2, 0; word width 1189 | %ix/load 1, 0, 0; part off 1190 | %assign/av v0x277ad80, 0, 8; 1191 | t_24 ; 1192 | T_7.144 ; 1193 | %ix/load 1, 3, 0; 1194 | %mov 4, 0, 1; 1195 | %jmp/1 T_7.150, 4; 1196 | %load/x1p 8, v0x277a5e0_0, 10; 1197 | %jmp T_7.151; 1198 | T_7.150 ; 1199 | %mov 8, 2, 10; 1200 | T_7.151 ; 1201 | ; Save base=8 wid=10 in lookaside. 1202 | %ix/get 3, 8, 10; 1203 | %jmp/1 t_25, 4; 1204 | %ix/load 0, 2, 0; word width 1205 | %ix/load 1, 0, 0; part off 1206 | %assign/av v0x277af20, 0, 0; 1207 | t_25 ; 1208 | %jmp T_7.98; 1209 | T_7.97 ; 1210 | %ix/load 1, 3, 0; 1211 | %mov 4, 0, 1; 1212 | %jmp/1 T_7.152, 4; 1213 | %load/x1p 9, v0x277a5e0_0, 10; 1214 | %jmp T_7.153; 1215 | T_7.152 ; 1216 | %mov 9, 2, 10; 1217 | T_7.153 ; 1218 | ; Save base=9 wid=10 in lookaside. 1219 | %ix/get 3, 9, 10; 1220 | %load/av 8, v0x277b7c0, 1; 1221 | %ix/load 1, 3, 0; 1222 | %mov 4, 0, 1; 1223 | %jmp/1 T_7.154, 4; 1224 | %load/x1p 28, v0x277a5e0_0, 10; 1225 | %jmp T_7.155; 1226 | T_7.154 ; 1227 | %mov 28, 2, 10; 1228 | T_7.155 ; 1229 | ; Save base=28 wid=10 in lookaside. 1230 | %ix/get 3, 28, 10; 1231 | %load/av 9, v0x277b8f0, 19; 1232 | %ix/load 1, 13, 0; 1233 | %mov 4, 0, 1; 1234 | %jmp/1 T_7.156, 4; 1235 | %load/x1p 28, v0x277a5e0_0, 19; 1236 | %jmp T_7.157; 1237 | T_7.156 ; 1238 | %mov 28, 2, 19; 1239 | T_7.157 ; 1240 | ; Save base=28 wid=19 in lookaside. 1241 | %cmp/u 9, 28, 19; 1242 | %mov 9, 4, 1; 1243 | %and 8, 9, 1; 1244 | %jmp/0xz T_7.158, 8; 1245 | %load/v 8, v0x277b4c0_0, 1; 1246 | %jmp/0xz T_7.160, 8; 1247 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 1248 | %mov 11, 0, 1; 1249 | %cmpi/u 8, 3, 4; 1250 | %or 5, 4, 1; 1251 | %mov 8, 5, 1; 1252 | %jmp/0 T_7.162, 8; 1253 | %ix/load 1, 3, 0; 1254 | %mov 4, 0, 1; 1255 | %jmp/1 T_7.165, 4; 1256 | %load/x1p 9, v0x277a5e0_0, 10; 1257 | %jmp T_7.166; 1258 | T_7.165 ; 1259 | %mov 9, 2, 10; 1260 | T_7.166 ; 1261 | ; Save base=9 wid=10 in lookaside. 1262 | %ix/get 3, 9, 10; 1263 | %jmp/1 T_7.167, 4; 1264 | %ix/get/s 0, 0, 2; 1265 | T_7.167 ; 1266 | %load/avx.p 9, v0x277b020, 0; 1267 | %load/avx.p 10, v0x277b020, 0; 1268 | %load/avx.p 11, v0x277b020, 0; 1269 | %load/avx.p 12, v0x277b020, 0; 1270 | %load/avx.p 13, v0x277b020, 0; 1271 | %load/avx.p 14, v0x277b020, 0; 1272 | %load/avx.p 15, v0x277b020, 0; 1273 | %load/avx.p 16, v0x277b020, 0; 1274 | %load/avx.p 17, v0x277b020, 0; 1275 | %load/avx.p 18, v0x277b020, 0; 1276 | %load/avx.p 19, v0x277b020, 0; 1277 | %load/avx.p 20, v0x277b020, 0; 1278 | %load/avx.p 21, v0x277b020, 0; 1279 | %load/avx.p 22, v0x277b020, 0; 1280 | %load/avx.p 23, v0x277b020, 0; 1281 | %load/avx.p 24, v0x277b020, 0; 1282 | %load/avx.p 25, v0x277b020, 0; 1283 | %load/avx.p 26, v0x277b020, 0; 1284 | %load/avx.p 27, v0x277b020, 0; 1285 | %load/avx.p 28, v0x277b020, 0; 1286 | %load/avx.p 29, v0x277b020, 0; 1287 | %load/avx.p 30, v0x277b020, 0; 1288 | %load/avx.p 31, v0x277b020, 0; 1289 | %load/avx.p 32, v0x277b020, 0; 1290 | %load/avx.p 33, v0x277b020, 0; 1291 | %load/avx.p 34, v0x277b020, 0; 1292 | %load/avx.p 35, v0x277b020, 0; 1293 | %load/avx.p 36, v0x277b020, 0; 1294 | %load/avx.p 37, v0x277b020, 0; 1295 | %load/avx.p 38, v0x277b020, 0; 1296 | %load/avx.p 39, v0x277b020, 0; 1297 | %load/avx.p 40, v0x277b020, 0; 1298 | ; Save base=9 wid=32 in lookaside. 1299 | %jmp/1 T_7.164, 8; 1300 | T_7.162 ; End of true expr. 1301 | %movi 41, 32, 7; 1302 | %ix/load 1, 3, 0; 1303 | %mov 4, 0, 1; 1304 | %jmp/1 T_7.168, 4; 1305 | %load/x1p 48, v0x277a5e0_0, 10; 1306 | %jmp T_7.169; 1307 | T_7.168 ; 1308 | %mov 48, 2, 10; 1309 | T_7.169 ; 1310 | ; Save base=48 wid=10 in lookaside. 1311 | %ix/get 3, 48, 10; 1312 | %jmp/1 T_7.170, 4; 1313 | %ix/get/s 0, 41, 7; 1314 | T_7.170 ; 1315 | %load/avx.p 41, v0x277b020, 0; 1316 | %load/avx.p 42, v0x277b020, 0; 1317 | %load/avx.p 43, v0x277b020, 0; 1318 | %load/avx.p 44, v0x277b020, 0; 1319 | %load/avx.p 45, v0x277b020, 0; 1320 | %load/avx.p 46, v0x277b020, 0; 1321 | %load/avx.p 47, v0x277b020, 0; 1322 | %load/avx.p 48, v0x277b020, 0; 1323 | %load/avx.p 49, v0x277b020, 0; 1324 | %load/avx.p 50, v0x277b020, 0; 1325 | %load/avx.p 51, v0x277b020, 0; 1326 | %load/avx.p 52, v0x277b020, 0; 1327 | %load/avx.p 53, v0x277b020, 0; 1328 | %load/avx.p 54, v0x277b020, 0; 1329 | %load/avx.p 55, v0x277b020, 0; 1330 | %load/avx.p 56, v0x277b020, 0; 1331 | %load/avx.p 57, v0x277b020, 0; 1332 | %load/avx.p 58, v0x277b020, 0; 1333 | %load/avx.p 59, v0x277b020, 0; 1334 | %load/avx.p 60, v0x277b020, 0; 1335 | %load/avx.p 61, v0x277b020, 0; 1336 | %load/avx.p 62, v0x277b020, 0; 1337 | %load/avx.p 63, v0x277b020, 0; 1338 | %load/avx.p 64, v0x277b020, 0; 1339 | %load/avx.p 65, v0x277b020, 0; 1340 | %load/avx.p 66, v0x277b020, 0; 1341 | %load/avx.p 67, v0x277b020, 0; 1342 | %load/avx.p 68, v0x277b020, 0; 1343 | %load/avx.p 69, v0x277b020, 0; 1344 | %load/avx.p 70, v0x277b020, 0; 1345 | %load/avx.p 71, v0x277b020, 0; 1346 | %load/avx.p 72, v0x277b020, 0; 1347 | ; Save base=41 wid=32 in lookaside. 1348 | %jmp/0 T_7.163, 8; 1349 | ; End of false expr. 1350 | %blend 9, 41, 32; Condition unknown. 1351 | %jmp T_7.164; 1352 | T_7.163 ; 1353 | %mov 9, 41, 32; Return false value 1354 | T_7.164 ; 1355 | %ix/load 0, 32, 0; 1356 | %assign/v0 v0x2778ed0_0, 0, 9; 1357 | %jmp T_7.161; 1358 | T_7.160 ; 1359 | %load/v 8, v0x277bc50_0, 1; 1360 | %jmp/0xz T_7.171, 8; 1361 | %set/v v0x2778ed0_0, 0, 32; 1362 | %ix/load 1, 3, 0; 1363 | %mov 4, 0, 1; 1364 | %jmp/1 T_7.173, 4; 1365 | %load/x1p 8, v0x277a5e0_0, 10; 1366 | %jmp T_7.174; 1367 | T_7.173 ; 1368 | %mov 8, 2, 10; 1369 | T_7.174 ; 1370 | ; Save base=8 wid=10 in lookaside. 1371 | %ix/get 3, 8, 10; 1372 | %jmp/1 t_26, 4; 1373 | %ix/load 0, 1, 0; word width 1374 | %ix/load 1, 0, 0; part off 1375 | %assign/av v0x277ac00, 0, 1; 1376 | t_26 ; 1377 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 1378 | %mov 11, 0, 1; 1379 | %cmpi/u 8, 3, 4; 1380 | %or 5, 4, 1; 1381 | %jmp/0xz T_7.175, 5; 1382 | %load/v 8, v0x277aa00_0, 32; 1383 | %ix/load 1, 3, 0; 1384 | %mov 4, 0, 1; 1385 | %jmp/1 T_7.177, 4; 1386 | %load/x1p 40, v0x277a5e0_0, 10; 1387 | %jmp T_7.178; 1388 | T_7.177 ; 1389 | %mov 40, 2, 10; 1390 | T_7.178 ; 1391 | ; Save base=40 wid=10 in lookaside. 1392 | %ix/get 3, 40, 10; 1393 | %jmp/1 t_27, 4; 1394 | %ix/load 0, 32, 0; word width 1395 | %ix/load 1, 0, 0; part off 1396 | %assign/av v0x277b020, 0, 8; 1397 | t_27 ; 1398 | %jmp T_7.176; 1399 | T_7.175 ; 1400 | %load/v 8, v0x277aa00_0, 32; 1401 | %ix/load 1, 3, 0; 1402 | %mov 4, 0, 1; 1403 | %jmp/1 T_7.179, 4; 1404 | %load/x1p 40, v0x277a5e0_0, 10; 1405 | %jmp T_7.180; 1406 | T_7.179 ; 1407 | %mov 40, 2, 10; 1408 | T_7.180 ; 1409 | ; Save base=40 wid=10 in lookaside. 1410 | %ix/get 3, 40, 10; 1411 | %jmp/1 t_28, 4; 1412 | %ix/load 0, 32, 0; word width 1413 | %ix/load 1, 32, 0; part off 1414 | %assign/av v0x277b020, 0, 8; 1415 | t_28 ; 1416 | T_7.176 ; 1417 | T_7.171 ; 1418 | T_7.161 ; 1419 | %ix/load 1, 3, 0; 1420 | %mov 4, 0, 1; 1421 | %jmp/1 T_7.181, 4; 1422 | %load/x1p 10, v0x277a5e0_0, 10; 1423 | %jmp T_7.182; 1424 | T_7.181 ; 1425 | %mov 10, 2, 10; 1426 | T_7.182 ; 1427 | ; Save base=10 wid=10 in lookaside. 1428 | %ix/get 3, 10, 10; 1429 | %load/av 8, v0x277aea0, 2; 1430 | %ix/load 1, 3, 0; 1431 | %mov 4, 0, 1; 1432 | %jmp/1 T_7.183, 4; 1433 | %load/x1p 12, v0x277a5e0_0, 10; 1434 | %jmp T_7.184; 1435 | T_7.183 ; 1436 | %mov 12, 2, 10; 1437 | T_7.184 ; 1438 | ; Save base=12 wid=10 in lookaside. 1439 | %ix/get 3, 12, 10; 1440 | %load/av 10, v0x277ad00, 2; 1441 | %cmp/u 8, 10, 2; 1442 | %or 5, 4, 1; 1443 | %jmp/0xz T_7.185, 5; 1444 | %ix/load 1, 3, 0; 1445 | %mov 4, 0, 1; 1446 | %jmp/1 T_7.187, 4; 1447 | %load/x1p 40, v0x277a5e0_0, 10; 1448 | %jmp T_7.188; 1449 | T_7.187 ; 1450 | %mov 40, 2, 10; 1451 | T_7.188 ; 1452 | ; Save base=40 wid=10 in lookaside. 1453 | %ix/get 3, 40, 10; 1454 | %load/av 8, v0x277aea0, 2; 1455 | %mov 10, 0, 30; 1456 | %addi 8, 1, 32; 1457 | %ix/load 1, 3, 0; 1458 | %mov 4, 0, 1; 1459 | %jmp/1 T_7.189, 4; 1460 | %load/x1p 40, v0x277a5e0_0, 10; 1461 | %jmp T_7.190; 1462 | T_7.189 ; 1463 | %mov 40, 2, 10; 1464 | T_7.190 ; 1465 | ; Save base=40 wid=10 in lookaside. 1466 | %ix/get 3, 40, 10; 1467 | %jmp/1 t_29, 4; 1468 | %ix/load 0, 2, 0; word width 1469 | %ix/load 1, 0, 0; part off 1470 | %assign/av v0x277aea0, 0, 8; 1471 | t_29 ; 1472 | T_7.185 ; 1473 | %ix/load 1, 3, 0; 1474 | %mov 4, 0, 1; 1475 | %jmp/1 T_7.191, 4; 1476 | %load/x1p 10, v0x277a5e0_0, 10; 1477 | %jmp T_7.192; 1478 | T_7.191 ; 1479 | %mov 10, 2, 10; 1480 | T_7.192 ; 1481 | ; Save base=10 wid=10 in lookaside. 1482 | %ix/get 3, 10, 10; 1483 | %load/av 8, v0x277af20, 2; 1484 | %ix/load 1, 3, 0; 1485 | %mov 4, 0, 1; 1486 | %jmp/1 T_7.193, 4; 1487 | %load/x1p 12, v0x277a5e0_0, 10; 1488 | %jmp T_7.194; 1489 | T_7.193 ; 1490 | %mov 12, 2, 10; 1491 | T_7.194 ; 1492 | ; Save base=12 wid=10 in lookaside. 1493 | %ix/get 3, 12, 10; 1494 | %load/av 10, v0x277ad00, 2; 1495 | %cmp/u 8, 10, 2; 1496 | %or 5, 4, 1; 1497 | %jmp/0xz T_7.195, 5; 1498 | %ix/load 1, 3, 0; 1499 | %mov 4, 0, 1; 1500 | %jmp/1 T_7.197, 4; 1501 | %load/x1p 40, v0x277a5e0_0, 10; 1502 | %jmp T_7.198; 1503 | T_7.197 ; 1504 | %mov 40, 2, 10; 1505 | T_7.198 ; 1506 | ; Save base=40 wid=10 in lookaside. 1507 | %ix/get 3, 40, 10; 1508 | %load/av 8, v0x277af20, 2; 1509 | %mov 10, 0, 30; 1510 | %addi 8, 1, 32; 1511 | %ix/load 1, 3, 0; 1512 | %mov 4, 0, 1; 1513 | %jmp/1 T_7.199, 4; 1514 | %load/x1p 40, v0x277a5e0_0, 10; 1515 | %jmp T_7.200; 1516 | T_7.199 ; 1517 | %mov 40, 2, 10; 1518 | T_7.200 ; 1519 | ; Save base=40 wid=10 in lookaside. 1520 | %ix/get 3, 40, 10; 1521 | %jmp/1 t_30, 4; 1522 | %ix/load 0, 2, 0; word width 1523 | %ix/load 1, 0, 0; part off 1524 | %assign/av v0x277af20, 0, 8; 1525 | t_30 ; 1526 | T_7.195 ; 1527 | %ix/load 1, 3, 0; 1528 | %mov 4, 0, 1; 1529 | %jmp/1 T_7.201, 4; 1530 | %load/x1p 10, v0x277a5e0_0, 10; 1531 | %jmp T_7.202; 1532 | T_7.201 ; 1533 | %mov 10, 2, 10; 1534 | T_7.202 ; 1535 | ; Save base=10 wid=10 in lookaside. 1536 | %ix/get 3, 10, 10; 1537 | %load/av 8, v0x277ad80, 2; 1538 | %ix/load 1, 3, 0; 1539 | %mov 4, 0, 1; 1540 | %jmp/1 T_7.203, 4; 1541 | %load/x1p 12, v0x277a5e0_0, 10; 1542 | %jmp T_7.204; 1543 | T_7.203 ; 1544 | %mov 12, 2, 10; 1545 | T_7.204 ; 1546 | ; Save base=12 wid=10 in lookaside. 1547 | %ix/get 3, 12, 10; 1548 | %load/av 10, v0x277ad00, 2; 1549 | %cmp/u 8, 10, 2; 1550 | %or 5, 4, 1; 1551 | %jmp/0xz T_7.205, 5; 1552 | %ix/load 1, 3, 0; 1553 | %mov 4, 0, 1; 1554 | %jmp/1 T_7.207, 4; 1555 | %load/x1p 40, v0x277a5e0_0, 10; 1556 | %jmp T_7.208; 1557 | T_7.207 ; 1558 | %mov 40, 2, 10; 1559 | T_7.208 ; 1560 | ; Save base=40 wid=10 in lookaside. 1561 | %ix/get 3, 40, 10; 1562 | %load/av 8, v0x277ad80, 2; 1563 | %mov 10, 0, 30; 1564 | %addi 8, 1, 32; 1565 | %ix/load 1, 3, 0; 1566 | %mov 4, 0, 1; 1567 | %jmp/1 T_7.209, 4; 1568 | %load/x1p 40, v0x277a5e0_0, 10; 1569 | %jmp T_7.210; 1570 | T_7.209 ; 1571 | %mov 40, 2, 10; 1572 | T_7.210 ; 1573 | ; Save base=40 wid=10 in lookaside. 1574 | %ix/get 3, 40, 10; 1575 | %jmp/1 t_31, 4; 1576 | %ix/load 0, 2, 0; word width 1577 | %ix/load 1, 0, 0; part off 1578 | %assign/av v0x277ad80, 0, 8; 1579 | t_31 ; 1580 | T_7.205 ; 1581 | %ix/load 1, 3, 0; 1582 | %mov 4, 0, 1; 1583 | %jmp/1 T_7.211, 4; 1584 | %load/x1p 8, v0x277a5e0_0, 10; 1585 | %jmp T_7.212; 1586 | T_7.211 ; 1587 | %mov 8, 2, 10; 1588 | T_7.212 ; 1589 | ; Save base=8 wid=10 in lookaside. 1590 | %ix/get 3, 8, 10; 1591 | %jmp/1 t_32, 4; 1592 | %ix/load 0, 2, 0; word width 1593 | %ix/load 1, 0, 0; part off 1594 | %assign/av v0x277ad00, 0, 0; 1595 | t_32 ; 1596 | %jmp T_7.159; 1597 | T_7.158 ; 1598 | %ix/load 1, 3, 0; 1599 | %mov 4, 0, 1; 1600 | %jmp/1 T_7.213, 4; 1601 | %load/x1p 9, v0x277a5e0_0, 10; 1602 | %jmp T_7.214; 1603 | T_7.213 ; 1604 | %mov 9, 2, 10; 1605 | T_7.214 ; 1606 | ; Save base=9 wid=10 in lookaside. 1607 | %ix/get 3, 9, 10; 1608 | %load/av 8, v0x277b840, 1; 1609 | %ix/load 1, 3, 0; 1610 | %mov 4, 0, 1; 1611 | %jmp/1 T_7.215, 4; 1612 | %load/x1p 28, v0x277a5e0_0, 10; 1613 | %jmp T_7.216; 1614 | T_7.215 ; 1615 | %mov 28, 2, 10; 1616 | T_7.216 ; 1617 | ; Save base=28 wid=10 in lookaside. 1618 | %ix/get 3, 28, 10; 1619 | %load/av 9, v0x277b970, 19; 1620 | %ix/load 1, 13, 0; 1621 | %mov 4, 0, 1; 1622 | %jmp/1 T_7.217, 4; 1623 | %load/x1p 28, v0x277a5e0_0, 19; 1624 | %jmp T_7.218; 1625 | T_7.217 ; 1626 | %mov 28, 2, 19; 1627 | T_7.218 ; 1628 | ; Save base=28 wid=19 in lookaside. 1629 | %cmp/u 9, 28, 19; 1630 | %mov 9, 4, 1; 1631 | %and 8, 9, 1; 1632 | %jmp/0xz T_7.219, 8; 1633 | %load/v 8, v0x277b4c0_0, 1; 1634 | %jmp/0xz T_7.221, 8; 1635 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 1636 | %mov 11, 0, 1; 1637 | %cmpi/u 8, 3, 4; 1638 | %or 5, 4, 1; 1639 | %mov 8, 5, 1; 1640 | %jmp/0 T_7.223, 8; 1641 | %ix/load 1, 3, 0; 1642 | %mov 4, 0, 1; 1643 | %jmp/1 T_7.226, 4; 1644 | %load/x1p 9, v0x277a5e0_0, 10; 1645 | %jmp T_7.227; 1646 | T_7.226 ; 1647 | %mov 9, 2, 10; 1648 | T_7.227 ; 1649 | ; Save base=9 wid=10 in lookaside. 1650 | %ix/get 3, 9, 10; 1651 | %jmp/1 T_7.228, 4; 1652 | %ix/get/s 0, 0, 2; 1653 | T_7.228 ; 1654 | %load/avx.p 9, v0x277b0a0, 0; 1655 | %load/avx.p 10, v0x277b0a0, 0; 1656 | %load/avx.p 11, v0x277b0a0, 0; 1657 | %load/avx.p 12, v0x277b0a0, 0; 1658 | %load/avx.p 13, v0x277b0a0, 0; 1659 | %load/avx.p 14, v0x277b0a0, 0; 1660 | %load/avx.p 15, v0x277b0a0, 0; 1661 | %load/avx.p 16, v0x277b0a0, 0; 1662 | %load/avx.p 17, v0x277b0a0, 0; 1663 | %load/avx.p 18, v0x277b0a0, 0; 1664 | %load/avx.p 19, v0x277b0a0, 0; 1665 | %load/avx.p 20, v0x277b0a0, 0; 1666 | %load/avx.p 21, v0x277b0a0, 0; 1667 | %load/avx.p 22, v0x277b0a0, 0; 1668 | %load/avx.p 23, v0x277b0a0, 0; 1669 | %load/avx.p 24, v0x277b0a0, 0; 1670 | %load/avx.p 25, v0x277b0a0, 0; 1671 | %load/avx.p 26, v0x277b0a0, 0; 1672 | %load/avx.p 27, v0x277b0a0, 0; 1673 | %load/avx.p 28, v0x277b0a0, 0; 1674 | %load/avx.p 29, v0x277b0a0, 0; 1675 | %load/avx.p 30, v0x277b0a0, 0; 1676 | %load/avx.p 31, v0x277b0a0, 0; 1677 | %load/avx.p 32, v0x277b0a0, 0; 1678 | %load/avx.p 33, v0x277b0a0, 0; 1679 | %load/avx.p 34, v0x277b0a0, 0; 1680 | %load/avx.p 35, v0x277b0a0, 0; 1681 | %load/avx.p 36, v0x277b0a0, 0; 1682 | %load/avx.p 37, v0x277b0a0, 0; 1683 | %load/avx.p 38, v0x277b0a0, 0; 1684 | %load/avx.p 39, v0x277b0a0, 0; 1685 | %load/avx.p 40, v0x277b0a0, 0; 1686 | ; Save base=9 wid=32 in lookaside. 1687 | %jmp/1 T_7.225, 8; 1688 | T_7.223 ; End of true expr. 1689 | %movi 41, 32, 7; 1690 | %ix/load 1, 3, 0; 1691 | %mov 4, 0, 1; 1692 | %jmp/1 T_7.229, 4; 1693 | %load/x1p 48, v0x277a5e0_0, 10; 1694 | %jmp T_7.230; 1695 | T_7.229 ; 1696 | %mov 48, 2, 10; 1697 | T_7.230 ; 1698 | ; Save base=48 wid=10 in lookaside. 1699 | %ix/get 3, 48, 10; 1700 | %jmp/1 T_7.231, 4; 1701 | %ix/get/s 0, 41, 7; 1702 | T_7.231 ; 1703 | %load/avx.p 41, v0x277b0a0, 0; 1704 | %load/avx.p 42, v0x277b0a0, 0; 1705 | %load/avx.p 43, v0x277b0a0, 0; 1706 | %load/avx.p 44, v0x277b0a0, 0; 1707 | %load/avx.p 45, v0x277b0a0, 0; 1708 | %load/avx.p 46, v0x277b0a0, 0; 1709 | %load/avx.p 47, v0x277b0a0, 0; 1710 | %load/avx.p 48, v0x277b0a0, 0; 1711 | %load/avx.p 49, v0x277b0a0, 0; 1712 | %load/avx.p 50, v0x277b0a0, 0; 1713 | %load/avx.p 51, v0x277b0a0, 0; 1714 | %load/avx.p 52, v0x277b0a0, 0; 1715 | %load/avx.p 53, v0x277b0a0, 0; 1716 | %load/avx.p 54, v0x277b0a0, 0; 1717 | %load/avx.p 55, v0x277b0a0, 0; 1718 | %load/avx.p 56, v0x277b0a0, 0; 1719 | %load/avx.p 57, v0x277b0a0, 0; 1720 | %load/avx.p 58, v0x277b0a0, 0; 1721 | %load/avx.p 59, v0x277b0a0, 0; 1722 | %load/avx.p 60, v0x277b0a0, 0; 1723 | %load/avx.p 61, v0x277b0a0, 0; 1724 | %load/avx.p 62, v0x277b0a0, 0; 1725 | %load/avx.p 63, v0x277b0a0, 0; 1726 | %load/avx.p 64, v0x277b0a0, 0; 1727 | %load/avx.p 65, v0x277b0a0, 0; 1728 | %load/avx.p 66, v0x277b0a0, 0; 1729 | %load/avx.p 67, v0x277b0a0, 0; 1730 | %load/avx.p 68, v0x277b0a0, 0; 1731 | %load/avx.p 69, v0x277b0a0, 0; 1732 | %load/avx.p 70, v0x277b0a0, 0; 1733 | %load/avx.p 71, v0x277b0a0, 0; 1734 | %load/avx.p 72, v0x277b0a0, 0; 1735 | ; Save base=41 wid=32 in lookaside. 1736 | %jmp/0 T_7.224, 8; 1737 | ; End of false expr. 1738 | %blend 9, 41, 32; Condition unknown. 1739 | %jmp T_7.225; 1740 | T_7.224 ; 1741 | %mov 9, 41, 32; Return false value 1742 | T_7.225 ; 1743 | %ix/load 0, 32, 0; 1744 | %assign/v0 v0x2778ed0_0, 0, 9; 1745 | %jmp T_7.222; 1746 | T_7.221 ; 1747 | %load/v 8, v0x277bc50_0, 1; 1748 | %jmp/0xz T_7.232, 8; 1749 | %set/v v0x2778ed0_0, 0, 32; 1750 | %ix/load 1, 3, 0; 1751 | %mov 4, 0, 1; 1752 | %jmp/1 T_7.234, 4; 1753 | %load/x1p 8, v0x277a5e0_0, 10; 1754 | %jmp T_7.235; 1755 | T_7.234 ; 1756 | %mov 8, 2, 10; 1757 | T_7.235 ; 1758 | ; Save base=8 wid=10 in lookaside. 1759 | %ix/get 3, 8, 10; 1760 | %jmp/1 t_33, 4; 1761 | %ix/load 0, 1, 0; word width 1762 | %ix/load 1, 0, 0; part off 1763 | %assign/av v0x277ac80, 0, 1; 1764 | t_33 ; 1765 | %load/v 8, v0x277a5e0_0, 3; Select 3 out of 32 bits 1766 | %mov 11, 0, 1; 1767 | %cmpi/u 8, 3, 4; 1768 | %or 5, 4, 1; 1769 | %jmp/0xz T_7.236, 5; 1770 | %load/v 8, v0x277aa00_0, 32; 1771 | %ix/load 1, 3, 0; 1772 | %mov 4, 0, 1; 1773 | %jmp/1 T_7.238, 4; 1774 | %load/x1p 40, v0x277a5e0_0, 10; 1775 | %jmp T_7.239; 1776 | T_7.238 ; 1777 | %mov 40, 2, 10; 1778 | T_7.239 ; 1779 | ; Save base=40 wid=10 in lookaside. 1780 | %ix/get 3, 40, 10; 1781 | %jmp/1 t_34, 4; 1782 | %ix/load 0, 32, 0; word width 1783 | %ix/load 1, 0, 0; part off 1784 | %assign/av v0x277b0a0, 0, 8; 1785 | t_34 ; 1786 | %jmp T_7.237; 1787 | T_7.236 ; 1788 | %load/v 8, v0x277aa00_0, 32; 1789 | %ix/load 1, 3, 0; 1790 | %mov 4, 0, 1; 1791 | %jmp/1 T_7.240, 4; 1792 | %load/x1p 40, v0x277a5e0_0, 10; 1793 | %jmp T_7.241; 1794 | T_7.240 ; 1795 | %mov 40, 2, 10; 1796 | T_7.241 ; 1797 | ; Save base=40 wid=10 in lookaside. 1798 | %ix/get 3, 40, 10; 1799 | %jmp/1 t_35, 4; 1800 | %ix/load 0, 32, 0; word width 1801 | %ix/load 1, 32, 0; part off 1802 | %assign/av v0x277b0a0, 0, 8; 1803 | t_35 ; 1804 | T_7.237 ; 1805 | T_7.232 ; 1806 | T_7.222 ; 1807 | %ix/load 1, 3, 0; 1808 | %mov 4, 0, 1; 1809 | %jmp/1 T_7.242, 4; 1810 | %load/x1p 10, v0x277a5e0_0, 10; 1811 | %jmp T_7.243; 1812 | T_7.242 ; 1813 | %mov 10, 2, 10; 1814 | T_7.243 ; 1815 | ; Save base=10 wid=10 in lookaside. 1816 | %ix/get 3, 10, 10; 1817 | %load/av 8, v0x277aea0, 2; 1818 | %ix/load 1, 3, 0; 1819 | %mov 4, 0, 1; 1820 | %jmp/1 T_7.244, 4; 1821 | %load/x1p 12, v0x277a5e0_0, 10; 1822 | %jmp T_7.245; 1823 | T_7.244 ; 1824 | %mov 12, 2, 10; 1825 | T_7.245 ; 1826 | ; Save base=12 wid=10 in lookaside. 1827 | %ix/get 3, 12, 10; 1828 | %load/av 10, v0x277ad80, 2; 1829 | %cmp/u 8, 10, 2; 1830 | %or 5, 4, 1; 1831 | %jmp/0xz T_7.246, 5; 1832 | %ix/load 1, 3, 0; 1833 | %mov 4, 0, 1; 1834 | %jmp/1 T_7.248, 4; 1835 | %load/x1p 40, v0x277a5e0_0, 10; 1836 | %jmp T_7.249; 1837 | T_7.248 ; 1838 | %mov 40, 2, 10; 1839 | T_7.249 ; 1840 | ; Save base=40 wid=10 in lookaside. 1841 | %ix/get 3, 40, 10; 1842 | %load/av 8, v0x277aea0, 2; 1843 | %mov 10, 0, 30; 1844 | %addi 8, 1, 32; 1845 | %ix/load 1, 3, 0; 1846 | %mov 4, 0, 1; 1847 | %jmp/1 T_7.250, 4; 1848 | %load/x1p 40, v0x277a5e0_0, 10; 1849 | %jmp T_7.251; 1850 | T_7.250 ; 1851 | %mov 40, 2, 10; 1852 | T_7.251 ; 1853 | ; Save base=40 wid=10 in lookaside. 1854 | %ix/get 3, 40, 10; 1855 | %jmp/1 t_36, 4; 1856 | %ix/load 0, 2, 0; word width 1857 | %ix/load 1, 0, 0; part off 1858 | %assign/av v0x277aea0, 0, 8; 1859 | t_36 ; 1860 | T_7.246 ; 1861 | %ix/load 1, 3, 0; 1862 | %mov 4, 0, 1; 1863 | %jmp/1 T_7.252, 4; 1864 | %load/x1p 10, v0x277a5e0_0, 10; 1865 | %jmp T_7.253; 1866 | T_7.252 ; 1867 | %mov 10, 2, 10; 1868 | T_7.253 ; 1869 | ; Save base=10 wid=10 in lookaside. 1870 | %ix/get 3, 10, 10; 1871 | %load/av 8, v0x277af20, 2; 1872 | %ix/load 1, 3, 0; 1873 | %mov 4, 0, 1; 1874 | %jmp/1 T_7.254, 4; 1875 | %load/x1p 12, v0x277a5e0_0, 10; 1876 | %jmp T_7.255; 1877 | T_7.254 ; 1878 | %mov 12, 2, 10; 1879 | T_7.255 ; 1880 | ; Save base=12 wid=10 in lookaside. 1881 | %ix/get 3, 12, 10; 1882 | %load/av 10, v0x277ad80, 2; 1883 | %cmp/u 8, 10, 2; 1884 | %or 5, 4, 1; 1885 | %jmp/0xz T_7.256, 5; 1886 | %ix/load 1, 3, 0; 1887 | %mov 4, 0, 1; 1888 | %jmp/1 T_7.258, 4; 1889 | %load/x1p 40, v0x277a5e0_0, 10; 1890 | %jmp T_7.259; 1891 | T_7.258 ; 1892 | %mov 40, 2, 10; 1893 | T_7.259 ; 1894 | ; Save base=40 wid=10 in lookaside. 1895 | %ix/get 3, 40, 10; 1896 | %load/av 8, v0x277af20, 2; 1897 | %mov 10, 0, 30; 1898 | %addi 8, 1, 32; 1899 | %ix/load 1, 3, 0; 1900 | %mov 4, 0, 1; 1901 | %jmp/1 T_7.260, 4; 1902 | %load/x1p 40, v0x277a5e0_0, 10; 1903 | %jmp T_7.261; 1904 | T_7.260 ; 1905 | %mov 40, 2, 10; 1906 | T_7.261 ; 1907 | ; Save base=40 wid=10 in lookaside. 1908 | %ix/get 3, 40, 10; 1909 | %jmp/1 t_37, 4; 1910 | %ix/load 0, 2, 0; word width 1911 | %ix/load 1, 0, 0; part off 1912 | %assign/av v0x277af20, 0, 8; 1913 | t_37 ; 1914 | T_7.256 ; 1915 | %ix/load 1, 3, 0; 1916 | %mov 4, 0, 1; 1917 | %jmp/1 T_7.262, 4; 1918 | %load/x1p 10, v0x277a5e0_0, 10; 1919 | %jmp T_7.263; 1920 | T_7.262 ; 1921 | %mov 10, 2, 10; 1922 | T_7.263 ; 1923 | ; Save base=10 wid=10 in lookaside. 1924 | %ix/get 3, 10, 10; 1925 | %load/av 8, v0x277ad00, 2; 1926 | %ix/load 1, 3, 0; 1927 | %mov 4, 0, 1; 1928 | %jmp/1 T_7.264, 4; 1929 | %load/x1p 12, v0x277a5e0_0, 10; 1930 | %jmp T_7.265; 1931 | T_7.264 ; 1932 | %mov 12, 2, 10; 1933 | T_7.265 ; 1934 | ; Save base=12 wid=10 in lookaside. 1935 | %ix/get 3, 12, 10; 1936 | %load/av 10, v0x277ad80, 2; 1937 | %cmp/u 8, 10, 2; 1938 | %or 5, 4, 1; 1939 | %jmp/0xz T_7.266, 5; 1940 | %ix/load 1, 3, 0; 1941 | %mov 4, 0, 1; 1942 | %jmp/1 T_7.268, 4; 1943 | %load/x1p 40, v0x277a5e0_0, 10; 1944 | %jmp T_7.269; 1945 | T_7.268 ; 1946 | %mov 40, 2, 10; 1947 | T_7.269 ; 1948 | ; Save base=40 wid=10 in lookaside. 1949 | %ix/get 3, 40, 10; 1950 | %load/av 8, v0x277ad00, 2; 1951 | %mov 10, 0, 30; 1952 | %addi 8, 1, 32; 1953 | %ix/load 1, 3, 0; 1954 | %mov 4, 0, 1; 1955 | %jmp/1 T_7.270, 4; 1956 | %load/x1p 40, v0x277a5e0_0, 10; 1957 | %jmp T_7.271; 1958 | T_7.270 ; 1959 | %mov 40, 2, 10; 1960 | T_7.271 ; 1961 | ; Save base=40 wid=10 in lookaside. 1962 | %ix/get 3, 40, 10; 1963 | %jmp/1 t_38, 4; 1964 | %ix/load 0, 2, 0; word width 1965 | %ix/load 1, 0, 0; part off 1966 | %assign/av v0x277ad00, 0, 8; 1967 | t_38 ; 1968 | T_7.266 ; 1969 | %ix/load 1, 3, 0; 1970 | %mov 4, 0, 1; 1971 | %jmp/1 T_7.272, 4; 1972 | %load/x1p 8, v0x277a5e0_0, 10; 1973 | %jmp T_7.273; 1974 | T_7.272 ; 1975 | %mov 8, 2, 10; 1976 | T_7.273 ; 1977 | ; Save base=8 wid=10 in lookaside. 1978 | %ix/get 3, 8, 10; 1979 | %jmp/1 t_39, 4; 1980 | %ix/load 0, 2, 0; word width 1981 | %ix/load 1, 0, 0; part off 1982 | %assign/av v0x277ad80, 0, 0; 1983 | t_39 ; 1984 | %jmp T_7.220; 1985 | T_7.219 ; 1986 | %ix/load 0, 1, 0; 1987 | %assign/v0 v0x277a980_0, 0, 1; 1988 | T_7.220 ; 1989 | T_7.159 ; 1990 | T_7.98 ; 1991 | T_7.37 ; 1992 | T_7.29 ; 1993 | %jmp T_7.3; 1994 | T_7.1 ; 1995 | %ix/load 1, 3, 0; 1996 | %mov 4, 0, 1; 1997 | %jmp/1 T_7.274, 4; 1998 | %load/x1p 9, v0x277a5e0_0, 10; 1999 | %jmp T_7.275; 2000 | T_7.274 ; 2001 | %mov 9, 2, 10; 2002 | T_7.275 ; 2003 | ; Save base=9 wid=10 in lookaside. 2004 | %ix/get 3, 9, 10; 2005 | %load/av 8, v0x277b6c0, 1; 2006 | %inv 8, 1; 2007 | %jmp/0xz T_7.276, 8; 2008 | %load/v 8, v0x277b3c0_0, 64; 2009 | %ix/load 1, 3, 0; 2010 | %mov 4, 0, 1; 2011 | %jmp/1 T_7.278, 4; 2012 | %load/x1p 72, v0x277a5e0_0, 10; 2013 | %jmp T_7.279; 2014 | T_7.278 ; 2015 | %mov 72, 2, 10; 2016 | T_7.279 ; 2017 | ; Save base=72 wid=10 in lookaside. 2018 | %ix/get 3, 72, 10; 2019 | %jmp/1 t_40, 4; 2020 | %ix/load 0, 64, 0; word width 2021 | %ix/load 1, 0, 0; part off 2022 | %assign/av v0x277b160, 0, 8; 2023 | t_40 ; 2024 | %ix/load 1, 13, 0; 2025 | %mov 4, 0, 1; 2026 | %jmp/1 T_7.280, 4; 2027 | %load/x1p 8, v0x277a5e0_0, 19; 2028 | %jmp T_7.281; 2029 | T_7.280 ; 2030 | %mov 8, 2, 19; 2031 | T_7.281 ; 2032 | ; Save base=8 wid=19 in lookaside. 2033 | %ix/load 1, 3, 0; 2034 | %mov 4, 0, 1; 2035 | %jmp/1 T_7.282, 4; 2036 | %load/x1p 27, v0x277a5e0_0, 10; 2037 | %jmp T_7.283; 2038 | T_7.282 ; 2039 | %mov 27, 2, 10; 2040 | T_7.283 ; 2041 | ; Save base=27 wid=10 in lookaside. 2042 | %ix/get 3, 27, 10; 2043 | %jmp/1 t_41, 4; 2044 | %ix/load 0, 19, 0; word width 2045 | %ix/load 1, 0, 0; part off 2046 | %assign/av v0x277b540, 0, 8; 2047 | t_41 ; 2048 | %ix/load 1, 3, 0; 2049 | %mov 4, 0, 1; 2050 | %jmp/1 T_7.284, 4; 2051 | %load/x1p 8, v0x277a5e0_0, 10; 2052 | %jmp T_7.285; 2053 | T_7.284 ; 2054 | %mov 8, 2, 10; 2055 | T_7.285 ; 2056 | ; Save base=8 wid=10 in lookaside. 2057 | %ix/get 3, 8, 10; 2058 | %jmp/1 t_42, 4; 2059 | %ix/load 0, 1, 0; word width 2060 | %ix/load 1, 0, 0; part off 2061 | %assign/av v0x277a820, 0, 0; 2062 | t_42 ; 2063 | %ix/load 1, 3, 0; 2064 | %mov 4, 0, 1; 2065 | %jmp/1 T_7.286, 4; 2066 | %load/x1p 8, v0x277a5e0_0, 10; 2067 | %jmp T_7.287; 2068 | T_7.286 ; 2069 | %mov 8, 2, 10; 2070 | T_7.287 ; 2071 | ; Save base=8 wid=10 in lookaside. 2072 | %ix/get 3, 8, 10; 2073 | %jmp/1 t_43, 4; 2074 | %ix/load 0, 1, 0; word width 2075 | %ix/load 1, 0, 0; part off 2076 | %assign/av v0x277b6c0, 0, 1; 2077 | t_43 ; 2078 | %jmp T_7.277; 2079 | T_7.276 ; 2080 | %ix/load 1, 3, 0; 2081 | %mov 4, 0, 1; 2082 | %jmp/1 T_7.288, 4; 2083 | %load/x1p 9, v0x277a5e0_0, 10; 2084 | %jmp T_7.289; 2085 | T_7.288 ; 2086 | %mov 9, 2, 10; 2087 | T_7.289 ; 2088 | ; Save base=9 wid=10 in lookaside. 2089 | %ix/get 3, 9, 10; 2090 | %load/av 8, v0x277b740, 1; 2091 | %inv 8, 1; 2092 | %jmp/0xz T_7.290, 8; 2093 | %load/v 8, v0x277b3c0_0, 64; 2094 | %ix/load 1, 3, 0; 2095 | %mov 4, 0, 1; 2096 | %jmp/1 T_7.292, 4; 2097 | %load/x1p 72, v0x277a5e0_0, 10; 2098 | %jmp T_7.293; 2099 | T_7.292 ; 2100 | %mov 72, 2, 10; 2101 | T_7.293 ; 2102 | ; Save base=72 wid=10 in lookaside. 2103 | %ix/get 3, 72, 10; 2104 | %jmp/1 t_44, 4; 2105 | %ix/load 0, 64, 0; word width 2106 | %ix/load 1, 0, 0; part off 2107 | %assign/av v0x277afa0, 0, 8; 2108 | t_44 ; 2109 | %ix/load 1, 13, 0; 2110 | %mov 4, 0, 1; 2111 | %jmp/1 T_7.294, 4; 2112 | %load/x1p 8, v0x277a5e0_0, 19; 2113 | %jmp T_7.295; 2114 | T_7.294 ; 2115 | %mov 8, 2, 19; 2116 | T_7.295 ; 2117 | ; Save base=8 wid=19 in lookaside. 2118 | %ix/load 1, 3, 0; 2119 | %mov 4, 0, 1; 2120 | %jmp/1 T_7.296, 4; 2121 | %load/x1p 27, v0x277a5e0_0, 10; 2122 | %jmp T_7.297; 2123 | T_7.296 ; 2124 | %mov 27, 2, 10; 2125 | T_7.297 ; 2126 | ; Save base=27 wid=10 in lookaside. 2127 | %ix/get 3, 27, 10; 2128 | %jmp/1 t_45, 4; 2129 | %ix/load 0, 19, 0; word width 2130 | %ix/load 1, 0, 0; part off 2131 | %assign/av v0x277b5c0, 0, 8; 2132 | t_45 ; 2133 | %ix/load 1, 3, 0; 2134 | %mov 4, 0, 1; 2135 | %jmp/1 T_7.298, 4; 2136 | %load/x1p 8, v0x277a5e0_0, 10; 2137 | %jmp T_7.299; 2138 | T_7.298 ; 2139 | %mov 8, 2, 10; 2140 | T_7.299 ; 2141 | ; Save base=8 wid=10 in lookaside. 2142 | %ix/get 3, 8, 10; 2143 | %jmp/1 t_46, 4; 2144 | %ix/load 0, 1, 0; word width 2145 | %ix/load 1, 0, 0; part off 2146 | %assign/av v0x277a8a0, 0, 0; 2147 | t_46 ; 2148 | %ix/load 1, 3, 0; 2149 | %mov 4, 0, 1; 2150 | %jmp/1 T_7.300, 4; 2151 | %load/x1p 8, v0x277a5e0_0, 10; 2152 | %jmp T_7.301; 2153 | T_7.300 ; 2154 | %mov 8, 2, 10; 2155 | T_7.301 ; 2156 | ; Save base=8 wid=10 in lookaside. 2157 | %ix/get 3, 8, 10; 2158 | %jmp/1 t_47, 4; 2159 | %ix/load 0, 1, 0; word width 2160 | %ix/load 1, 0, 0; part off 2161 | %assign/av v0x277b740, 0, 1; 2162 | t_47 ; 2163 | %jmp T_7.291; 2164 | T_7.290 ; 2165 | %ix/load 1, 3, 0; 2166 | %mov 4, 0, 1; 2167 | %jmp/1 T_7.302, 4; 2168 | %load/x1p 9, v0x277a5e0_0, 10; 2169 | %jmp T_7.303; 2170 | T_7.302 ; 2171 | %mov 9, 2, 10; 2172 | T_7.303 ; 2173 | ; Save base=9 wid=10 in lookaside. 2174 | %ix/get 3, 9, 10; 2175 | %load/av 8, v0x277b7c0, 1; 2176 | %inv 8, 1; 2177 | %jmp/0xz T_7.304, 8; 2178 | %load/v 8, v0x277b3c0_0, 64; 2179 | %ix/load 1, 3, 0; 2180 | %mov 4, 0, 1; 2181 | %jmp/1 T_7.306, 4; 2182 | %load/x1p 72, v0x277a5e0_0, 10; 2183 | %jmp T_7.307; 2184 | T_7.306 ; 2185 | %mov 72, 2, 10; 2186 | T_7.307 ; 2187 | ; Save base=72 wid=10 in lookaside. 2188 | %ix/get 3, 72, 10; 2189 | %jmp/1 t_48, 4; 2190 | %ix/load 0, 64, 0; word width 2191 | %ix/load 1, 0, 0; part off 2192 | %assign/av v0x277b020, 0, 8; 2193 | t_48 ; 2194 | %ix/load 1, 13, 0; 2195 | %mov 4, 0, 1; 2196 | %jmp/1 T_7.308, 4; 2197 | %load/x1p 8, v0x277a5e0_0, 19; 2198 | %jmp T_7.309; 2199 | T_7.308 ; 2200 | %mov 8, 2, 19; 2201 | T_7.309 ; 2202 | ; Save base=8 wid=19 in lookaside. 2203 | %ix/load 1, 3, 0; 2204 | %mov 4, 0, 1; 2205 | %jmp/1 T_7.310, 4; 2206 | %load/x1p 27, v0x277a5e0_0, 10; 2207 | %jmp T_7.311; 2208 | T_7.310 ; 2209 | %mov 27, 2, 10; 2210 | T_7.311 ; 2211 | ; Save base=27 wid=10 in lookaside. 2212 | %ix/get 3, 27, 10; 2213 | %jmp/1 t_49, 4; 2214 | %ix/load 0, 19, 0; word width 2215 | %ix/load 1, 0, 0; part off 2216 | %assign/av v0x277b8f0, 0, 8; 2217 | t_49 ; 2218 | %ix/load 1, 3, 0; 2219 | %mov 4, 0, 1; 2220 | %jmp/1 T_7.312, 4; 2221 | %load/x1p 8, v0x277a5e0_0, 10; 2222 | %jmp T_7.313; 2223 | T_7.312 ; 2224 | %mov 8, 2, 10; 2225 | T_7.313 ; 2226 | ; Save base=8 wid=10 in lookaside. 2227 | %ix/get 3, 8, 10; 2228 | %jmp/1 t_50, 4; 2229 | %ix/load 0, 1, 0; word width 2230 | %ix/load 1, 0, 0; part off 2231 | %assign/av v0x277ac00, 0, 0; 2232 | t_50 ; 2233 | %ix/load 1, 3, 0; 2234 | %mov 4, 0, 1; 2235 | %jmp/1 T_7.314, 4; 2236 | %load/x1p 8, v0x277a5e0_0, 10; 2237 | %jmp T_7.315; 2238 | T_7.314 ; 2239 | %mov 8, 2, 10; 2240 | T_7.315 ; 2241 | ; Save base=8 wid=10 in lookaside. 2242 | %ix/get 3, 8, 10; 2243 | %jmp/1 t_51, 4; 2244 | %ix/load 0, 1, 0; word width 2245 | %ix/load 1, 0, 0; part off 2246 | %assign/av v0x277b7c0, 0, 1; 2247 | t_51 ; 2248 | %jmp T_7.305; 2249 | T_7.304 ; 2250 | %ix/load 1, 3, 0; 2251 | %mov 4, 0, 1; 2252 | %jmp/1 T_7.316, 4; 2253 | %load/x1p 9, v0x277a5e0_0, 10; 2254 | %jmp T_7.317; 2255 | T_7.316 ; 2256 | %mov 9, 2, 10; 2257 | T_7.317 ; 2258 | ; Save base=9 wid=10 in lookaside. 2259 | %ix/get 3, 9, 10; 2260 | %load/av 8, v0x277b840, 1; 2261 | %inv 8, 1; 2262 | %jmp/0xz T_7.318, 8; 2263 | %load/v 8, v0x277b3c0_0, 64; 2264 | %ix/load 1, 3, 0; 2265 | %mov 4, 0, 1; 2266 | %jmp/1 T_7.320, 4; 2267 | %load/x1p 72, v0x277a5e0_0, 10; 2268 | %jmp T_7.321; 2269 | T_7.320 ; 2270 | %mov 72, 2, 10; 2271 | T_7.321 ; 2272 | ; Save base=72 wid=10 in lookaside. 2273 | %ix/get 3, 72, 10; 2274 | %jmp/1 t_52, 4; 2275 | %ix/load 0, 64, 0; word width 2276 | %ix/load 1, 0, 0; part off 2277 | %assign/av v0x277b0a0, 0, 8; 2278 | t_52 ; 2279 | %ix/load 1, 13, 0; 2280 | %mov 4, 0, 1; 2281 | %jmp/1 T_7.322, 4; 2282 | %load/x1p 8, v0x277a5e0_0, 19; 2283 | %jmp T_7.323; 2284 | T_7.322 ; 2285 | %mov 8, 2, 19; 2286 | T_7.323 ; 2287 | ; Save base=8 wid=19 in lookaside. 2288 | %ix/load 1, 3, 0; 2289 | %mov 4, 0, 1; 2290 | %jmp/1 T_7.324, 4; 2291 | %load/x1p 27, v0x277a5e0_0, 10; 2292 | %jmp T_7.325; 2293 | T_7.324 ; 2294 | %mov 27, 2, 10; 2295 | T_7.325 ; 2296 | ; Save base=27 wid=10 in lookaside. 2297 | %ix/get 3, 27, 10; 2298 | %jmp/1 t_53, 4; 2299 | %ix/load 0, 19, 0; word width 2300 | %ix/load 1, 0, 0; part off 2301 | %assign/av v0x277b970, 0, 8; 2302 | t_53 ; 2303 | %ix/load 1, 3, 0; 2304 | %mov 4, 0, 1; 2305 | %jmp/1 T_7.326, 4; 2306 | %load/x1p 8, v0x277a5e0_0, 10; 2307 | %jmp T_7.327; 2308 | T_7.326 ; 2309 | %mov 8, 2, 10; 2310 | T_7.327 ; 2311 | ; Save base=8 wid=10 in lookaside. 2312 | %ix/get 3, 8, 10; 2313 | %jmp/1 t_54, 4; 2314 | %ix/load 0, 1, 0; word width 2315 | %ix/load 1, 0, 0; part off 2316 | %assign/av v0x277ac80, 0, 0; 2317 | t_54 ; 2318 | %ix/load 1, 3, 0; 2319 | %mov 4, 0, 1; 2320 | %jmp/1 T_7.328, 4; 2321 | %load/x1p 8, v0x277a5e0_0, 10; 2322 | %jmp T_7.329; 2323 | T_7.328 ; 2324 | %mov 8, 2, 10; 2325 | T_7.329 ; 2326 | ; Save base=8 wid=10 in lookaside. 2327 | %ix/get 3, 8, 10; 2328 | %jmp/1 t_55, 4; 2329 | %ix/load 0, 1, 0; word width 2330 | %ix/load 1, 0, 0; part off 2331 | %assign/av v0x277b840, 0, 1; 2332 | t_55 ; 2333 | %jmp T_7.319; 2334 | T_7.318 ; 2335 | %ix/load 1, 3, 0; 2336 | %mov 4, 0, 1; 2337 | %jmp/1 T_7.330, 4; 2338 | %load/x1p 12, v0x277a5e0_0, 10; 2339 | %jmp T_7.331; 2340 | T_7.330 ; 2341 | %mov 12, 2, 10; 2342 | T_7.331 ; 2343 | ; Save base=12 wid=10 in lookaside. 2344 | %ix/get 3, 12, 10; 2345 | %load/av 8, v0x277aea0, 2; 2346 | %mov 10, 0, 2; 2347 | %cmpi/u 8, 3, 4; 2348 | %jmp/0xz T_7.332, 4; 2349 | %ix/load 1, 3, 0; 2350 | %mov 4, 0, 1; 2351 | %jmp/1 T_7.334, 4; 2352 | %load/x1p 11, v0x277a5e0_0, 10; 2353 | %jmp T_7.335; 2354 | T_7.334 ; 2355 | %mov 11, 2, 10; 2356 | T_7.335 ; 2357 | ; Save base=11 wid=10 in lookaside. 2358 | %ix/get 3, 11, 10; 2359 | %load/av 8, v0x277a820, 1; 2360 | %mov 9, 0, 2; 2361 | %cmpi/u 8, 1, 3; 2362 | %jmp/0xz T_7.336, 4; 2363 | %ix/load 1, 3, 0; 2364 | %mov 4, 0, 1; 2365 | %jmp/1 T_7.338, 4; 2366 | %load/x1p 69, v0x277a5e0_0, 10; 2367 | %jmp T_7.339; 2368 | T_7.338 ; 2369 | %mov 69, 2, 10; 2370 | T_7.339 ; 2371 | %mov 40, 69, 10; Move signal select into place 2372 | %ix/load 1, 3, 0; 2373 | %mov 4, 0, 1; 2374 | %jmp/1 T_7.340, 4; 2375 | %load/x1p 69, v0x277a5e0_0, 10; 2376 | %jmp T_7.341; 2377 | T_7.340 ; 2378 | %mov 69, 2, 10; 2379 | T_7.341 ; 2380 | ; Save base=69 wid=10 in lookaside. 2381 | %ix/get 3, 69, 10; 2382 | %load/av 50, v0x277b540, 19; 2383 | %mov 8, 40, 29; 2384 | %mov 37, 0, 3; 2385 | %ix/load 0, 32, 0; 2386 | %assign/v0 v0x2778db0_0, 0, 8; 2387 | %ix/load 0, 1, 0; 2388 | %assign/v0 v0x2778e50_0, 0, 1; 2389 | %ix/load 1, 3, 0; 2390 | %mov 4, 0, 1; 2391 | %jmp/1 T_7.342, 4; 2392 | %load/x1p 72, v0x277a5e0_0, 10; 2393 | %jmp T_7.343; 2394 | T_7.342 ; 2395 | %mov 72, 2, 10; 2396 | T_7.343 ; 2397 | ; Save base=72 wid=10 in lookaside. 2398 | %ix/get 3, 72, 10; 2399 | %load/av 8, v0x277b160, 64; 2400 | %ix/load 0, 64, 0; 2401 | %assign/v0 v0x2778d10_0, 0, 8; 2402 | T_7.336 ; 2403 | %load/v 8, v0x277b3c0_0, 64; 2404 | %ix/load 1, 3, 0; 2405 | %mov 4, 0, 1; 2406 | %jmp/1 T_7.344, 4; 2407 | %load/x1p 72, v0x277a5e0_0, 10; 2408 | %jmp T_7.345; 2409 | T_7.344 ; 2410 | %mov 72, 2, 10; 2411 | T_7.345 ; 2412 | ; Save base=72 wid=10 in lookaside. 2413 | %ix/get 3, 72, 10; 2414 | %jmp/1 t_56, 4; 2415 | %ix/load 0, 64, 0; word width 2416 | %ix/load 1, 0, 0; part off 2417 | %assign/av v0x277b160, 0, 8; 2418 | t_56 ; 2419 | %ix/load 1, 13, 0; 2420 | %mov 4, 0, 1; 2421 | %jmp/1 T_7.346, 4; 2422 | %load/x1p 8, v0x277a5e0_0, 19; 2423 | %jmp T_7.347; 2424 | T_7.346 ; 2425 | %mov 8, 2, 19; 2426 | T_7.347 ; 2427 | ; Save base=8 wid=19 in lookaside. 2428 | %ix/load 1, 3, 0; 2429 | %mov 4, 0, 1; 2430 | %jmp/1 T_7.348, 4; 2431 | %load/x1p 27, v0x277a5e0_0, 10; 2432 | %jmp T_7.349; 2433 | T_7.348 ; 2434 | %mov 27, 2, 10; 2435 | T_7.349 ; 2436 | ; Save base=27 wid=10 in lookaside. 2437 | %ix/get 3, 27, 10; 2438 | %jmp/1 t_57, 4; 2439 | %ix/load 0, 19, 0; word width 2440 | %ix/load 1, 0, 0; part off 2441 | %assign/av v0x277b540, 0, 8; 2442 | t_57 ; 2443 | %ix/load 1, 3, 0; 2444 | %mov 4, 0, 1; 2445 | %jmp/1 T_7.350, 4; 2446 | %load/x1p 8, v0x277a5e0_0, 10; 2447 | %jmp T_7.351; 2448 | T_7.350 ; 2449 | %mov 8, 2, 10; 2450 | T_7.351 ; 2451 | ; Save base=8 wid=10 in lookaside. 2452 | %ix/get 3, 8, 10; 2453 | %jmp/1 t_58, 4; 2454 | %ix/load 0, 1, 0; word width 2455 | %ix/load 1, 0, 0; part off 2456 | %assign/av v0x277a820, 0, 0; 2457 | t_58 ; 2458 | %ix/load 1, 3, 0; 2459 | %mov 4, 0, 1; 2460 | %jmp/1 T_7.352, 4; 2461 | %load/x1p 8, v0x277a5e0_0, 10; 2462 | %jmp T_7.353; 2463 | T_7.352 ; 2464 | %mov 8, 2, 10; 2465 | T_7.353 ; 2466 | ; Save base=8 wid=10 in lookaside. 2467 | %ix/get 3, 8, 10; 2468 | %jmp/1 t_59, 4; 2469 | %ix/load 0, 1, 0; word width 2470 | %ix/load 1, 0, 0; part off 2471 | %assign/av v0x277b6c0, 0, 1; 2472 | t_59 ; 2473 | %jmp T_7.333; 2474 | T_7.332 ; 2475 | %ix/load 1, 3, 0; 2476 | %mov 4, 0, 1; 2477 | %jmp/1 T_7.354, 4; 2478 | %load/x1p 12, v0x277a5e0_0, 10; 2479 | %jmp T_7.355; 2480 | T_7.354 ; 2481 | %mov 12, 2, 10; 2482 | T_7.355 ; 2483 | ; Save base=12 wid=10 in lookaside. 2484 | %ix/get 3, 12, 10; 2485 | %load/av 8, v0x277af20, 2; 2486 | %mov 10, 0, 2; 2487 | %cmpi/u 8, 3, 4; 2488 | %jmp/0xz T_7.356, 4; 2489 | %ix/load 1, 3, 0; 2490 | %mov 4, 0, 1; 2491 | %jmp/1 T_7.358, 4; 2492 | %load/x1p 11, v0x277a5e0_0, 10; 2493 | %jmp T_7.359; 2494 | T_7.358 ; 2495 | %mov 11, 2, 10; 2496 | T_7.359 ; 2497 | ; Save base=11 wid=10 in lookaside. 2498 | %ix/get 3, 11, 10; 2499 | %load/av 8, v0x277a8a0, 1; 2500 | %mov 9, 0, 2; 2501 | %cmpi/u 8, 1, 3; 2502 | %jmp/0xz T_7.360, 4; 2503 | %ix/load 1, 3, 0; 2504 | %mov 4, 0, 1; 2505 | %jmp/1 T_7.362, 4; 2506 | %load/x1p 69, v0x277a5e0_0, 10; 2507 | %jmp T_7.363; 2508 | T_7.362 ; 2509 | %mov 69, 2, 10; 2510 | T_7.363 ; 2511 | %mov 40, 69, 10; Move signal select into place 2512 | %ix/load 1, 3, 0; 2513 | %mov 4, 0, 1; 2514 | %jmp/1 T_7.364, 4; 2515 | %load/x1p 69, v0x277a5e0_0, 10; 2516 | %jmp T_7.365; 2517 | T_7.364 ; 2518 | %mov 69, 2, 10; 2519 | T_7.365 ; 2520 | ; Save base=69 wid=10 in lookaside. 2521 | %ix/get 3, 69, 10; 2522 | %load/av 50, v0x277b5c0, 19; 2523 | %mov 8, 40, 29; 2524 | %mov 37, 0, 3; 2525 | %ix/load 0, 32, 0; 2526 | %assign/v0 v0x2778db0_0, 0, 8; 2527 | %ix/load 0, 1, 0; 2528 | %assign/v0 v0x2778e50_0, 0, 1; 2529 | %ix/load 1, 3, 0; 2530 | %mov 4, 0, 1; 2531 | %jmp/1 T_7.366, 4; 2532 | %load/x1p 72, v0x277a5e0_0, 10; 2533 | %jmp T_7.367; 2534 | T_7.366 ; 2535 | %mov 72, 2, 10; 2536 | T_7.367 ; 2537 | ; Save base=72 wid=10 in lookaside. 2538 | %ix/get 3, 72, 10; 2539 | %load/av 8, v0x277afa0, 64; 2540 | %ix/load 0, 64, 0; 2541 | %assign/v0 v0x2778d10_0, 0, 8; 2542 | T_7.360 ; 2543 | %load/v 8, v0x277b3c0_0, 64; 2544 | %ix/load 1, 3, 0; 2545 | %mov 4, 0, 1; 2546 | %jmp/1 T_7.368, 4; 2547 | %load/x1p 72, v0x277a5e0_0, 10; 2548 | %jmp T_7.369; 2549 | T_7.368 ; 2550 | %mov 72, 2, 10; 2551 | T_7.369 ; 2552 | ; Save base=72 wid=10 in lookaside. 2553 | %ix/get 3, 72, 10; 2554 | %jmp/1 t_60, 4; 2555 | %ix/load 0, 64, 0; word width 2556 | %ix/load 1, 0, 0; part off 2557 | %assign/av v0x277afa0, 0, 8; 2558 | t_60 ; 2559 | %ix/load 1, 13, 0; 2560 | %mov 4, 0, 1; 2561 | %jmp/1 T_7.370, 4; 2562 | %load/x1p 8, v0x277a5e0_0, 19; 2563 | %jmp T_7.371; 2564 | T_7.370 ; 2565 | %mov 8, 2, 19; 2566 | T_7.371 ; 2567 | ; Save base=8 wid=19 in lookaside. 2568 | %ix/load 1, 3, 0; 2569 | %mov 4, 0, 1; 2570 | %jmp/1 T_7.372, 4; 2571 | %load/x1p 27, v0x277a5e0_0, 10; 2572 | %jmp T_7.373; 2573 | T_7.372 ; 2574 | %mov 27, 2, 10; 2575 | T_7.373 ; 2576 | ; Save base=27 wid=10 in lookaside. 2577 | %ix/get 3, 27, 10; 2578 | %jmp/1 t_61, 4; 2579 | %ix/load 0, 19, 0; word width 2580 | %ix/load 1, 0, 0; part off 2581 | %assign/av v0x277b5c0, 0, 8; 2582 | t_61 ; 2583 | %ix/load 1, 3, 0; 2584 | %mov 4, 0, 1; 2585 | %jmp/1 T_7.374, 4; 2586 | %load/x1p 8, v0x277a5e0_0, 10; 2587 | %jmp T_7.375; 2588 | T_7.374 ; 2589 | %mov 8, 2, 10; 2590 | T_7.375 ; 2591 | ; Save base=8 wid=10 in lookaside. 2592 | %ix/get 3, 8, 10; 2593 | %jmp/1 t_62, 4; 2594 | %ix/load 0, 1, 0; word width 2595 | %ix/load 1, 0, 0; part off 2596 | %assign/av v0x277a8a0, 0, 0; 2597 | t_62 ; 2598 | %ix/load 1, 3, 0; 2599 | %mov 4, 0, 1; 2600 | %jmp/1 T_7.376, 4; 2601 | %load/x1p 8, v0x277a5e0_0, 10; 2602 | %jmp T_7.377; 2603 | T_7.376 ; 2604 | %mov 8, 2, 10; 2605 | T_7.377 ; 2606 | ; Save base=8 wid=10 in lookaside. 2607 | %ix/get 3, 8, 10; 2608 | %jmp/1 t_63, 4; 2609 | %ix/load 0, 1, 0; word width 2610 | %ix/load 1, 0, 0; part off 2611 | %assign/av v0x277b740, 0, 1; 2612 | t_63 ; 2613 | %jmp T_7.357; 2614 | T_7.356 ; 2615 | %ix/load 1, 3, 0; 2616 | %mov 4, 0, 1; 2617 | %jmp/1 T_7.378, 4; 2618 | %load/x1p 12, v0x277a5e0_0, 10; 2619 | %jmp T_7.379; 2620 | T_7.378 ; 2621 | %mov 12, 2, 10; 2622 | T_7.379 ; 2623 | ; Save base=12 wid=10 in lookaside. 2624 | %ix/get 3, 12, 10; 2625 | %load/av 8, v0x277ad00, 2; 2626 | %mov 10, 0, 2; 2627 | %cmpi/u 8, 3, 4; 2628 | %jmp/0xz T_7.380, 4; 2629 | %ix/load 1, 3, 0; 2630 | %mov 4, 0, 1; 2631 | %jmp/1 T_7.382, 4; 2632 | %load/x1p 11, v0x277a5e0_0, 10; 2633 | %jmp T_7.383; 2634 | T_7.382 ; 2635 | %mov 11, 2, 10; 2636 | T_7.383 ; 2637 | ; Save base=11 wid=10 in lookaside. 2638 | %ix/get 3, 11, 10; 2639 | %load/av 8, v0x277ac00, 1; 2640 | %mov 9, 0, 2; 2641 | %cmpi/u 8, 1, 3; 2642 | %jmp/0xz T_7.384, 4; 2643 | %ix/load 1, 3, 0; 2644 | %mov 4, 0, 1; 2645 | %jmp/1 T_7.386, 4; 2646 | %load/x1p 69, v0x277a5e0_0, 10; 2647 | %jmp T_7.387; 2648 | T_7.386 ; 2649 | %mov 69, 2, 10; 2650 | T_7.387 ; 2651 | %mov 40, 69, 10; Move signal select into place 2652 | %ix/load 1, 3, 0; 2653 | %mov 4, 0, 1; 2654 | %jmp/1 T_7.388, 4; 2655 | %load/x1p 69, v0x277a5e0_0, 10; 2656 | %jmp T_7.389; 2657 | T_7.388 ; 2658 | %mov 69, 2, 10; 2659 | T_7.389 ; 2660 | ; Save base=69 wid=10 in lookaside. 2661 | %ix/get 3, 69, 10; 2662 | %load/av 50, v0x277b8f0, 19; 2663 | %mov 8, 40, 29; 2664 | %mov 37, 0, 3; 2665 | %ix/load 0, 32, 0; 2666 | %assign/v0 v0x2778db0_0, 0, 8; 2667 | %ix/load 0, 1, 0; 2668 | %assign/v0 v0x2778e50_0, 0, 1; 2669 | %ix/load 1, 3, 0; 2670 | %mov 4, 0, 1; 2671 | %jmp/1 T_7.390, 4; 2672 | %load/x1p 72, v0x277a5e0_0, 10; 2673 | %jmp T_7.391; 2674 | T_7.390 ; 2675 | %mov 72, 2, 10; 2676 | T_7.391 ; 2677 | ; Save base=72 wid=10 in lookaside. 2678 | %ix/get 3, 72, 10; 2679 | %load/av 8, v0x277b020, 64; 2680 | %ix/load 0, 64, 0; 2681 | %assign/v0 v0x2778d10_0, 0, 8; 2682 | T_7.384 ; 2683 | %load/v 8, v0x277b3c0_0, 64; 2684 | %ix/load 1, 3, 0; 2685 | %mov 4, 0, 1; 2686 | %jmp/1 T_7.392, 4; 2687 | %load/x1p 72, v0x277a5e0_0, 10; 2688 | %jmp T_7.393; 2689 | T_7.392 ; 2690 | %mov 72, 2, 10; 2691 | T_7.393 ; 2692 | ; Save base=72 wid=10 in lookaside. 2693 | %ix/get 3, 72, 10; 2694 | %jmp/1 t_64, 4; 2695 | %ix/load 0, 64, 0; word width 2696 | %ix/load 1, 0, 0; part off 2697 | %assign/av v0x277b020, 0, 8; 2698 | t_64 ; 2699 | %ix/load 1, 13, 0; 2700 | %mov 4, 0, 1; 2701 | %jmp/1 T_7.394, 4; 2702 | %load/x1p 8, v0x277a5e0_0, 19; 2703 | %jmp T_7.395; 2704 | T_7.394 ; 2705 | %mov 8, 2, 19; 2706 | T_7.395 ; 2707 | ; Save base=8 wid=19 in lookaside. 2708 | %ix/load 1, 3, 0; 2709 | %mov 4, 0, 1; 2710 | %jmp/1 T_7.396, 4; 2711 | %load/x1p 27, v0x277a5e0_0, 10; 2712 | %jmp T_7.397; 2713 | T_7.396 ; 2714 | %mov 27, 2, 10; 2715 | T_7.397 ; 2716 | ; Save base=27 wid=10 in lookaside. 2717 | %ix/get 3, 27, 10; 2718 | %jmp/1 t_65, 4; 2719 | %ix/load 0, 19, 0; word width 2720 | %ix/load 1, 0, 0; part off 2721 | %assign/av v0x277b8f0, 0, 8; 2722 | t_65 ; 2723 | %ix/load 1, 3, 0; 2724 | %mov 4, 0, 1; 2725 | %jmp/1 T_7.398, 4; 2726 | %load/x1p 8, v0x277a5e0_0, 10; 2727 | %jmp T_7.399; 2728 | T_7.398 ; 2729 | %mov 8, 2, 10; 2730 | T_7.399 ; 2731 | ; Save base=8 wid=10 in lookaside. 2732 | %ix/get 3, 8, 10; 2733 | %jmp/1 t_66, 4; 2734 | %ix/load 0, 1, 0; word width 2735 | %ix/load 1, 0, 0; part off 2736 | %assign/av v0x277ac00, 0, 0; 2737 | t_66 ; 2738 | %ix/load 1, 3, 0; 2739 | %mov 4, 0, 1; 2740 | %jmp/1 T_7.400, 4; 2741 | %load/x1p 8, v0x277a5e0_0, 10; 2742 | %jmp T_7.401; 2743 | T_7.400 ; 2744 | %mov 8, 2, 10; 2745 | T_7.401 ; 2746 | ; Save base=8 wid=10 in lookaside. 2747 | %ix/get 3, 8, 10; 2748 | %jmp/1 t_67, 4; 2749 | %ix/load 0, 1, 0; word width 2750 | %ix/load 1, 0, 0; part off 2751 | %assign/av v0x277b7c0, 0, 1; 2752 | t_67 ; 2753 | %jmp T_7.381; 2754 | T_7.380 ; 2755 | %ix/load 1, 3, 0; 2756 | %mov 4, 0, 1; 2757 | %jmp/1 T_7.402, 4; 2758 | %load/x1p 12, v0x277a5e0_0, 10; 2759 | %jmp T_7.403; 2760 | T_7.402 ; 2761 | %mov 12, 2, 10; 2762 | T_7.403 ; 2763 | ; Save base=12 wid=10 in lookaside. 2764 | %ix/get 3, 12, 10; 2765 | %load/av 8, v0x277ad80, 2; 2766 | %mov 10, 0, 2; 2767 | %cmpi/u 8, 3, 4; 2768 | %jmp/0xz T_7.404, 4; 2769 | %ix/load 1, 3, 0; 2770 | %mov 4, 0, 1; 2771 | %jmp/1 T_7.406, 4; 2772 | %load/x1p 11, v0x277a5e0_0, 10; 2773 | %jmp T_7.407; 2774 | T_7.406 ; 2775 | %mov 11, 2, 10; 2776 | T_7.407 ; 2777 | ; Save base=11 wid=10 in lookaside. 2778 | %ix/get 3, 11, 10; 2779 | %load/av 8, v0x277ac80, 1; 2780 | %mov 9, 0, 2; 2781 | %cmpi/u 8, 1, 3; 2782 | %jmp/0xz T_7.408, 4; 2783 | %ix/load 1, 3, 0; 2784 | %mov 4, 0, 1; 2785 | %jmp/1 T_7.410, 4; 2786 | %load/x1p 69, v0x277a5e0_0, 10; 2787 | %jmp T_7.411; 2788 | T_7.410 ; 2789 | %mov 69, 2, 10; 2790 | T_7.411 ; 2791 | %mov 40, 69, 10; Move signal select into place 2792 | %ix/load 1, 3, 0; 2793 | %mov 4, 0, 1; 2794 | %jmp/1 T_7.412, 4; 2795 | %load/x1p 69, v0x277a5e0_0, 10; 2796 | %jmp T_7.413; 2797 | T_7.412 ; 2798 | %mov 69, 2, 10; 2799 | T_7.413 ; 2800 | ; Save base=69 wid=10 in lookaside. 2801 | %ix/get 3, 69, 10; 2802 | %load/av 50, v0x277b970, 19; 2803 | %mov 8, 40, 29; 2804 | %mov 37, 0, 3; 2805 | %ix/load 0, 32, 0; 2806 | %assign/v0 v0x2778db0_0, 0, 8; 2807 | %ix/load 0, 1, 0; 2808 | %assign/v0 v0x2778e50_0, 0, 1; 2809 | %ix/load 1, 3, 0; 2810 | %mov 4, 0, 1; 2811 | %jmp/1 T_7.414, 4; 2812 | %load/x1p 72, v0x277a5e0_0, 10; 2813 | %jmp T_7.415; 2814 | T_7.414 ; 2815 | %mov 72, 2, 10; 2816 | T_7.415 ; 2817 | ; Save base=72 wid=10 in lookaside. 2818 | %ix/get 3, 72, 10; 2819 | %load/av 8, v0x277b0a0, 64; 2820 | %ix/load 0, 64, 0; 2821 | %assign/v0 v0x2778d10_0, 0, 8; 2822 | T_7.408 ; 2823 | %load/v 8, v0x277b3c0_0, 64; 2824 | %ix/load 1, 3, 0; 2825 | %mov 4, 0, 1; 2826 | %jmp/1 T_7.416, 4; 2827 | %load/x1p 72, v0x277a5e0_0, 10; 2828 | %jmp T_7.417; 2829 | T_7.416 ; 2830 | %mov 72, 2, 10; 2831 | T_7.417 ; 2832 | ; Save base=72 wid=10 in lookaside. 2833 | %ix/get 3, 72, 10; 2834 | %jmp/1 t_68, 4; 2835 | %ix/load 0, 64, 0; word width 2836 | %ix/load 1, 0, 0; part off 2837 | %assign/av v0x277b0a0, 0, 8; 2838 | t_68 ; 2839 | %ix/load 1, 13, 0; 2840 | %mov 4, 0, 1; 2841 | %jmp/1 T_7.418, 4; 2842 | %load/x1p 8, v0x277a5e0_0, 19; 2843 | %jmp T_7.419; 2844 | T_7.418 ; 2845 | %mov 8, 2, 19; 2846 | T_7.419 ; 2847 | ; Save base=8 wid=19 in lookaside. 2848 | %ix/load 1, 3, 0; 2849 | %mov 4, 0, 1; 2850 | %jmp/1 T_7.420, 4; 2851 | %load/x1p 27, v0x277a5e0_0, 10; 2852 | %jmp T_7.421; 2853 | T_7.420 ; 2854 | %mov 27, 2, 10; 2855 | T_7.421 ; 2856 | ; Save base=27 wid=10 in lookaside. 2857 | %ix/get 3, 27, 10; 2858 | %jmp/1 t_69, 4; 2859 | %ix/load 0, 19, 0; word width 2860 | %ix/load 1, 0, 0; part off 2861 | %assign/av v0x277b970, 0, 8; 2862 | t_69 ; 2863 | %ix/load 1, 3, 0; 2864 | %mov 4, 0, 1; 2865 | %jmp/1 T_7.422, 4; 2866 | %load/x1p 8, v0x277a5e0_0, 10; 2867 | %jmp T_7.423; 2868 | T_7.422 ; 2869 | %mov 8, 2, 10; 2870 | T_7.423 ; 2871 | ; Save base=8 wid=10 in lookaside. 2872 | %ix/get 3, 8, 10; 2873 | %jmp/1 t_70, 4; 2874 | %ix/load 0, 1, 0; word width 2875 | %ix/load 1, 0, 0; part off 2876 | %assign/av v0x277ac80, 0, 0; 2877 | t_70 ; 2878 | %ix/load 1, 3, 0; 2879 | %mov 4, 0, 1; 2880 | %jmp/1 T_7.424, 4; 2881 | %load/x1p 8, v0x277a5e0_0, 10; 2882 | %jmp T_7.425; 2883 | T_7.424 ; 2884 | %mov 8, 2, 10; 2885 | T_7.425 ; 2886 | ; Save base=8 wid=10 in lookaside. 2887 | %ix/get 3, 8, 10; 2888 | %jmp/1 t_71, 4; 2889 | %ix/load 0, 1, 0; word width 2890 | %ix/load 1, 0, 0; part off 2891 | %assign/av v0x277b840, 0, 1; 2892 | t_71 ; 2893 | T_7.404 ; 2894 | T_7.381 ; 2895 | T_7.357 ; 2896 | T_7.333 ; 2897 | T_7.319 ; 2898 | T_7.305 ; 2899 | T_7.291 ; 2900 | T_7.277 ; 2901 | %ix/load 0, 1, 0; 2902 | %assign/v0 v0x277a980_0, 0, 0; 2903 | %jmp T_7.3; 2904 | T_7.3 ; 2905 | %jmp T_7; 2906 | .thread T_7; 2907 | .scope S_0x26f7d70; 2908 | T_8 ; 2909 | %vpi_call 4 37 "$readmemh", P_0x2753360, v0x2778000; 2910 | %end; 2911 | .thread T_8; 2912 | .scope S_0x26f7d70; 2913 | T_9 ; 2914 | %wait E_0x2759140; 2915 | %load/v 8, v0x2778350_0, 1; 2916 | %jmp/0xz T_9.0, 8; 2917 | %load/v 8, v0x2777f60_0, 64; 2918 | %ix/getv 3, v0x27782b0_0; 2919 | %jmp/1 t_72, 4; 2920 | %ix/load 0, 64, 0; word width 2921 | %ix/load 1, 0, 0; part off 2922 | %assign/av v0x2778000, 0, 8; 2923 | t_72 ; 2924 | T_9.0 ; 2925 | %jmp T_9; 2926 | .thread T_9; 2927 | .scope S_0x26f7d70; 2928 | T_10 ; 2929 | %wait E_0x2759140; 2930 | %load/v 8, v0x27781d0_0, 1; 2931 | %jmp/0xz T_10.0, 8; 2932 | %ix/getv 3, v0x2778130_0; 2933 | %load/av 8, v0x2778000, 64; 2934 | %ix/load 0, 64, 0; 2935 | %assign/v0 v0x2778080_0, 0, 8; 2936 | T_10.0 ; 2937 | %jmp T_10; 2938 | .thread T_10; 2939 | .scope S_0x26f8000; 2940 | T_11 ; 2941 | %set/v v0x277bd50_0, 0, 32; 2942 | %end; 2943 | .thread T_11; 2944 | .scope S_0x26f8000; 2945 | T_12 ; 2946 | %set/v v0x277bdd0_0, 0, 32; 2947 | %end; 2948 | .thread T_12; 2949 | .scope S_0x26f8000; 2950 | T_13 ; 2951 | %set/v v0x277bf50_0, 0, 1; 2952 | %end; 2953 | .thread T_13; 2954 | .scope S_0x26f8000; 2955 | T_14 ; 2956 | %set/v v0x277bfd0_0, 0, 1; 2957 | %end; 2958 | .thread T_14; 2959 | .scope S_0x26f8000; 2960 | T_15 ; 2961 | %delay 100000, 0; 2962 | %movi 8, 8, 32; 2963 | %ix/load 0, 32, 0; 2964 | %assign/v0 v0x277bd50_0, 0, 8; 2965 | %ix/load 0, 32, 0; 2966 | %assign/v0 v0x277bdd0_0, 0, 0; 2967 | %ix/load 0, 1, 0; 2968 | %assign/v0 v0x277bf50_0, 0, 1; 2969 | %ix/load 0, 1, 0; 2970 | %assign/v0 v0x277bfd0_0, 0, 0; 2971 | %delay 100000, 0; 2972 | %movi 8, 8, 32; 2973 | %ix/load 0, 32, 0; 2974 | %assign/v0 v0x277bd50_0, 0, 8; 2975 | %movi 8, 3135094511, 32; 2976 | %ix/load 0, 32, 0; 2977 | %assign/v0 v0x277bdd0_0, 0, 8; 2978 | %ix/load 0, 1, 0; 2979 | %assign/v0 v0x277bf50_0, 0, 0; 2980 | %ix/load 0, 1, 0; 2981 | %assign/v0 v0x277bfd0_0, 0, 1; 2982 | %delay 100000, 0; 2983 | %movi 8, 11, 32; 2984 | %ix/load 0, 32, 0; 2985 | %assign/v0 v0x277bd50_0, 0, 8; 2986 | %ix/load 0, 32, 0; 2987 | %assign/v0 v0x277bdd0_0, 0, 0; 2988 | %ix/load 0, 1, 0; 2989 | %assign/v0 v0x277bf50_0, 0, 0; 2990 | %ix/load 0, 1, 0; 2991 | %assign/v0 v0x277bfd0_0, 0, 1; 2992 | %delay 100000, 0; 2993 | %movi 8, 12, 32; 2994 | %ix/load 0, 32, 0; 2995 | %assign/v0 v0x277bd50_0, 0, 8; 2996 | %movi 8, 2863311530, 32; 2997 | %ix/load 0, 32, 0; 2998 | %assign/v0 v0x277bdd0_0, 0, 8; 2999 | %ix/load 0, 1, 0; 3000 | %assign/v0 v0x277bf50_0, 0, 0; 3001 | %ix/load 0, 1, 0; 3002 | %assign/v0 v0x277bfd0_0, 0, 1; 3003 | %delay 100000, 0; 3004 | %movi 8, 268435464, 32; 3005 | %ix/load 0, 32, 0; 3006 | %assign/v0 v0x277bd50_0, 0, 8; 3007 | %ix/load 0, 32, 0; 3008 | %assign/v0 v0x277bdd0_0, 0, 0; 3009 | %ix/load 0, 1, 0; 3010 | %assign/v0 v0x277bf50_0, 0, 1; 3011 | %ix/load 0, 1, 0; 3012 | %assign/v0 v0x277bfd0_0, 0, 0; 3013 | %delay 100000, 0; 3014 | %movi 8, 536870920, 32; 3015 | %ix/load 0, 32, 0; 3016 | %assign/v0 v0x277bd50_0, 0, 8; 3017 | %ix/load 0, 32, 0; 3018 | %assign/v0 v0x277bdd0_0, 0, 0; 3019 | %ix/load 0, 1, 0; 3020 | %assign/v0 v0x277bf50_0, 0, 1; 3021 | %ix/load 0, 1, 0; 3022 | %assign/v0 v0x277bfd0_0, 0, 0; 3023 | %delay 100000, 0; 3024 | %movi 8, 805306376, 32; 3025 | %ix/load 0, 32, 0; 3026 | %assign/v0 v0x277bd50_0, 0, 8; 3027 | %ix/load 0, 32, 0; 3028 | %assign/v0 v0x277bdd0_0, 0, 0; 3029 | %ix/load 0, 1, 0; 3030 | %assign/v0 v0x277bf50_0, 0, 1; 3031 | %ix/load 0, 1, 0; 3032 | %assign/v0 v0x277bfd0_0, 0, 0; 3033 | %delay 100000, 0; 3034 | %movi 8, 1073741832, 32; 3035 | %ix/load 0, 32, 0; 3036 | %assign/v0 v0x277bd50_0, 0, 8; 3037 | %ix/load 0, 32, 0; 3038 | %assign/v0 v0x277bdd0_0, 0, 0; 3039 | %ix/load 0, 1, 0; 3040 | %assign/v0 v0x277bf50_0, 0, 1; 3041 | %ix/load 0, 1, 0; 3042 | %assign/v0 v0x277bfd0_0, 0, 0; 3043 | %delay 100000, 0; 3044 | %movi 8, 8, 32; 3045 | %ix/load 0, 32, 0; 3046 | %assign/v0 v0x277bd50_0, 0, 8; 3047 | %ix/load 0, 32, 0; 3048 | %assign/v0 v0x277bdd0_0, 0, 0; 3049 | %ix/load 0, 1, 0; 3050 | %assign/v0 v0x277bf50_0, 0, 1; 3051 | %ix/load 0, 1, 0; 3052 | %assign/v0 v0x277bfd0_0, 0, 0; 3053 | %delay 100000, 0; 3054 | %movi 8, 268435464, 32; 3055 | %ix/load 0, 32, 0; 3056 | %assign/v0 v0x277bd50_0, 0, 8; 3057 | %movi 8, 3135094511, 32; 3058 | %ix/load 0, 32, 0; 3059 | %assign/v0 v0x277bdd0_0, 0, 8; 3060 | %ix/load 0, 1, 0; 3061 | %assign/v0 v0x277bf50_0, 0, 0; 3062 | %ix/load 0, 1, 0; 3063 | %assign/v0 v0x277bfd0_0, 0, 1; 3064 | %delay 100000, 0; 3065 | %movi 8, 305419896, 32; 3066 | %ix/load 0, 32, 0; 3067 | %assign/v0 v0x277bd50_0, 0, 8; 3068 | %movi 8, 3135094511, 32; 3069 | %ix/load 0, 32, 0; 3070 | %assign/v0 v0x277bdd0_0, 0, 8; 3071 | %ix/load 0, 1, 0; 3072 | %assign/v0 v0x277bf50_0, 0, 1; 3073 | %ix/load 0, 1, 0; 3074 | %assign/v0 v0x277bfd0_0, 0, 0; 3075 | %delay 50000, 0; 3076 | %vpi_call 2 237 "$finish"; 3077 | %jmp T_15; 3078 | .thread T_15; 3079 | .scope S_0x26f8000; 3080 | T_16 ; 3081 | %vpi_call 2 243 "$monitor", "time=%4d | addr=%10d | hm=%b | q=%08x | way1=%08h | way2=%08h | way3=%08h | way4=%08h | mem[1]=%08h | lru1=%d | lru2=%d | lru3=%d | lru4=%d", $time, v0x277bd50_0, v0x277be50_0, v0x277b440_0, &A, &A, &A, &A, &A, &A, &A, &A, &A; 3082 | %end; 3083 | .thread T_16; 3084 | .scope S_0x26f8000; 3085 | T_17 ; 3086 | %set/v v0x277bcd0_0, 1, 1; 3087 | %delay 5000, 0; 3088 | %set/v v0x277bcd0_0, 0, 1; 3089 | %delay 5000, 0; 3090 | %jmp T_17; 3091 | .thread T_17; 3092 | # The file index is used to find the file name in the following table. 3093 | :file_names 5; 3094 | "N/A"; 3095 | ""; 3096 | "d_cache_tb.v"; 3097 | "../d_cache.v"; 3098 | "../mem.v"; 3099 | -------------------------------------------------------------------------------- /project_caches/d_cache_tb/d_cache_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module d_cache_test; 5 | reg clk; 6 | 7 | wire [63:0] data_in; 8 | wire [63:0] data_out; 9 | wire [31:0] rd_addr; 10 | wire rd_en; 11 | wire [31:0] wr_addr; 12 | wire wr_en; 13 | 14 | reg [31:0] d_cache_addr = 0; 15 | reg [31:0] d_cache_din = 0; 16 | reg d_cache_rden = 0; 17 | reg d_cache_wren = 0; 18 | wire d_cache_hit_miss; 19 | wire [31:0] d_cache_q; 20 | 21 | d_cache DUT_CACHE ( 22 | .clock(clk), 23 | .address(d_cache_addr), 24 | .din(d_cache_din), 25 | .rden(d_cache_rden), 26 | .wren(d_cache_wren), 27 | .hit_miss(d_cache_hit_miss), 28 | .q(d_cache_q), 29 | .mdout(data_in), 30 | .mrdaddress(rd_addr), 31 | .mrden(rd_en), 32 | .mwraddress(wr_addr), 33 | .mwren(wr_en), 34 | .mq(data_out) 35 | ); 36 | 37 | defparam DUT_CACHE.SIZE = 32*1024*8; 38 | defparam DUT_CACHE.NWAYS = 4; 39 | defparam DUT_CACHE.NSETS = 1024; 40 | defparam DUT_CACHE.BLOCK_SIZE = 64; 41 | defparam DUT_CACHE.WIDTH = 32; 42 | defparam DUT_CACHE.MWIDTH = 64; 43 | 44 | mem DUT_MEM ( 45 | .clock(clk), 46 | .data(data_in), 47 | .rdaddress(rd_addr), 48 | .rden(rd_en), 49 | .wraddress(wr_addr), 50 | .wren(wr_en), 51 | .q(data_out) 52 | ); 53 | 54 | defparam DUT_MEM.WIDTH = 64; 55 | defparam DUT_MEM.DEPTH = 128; 56 | defparam DUT_MEM.FILE = "d_mem_data.txt"; 57 | 58 | integer i; 59 | 60 | always 61 | begin 62 | 63 | // basic writeback ///////////////////////////////////////////////////////////////////////////////////////////////////////// 64 | 65 | /*# 100; // This should be a miss 66 | 67 | d_cache_addr <= 32'h00000008; 68 | d_cache_din <= 0; 69 | d_cache_rden <= 1; 70 | d_cache_wren <= 0; 71 | 72 | # 100; // This should be a hit 73 | 74 | d_cache_addr <= 32'h00000008; 75 | d_cache_din <= 32'hBADDBEEF; 76 | d_cache_rden <= 0; 77 | d_cache_wren <= 1; 78 | 79 | # 100; // This should be a miss 80 | 81 | d_cache_addr <= 32'h10000008; 82 | d_cache_din <= 0; 83 | d_cache_rden <= 1; 84 | d_cache_wren <= 0; 85 | 86 | # 100; // This should be a miss 87 | 88 | d_cache_addr <= 32'h20000008; 89 | d_cache_din <= 0; 90 | d_cache_rden <= 1; 91 | d_cache_wren <= 0; 92 | 93 | # 100; // This should be a miss 94 | 95 | d_cache_addr <= 32'h30000008; 96 | d_cache_din <= 0; 97 | d_cache_rden <= 1; 98 | d_cache_wren <= 0; 99 | 100 | # 100; // This should be a miss and eviction 101 | 102 | d_cache_addr <= 32'h40000008; 103 | d_cache_din <= 0; 104 | d_cache_rden <= 1; 105 | d_cache_wren <= 0; 106 | 107 | # 100; // This should be a miss (evicted) 108 | 109 | d_cache_addr <= 32'h00000008; 110 | d_cache_din <= 0; 111 | d_cache_rden <= 1; 112 | d_cache_wren <= 0; 113 | 114 | # 100; // This should be a hit 115 | 116 | d_cache_addr <= 32'h30000008; 117 | d_cache_din <= 0; 118 | d_cache_rden <= 1; 119 | d_cache_wren <= 0;*/ 120 | 121 | // repeated writes (w/ offset) ///////////////////////////////////////////////////////////////////////////////////////////////////////// 122 | 123 | # 100; // This should be a miss 124 | 125 | d_cache_addr <= 32'h00000008; 126 | d_cache_din <= 0; 127 | d_cache_rden <= 1; 128 | d_cache_wren <= 0; 129 | 130 | # 100; // This should be a hit 131 | 132 | d_cache_addr <= 32'h00000008; 133 | d_cache_din <= 32'hBADDBEEF; 134 | d_cache_rden <= 0; 135 | d_cache_wren <= 1; 136 | 137 | # 100; // This should be a hit 138 | 139 | d_cache_addr <= 32'h0000000B; 140 | d_cache_din <= 32'h00000000; 141 | d_cache_rden <= 0; 142 | d_cache_wren <= 1; 143 | 144 | # 100; // This should be a hit 145 | 146 | d_cache_addr <= 32'h0000000C; 147 | d_cache_din <= 32'hAAAAAAAA; 148 | d_cache_rden <= 0; 149 | d_cache_wren <= 1; 150 | 151 | # 100; // This should be a miss 152 | 153 | d_cache_addr <= 32'h10000008; 154 | d_cache_din <= 0; 155 | d_cache_rden <= 1; 156 | d_cache_wren <= 0; 157 | 158 | # 100; // This should be a miss 159 | 160 | d_cache_addr <= 32'h20000008; 161 | d_cache_din <= 0; 162 | d_cache_rden <= 1; 163 | d_cache_wren <= 0; 164 | 165 | # 100; // This should be a miss 166 | 167 | d_cache_addr <= 32'h30000008; 168 | d_cache_din <= 0; 169 | d_cache_rden <= 1; 170 | d_cache_wren <= 0; 171 | 172 | # 100; // This should be a miss and eviction 173 | 174 | d_cache_addr <= 32'h40000008; 175 | d_cache_din <= 0; 176 | d_cache_rden <= 1; 177 | d_cache_wren <= 0; 178 | 179 | # 100; // This should be a miss (evicted) 180 | 181 | d_cache_addr <= 32'h00000008; 182 | d_cache_din <= 0; 183 | d_cache_rden <= 1; 184 | d_cache_wren <= 0; 185 | 186 | # 100; // This should be a miss 187 | 188 | d_cache_addr <= 32'h10000008; 189 | d_cache_din <= 32'hBADDBEEF; 190 | d_cache_rden <= 0; 191 | d_cache_wren <= 1; 192 | 193 | // repeated reads (w/ offset) ///////////////////////////////////////////////////////////////////////////////////////////////////////// 194 | 195 | /*# 100; // This should be a miss 196 | 197 | d_cache_addr <= 32'h00000008; 198 | d_cache_din <= 0; 199 | d_cache_rden <= 1; 200 | d_cache_wren <= 0; 201 | 202 | # 100; // This should be a hit 203 | 204 | d_cache_addr <= 32'h0000000B; 205 | d_cache_din <= 32'hBADDBEEF; 206 | d_cache_rden <= 1; 207 | d_cache_wren <= 0; 208 | 209 | # 100; // This should be a hit 210 | 211 | d_cache_addr <= 32'h0000000C; 212 | d_cache_din <= 32'h00000000; 213 | d_cache_rden <= 1; 214 | d_cache_wren <= 0; 215 | 216 | # 100; // This should be a hit 217 | 218 | d_cache_addr <= 32'h0000000F; 219 | d_cache_din <= 32'hAAAAAAAA; 220 | d_cache_rden <= 1; 221 | d_cache_wren <= 0; */ 222 | 223 | #50; 224 | 225 | /*for (i = 0; i < DUT_MEM.DEPTH; i = i + 1) 226 | begin 227 | $display("%b", DUT_MEM.mem[i]); 228 | end*/ 229 | 230 | $finish; 231 | end 232 | 233 | initial 234 | begin 235 | //$monitor("time=%3d, addr=%1b, din=%1b, rden=%1b, wren=%1b, q=%1b, hit_miss=%1b", $time,d_cache_addr,d_cache_din,d_cache_rden,d_cache_wren,d_cache_q,d_cache_hit_miss); 236 | $monitor("time=%4d | addr=%10d | hm=%b | q=%08x | way1=%08h | way2=%08h | way3=%08h | way4=%08h | mem[1]=%08h | lru1=%d | lru2=%d | lru3=%d | lru4=%d" ,$time,d_cache_addr,d_cache_hit_miss,DUT_CACHE.q,DUT_CACHE.mem1[1],DUT_CACHE.mem2[1],DUT_CACHE.mem3[1],DUT_CACHE.mem4[1],DUT_MEM.mem[1],DUT_CACHE.lru1[1],DUT_CACHE.lru2[1],DUT_CACHE.lru3[1],DUT_CACHE.lru4[1]); 237 | end 238 | 239 | always 240 | begin 241 | clk = 1'b1; 242 | #5; 243 | clk = 1'b0; 244 | #5; 245 | end 246 | 247 | endmodule 248 | -------------------------------------------------------------------------------- /project_caches/d_cache_tb/d_mem_data.txt: -------------------------------------------------------------------------------- 1 | 0000000000000000 2 | 0123456789ABCDEF 3 | 0000000000000000 4 | 0000000000000001 5 | 0000000000000000 6 | 0000000000000001 7 | 0000000000000000 8 | 0000000000000001 9 | 0000000000000000 10 | 0000000000000001 11 | 0000000000000000 12 | 0000000000000001 13 | 0000000000000000 14 | 0000000000000001 15 | 0000000000000000 16 | 0000000000000001 17 | 0000000000000000 18 | 0000000000000001 19 | 0000000000000000 20 | 0000000000000001 21 | 0000000000000000 22 | 0000000000000001 23 | 0000000000000000 24 | 0000000000000001 25 | 0000000000000000 26 | 0000000000000001 27 | 0000000000000000 28 | 0000000000000001 29 | 0000000000000000 30 | 0000000000000001 31 | 0000000000000000 32 | 0000000000000001 33 | 0000000000000000 34 | 0000000000000001 35 | 0000000000000000 36 | 0000000000000001 37 | 0000000000000000 38 | 0000000000000001 39 | 0000000000000000 40 | 0000000000000001 41 | 0000000000000000 42 | 0000000000000001 43 | 0000000000000000 44 | 0000000000000001 45 | 0000000000000000 46 | 0000000000000001 47 | 0000000000000000 48 | 0000000000000001 49 | 0000000000000000 50 | 0000000000000001 51 | 0000000000000000 52 | 0000000000000001 53 | 0000000000000000 54 | 0000000000000001 55 | 0000000000000000 56 | 0000000000000001 57 | 0000000000000000 58 | 0000000000000001 59 | 0000000000000000 60 | 0000000000000001 61 | 0000000000000000 62 | 0000000000000001 63 | 0000000000000000 64 | 0000000000000001 65 | 0000000000000000 66 | 0000000000000001 67 | 0000000000000000 68 | 0000000000000001 69 | 0000000000000000 70 | 0000000000000001 71 | 0000000000000000 72 | 0000000000000001 73 | 0000000000000000 74 | 0000000000000001 75 | 0000000000000000 76 | 0000000000000001 77 | 0000000000000000 78 | 0000000000000001 79 | 0000000000000000 80 | 0000000000000001 81 | 0000000000000000 82 | 0000000000000001 83 | 0000000000000000 84 | 0000000000000001 85 | 0000000000000000 86 | 0000000000000001 87 | 0000000000000000 88 | 0000000000000001 89 | 0000000000000000 90 | 0000000000000001 91 | 0000000000000000 92 | 0000000000000001 93 | 0000000000000000 94 | 0000000000000001 95 | 0000000000000000 96 | 0000000000000001 97 | 0000000000000000 98 | 0000000000000001 99 | 0000000000000000 100 | 0000000000000001 101 | 0000000000000000 102 | 0000000000000001 103 | 0000000000000000 104 | 0000000000000001 105 | 0000000000000000 106 | 0000000000000001 107 | 0000000000000000 108 | 0000000000000001 109 | 0000000000000000 110 | 0000000000000001 111 | 0000000000000000 112 | 0000000000000001 113 | 0000000000000000 114 | 0000000000000001 115 | 0000000000000000 116 | 0000000000000001 117 | 0000000000000000 118 | 0000000000000001 119 | 0000000000000000 120 | 0000000000000001 121 | 0000000000000000 122 | 0000000000000001 123 | 0000000000000000 124 | 0000000000000001 125 | 0000000000000000 126 | 0000000000000001 127 | 0000000000000000 128 | 0000000000000001 129 | -------------------------------------------------------------------------------- /project_caches/hardware/dec_2_to_1.v: -------------------------------------------------------------------------------- 1 | module dec_2_to_1 2 | ( 3 | output wire out, 4 | input wire [1:0] in 5 | ); 6 | 7 | reg _out; 8 | assign out = _out; 9 | 10 | always @(*) begin 11 | case (in) 12 | 2'b01: _out = 1'b0; 13 | 2'b10: _out = 1'b1; 14 | default: _out = 1'bz; 15 | endcase 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /project_caches/hardware/dec_4_to_2.v: -------------------------------------------------------------------------------- 1 | module dec_4_to_2 2 | ( 3 | output wire [1:0] out, 4 | input wire [3:0] in 5 | ); 6 | 7 | reg [1:0] _out; 8 | assign out = _out; 9 | 10 | always @(*) begin 11 | case (in) 12 | 4'b0001: _out = 2'b00; 13 | 4'b0010: _out = 2'b01; 14 | 4'b0100: _out = 2'b10; 15 | 4'b1000: _out = 2'b11; 16 | default: _out = 2'bzz; 17 | endcase 18 | end 19 | 20 | endmodule -------------------------------------------------------------------------------- /project_caches/hardware/mux_2_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_2_to_1 2 | ( 3 | output wire [31:0] Y, 4 | input wire [31:0] A, B, 5 | input wire sel 6 | ); 7 | 8 | reg [31:0] _Y; 9 | assign Y = _Y; 10 | 11 | always @(*) begin 12 | case (sel) 13 | 1'b0: _Y = A; 14 | 1'b1: _Y = B; 15 | endcase 16 | end 17 | 18 | endmodule -------------------------------------------------------------------------------- /project_caches/hardware/mux_4_to_1.v: -------------------------------------------------------------------------------- 1 | module mux_4_to_1 2 | ( 3 | output wire [63:0] Y, 4 | input wire [63:0] A, B, C, D, 5 | input wire [1:0] sel 6 | ); 7 | 8 | reg [63:0] _Y; 9 | assign Y = _Y; 10 | 11 | always @(*) begin 12 | case (sel) 13 | 2'b00: _Y = A; 14 | 2'b01: _Y = B; 15 | 2'b10: _Y = C; 16 | 2'b11: _Y = D; 17 | endcase 18 | end 19 | 20 | endmodule -------------------------------------------------------------------------------- /project_caches/i_cache.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * 4 | * An instruction cache module 5 | * 6 | */ 7 | 8 | `define TAG 31:13 // position of tag in address 9 | `define INDEX 12:2 // position of index in address 10 | `define OFFSET 1:0 // position of offset in address 11 | 12 | module i_cache 13 | #( 14 | // Cache parameters 15 | parameter SIZE = 16*1024*8, 16 | parameter NWAYS = 2, 17 | parameter NSETS = 2048, 18 | parameter BLOCK_SIZE = 32, 19 | parameter WIDTH = 32, 20 | // Memory related paramter, make sure it matches memory module 21 | parameter MWIDTH = 32, // same as block size 22 | // More cache related parameters 23 | parameter INDEX_WIDTH = 11, 24 | parameter TAG_WIDTH = 19, 25 | parameter OFFSET_WIDTH = 2 26 | ) 27 | ( 28 | input wire clock, 29 | input wire [WIDTH-1:0] address, // address form CPU 30 | input wire [WIDTH-1:0] din, // data from CPU (if st inst) 31 | input wire rden, // 1 if ld instruction 32 | input wire wren, // 1 if st instruction 33 | output wire hit_miss, // 1 if hit, 0 while handling miss 34 | output wire [WIDTH-1:0] q, // data from cache to CPU 35 | output wire [MWIDTH-1:0] mdout, // data from cache to memory 36 | output wire [WIDTH-1:0] mrdaddress, // memory read address 37 | output wire mrden, // read enable, 1 if reading from memory 38 | output wire [WIDTH-1:0] mwraddress, // memory write address 39 | output wire mwren, // write enable, 1 if writing to memory 40 | input wire [MWIDTH-1:0] mq // data coming from memory 41 | ); 42 | 43 | /******************************************************************* 44 | * Global Parameters and Initializations 45 | *******************************************************************/ 46 | 47 | // WAY 1 cache data 48 | reg valid1 [0:NSETS-1]; 49 | reg dirty1 [0:NSETS-1]; 50 | reg lru1 [0:NSETS-1]; 51 | reg [TAG_WIDTH-1:0] tag1 [0:NSETS-1]; 52 | reg [MWIDTH-1:0] mem1 [0:NSETS-1] /* synthesis ramstyle = "M20K" */; 53 | 54 | // WAY 2 cache data 55 | reg valid2 [0:NSETS-1]; 56 | reg dirty2 [0:NSETS-1]; 57 | reg lru2 [0:NSETS-1]; 58 | reg [TAG_WIDTH-1:0] tag2 [0:NSETS-1]; 59 | reg [MWIDTH-1:0] mem2 [0:NSETS-1] /* synthesis ramstyle = "M20K" */; 60 | 61 | // initialize everything to 0 62 | integer k; 63 | initial 64 | begin 65 | for(k = 0; k < NSETS; k = k +1) 66 | begin 67 | valid1[k] = 0; 68 | valid2[k] = 0; 69 | dirty1[k] = 0; 70 | dirty2[k] = 0; 71 | lru1[k] = 0; 72 | lru2[k] = 0; 73 | end 74 | end 75 | 76 | // internal registers 77 | reg _hit_miss = 1'b0; 78 | reg [WIDTH-1:0] _q = {WIDTH{1'b0}}; 79 | reg [MWIDTH-1:0] _mdout = {MWIDTH{1'b0}}; 80 | reg [WIDTH-1:0] _mwraddress = {WIDTH{1'b0}}; 81 | reg _mwren = 1'b0; 82 | 83 | // output assignments of internal registers 84 | assign hit_miss = _hit_miss; 85 | assign mrden = !((valid1[address[`INDEX]] && (tag1[address[`INDEX]] == address[`TAG])) 86 | || (valid2[address[`INDEX]] && (tag2[address[`INDEX]] == address[`TAG]))); 87 | assign mwren = _mwren; 88 | assign mdout = _mdout; 89 | assign mrdaddress = {address[`TAG],address[`INDEX]}; 90 | assign mwraddress = _mwraddress; 91 | assign q = _q; 92 | 93 | // state parameters 94 | parameter idle = 1'b0; // receive requests from CPU 95 | parameter miss = 1'b1; // miss state: write back dirty block and request memory data 96 | 97 | // state register 98 | reg currentState = idle; 99 | 100 | /******************************************************************* 101 | * State Machine 102 | *******************************************************************/ 103 | 104 | always @(posedge clock) 105 | begin 106 | case (currentState) 107 | idle: begin 108 | // reset write enable, if it was turned on 109 | _mwren <= 0; 110 | // set _hit_miss register 111 | _hit_miss <= ((valid1[address[`INDEX]] && (tag1[address[`INDEX]] == address[`TAG])) 112 | || (valid2[address[`INDEX]] && (tag2[address[`INDEX]] == address[`TAG]))); 113 | 114 | // do nothing on null request 115 | if(~rden && ~wren) currentState <= idle; 116 | 117 | // check way 1 118 | else if(valid1[address[`INDEX]] && (tag1[address[`INDEX]] == address[`TAG])) 119 | begin 120 | // read hit 121 | if(rden) _q <= mem1[address[`INDEX]]; 122 | // write hit 123 | else if(wren) 124 | begin 125 | _q = {WIDTH{1'b0}}; 126 | mem1[address[`INDEX]] <= din; 127 | dirty1[address[`INDEX]] <= 1; 128 | end 129 | // update LRU data 130 | lru1[address[`INDEX]] <= 0; 131 | lru2[address[`INDEX]] <= 1; 132 | end 133 | 134 | // check way 2 135 | else if(valid2[address[`INDEX]] && (tag2[address[`INDEX]] == address[`TAG])) 136 | begin 137 | // read hit 138 | if(rden) _q <= mem2[address[`INDEX]]; 139 | // write hit 140 | else if(wren) 141 | begin 142 | _q = {WIDTH{1'b0}}; 143 | mem2[address[`INDEX]] <= din; 144 | dirty2[address[`INDEX]] <= 1; 145 | end 146 | // update LRU data 147 | lru1[address[`INDEX]] <= 1; 148 | lru2[address[`INDEX]] <= 0; 149 | end 150 | 151 | // miss 152 | else currentState <= miss; 153 | end 154 | 155 | miss: begin 156 | // one of the ways is invalid -- no need to evict 157 | if(~valid1[address[`INDEX]]) 158 | begin 159 | mem1[address[`INDEX]] <= mq; 160 | tag1[address[`INDEX]] <= address[`TAG]; 161 | dirty1[address[`INDEX]] <= 0; 162 | valid1[address[`INDEX]] <= 1; 163 | end 164 | 165 | else if(~valid2[address[`INDEX]]) 166 | begin 167 | mem2[address[`INDEX]] <= mq; 168 | tag2[address[`INDEX]] <= address[`TAG]; 169 | dirty2[address[`INDEX]] <= 0; 170 | valid2[address[`INDEX]] <= 1; 171 | end 172 | 173 | // way 1 is LRU 174 | else if(lru1[address[`INDEX]] == 1) 175 | begin 176 | // dirty block writeback 177 | if(dirty1[address[`INDEX]] == 1) 178 | begin 179 | _mwraddress <= {tag1[address[`INDEX]],address[`INDEX]}; 180 | _mwren <= 1; 181 | _mdout <= mem1[address[`INDEX]]; 182 | end 183 | mem1[address[`INDEX]] <= mq; 184 | tag1[address[`INDEX]] <= address[`TAG]; 185 | dirty1[address[`INDEX]] <= 0; 186 | valid1[address[`INDEX]] <= 1; 187 | end 188 | 189 | // way 2 is LRU 190 | else if(lru2[address[`INDEX]] == 1) 191 | begin 192 | // dirty block writeback 193 | if(dirty2[address[`INDEX]] == 1) 194 | begin 195 | _mwraddress <= {tag2[address[`INDEX]],address[`INDEX]}; 196 | _mwren <= 1; 197 | _mdout <= mem2[address[`INDEX]]; 198 | end 199 | mem2[address[`INDEX]] <= mq; 200 | tag2[address[`INDEX]] <= address[`TAG]; 201 | dirty2[address[`INDEX]] <= 0; 202 | valid2[address[`INDEX]] <= 1; 203 | end 204 | 205 | currentState <= idle; 206 | end 207 | 208 | default: currentState <= idle; 209 | 210 | endcase 211 | 212 | end 213 | 214 | endmodule 215 | -------------------------------------------------------------------------------- /project_caches/i_cache_tb/Makefile: -------------------------------------------------------------------------------- 1 | SHELL := /bin/bash 2 | 3 | all: run 4 | 5 | i_cache.vvp: ../i_cache.v ../clog2.v ../mem.v i_cache_tb.v 6 | @echo "Building..." 7 | iverilog -Wall -Wno-timescale -o i_cache.vvp ../i_cache.v ../clog2.v ../mem.v i_cache_tb.v 8 | @echo "Done building." 9 | 10 | run: i_cache.vvp 11 | @echo "Simulating..." 12 | @./i_cache.vvp 13 | @echo "Done simulating." 14 | 15 | clean: 16 | rm -f i_cache.vvp 17 | 18 | -------------------------------------------------------------------------------- /project_caches/i_cache_tb/i_cache.vvp: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "0.9.7 " "(v0_9_7)"; 3 | :vpi_time_precision - 12; 4 | :vpi_module "system"; 5 | :vpi_module "v2005_math"; 6 | :vpi_module "va_math"; 7 | S_0x1d44850 .scope module, "i_cache_test" "i_cache_test" 2 4; 8 | .timescale -9 -12; 9 | v0x1d68320_0 .var "clk", 0 0; 10 | v0x1d683a0_0 .net "data_in", 31 0, v0x1d66640_0; 1 drivers 11 | v0x1d686b0_0 .net "data_out", 31 0, v0x1d65ac0_0; 1 drivers 12 | v0x1d68780_0 .var "i_cache_addr", 31 0; 13 | v0x1d68800_0 .var "i_cache_din", 31 0; 14 | v0x1d68880_0 .net "i_cache_hit_miss", 0 0, v0x1d665a0_0; 1 drivers 15 | v0x1d68900_0 .net "i_cache_q", 31 0, v0x1d66800_0; 1 drivers 16 | v0x1d689b0_0 .var "i_cache_rden", 0 0; 17 | v0x1d68ab0_0 .var "i_cache_wren", 0 0; 18 | v0x1d68b60_0 .net "rd_addr", 31 0, L_0x1d6a1d0; 1 drivers 19 | v0x1d68c10_0 .net "rd_en", 0 0, L_0x1d69c90; 1 drivers 20 | v0x1d68c90_0 .net "wr_addr", 31 0, v0x1d666e0_0; 1 drivers 21 | v0x1d68d10_0 .net "wr_en", 0 0, v0x1d66780_0; 1 drivers 22 | L_0x1d6a510 .part L_0x1d6a1d0, 0, 7; 23 | L_0x1d6a5b0 .part v0x1d666e0_0, 0, 7; 24 | S_0x1d65e80 .scope module, "DUT_CACHE" "i_cache" 2 21, 3 12, S_0x1d44850; 25 | .timescale 0 0; 26 | P_0x1d65f78 .param/l "BLOCK_SIZE" 3 18, +C4<0100000>; 27 | P_0x1d65fa0 .param/l "INDEX_WIDTH" 3 23, +C4<01011>; 28 | P_0x1d65fc8 .param/l "MWIDTH" 3 21, +C4<0100000>; 29 | P_0x1d65ff0 .param/l "NSETS" 3 17, +C4<0100000000000>; 30 | P_0x1d66018 .param/l "NWAYS" 3 16, +C4<010>; 31 | P_0x1d66040 .param/l "OFFSET_WIDTH" 3 25, +C4<010>; 32 | P_0x1d66068 .param/l "SIZE" 3 15, +C4<0100000000000000000>; 33 | P_0x1d66090 .param/l "TAG_WIDTH" 3 24, +C4<010011>; 34 | P_0x1d660b8 .param/l "WIDTH" 3 19, +C4<0100000>; 35 | P_0x1d660e0 .param/l "idle" 3 94, C4<0>; 36 | P_0x1d66108 .param/l "miss" 3 95, C4<1>; 37 | L_0x1d69420 .functor AND 1, L_0x1d68e30, L_0x1d69300, C4<1>, C4<1>; 38 | L_0x1d69890 .functor AND 1, L_0x1d69520, L_0x1d69990, C4<1>, C4<1>; 39 | L_0x1d69b90 .functor OR 1, L_0x1d69420, L_0x1d69890, C4<0>, C4<0>; 40 | v0x1d665a0_0 .var "_hit_miss", 0 0; 41 | v0x1d66640_0 .var "_mdout", 31 0; 42 | v0x1d666e0_0 .var "_mwraddress", 31 0; 43 | v0x1d66780_0 .var "_mwren", 0 0; 44 | v0x1d66800_0 .var "_q", 31 0; 45 | v0x1d668a0_0 .net *"_s11", 18 0, L_0x1d691d0; 1 drivers 46 | v0x1d66980_0 .net *"_s12", 0 0, L_0x1d69300; 1 drivers 47 | v0x1d66a20_0 .net *"_s14", 0 0, L_0x1d69420; 1 drivers 48 | v0x1d66b10_0 .net *"_s16", 0 0, L_0x1d69520; 1 drivers 49 | v0x1d66bb0_0 .net *"_s19", 10 0, L_0x1d695c0; 1 drivers 50 | v0x1d66c50_0 .net *"_s2", 0 0, L_0x1d68e30; 1 drivers 51 | v0x1d66cf0_0 .net *"_s20", 18 0, L_0x1d69700; 1 drivers 52 | v0x1d66e00_0 .net *"_s23", 10 0, L_0x1d697a0; 1 drivers 53 | v0x1d66ea0_0 .net *"_s25", 18 0, L_0x1d698f0; 1 drivers 54 | v0x1d66fc0_0 .net *"_s26", 0 0, L_0x1d69990; 1 drivers 55 | v0x1d67060_0 .net *"_s28", 0 0, L_0x1d69890; 1 drivers 56 | v0x1d66f20_0 .net *"_s30", 0 0, L_0x1d69b90; 1 drivers 57 | v0x1d671b0_0 .net *"_s39", 18 0, L_0x1d69e40; 1 drivers 58 | v0x1d672d0_0 .net *"_s41", 10 0, L_0x1d69ff0; 1 drivers 59 | v0x1d67350_0 .net *"_s42", 29 0, L_0x1d6a090; 1 drivers 60 | v0x1d67230_0 .net *"_s47", 1 0, C4<00>; 1 drivers 61 | v0x1d67480_0 .net *"_s5", 10 0, L_0x1d68f00; 1 drivers 62 | v0x1d673d0_0 .net *"_s6", 18 0, L_0x1d69040; 1 drivers 63 | v0x1d675c0_0 .net *"_s9", 10 0, L_0x1d690e0; 1 drivers 64 | v0x1d67520_0 .net "address", 31 0, v0x1d68780_0; 1 drivers 65 | v0x1d67710_0 .net "clock", 0 0, v0x1d68320_0; 1 drivers 66 | v0x1d67640_0 .var "currentState", 0 0; 67 | v0x1d67870_0 .net "din", 31 0, v0x1d68800_0; 1 drivers 68 | v0x1d67790 .array "dirty1", 2047 0, 0 0; 69 | v0x1d679e0 .array "dirty2", 2047 0, 0 0; 70 | v0x1d678f0_0 .alias "hit_miss", 0 0, v0x1d68880_0; 71 | v0x1d67b60_0 .var/i "k", 31 0; 72 | v0x1d67a60 .array "lru1", 2047 0, 0 0; 73 | v0x1d67ae0 .array "lru2", 2047 0, 0 0; 74 | v0x1d67d00_0 .alias "mdout", 31 0, v0x1d683a0_0; 75 | v0x1d67d80 .array "mem1", 2047 0, 31 0; 76 | v0x1d67be0 .array "mem2", 2047 0, 31 0; 77 | v0x1d67c60_0 .alias "mq", 31 0, v0x1d686b0_0; 78 | v0x1d67f40_0 .alias "mrdaddress", 31 0, v0x1d68b60_0; 79 | v0x1d67fc0_0 .alias "mrden", 0 0, v0x1d68c10_0; 80 | v0x1d67e00_0 .alias "mwraddress", 31 0, v0x1d68c90_0; 81 | v0x1d67e80_0 .alias "mwren", 0 0, v0x1d68d10_0; 82 | v0x1d681a0_0 .alias "q", 31 0, v0x1d68900_0; 83 | v0x1d68220_0 .net "rden", 0 0, v0x1d689b0_0; 1 drivers 84 | v0x1d68040 .array "tag1", 2047 0, 18 0; 85 | v0x1d680c0 .array "tag2", 2047 0, 18 0; 86 | v0x1d68420 .array "valid1", 2047 0, 0 0; 87 | v0x1d684a0 .array "valid2", 2047 0, 0 0; 88 | v0x1d682a0_0 .net "wren", 0 0, v0x1d68ab0_0; 1 drivers 89 | L_0x1d68e30 .array/port v0x1d68420, L_0x1d68f00; 90 | L_0x1d68f00 .part v0x1d68780_0, 2, 11; 91 | L_0x1d69040 .array/port v0x1d68040, L_0x1d690e0; 92 | L_0x1d690e0 .part v0x1d68780_0, 2, 11; 93 | L_0x1d691d0 .part v0x1d68780_0, 13, 19; 94 | L_0x1d69300 .cmp/eq 19, L_0x1d69040, L_0x1d691d0; 95 | L_0x1d69520 .array/port v0x1d684a0, L_0x1d695c0; 96 | L_0x1d695c0 .part v0x1d68780_0, 2, 11; 97 | L_0x1d69700 .array/port v0x1d680c0, L_0x1d697a0; 98 | L_0x1d697a0 .part v0x1d68780_0, 2, 11; 99 | L_0x1d698f0 .part v0x1d68780_0, 13, 19; 100 | L_0x1d69990 .cmp/eq 19, L_0x1d69700, L_0x1d698f0; 101 | L_0x1d69c90 .reduce/nor L_0x1d69b90; 102 | L_0x1d69e40 .part v0x1d68780_0, 13, 19; 103 | L_0x1d69ff0 .part v0x1d68780_0, 2, 11; 104 | L_0x1d6a090 .concat [ 11 19 0 0], L_0x1d69ff0, L_0x1d69e40; 105 | L_0x1d6a1d0 .concat [ 30 2 0 0], L_0x1d6a090, C4<00>; 106 | S_0x1d12980 .scope module, "DUT_MEM" "mem" 2 44, 4 9, S_0x1d44850; 107 | .timescale 0 0; 108 | P_0x1d31be8 .param/l "DEPTH" 4 12, +C4<010000000>; 109 | P_0x1d31c10 .param/str "FILE" 4 13, "i_mem_data.txt"; 110 | P_0x1d31c38 .param/l "INIT" 4 14, +C4<0>; 111 | P_0x1d31c60 .param/l "WIDTH" 4 11, +C4<0100000>; 112 | v0x1d3a970_0 .alias "clock", 0 0, v0x1d67710_0; 113 | v0x1d659a0_0 .alias "data", 31 0, v0x1d683a0_0; 114 | v0x1d65a40 .array "mem", 127 0, 31 0; 115 | v0x1d65ac0_0 .var "q", 31 0; 116 | v0x1d65b70_0 .net "rdaddress", 6 0, L_0x1d6a510; 1 drivers 117 | v0x1d65c10_0 .alias "rden", 0 0, v0x1d68c10_0; 118 | v0x1d65cf0_0 .net "wraddress", 6 0, L_0x1d6a5b0; 1 drivers 119 | v0x1d65d90_0 .alias "wren", 0 0, v0x1d68d10_0; 120 | E_0x1d46070 .event posedge, v0x1d3a970_0; 121 | .scope S_0x1d65e80; 122 | T_0 ; 123 | %set/v v0x1d67b60_0, 0, 32; 124 | T_0.0 ; 125 | %load/v 8, v0x1d67b60_0, 32; 126 | %cmpi/s 8, 2048, 32; 127 | %jmp/0xz T_0.1, 5; 128 | %ix/getv/s 3, v0x1d67b60_0; 129 | %jmp/1 t_0, 4; 130 | %ix/load 1, 0, 0; 131 | %set/av v0x1d68420, 0, 1; 132 | t_0 ; 133 | %ix/getv/s 3, v0x1d67b60_0; 134 | %jmp/1 t_1, 4; 135 | %ix/load 1, 0, 0; 136 | %set/av v0x1d684a0, 0, 1; 137 | t_1 ; 138 | %ix/getv/s 3, v0x1d67b60_0; 139 | %jmp/1 t_2, 4; 140 | %ix/load 1, 0, 0; 141 | %set/av v0x1d67790, 0, 1; 142 | t_2 ; 143 | %ix/getv/s 3, v0x1d67b60_0; 144 | %jmp/1 t_3, 4; 145 | %ix/load 1, 0, 0; 146 | %set/av v0x1d679e0, 0, 1; 147 | t_3 ; 148 | %ix/getv/s 3, v0x1d67b60_0; 149 | %jmp/1 t_4, 4; 150 | %ix/load 1, 0, 0; 151 | %set/av v0x1d67a60, 0, 1; 152 | t_4 ; 153 | %ix/getv/s 3, v0x1d67b60_0; 154 | %jmp/1 t_5, 4; 155 | %ix/load 1, 0, 0; 156 | %set/av v0x1d67ae0, 0, 1; 157 | t_5 ; 158 | %ix/load 0, 1, 0; 159 | %load/vp0/s 8, v0x1d67b60_0, 32; 160 | %set/v v0x1d67b60_0, 8, 32; 161 | %jmp T_0.0; 162 | T_0.1 ; 163 | %end; 164 | .thread T_0; 165 | .scope S_0x1d65e80; 166 | T_1 ; 167 | %set/v v0x1d665a0_0, 0, 1; 168 | %end; 169 | .thread T_1; 170 | .scope S_0x1d65e80; 171 | T_2 ; 172 | %set/v v0x1d66800_0, 0, 32; 173 | %end; 174 | .thread T_2; 175 | .scope S_0x1d65e80; 176 | T_3 ; 177 | %set/v v0x1d66640_0, 0, 32; 178 | %end; 179 | .thread T_3; 180 | .scope S_0x1d65e80; 181 | T_4 ; 182 | %set/v v0x1d666e0_0, 0, 32; 183 | %end; 184 | .thread T_4; 185 | .scope S_0x1d65e80; 186 | T_5 ; 187 | %set/v v0x1d66780_0, 0, 1; 188 | %end; 189 | .thread T_5; 190 | .scope S_0x1d65e80; 191 | T_6 ; 192 | %set/v v0x1d67640_0, 0, 1; 193 | %end; 194 | .thread T_6; 195 | .scope S_0x1d65e80; 196 | T_7 ; 197 | %wait E_0x1d46070; 198 | %load/v 8, v0x1d67640_0, 1; 199 | %cmpi/u 8, 0, 1; 200 | %jmp/1 T_7.0, 6; 201 | %cmpi/u 8, 1, 1; 202 | %jmp/1 T_7.1, 6; 203 | %ix/load 0, 1, 0; 204 | %assign/v0 v0x1d67640_0, 0, 0; 205 | %jmp T_7.3; 206 | T_7.0 ; 207 | %ix/load 0, 1, 0; 208 | %assign/v0 v0x1d66780_0, 0, 0; 209 | %ix/load 1, 2, 0; 210 | %mov 4, 0, 1; 211 | %jmp/1 T_7.4, 4; 212 | %load/x1p 9, v0x1d67520_0, 11; 213 | %jmp T_7.5; 214 | T_7.4 ; 215 | %mov 9, 2, 11; 216 | T_7.5 ; 217 | ; Save base=9 wid=11 in lookaside. 218 | %ix/get 3, 9, 11; 219 | %load/av 8, v0x1d68420, 1; 220 | %ix/load 1, 2, 0; 221 | %mov 4, 0, 1; 222 | %jmp/1 T_7.6, 4; 223 | %load/x1p 28, v0x1d67520_0, 11; 224 | %jmp T_7.7; 225 | T_7.6 ; 226 | %mov 28, 2, 11; 227 | T_7.7 ; 228 | ; Save base=28 wid=11 in lookaside. 229 | %ix/get 3, 28, 11; 230 | %load/av 9, v0x1d68040, 19; 231 | %ix/load 1, 13, 0; 232 | %mov 4, 0, 1; 233 | %jmp/1 T_7.8, 4; 234 | %load/x1p 28, v0x1d67520_0, 19; 235 | %jmp T_7.9; 236 | T_7.8 ; 237 | %mov 28, 2, 19; 238 | T_7.9 ; 239 | ; Save base=28 wid=19 in lookaside. 240 | %cmp/u 9, 28, 19; 241 | %mov 9, 4, 1; 242 | %and 8, 9, 1; 243 | %ix/load 1, 2, 0; 244 | %mov 4, 0, 1; 245 | %jmp/1 T_7.10, 4; 246 | %load/x1p 10, v0x1d67520_0, 11; 247 | %jmp T_7.11; 248 | T_7.10 ; 249 | %mov 10, 2, 11; 250 | T_7.11 ; 251 | ; Save base=10 wid=11 in lookaside. 252 | %ix/get 3, 10, 11; 253 | %load/av 9, v0x1d684a0, 1; 254 | %ix/load 1, 2, 0; 255 | %mov 4, 0, 1; 256 | %jmp/1 T_7.12, 4; 257 | %load/x1p 29, v0x1d67520_0, 11; 258 | %jmp T_7.13; 259 | T_7.12 ; 260 | %mov 29, 2, 11; 261 | T_7.13 ; 262 | ; Save base=29 wid=11 in lookaside. 263 | %ix/get 3, 29, 11; 264 | %load/av 10, v0x1d680c0, 19; 265 | %ix/load 1, 13, 0; 266 | %mov 4, 0, 1; 267 | %jmp/1 T_7.14, 4; 268 | %load/x1p 29, v0x1d67520_0, 19; 269 | %jmp T_7.15; 270 | T_7.14 ; 271 | %mov 29, 2, 19; 272 | T_7.15 ; 273 | ; Save base=29 wid=19 in lookaside. 274 | %cmp/u 10, 29, 19; 275 | %mov 10, 4, 1; 276 | %and 9, 10, 1; 277 | %or 8, 9, 1; 278 | %ix/load 0, 1, 0; 279 | %assign/v0 v0x1d665a0_0, 0, 8; 280 | %load/v 8, v0x1d68220_0, 1; 281 | %inv 8, 1; 282 | %load/v 9, v0x1d682a0_0, 1; 283 | %inv 9, 1; 284 | %and 8, 9, 1; 285 | %jmp/0xz T_7.16, 8; 286 | %ix/load 0, 1, 0; 287 | %assign/v0 v0x1d67640_0, 0, 0; 288 | %jmp T_7.17; 289 | T_7.16 ; 290 | %ix/load 1, 2, 0; 291 | %mov 4, 0, 1; 292 | %jmp/1 T_7.18, 4; 293 | %load/x1p 9, v0x1d67520_0, 11; 294 | %jmp T_7.19; 295 | T_7.18 ; 296 | %mov 9, 2, 11; 297 | T_7.19 ; 298 | ; Save base=9 wid=11 in lookaside. 299 | %ix/get 3, 9, 11; 300 | %load/av 8, v0x1d68420, 1; 301 | %ix/load 1, 2, 0; 302 | %mov 4, 0, 1; 303 | %jmp/1 T_7.20, 4; 304 | %load/x1p 28, v0x1d67520_0, 11; 305 | %jmp T_7.21; 306 | T_7.20 ; 307 | %mov 28, 2, 11; 308 | T_7.21 ; 309 | ; Save base=28 wid=11 in lookaside. 310 | %ix/get 3, 28, 11; 311 | %load/av 9, v0x1d68040, 19; 312 | %ix/load 1, 13, 0; 313 | %mov 4, 0, 1; 314 | %jmp/1 T_7.22, 4; 315 | %load/x1p 28, v0x1d67520_0, 19; 316 | %jmp T_7.23; 317 | T_7.22 ; 318 | %mov 28, 2, 19; 319 | T_7.23 ; 320 | ; Save base=28 wid=19 in lookaside. 321 | %cmp/u 9, 28, 19; 322 | %mov 9, 4, 1; 323 | %and 8, 9, 1; 324 | %jmp/0xz T_7.24, 8; 325 | %load/v 8, v0x1d68220_0, 1; 326 | %jmp/0xz T_7.26, 8; 327 | %ix/load 1, 2, 0; 328 | %mov 4, 0, 1; 329 | %jmp/1 T_7.28, 4; 330 | %load/x1p 40, v0x1d67520_0, 11; 331 | %jmp T_7.29; 332 | T_7.28 ; 333 | %mov 40, 2, 11; 334 | T_7.29 ; 335 | ; Save base=40 wid=11 in lookaside. 336 | %ix/get 3, 40, 11; 337 | %load/av 8, v0x1d67d80, 32; 338 | %ix/load 0, 32, 0; 339 | %assign/v0 v0x1d66800_0, 0, 8; 340 | %jmp T_7.27; 341 | T_7.26 ; 342 | %load/v 8, v0x1d682a0_0, 1; 343 | %jmp/0xz T_7.30, 8; 344 | %set/v v0x1d66800_0, 0, 32; 345 | %load/v 8, v0x1d67870_0, 32; 346 | %ix/load 1, 2, 0; 347 | %mov 4, 0, 1; 348 | %jmp/1 T_7.32, 4; 349 | %load/x1p 40, v0x1d67520_0, 11; 350 | %jmp T_7.33; 351 | T_7.32 ; 352 | %mov 40, 2, 11; 353 | T_7.33 ; 354 | ; Save base=40 wid=11 in lookaside. 355 | %ix/get 3, 40, 11; 356 | %jmp/1 t_6, 4; 357 | %ix/load 0, 32, 0; word width 358 | %ix/load 1, 0, 0; part off 359 | %assign/av v0x1d67d80, 0, 8; 360 | t_6 ; 361 | %ix/load 1, 2, 0; 362 | %mov 4, 0, 1; 363 | %jmp/1 T_7.34, 4; 364 | %load/x1p 8, v0x1d67520_0, 11; 365 | %jmp T_7.35; 366 | T_7.34 ; 367 | %mov 8, 2, 11; 368 | T_7.35 ; 369 | ; Save base=8 wid=11 in lookaside. 370 | %ix/get 3, 8, 11; 371 | %jmp/1 t_7, 4; 372 | %ix/load 0, 1, 0; word width 373 | %ix/load 1, 0, 0; part off 374 | %assign/av v0x1d67790, 0, 1; 375 | t_7 ; 376 | T_7.30 ; 377 | T_7.27 ; 378 | %ix/load 1, 2, 0; 379 | %mov 4, 0, 1; 380 | %jmp/1 T_7.36, 4; 381 | %load/x1p 8, v0x1d67520_0, 11; 382 | %jmp T_7.37; 383 | T_7.36 ; 384 | %mov 8, 2, 11; 385 | T_7.37 ; 386 | ; Save base=8 wid=11 in lookaside. 387 | %ix/get 3, 8, 11; 388 | %jmp/1 t_8, 4; 389 | %ix/load 0, 1, 0; word width 390 | %ix/load 1, 0, 0; part off 391 | %assign/av v0x1d67a60, 0, 0; 392 | t_8 ; 393 | %ix/load 1, 2, 0; 394 | %mov 4, 0, 1; 395 | %jmp/1 T_7.38, 4; 396 | %load/x1p 8, v0x1d67520_0, 11; 397 | %jmp T_7.39; 398 | T_7.38 ; 399 | %mov 8, 2, 11; 400 | T_7.39 ; 401 | ; Save base=8 wid=11 in lookaside. 402 | %ix/get 3, 8, 11; 403 | %jmp/1 t_9, 4; 404 | %ix/load 0, 1, 0; word width 405 | %ix/load 1, 0, 0; part off 406 | %assign/av v0x1d67ae0, 0, 1; 407 | t_9 ; 408 | %jmp T_7.25; 409 | T_7.24 ; 410 | %ix/load 1, 2, 0; 411 | %mov 4, 0, 1; 412 | %jmp/1 T_7.40, 4; 413 | %load/x1p 9, v0x1d67520_0, 11; 414 | %jmp T_7.41; 415 | T_7.40 ; 416 | %mov 9, 2, 11; 417 | T_7.41 ; 418 | ; Save base=9 wid=11 in lookaside. 419 | %ix/get 3, 9, 11; 420 | %load/av 8, v0x1d684a0, 1; 421 | %ix/load 1, 2, 0; 422 | %mov 4, 0, 1; 423 | %jmp/1 T_7.42, 4; 424 | %load/x1p 28, v0x1d67520_0, 11; 425 | %jmp T_7.43; 426 | T_7.42 ; 427 | %mov 28, 2, 11; 428 | T_7.43 ; 429 | ; Save base=28 wid=11 in lookaside. 430 | %ix/get 3, 28, 11; 431 | %load/av 9, v0x1d680c0, 19; 432 | %ix/load 1, 13, 0; 433 | %mov 4, 0, 1; 434 | %jmp/1 T_7.44, 4; 435 | %load/x1p 28, v0x1d67520_0, 19; 436 | %jmp T_7.45; 437 | T_7.44 ; 438 | %mov 28, 2, 19; 439 | T_7.45 ; 440 | ; Save base=28 wid=19 in lookaside. 441 | %cmp/u 9, 28, 19; 442 | %mov 9, 4, 1; 443 | %and 8, 9, 1; 444 | %jmp/0xz T_7.46, 8; 445 | %load/v 8, v0x1d68220_0, 1; 446 | %jmp/0xz T_7.48, 8; 447 | %ix/load 1, 2, 0; 448 | %mov 4, 0, 1; 449 | %jmp/1 T_7.50, 4; 450 | %load/x1p 40, v0x1d67520_0, 11; 451 | %jmp T_7.51; 452 | T_7.50 ; 453 | %mov 40, 2, 11; 454 | T_7.51 ; 455 | ; Save base=40 wid=11 in lookaside. 456 | %ix/get 3, 40, 11; 457 | %load/av 8, v0x1d67be0, 32; 458 | %ix/load 0, 32, 0; 459 | %assign/v0 v0x1d66800_0, 0, 8; 460 | %jmp T_7.49; 461 | T_7.48 ; 462 | %load/v 8, v0x1d682a0_0, 1; 463 | %jmp/0xz T_7.52, 8; 464 | %set/v v0x1d66800_0, 0, 32; 465 | %load/v 8, v0x1d67870_0, 32; 466 | %ix/load 1, 2, 0; 467 | %mov 4, 0, 1; 468 | %jmp/1 T_7.54, 4; 469 | %load/x1p 40, v0x1d67520_0, 11; 470 | %jmp T_7.55; 471 | T_7.54 ; 472 | %mov 40, 2, 11; 473 | T_7.55 ; 474 | ; Save base=40 wid=11 in lookaside. 475 | %ix/get 3, 40, 11; 476 | %jmp/1 t_10, 4; 477 | %ix/load 0, 32, 0; word width 478 | %ix/load 1, 0, 0; part off 479 | %assign/av v0x1d67be0, 0, 8; 480 | t_10 ; 481 | %ix/load 1, 2, 0; 482 | %mov 4, 0, 1; 483 | %jmp/1 T_7.56, 4; 484 | %load/x1p 8, v0x1d67520_0, 11; 485 | %jmp T_7.57; 486 | T_7.56 ; 487 | %mov 8, 2, 11; 488 | T_7.57 ; 489 | ; Save base=8 wid=11 in lookaside. 490 | %ix/get 3, 8, 11; 491 | %jmp/1 t_11, 4; 492 | %ix/load 0, 1, 0; word width 493 | %ix/load 1, 0, 0; part off 494 | %assign/av v0x1d679e0, 0, 1; 495 | t_11 ; 496 | T_7.52 ; 497 | T_7.49 ; 498 | %ix/load 1, 2, 0; 499 | %mov 4, 0, 1; 500 | %jmp/1 T_7.58, 4; 501 | %load/x1p 8, v0x1d67520_0, 11; 502 | %jmp T_7.59; 503 | T_7.58 ; 504 | %mov 8, 2, 11; 505 | T_7.59 ; 506 | ; Save base=8 wid=11 in lookaside. 507 | %ix/get 3, 8, 11; 508 | %jmp/1 t_12, 4; 509 | %ix/load 0, 1, 0; word width 510 | %ix/load 1, 0, 0; part off 511 | %assign/av v0x1d67a60, 0, 1; 512 | t_12 ; 513 | %ix/load 1, 2, 0; 514 | %mov 4, 0, 1; 515 | %jmp/1 T_7.60, 4; 516 | %load/x1p 8, v0x1d67520_0, 11; 517 | %jmp T_7.61; 518 | T_7.60 ; 519 | %mov 8, 2, 11; 520 | T_7.61 ; 521 | ; Save base=8 wid=11 in lookaside. 522 | %ix/get 3, 8, 11; 523 | %jmp/1 t_13, 4; 524 | %ix/load 0, 1, 0; word width 525 | %ix/load 1, 0, 0; part off 526 | %assign/av v0x1d67ae0, 0, 0; 527 | t_13 ; 528 | %jmp T_7.47; 529 | T_7.46 ; 530 | %ix/load 0, 1, 0; 531 | %assign/v0 v0x1d67640_0, 0, 1; 532 | T_7.47 ; 533 | T_7.25 ; 534 | T_7.17 ; 535 | %jmp T_7.3; 536 | T_7.1 ; 537 | %ix/load 1, 2, 0; 538 | %mov 4, 0, 1; 539 | %jmp/1 T_7.62, 4; 540 | %load/x1p 9, v0x1d67520_0, 11; 541 | %jmp T_7.63; 542 | T_7.62 ; 543 | %mov 9, 2, 11; 544 | T_7.63 ; 545 | ; Save base=9 wid=11 in lookaside. 546 | %ix/get 3, 9, 11; 547 | %load/av 8, v0x1d68420, 1; 548 | %inv 8, 1; 549 | %jmp/0xz T_7.64, 8; 550 | %load/v 8, v0x1d67c60_0, 32; 551 | %ix/load 1, 2, 0; 552 | %mov 4, 0, 1; 553 | %jmp/1 T_7.66, 4; 554 | %load/x1p 40, v0x1d67520_0, 11; 555 | %jmp T_7.67; 556 | T_7.66 ; 557 | %mov 40, 2, 11; 558 | T_7.67 ; 559 | ; Save base=40 wid=11 in lookaside. 560 | %ix/get 3, 40, 11; 561 | %jmp/1 t_14, 4; 562 | %ix/load 0, 32, 0; word width 563 | %ix/load 1, 0, 0; part off 564 | %assign/av v0x1d67d80, 0, 8; 565 | t_14 ; 566 | %ix/load 1, 13, 0; 567 | %mov 4, 0, 1; 568 | %jmp/1 T_7.68, 4; 569 | %load/x1p 8, v0x1d67520_0, 19; 570 | %jmp T_7.69; 571 | T_7.68 ; 572 | %mov 8, 2, 19; 573 | T_7.69 ; 574 | ; Save base=8 wid=19 in lookaside. 575 | %ix/load 1, 2, 0; 576 | %mov 4, 0, 1; 577 | %jmp/1 T_7.70, 4; 578 | %load/x1p 27, v0x1d67520_0, 11; 579 | %jmp T_7.71; 580 | T_7.70 ; 581 | %mov 27, 2, 11; 582 | T_7.71 ; 583 | ; Save base=27 wid=11 in lookaside. 584 | %ix/get 3, 27, 11; 585 | %jmp/1 t_15, 4; 586 | %ix/load 0, 19, 0; word width 587 | %ix/load 1, 0, 0; part off 588 | %assign/av v0x1d68040, 0, 8; 589 | t_15 ; 590 | %ix/load 1, 2, 0; 591 | %mov 4, 0, 1; 592 | %jmp/1 T_7.72, 4; 593 | %load/x1p 8, v0x1d67520_0, 11; 594 | %jmp T_7.73; 595 | T_7.72 ; 596 | %mov 8, 2, 11; 597 | T_7.73 ; 598 | ; Save base=8 wid=11 in lookaside. 599 | %ix/get 3, 8, 11; 600 | %jmp/1 t_16, 4; 601 | %ix/load 0, 1, 0; word width 602 | %ix/load 1, 0, 0; part off 603 | %assign/av v0x1d67790, 0, 0; 604 | t_16 ; 605 | %ix/load 1, 2, 0; 606 | %mov 4, 0, 1; 607 | %jmp/1 T_7.74, 4; 608 | %load/x1p 8, v0x1d67520_0, 11; 609 | %jmp T_7.75; 610 | T_7.74 ; 611 | %mov 8, 2, 11; 612 | T_7.75 ; 613 | ; Save base=8 wid=11 in lookaside. 614 | %ix/get 3, 8, 11; 615 | %jmp/1 t_17, 4; 616 | %ix/load 0, 1, 0; word width 617 | %ix/load 1, 0, 0; part off 618 | %assign/av v0x1d68420, 0, 1; 619 | t_17 ; 620 | %jmp T_7.65; 621 | T_7.64 ; 622 | %ix/load 1, 2, 0; 623 | %mov 4, 0, 1; 624 | %jmp/1 T_7.76, 4; 625 | %load/x1p 9, v0x1d67520_0, 11; 626 | %jmp T_7.77; 627 | T_7.76 ; 628 | %mov 9, 2, 11; 629 | T_7.77 ; 630 | ; Save base=9 wid=11 in lookaside. 631 | %ix/get 3, 9, 11; 632 | %load/av 8, v0x1d684a0, 1; 633 | %inv 8, 1; 634 | %jmp/0xz T_7.78, 8; 635 | %load/v 8, v0x1d67c60_0, 32; 636 | %ix/load 1, 2, 0; 637 | %mov 4, 0, 1; 638 | %jmp/1 T_7.80, 4; 639 | %load/x1p 40, v0x1d67520_0, 11; 640 | %jmp T_7.81; 641 | T_7.80 ; 642 | %mov 40, 2, 11; 643 | T_7.81 ; 644 | ; Save base=40 wid=11 in lookaside. 645 | %ix/get 3, 40, 11; 646 | %jmp/1 t_18, 4; 647 | %ix/load 0, 32, 0; word width 648 | %ix/load 1, 0, 0; part off 649 | %assign/av v0x1d67be0, 0, 8; 650 | t_18 ; 651 | %ix/load 1, 13, 0; 652 | %mov 4, 0, 1; 653 | %jmp/1 T_7.82, 4; 654 | %load/x1p 8, v0x1d67520_0, 19; 655 | %jmp T_7.83; 656 | T_7.82 ; 657 | %mov 8, 2, 19; 658 | T_7.83 ; 659 | ; Save base=8 wid=19 in lookaside. 660 | %ix/load 1, 2, 0; 661 | %mov 4, 0, 1; 662 | %jmp/1 T_7.84, 4; 663 | %load/x1p 27, v0x1d67520_0, 11; 664 | %jmp T_7.85; 665 | T_7.84 ; 666 | %mov 27, 2, 11; 667 | T_7.85 ; 668 | ; Save base=27 wid=11 in lookaside. 669 | %ix/get 3, 27, 11; 670 | %jmp/1 t_19, 4; 671 | %ix/load 0, 19, 0; word width 672 | %ix/load 1, 0, 0; part off 673 | %assign/av v0x1d680c0, 0, 8; 674 | t_19 ; 675 | %ix/load 1, 2, 0; 676 | %mov 4, 0, 1; 677 | %jmp/1 T_7.86, 4; 678 | %load/x1p 8, v0x1d67520_0, 11; 679 | %jmp T_7.87; 680 | T_7.86 ; 681 | %mov 8, 2, 11; 682 | T_7.87 ; 683 | ; Save base=8 wid=11 in lookaside. 684 | %ix/get 3, 8, 11; 685 | %jmp/1 t_20, 4; 686 | %ix/load 0, 1, 0; word width 687 | %ix/load 1, 0, 0; part off 688 | %assign/av v0x1d679e0, 0, 0; 689 | t_20 ; 690 | %ix/load 1, 2, 0; 691 | %mov 4, 0, 1; 692 | %jmp/1 T_7.88, 4; 693 | %load/x1p 8, v0x1d67520_0, 11; 694 | %jmp T_7.89; 695 | T_7.88 ; 696 | %mov 8, 2, 11; 697 | T_7.89 ; 698 | ; Save base=8 wid=11 in lookaside. 699 | %ix/get 3, 8, 11; 700 | %jmp/1 t_21, 4; 701 | %ix/load 0, 1, 0; word width 702 | %ix/load 1, 0, 0; part off 703 | %assign/av v0x1d684a0, 0, 1; 704 | t_21 ; 705 | %jmp T_7.79; 706 | T_7.78 ; 707 | %ix/load 1, 2, 0; 708 | %mov 4, 0, 1; 709 | %jmp/1 T_7.90, 4; 710 | %load/x1p 11, v0x1d67520_0, 11; 711 | %jmp T_7.91; 712 | T_7.90 ; 713 | %mov 11, 2, 11; 714 | T_7.91 ; 715 | ; Save base=11 wid=11 in lookaside. 716 | %ix/get 3, 11, 11; 717 | %load/av 8, v0x1d67a60, 1; 718 | %mov 9, 0, 2; 719 | %cmpi/u 8, 1, 3; 720 | %jmp/0xz T_7.92, 4; 721 | %ix/load 1, 2, 0; 722 | %mov 4, 0, 1; 723 | %jmp/1 T_7.94, 4; 724 | %load/x1p 11, v0x1d67520_0, 11; 725 | %jmp T_7.95; 726 | T_7.94 ; 727 | %mov 11, 2, 11; 728 | T_7.95 ; 729 | ; Save base=11 wid=11 in lookaside. 730 | %ix/get 3, 11, 11; 731 | %load/av 8, v0x1d67790, 1; 732 | %mov 9, 0, 2; 733 | %cmpi/u 8, 1, 3; 734 | %jmp/0xz T_7.96, 4; 735 | %ix/load 1, 2, 0; 736 | %mov 4, 0, 1; 737 | %jmp/1 T_7.98, 4; 738 | %load/x1p 70, v0x1d67520_0, 11; 739 | %jmp T_7.99; 740 | T_7.98 ; 741 | %mov 70, 2, 11; 742 | T_7.99 ; 743 | %mov 40, 70, 11; Move signal select into place 744 | %ix/load 1, 2, 0; 745 | %mov 4, 0, 1; 746 | %jmp/1 T_7.100, 4; 747 | %load/x1p 70, v0x1d67520_0, 11; 748 | %jmp T_7.101; 749 | T_7.100 ; 750 | %mov 70, 2, 11; 751 | T_7.101 ; 752 | ; Save base=70 wid=11 in lookaside. 753 | %ix/get 3, 70, 11; 754 | %load/av 51, v0x1d68040, 19; 755 | %mov 8, 40, 30; 756 | %mov 38, 0, 2; 757 | %ix/load 0, 32, 0; 758 | %assign/v0 v0x1d666e0_0, 0, 8; 759 | %ix/load 0, 1, 0; 760 | %assign/v0 v0x1d66780_0, 0, 1; 761 | %ix/load 1, 2, 0; 762 | %mov 4, 0, 1; 763 | %jmp/1 T_7.102, 4; 764 | %load/x1p 40, v0x1d67520_0, 11; 765 | %jmp T_7.103; 766 | T_7.102 ; 767 | %mov 40, 2, 11; 768 | T_7.103 ; 769 | ; Save base=40 wid=11 in lookaside. 770 | %ix/get 3, 40, 11; 771 | %load/av 8, v0x1d67d80, 32; 772 | %ix/load 0, 32, 0; 773 | %assign/v0 v0x1d66640_0, 0, 8; 774 | T_7.96 ; 775 | %load/v 8, v0x1d67c60_0, 32; 776 | %ix/load 1, 2, 0; 777 | %mov 4, 0, 1; 778 | %jmp/1 T_7.104, 4; 779 | %load/x1p 40, v0x1d67520_0, 11; 780 | %jmp T_7.105; 781 | T_7.104 ; 782 | %mov 40, 2, 11; 783 | T_7.105 ; 784 | ; Save base=40 wid=11 in lookaside. 785 | %ix/get 3, 40, 11; 786 | %jmp/1 t_22, 4; 787 | %ix/load 0, 32, 0; word width 788 | %ix/load 1, 0, 0; part off 789 | %assign/av v0x1d67d80, 0, 8; 790 | t_22 ; 791 | %ix/load 1, 13, 0; 792 | %mov 4, 0, 1; 793 | %jmp/1 T_7.106, 4; 794 | %load/x1p 8, v0x1d67520_0, 19; 795 | %jmp T_7.107; 796 | T_7.106 ; 797 | %mov 8, 2, 19; 798 | T_7.107 ; 799 | ; Save base=8 wid=19 in lookaside. 800 | %ix/load 1, 2, 0; 801 | %mov 4, 0, 1; 802 | %jmp/1 T_7.108, 4; 803 | %load/x1p 27, v0x1d67520_0, 11; 804 | %jmp T_7.109; 805 | T_7.108 ; 806 | %mov 27, 2, 11; 807 | T_7.109 ; 808 | ; Save base=27 wid=11 in lookaside. 809 | %ix/get 3, 27, 11; 810 | %jmp/1 t_23, 4; 811 | %ix/load 0, 19, 0; word width 812 | %ix/load 1, 0, 0; part off 813 | %assign/av v0x1d68040, 0, 8; 814 | t_23 ; 815 | %ix/load 1, 2, 0; 816 | %mov 4, 0, 1; 817 | %jmp/1 T_7.110, 4; 818 | %load/x1p 8, v0x1d67520_0, 11; 819 | %jmp T_7.111; 820 | T_7.110 ; 821 | %mov 8, 2, 11; 822 | T_7.111 ; 823 | ; Save base=8 wid=11 in lookaside. 824 | %ix/get 3, 8, 11; 825 | %jmp/1 t_24, 4; 826 | %ix/load 0, 1, 0; word width 827 | %ix/load 1, 0, 0; part off 828 | %assign/av v0x1d67790, 0, 0; 829 | t_24 ; 830 | %ix/load 1, 2, 0; 831 | %mov 4, 0, 1; 832 | %jmp/1 T_7.112, 4; 833 | %load/x1p 8, v0x1d67520_0, 11; 834 | %jmp T_7.113; 835 | T_7.112 ; 836 | %mov 8, 2, 11; 837 | T_7.113 ; 838 | ; Save base=8 wid=11 in lookaside. 839 | %ix/get 3, 8, 11; 840 | %jmp/1 t_25, 4; 841 | %ix/load 0, 1, 0; word width 842 | %ix/load 1, 0, 0; part off 843 | %assign/av v0x1d68420, 0, 1; 844 | t_25 ; 845 | %jmp T_7.93; 846 | T_7.92 ; 847 | %ix/load 1, 2, 0; 848 | %mov 4, 0, 1; 849 | %jmp/1 T_7.114, 4; 850 | %load/x1p 11, v0x1d67520_0, 11; 851 | %jmp T_7.115; 852 | T_7.114 ; 853 | %mov 11, 2, 11; 854 | T_7.115 ; 855 | ; Save base=11 wid=11 in lookaside. 856 | %ix/get 3, 11, 11; 857 | %load/av 8, v0x1d67ae0, 1; 858 | %mov 9, 0, 2; 859 | %cmpi/u 8, 1, 3; 860 | %jmp/0xz T_7.116, 4; 861 | %ix/load 1, 2, 0; 862 | %mov 4, 0, 1; 863 | %jmp/1 T_7.118, 4; 864 | %load/x1p 11, v0x1d67520_0, 11; 865 | %jmp T_7.119; 866 | T_7.118 ; 867 | %mov 11, 2, 11; 868 | T_7.119 ; 869 | ; Save base=11 wid=11 in lookaside. 870 | %ix/get 3, 11, 11; 871 | %load/av 8, v0x1d679e0, 1; 872 | %mov 9, 0, 2; 873 | %cmpi/u 8, 1, 3; 874 | %jmp/0xz T_7.120, 4; 875 | %ix/load 1, 2, 0; 876 | %mov 4, 0, 1; 877 | %jmp/1 T_7.122, 4; 878 | %load/x1p 70, v0x1d67520_0, 11; 879 | %jmp T_7.123; 880 | T_7.122 ; 881 | %mov 70, 2, 11; 882 | T_7.123 ; 883 | %mov 40, 70, 11; Move signal select into place 884 | %ix/load 1, 2, 0; 885 | %mov 4, 0, 1; 886 | %jmp/1 T_7.124, 4; 887 | %load/x1p 70, v0x1d67520_0, 11; 888 | %jmp T_7.125; 889 | T_7.124 ; 890 | %mov 70, 2, 11; 891 | T_7.125 ; 892 | ; Save base=70 wid=11 in lookaside. 893 | %ix/get 3, 70, 11; 894 | %load/av 51, v0x1d680c0, 19; 895 | %mov 8, 40, 30; 896 | %mov 38, 0, 2; 897 | %ix/load 0, 32, 0; 898 | %assign/v0 v0x1d666e0_0, 0, 8; 899 | %ix/load 0, 1, 0; 900 | %assign/v0 v0x1d66780_0, 0, 1; 901 | %ix/load 1, 2, 0; 902 | %mov 4, 0, 1; 903 | %jmp/1 T_7.126, 4; 904 | %load/x1p 40, v0x1d67520_0, 11; 905 | %jmp T_7.127; 906 | T_7.126 ; 907 | %mov 40, 2, 11; 908 | T_7.127 ; 909 | ; Save base=40 wid=11 in lookaside. 910 | %ix/get 3, 40, 11; 911 | %load/av 8, v0x1d67be0, 32; 912 | %ix/load 0, 32, 0; 913 | %assign/v0 v0x1d66640_0, 0, 8; 914 | T_7.120 ; 915 | %load/v 8, v0x1d67c60_0, 32; 916 | %ix/load 1, 2, 0; 917 | %mov 4, 0, 1; 918 | %jmp/1 T_7.128, 4; 919 | %load/x1p 40, v0x1d67520_0, 11; 920 | %jmp T_7.129; 921 | T_7.128 ; 922 | %mov 40, 2, 11; 923 | T_7.129 ; 924 | ; Save base=40 wid=11 in lookaside. 925 | %ix/get 3, 40, 11; 926 | %jmp/1 t_26, 4; 927 | %ix/load 0, 32, 0; word width 928 | %ix/load 1, 0, 0; part off 929 | %assign/av v0x1d67be0, 0, 8; 930 | t_26 ; 931 | %ix/load 1, 13, 0; 932 | %mov 4, 0, 1; 933 | %jmp/1 T_7.130, 4; 934 | %load/x1p 8, v0x1d67520_0, 19; 935 | %jmp T_7.131; 936 | T_7.130 ; 937 | %mov 8, 2, 19; 938 | T_7.131 ; 939 | ; Save base=8 wid=19 in lookaside. 940 | %ix/load 1, 2, 0; 941 | %mov 4, 0, 1; 942 | %jmp/1 T_7.132, 4; 943 | %load/x1p 27, v0x1d67520_0, 11; 944 | %jmp T_7.133; 945 | T_7.132 ; 946 | %mov 27, 2, 11; 947 | T_7.133 ; 948 | ; Save base=27 wid=11 in lookaside. 949 | %ix/get 3, 27, 11; 950 | %jmp/1 t_27, 4; 951 | %ix/load 0, 19, 0; word width 952 | %ix/load 1, 0, 0; part off 953 | %assign/av v0x1d680c0, 0, 8; 954 | t_27 ; 955 | %ix/load 1, 2, 0; 956 | %mov 4, 0, 1; 957 | %jmp/1 T_7.134, 4; 958 | %load/x1p 8, v0x1d67520_0, 11; 959 | %jmp T_7.135; 960 | T_7.134 ; 961 | %mov 8, 2, 11; 962 | T_7.135 ; 963 | ; Save base=8 wid=11 in lookaside. 964 | %ix/get 3, 8, 11; 965 | %jmp/1 t_28, 4; 966 | %ix/load 0, 1, 0; word width 967 | %ix/load 1, 0, 0; part off 968 | %assign/av v0x1d679e0, 0, 0; 969 | t_28 ; 970 | %ix/load 1, 2, 0; 971 | %mov 4, 0, 1; 972 | %jmp/1 T_7.136, 4; 973 | %load/x1p 8, v0x1d67520_0, 11; 974 | %jmp T_7.137; 975 | T_7.136 ; 976 | %mov 8, 2, 11; 977 | T_7.137 ; 978 | ; Save base=8 wid=11 in lookaside. 979 | %ix/get 3, 8, 11; 980 | %jmp/1 t_29, 4; 981 | %ix/load 0, 1, 0; word width 982 | %ix/load 1, 0, 0; part off 983 | %assign/av v0x1d684a0, 0, 1; 984 | t_29 ; 985 | T_7.116 ; 986 | T_7.93 ; 987 | T_7.79 ; 988 | T_7.65 ; 989 | %ix/load 0, 1, 0; 990 | %assign/v0 v0x1d67640_0, 0, 0; 991 | %jmp T_7.3; 992 | T_7.3 ; 993 | %jmp T_7; 994 | .thread T_7; 995 | .scope S_0x1d12980; 996 | T_8 ; 997 | %vpi_call 4 37 "$readmemh", P_0x1d31c10, v0x1d65a40; 998 | %end; 999 | .thread T_8; 1000 | .scope S_0x1d12980; 1001 | T_9 ; 1002 | %wait E_0x1d46070; 1003 | %load/v 8, v0x1d65d90_0, 1; 1004 | %jmp/0xz T_9.0, 8; 1005 | %load/v 8, v0x1d659a0_0, 32; 1006 | %ix/getv 3, v0x1d65cf0_0; 1007 | %jmp/1 t_30, 4; 1008 | %ix/load 0, 32, 0; word width 1009 | %ix/load 1, 0, 0; part off 1010 | %assign/av v0x1d65a40, 0, 8; 1011 | t_30 ; 1012 | T_9.0 ; 1013 | %jmp T_9; 1014 | .thread T_9; 1015 | .scope S_0x1d12980; 1016 | T_10 ; 1017 | %wait E_0x1d46070; 1018 | %load/v 8, v0x1d65c10_0, 1; 1019 | %jmp/0xz T_10.0, 8; 1020 | %ix/getv 3, v0x1d65b70_0; 1021 | %load/av 8, v0x1d65a40, 32; 1022 | %ix/load 0, 32, 0; 1023 | %assign/v0 v0x1d65ac0_0, 0, 8; 1024 | T_10.0 ; 1025 | %jmp T_10; 1026 | .thread T_10; 1027 | .scope S_0x1d44850; 1028 | T_11 ; 1029 | %set/v v0x1d68780_0, 0, 32; 1030 | %end; 1031 | .thread T_11; 1032 | .scope S_0x1d44850; 1033 | T_12 ; 1034 | %set/v v0x1d68800_0, 0, 32; 1035 | %end; 1036 | .thread T_12; 1037 | .scope S_0x1d44850; 1038 | T_13 ; 1039 | %set/v v0x1d689b0_0, 0, 1; 1040 | %end; 1041 | .thread T_13; 1042 | .scope S_0x1d44850; 1043 | T_14 ; 1044 | %set/v v0x1d68ab0_0, 0, 1; 1045 | %end; 1046 | .thread T_14; 1047 | .scope S_0x1d44850; 1048 | T_15 ; 1049 | %delay 100000, 0; 1050 | %movi 8, 4, 32; 1051 | %ix/load 0, 32, 0; 1052 | %assign/v0 v0x1d68780_0, 0, 8; 1053 | %ix/load 0, 32, 0; 1054 | %assign/v0 v0x1d68800_0, 0, 0; 1055 | %ix/load 0, 1, 0; 1056 | %assign/v0 v0x1d689b0_0, 0, 1; 1057 | %ix/load 0, 1, 0; 1058 | %assign/v0 v0x1d68ab0_0, 0, 0; 1059 | %delay 100000, 0; 1060 | %movi 8, 268435460, 32; 1061 | %ix/load 0, 32, 0; 1062 | %assign/v0 v0x1d68780_0, 0, 8; 1063 | %ix/load 0, 32, 0; 1064 | %assign/v0 v0x1d68800_0, 0, 0; 1065 | %ix/load 0, 1, 0; 1066 | %assign/v0 v0x1d689b0_0, 0, 1; 1067 | %ix/load 0, 1, 0; 1068 | %assign/v0 v0x1d68ab0_0, 0, 0; 1069 | %delay 100000, 0; 1070 | %movi 8, 5, 32; 1071 | %ix/load 0, 32, 0; 1072 | %assign/v0 v0x1d68780_0, 0, 8; 1073 | %movi 8, 3135094511, 32; 1074 | %ix/load 0, 32, 0; 1075 | %assign/v0 v0x1d68800_0, 0, 8; 1076 | %ix/load 0, 1, 0; 1077 | %assign/v0 v0x1d689b0_0, 0, 1; 1078 | %ix/load 0, 1, 0; 1079 | %assign/v0 v0x1d68ab0_0, 0, 0; 1080 | %delay 100000, 0; 1081 | %movi 8, 268435462, 32; 1082 | %ix/load 0, 32, 0; 1083 | %assign/v0 v0x1d68780_0, 0, 8; 1084 | %ix/load 0, 32, 0; 1085 | %assign/v0 v0x1d68800_0, 0, 0; 1086 | %ix/load 0, 1, 0; 1087 | %assign/v0 v0x1d689b0_0, 0, 1; 1088 | %ix/load 0, 1, 0; 1089 | %assign/v0 v0x1d68ab0_0, 0, 0; 1090 | %delay 100000, 0; 1091 | %movi 8, 7, 32; 1092 | %ix/load 0, 32, 0; 1093 | %assign/v0 v0x1d68780_0, 0, 8; 1094 | %movi 8, 2863311530, 32; 1095 | %ix/load 0, 32, 0; 1096 | %assign/v0 v0x1d68800_0, 0, 8; 1097 | %ix/load 0, 1, 0; 1098 | %assign/v0 v0x1d689b0_0, 0, 1; 1099 | %ix/load 0, 1, 0; 1100 | %assign/v0 v0x1d68ab0_0, 0, 0; 1101 | %delay 50000, 0; 1102 | %vpi_call 2 202 "$finish"; 1103 | %jmp T_15; 1104 | .thread T_15; 1105 | .scope S_0x1d44850; 1106 | T_16 ; 1107 | %vpi_call 2 208 "$monitor", "time=%4d | addr=%10d | hm=%b | q=%08x | way1=%08h | way2=%08h | mem1=%08h | lru1=%d | lru2=%d", $time, v0x1d68780_0, v0x1d68880_0, v0x1d681a0_0, &A, &A, &A, &A, &A; 1108 | %end; 1109 | .thread T_16; 1110 | .scope S_0x1d44850; 1111 | T_17 ; 1112 | %set/v v0x1d68320_0, 1, 1; 1113 | %delay 5000, 0; 1114 | %set/v v0x1d68320_0, 0, 1; 1115 | %delay 5000, 0; 1116 | %jmp T_17; 1117 | .thread T_17; 1118 | # The file index is used to find the file name in the following table. 1119 | :file_names 5; 1120 | "N/A"; 1121 | ""; 1122 | "i_cache_tb.v"; 1123 | "../i_cache.v"; 1124 | "../mem.v"; 1125 | -------------------------------------------------------------------------------- /project_caches/i_cache_tb/i_cache_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ns / 1ps 3 | 4 | module i_cache_test; 5 | reg clk; 6 | 7 | wire [31:0] data_in; 8 | wire [31:0] data_out; 9 | wire [31:0] rd_addr; 10 | wire rd_en; 11 | wire [31:0] wr_addr; 12 | wire wr_en; 13 | 14 | reg [31:0] i_cache_addr = 0; 15 | reg [31:0] i_cache_din = 0; 16 | reg i_cache_rden = 0; 17 | reg i_cache_wren = 0; 18 | wire i_cache_hit_miss; 19 | wire [31:0] i_cache_q; 20 | 21 | i_cache DUT_CACHE ( 22 | .clock(clk), 23 | .address(i_cache_addr), 24 | .din(i_cache_din), 25 | .rden(i_cache_rden), 26 | .wren(i_cache_wren), 27 | .hit_miss(i_cache_hit_miss), 28 | .q(i_cache_q), 29 | .mdout(data_in), 30 | .mrdaddress(rd_addr), 31 | .mrden(rd_en), 32 | .mwraddress(wr_addr), 33 | .mwren(wr_en), 34 | .mq(data_out) 35 | ); 36 | 37 | defparam DUT_CACHE.SIZE = 16*1024*8; 38 | defparam DUT_CACHE.NWAYS = 2; 39 | defparam DUT_CACHE.NSETS = 2048; 40 | defparam DUT_CACHE.BLOCK_SIZE = 32; 41 | defparam DUT_CACHE.WIDTH = 32; 42 | defparam DUT_CACHE.MWIDTH = 32; 43 | 44 | mem DUT_MEM ( 45 | .clock(clk), 46 | .data(data_in), 47 | .rdaddress(rd_addr), 48 | .rden(rd_en), 49 | .wraddress(wr_addr), 50 | .wren(wr_en), 51 | .q(data_out) 52 | ); 53 | 54 | defparam DUT_MEM.WIDTH = 32; 55 | defparam DUT_MEM.DEPTH = 128; 56 | defparam DUT_MEM.FILE = "i_mem_data.txt"; 57 | 58 | integer i; 59 | 60 | always 61 | begin 62 | 63 | // basic writeback ///////////////////////////////////////////////////////////////////////////////////////////////////////// 64 | 65 | /*# 100; // This should be a miss 66 | 67 | i_cache_addr <= 32'h00000004; 68 | i_cache_din <= 0; 69 | i_cache_rden <= 1; 70 | i_cache_wren <= 0; 71 | 72 | # 100; // This should be a hit 73 | 74 | i_cache_addr <= 32'h00000004; 75 | i_cache_din <= 32'hBADDBEEF; 76 | i_cache_rden <= 0; 77 | i_cache_wren <= 1; 78 | 79 | # 100; // This should be a miss 80 | 81 | i_cache_addr <= 32'h10000004; 82 | i_cache_din <= 0; 83 | i_cache_rden <= 1; 84 | i_cache_wren <= 0; 85 | 86 | # 100; // This should be a miss 87 | 88 | i_cache_addr <= 32'h20000004; 89 | i_cache_din <= 0; 90 | i_cache_rden <= 1; 91 | i_cache_wren <= 0; 92 | 93 | # 100; // This should be a miss (evicted) 94 | 95 | i_cache_addr <= 32'h00000004; 96 | i_cache_din <= 0; 97 | i_cache_rden <= 1; 98 | i_cache_wren <= 0; 99 | 100 | # 100; // This should be a hit 101 | 102 | i_cache_addr <= 32'h20000004; 103 | i_cache_din <= 0; 104 | i_cache_rden <= 1; 105 | i_cache_wren <= 0;*/ 106 | 107 | // repeated writes (w/ offset) ///////////////////////////////////////////////////////////////////////////////////////////////////////// 108 | 109 | /*# 100; // This should be a miss 110 | 111 | i_cache_addr <= 32'h00000004; 112 | i_cache_din <= 0; 113 | i_cache_rden <= 1; 114 | i_cache_wren <= 0; 115 | 116 | # 100; // This should be a hit 117 | 118 | i_cache_addr <= 32'h00000004; 119 | i_cache_din <= 32'hBADDBEEF; 120 | i_cache_rden <= 0; 121 | i_cache_wren <= 1; 122 | 123 | # 100; // This should be a hit 124 | 125 | i_cache_addr <= 32'h00000006; 126 | i_cache_din <= 32'h00000000; 127 | i_cache_rden <= 0; 128 | i_cache_wren <= 1; 129 | 130 | # 100; // This should be a miss 131 | 132 | i_cache_addr <= 32'h10000004; 133 | i_cache_din <= 0; 134 | i_cache_rden <= 1; 135 | i_cache_wren <= 0; 136 | 137 | # 100; // This should be a miss 138 | 139 | i_cache_addr <= 32'h20000004; 140 | i_cache_din <= 0; 141 | i_cache_rden <= 1; 142 | i_cache_wren <= 0; 143 | 144 | # 100; // This should be a miss (evicted) 145 | 146 | i_cache_addr <= 32'h00000004; 147 | i_cache_din <= 0; 148 | i_cache_rden <= 1; 149 | i_cache_wren <= 0; 150 | 151 | # 100; // This should be a hit 152 | 153 | i_cache_addr <= 32'h20000004; 154 | i_cache_din <= 0; 155 | i_cache_rden <= 1; 156 | i_cache_wren <= 0;*/ 157 | 158 | // repeated reads (w/ offset) ///////////////////////////////////////////////////////////////////////////////////////////////////////// 159 | 160 | # 100; // This should be a miss 161 | 162 | i_cache_addr <= 32'h00000004; 163 | i_cache_din <= 0; 164 | i_cache_rden <= 1; 165 | i_cache_wren <= 0; 166 | 167 | # 100; // This should be a miss 168 | 169 | i_cache_addr <= 32'h10000004; 170 | i_cache_din <= 0; 171 | i_cache_rden <= 1; 172 | i_cache_wren <= 0; 173 | 174 | # 100; // This should be a hit 175 | 176 | i_cache_addr <= 32'h00000005; 177 | i_cache_din <= 32'hBADDBEEF; 178 | i_cache_rden <= 1; 179 | i_cache_wren <= 0; 180 | 181 | # 100; // This should be a hit 182 | 183 | i_cache_addr <= 32'h10000006; 184 | i_cache_din <= 32'h00000000; 185 | i_cache_rden <= 1; 186 | i_cache_wren <= 0; 187 | 188 | # 100; // This should be a hit 189 | 190 | i_cache_addr <= 32'h00000007; 191 | i_cache_din <= 32'hAAAAAAAA; 192 | i_cache_rden <= 1; 193 | i_cache_wren <= 0; 194 | 195 | #50; 196 | 197 | /*for (i = 0; i < DUT_MEM.DEPTH; i = i + 1) 198 | begin 199 | $display("%b", DUT_MEM.mem[i]); 200 | end*/ 201 | 202 | $finish; 203 | end 204 | 205 | initial 206 | begin 207 | //$monitor("time=%3d, addr=%1b, din=%1b, rden=%1b, wren=%1b, q=%1b, hit_miss=%1b", $time,i_cache_addr,i_cache_din,i_cache_rden,i_cache_wren,i_cache_q,i_cache_hit_miss); 208 | $monitor("time=%4d | addr=%10d | hm=%b | q=%08x | way1=%08h | way2=%08h | mem1=%08h | lru1=%d | lru2=%d" ,$time,i_cache_addr,i_cache_hit_miss,DUT_CACHE.q,DUT_CACHE.mem1[1],DUT_CACHE.mem2[1],DUT_MEM.mem[1],DUT_CACHE.lru1[1],DUT_CACHE.lru2[1]); 209 | end 210 | 211 | always 212 | begin 213 | clk = 1'b1; 214 | #5; 215 | clk = 1'b0; 216 | #5; 217 | end 218 | 219 | endmodule 220 | -------------------------------------------------------------------------------- /project_caches/i_cache_tb/i_mem_data.txt: -------------------------------------------------------------------------------- 1 | 00000000 2 | 12345678 3 | 00000000 4 | 00000001 5 | 00000000 6 | 00000001 7 | 00000000 8 | 00000001 9 | 00000000 10 | 00000001 11 | 00000000 12 | 00000001 13 | 00000000 14 | 00000001 15 | 00000000 16 | 00000001 17 | 00000000 18 | 00000001 19 | 00000000 20 | 00000001 21 | 00000000 22 | 00000001 23 | 00000000 24 | 00000001 25 | 00000000 26 | 00000001 27 | 00000000 28 | 00000001 29 | 00000000 30 | 00000001 31 | 00000000 32 | 00000001 33 | 00000000 34 | 00000001 35 | 00000000 36 | 00000001 37 | 00000000 38 | 00000001 39 | 00000000 40 | 00000001 41 | 00000000 42 | 00000001 43 | 00000000 44 | 00000001 45 | 00000000 46 | 00000001 47 | 00000000 48 | 00000001 49 | 00000000 50 | 00000001 51 | 00000000 52 | 00000001 53 | 00000000 54 | 00000001 55 | 00000000 56 | 00000001 57 | 00000000 58 | 00000001 59 | 00000000 60 | 00000001 61 | 00000000 62 | 00000001 63 | 00000000 64 | 00000001 65 | 00000000 66 | 00000001 67 | 00000000 68 | 00000001 69 | 00000000 70 | 00000001 71 | 00000000 72 | 00000001 73 | 00000000 74 | 00000001 75 | 00000000 76 | 00000001 77 | 00000000 78 | 00000001 79 | 00000000 80 | 00000001 81 | 00000000 82 | 00000001 83 | 00000000 84 | 00000001 85 | 00000000 86 | 00000001 87 | 00000000 88 | 00000001 89 | 00000000 90 | 00000001 91 | 00000000 92 | 00000001 93 | 00000000 94 | 00000001 95 | 00000000 96 | 00000001 97 | 00000000 98 | 00000001 99 | 00000000 100 | 00000001 101 | 00000000 102 | 00000001 103 | 00000000 104 | 00000001 105 | 00000000 106 | 00000001 107 | 00000000 108 | 00000001 109 | 00000000 110 | 00000001 111 | 00000000 112 | 00000001 113 | 00000000 114 | 00000001 115 | 00000000 116 | 00000001 117 | 00000000 118 | 00000001 119 | 00000000 120 | 00000001 121 | 00000000 122 | 00000001 123 | 00000000 124 | 00000001 125 | 00000000 126 | 00000001 127 | 00000000 128 | 00000001 129 | -------------------------------------------------------------------------------- /project_caches/mem.v: -------------------------------------------------------------------------------- 1 | 2 | /* 3 | * Single-ported memory module. 4 | * 5 | * Public domain. 6 | * 7 | */ 8 | 9 | module mem 10 | #( 11 | parameter WIDTH = 8, 12 | parameter DEPTH = 64, 13 | parameter FILE = "", 14 | parameter INIT = 0 15 | ) 16 | ( 17 | input wire clock, 18 | input wire [WIDTH-1:0] data, 19 | input wire [`CLOG2(DEPTH)-1:0] rdaddress, 20 | input wire rden, 21 | input wire [`CLOG2(DEPTH)-1:0] wraddress, 22 | input wire wren, 23 | output reg [WIDTH-1:0] q 24 | ); 25 | 26 | reg [WIDTH-1:0] mem [0:DEPTH-1] /* synthesis ramstyle = "M20K" */; 27 | 28 | integer file; 29 | integer scan; 30 | integer i; 31 | 32 | initial 33 | begin 34 | // read file contents if FILE is given 35 | if (FILE != "") 36 | // If you get error here, check path to FILE 37 | $readmemh(FILE, mem); 38 | 39 | // set all data to 0 if INIT is true 40 | if (INIT) 41 | for (i = 0; i < DEPTH; i = i + 1) 42 | mem[i] = {WIDTH{1'b0}}; 43 | end 44 | 45 | always @ (posedge clock) 46 | begin 47 | if (wren) 48 | mem[wraddress] <= data; 49 | end 50 | 51 | always @ (posedge clock) 52 | begin 53 | if (rden) 54 | q <= mem[rdaddress]; 55 | end 56 | 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /project_caches/old/notes.txt: -------------------------------------------------------------------------------- 1 | iCache: 2 | 3 | address inputs: 4 | 19 tag bits 5 | 11 index bits 6 | 2 offset bits 7 | 8 | cache line: 9 | 1 LRU bit 10 | 1 valid bit 11 | 1 dirty bit 12 | 18 tag bits 13 | 32 data bits 14 | 15 | dCache: 16 | 17 | address inputs: 18 | 19 tag bits 19 | 10 index bits 20 | 3 offset bits 21 | 22 | cache line: 23 | 2 LRU bits 24 | 1 valid bit 25 | 1 dirty bit 26 | 19 tag bits 27 | 64 data bits -------------------------------------------------------------------------------- /project_caches/report_part_A.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zebmehring/Processor-Cache/898f61b0a6eb9db44bf947c09baacdcad66799b8/project_caches/report_part_A.pdf --------------------------------------------------------------------------------