├── .clang-format ├── .flake8 ├── .github ├── dependabot.yml └── workflows │ ├── documentation.yml │ ├── lint.yml │ ├── regression.yml │ └── wheels.yml ├── .gitignore ├── .gitmodules ├── CODE_OF_CONDUCT.md ├── CONTRIBUTING.md ├── LICENSE ├── MANIFEST.in ├── README.md ├── Rules.mk ├── SECURITY.md ├── docs ├── Makefile ├── make.bat └── source │ ├── conf.py │ ├── index.rst │ ├── switchboard.bitvector.rst │ ├── switchboard.icarus.rst │ ├── switchboard.loopback.rst │ ├── switchboard.rst │ ├── switchboard.sbdut.rst │ ├── switchboard.sbtcp.rst │ ├── switchboard.uart_xactor.rst │ ├── switchboard.umi.rst │ ├── switchboard.util.rst │ └── switchboard.verilator.rst ├── examples ├── README.md ├── args │ ├── Makefile │ ├── test.py │ └── testbench.sv ├── axi │ ├── Makefile │ ├── README.md │ └── test.py ├── axil │ ├── Makefile │ ├── README.md │ └── test.py ├── axil_ram │ ├── Makefile │ ├── README.md │ ├── test.py │ └── testbench.sv ├── clean.sh ├── common │ ├── verilator │ │ ├── config.vlt │ │ └── testbench.cc │ └── verilog │ │ ├── sb_loopback.v │ │ ├── umiparam.sv │ │ └── umiram.sv ├── fpga_loopback │ ├── Makefile │ ├── README.md │ ├── test.py │ ├── testbench.cc │ └── testbench.sv ├── minimal │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── client.cc │ ├── test.py │ └── testbench.sv ├── network-fifo-chain │ ├── Makefile │ └── test.py ├── network │ ├── Makefile │ ├── README.md │ └── test.py ├── pcie_ping │ ├── .gitignore │ ├── Makefile │ ├── README.md │ └── pcie-ping.cc ├── python │ ├── Makefile │ ├── README.md │ ├── test.py │ └── testbench.sv ├── requirements.txt ├── router │ ├── .gitignore │ ├── Makefile │ ├── client.cc │ ├── test.py │ └── testbench.sv ├── stream │ ├── .gitignore │ ├── Makefile │ ├── client.cc │ └── test.py ├── tcp-fifo-chain │ ├── Makefile │ └── test.py ├── tcp │ ├── Makefile │ ├── README.md │ ├── fifos │ │ └── fifos.py │ ├── ram │ │ └── ram.py │ └── test.py ├── test_bit_vector.py ├── test_examples.py ├── umi_endpoint │ ├── Makefile │ ├── README.md │ ├── test.py │ └── testbench.sv ├── umi_fifo │ ├── Makefile │ ├── README.md │ └── test.py ├── umi_fifo_flex │ ├── Makefile │ ├── README.md │ └── test.py ├── umi_gpio │ ├── Makefile │ ├── README.md │ ├── funcs.v │ └── test.py ├── umi_mem_cpp │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── test.py │ ├── umi_mem.cc │ └── util.py ├── umi_splitter │ ├── Makefile │ ├── README.md │ └── test.py ├── umiparam-network │ ├── Makefile │ └── test.py ├── umiparam │ ├── Makefile │ └── test.py ├── umiram │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── __init__.py │ ├── client.cc │ ├── test.py │ ├── testbench.sv │ └── umiram.py └── xyce │ ├── Makefile │ ├── README.md │ ├── mycircuit.cir │ ├── test.py │ └── testbench.sv ├── pyproject.toml ├── pytest.ini ├── python └── switchboard_pybind.cc ├── random └── mkqueues.py ├── requirements.txt ├── setup.py ├── switchboard ├── __init__.py ├── ams.py ├── apb.py ├── autowrap.py ├── axi.py ├── axil.py ├── bitvector.py ├── cmdline.py ├── cpp │ ├── .gitignore │ ├── Makefile │ ├── bitutil.h │ ├── pagemap.h │ ├── pciedev.h │ ├── router.cc │ ├── spsc_queue.h │ ├── switchboard.hpp │ ├── switchboard_pcie.hpp │ ├── switchboard_tlm.hpp │ ├── umilib.h │ ├── umilib.hpp │ ├── umisb.hpp │ └── xyce.hpp ├── deps │ ├── __init__.py │ └── verilog_axi.py ├── dpi │ ├── __init__.py │ ├── switchboard_dpi.cc │ ├── switchboard_dpi.py │ └── xyce_dpi.cc ├── gpio.py ├── icarus.py ├── loopback.py ├── network.py ├── pytest_plugin.py ├── sbdesign.py ├── sbdut.py ├── sbtcp.py ├── sc │ ├── __init__.py │ ├── morty │ │ ├── __init__.py │ │ └── uniquify.py │ ├── sed │ │ ├── __init__.py │ │ └── sed_remove.py │ └── standalone_netlist_flow.py ├── switchboard.py ├── test_util.py ├── uart_xactor.py ├── umi.py ├── util.py ├── verilator │ ├── __init__.py │ ├── config.vlt │ ├── testbench.cc │ └── verilator.py ├── verilator_run.py ├── verilog │ ├── __init__.py │ ├── common │ │ ├── __init__.py │ │ ├── common.py │ │ ├── switchboard.vh │ │ ├── uart_xactor.sv │ │ └── umi_gpio.v │ ├── fpga │ │ ├── README.md │ │ ├── __init__.py │ │ ├── axi_reader.sv │ │ ├── axi_writer.sv │ │ ├── config_registers.sv │ │ ├── fpga.py │ │ ├── include │ │ │ ├── sb_queue_regmap.vh │ │ │ └── spsc_queue.vh │ │ ├── memory_fault.sv │ │ ├── sb_fpga_queues.sv │ │ ├── sb_rx_fpga.sv │ │ ├── sb_tx_fpga.sv │ │ └── umi_fpga_queues.sv │ └── sim │ │ ├── __init__.py │ │ ├── auto_stop_sim.sv │ │ ├── perf_meas_sim.sv │ │ ├── queue_to_sb_sim.sv │ │ ├── queue_to_umi_sim.sv │ │ ├── sb_apb_m.sv │ │ ├── sb_axi_m.sv │ │ ├── sb_axil_m.sv │ │ ├── sb_axil_s.sv │ │ ├── sb_clk_gen.sv │ │ ├── sb_jtag_rbb_sim.sv │ │ ├── sb_rx_sim.sv │ │ ├── sb_to_queue_sim.sv │ │ ├── sb_tx_sim.sv │ │ ├── switchboard_sim.py │ │ ├── umi_rx_sim.sv │ │ ├── umi_to_queue_sim.sv │ │ ├── umi_tx_sim.sv │ │ └── xyce_intf.sv ├── vpi │ ├── switchboard_vpi.cc │ └── xyce_vpi.cc ├── warn.py └── xyce.py ├── tests ├── Makefile ├── bandwidth.cc ├── hello.cc ├── latency.cc ├── test.py └── torture.c └── verible_lint.txt /.clang-format: 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