├── assets ├── DataMemory.asm ├── readme │ ├── debugger.jpg │ ├── schematic.png │ ├── organization.png │ ├── code-generation.png │ └── debugger-design.png ├── generate-debug-registers.sh ├── InstructionMemory.asm ├── debugger-input.txt ├── debugger-design.txt ├── generate-stage-instantiation.py ├── generate-pipeline-registers.py ├── generate-debugger.py └── Font.coe ├── ipcore_dir ├── .gitignore ├── InstructionMemory.coe ├── DataMemory.coe ├── Font.xco ├── Background.xco ├── DataMemory.xco ├── InstructionMemory.xco ├── Font.xise ├── Background.xise ├── DataMemory.xise ├── InstructionMemory.xise ├── Background.coe └── Font.coe ├── .gitignore ├── BooleanTextConverter.v ├── HexCharacterConverter.v ├── ClockDivider.v ├── Anti_jitter.v ├── WbStage.v ├── Pc.v ├── MemStage.v ├── IfStage.v ├── IfIdRegisters.v ├── Alu.v ├── ExStage.v ├── MemWbRegisters.v ├── Terminal.v ├── VgaController.v ├── RegisterFile.v ├── ExMemRegisters.v ├── CpuTest.v ├── README.md ├── IdExRegisters.v ├── archexp.v ├── IdStage.v ├── Disassembler.v ├── ControlUnit.v ├── Cpu.v ├── Debugger.v ├── nexys3.ucf └── LICENSE.md /assets/DataMemory.asm: -------------------------------------------------------------------------------- 1 | .data 80 2 | .word 1 3 | .word 4 4 | -------------------------------------------------------------------------------- /ipcore_dir/.gitignore: -------------------------------------------------------------------------------- 1 | /* 2 | !/.gitignore 3 | !/*.coe 4 | !/*.xco 5 | !/*.xise 6 | -------------------------------------------------------------------------------- /assets/readme/debugger.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhanghai/archexp/HEAD/assets/readme/debugger.jpg -------------------------------------------------------------------------------- /assets/readme/schematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhanghai/archexp/HEAD/assets/readme/schematic.png -------------------------------------------------------------------------------- /assets/readme/organization.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhanghai/archexp/HEAD/assets/readme/organization.png -------------------------------------------------------------------------------- /assets/readme/code-generation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhanghai/archexp/HEAD/assets/readme/code-generation.png -------------------------------------------------------------------------------- /assets/readme/debugger-design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhanghai/archexp/HEAD/assets/readme/debugger-design.png -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /* 2 | !/.gitignore 3 | !/assets/ 4 | !/ipcore_dir/ 5 | !/*.md 6 | !/*.ngc 7 | /archexp.ngc 8 | !/*.sch 9 | !/*.sym 10 | !/*.ucf 11 | !/*.v 12 | !/*.xise 13 | -------------------------------------------------------------------------------- /BooleanTextConverter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module BooleanTextConverter ( 4 | input boolean, 5 | output [5 * 8 - 1 : 0] text 6 | ); 7 | 8 | assign text = boolean ? "True " : "False"; 9 | endmodule 10 | -------------------------------------------------------------------------------- /HexCharacterConverter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module HexCharacterConverter ( 4 | input [3:0] hex, 5 | output [7:0] character 6 | ); 7 | 8 | assign character = hex < 4'd10 ? hex + "0" : hex - 4'd10 + "A"; 9 | endmodule 10 | -------------------------------------------------------------------------------- /assets/generate-debug-registers.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | for i in `seq 0 31`; do 3 | echo "wire [31:0] cpu_id_register${i} = cpu_id_registers[$((${i} + 1)) * 32 - 1 : ${i} * 32];" 4 | done 5 | echo 6 | for i in `seq 0 31`; do 7 | echo "cpu_id_register${i}" 8 | done 9 | -------------------------------------------------------------------------------- /ipcore_dir/InstructionMemory.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 8C010054, 00211020, 00221822, 10210003, 00000000, 30440000, 20850001, 34660000, 4 | 14C30003, 00000000, 8C070050, AC070054, 20E80001, 08000000, 00000000, 31090001; 5 | -------------------------------------------------------------------------------- /ipcore_dir/DataMemory.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 00000000, 00000000, 00000000, 00000000, 00000000, 00000000, 00000000, 00000000, 4 | 00000000, 00000000, 00000000, 00000000, 00000000, 00000000, 00000000, 00000000, 5 | 00000000, 00000000, 00000000, 00000000, 00000001, 00000004; 6 | -------------------------------------------------------------------------------- /assets/InstructionMemory.asm: -------------------------------------------------------------------------------- 1 | label_0: 2 | lw $1, 84($0) 3 | add $2, $1, $1 4 | sub $3, $1, $2 5 | beq $1, $1, label_1 6 | andi $4, $2, 0 7 | addi $5, $4, 1 8 | label_1: 9 | ori $6, $3, 0 10 | bne $6, $3, label_2 11 | lw $7, 80($0) 12 | sw $7, 84($0) 13 | label_2: 14 | addi $8, $7, 1 15 | j label_0 16 | andi $9, $8, 1 17 | -------------------------------------------------------------------------------- /ClockDivider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ClockDivider( 4 | input clock, 5 | input reset, 6 | output reg [31:0] counter 7 | ); 8 | 9 | always @(posedge clock) begin 10 | if (reset) begin 11 | counter <= 0; 12 | end else begin 13 | counter <= counter + 1'b1; 14 | end 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /Anti_jitter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Anti_jitter( 4 | input clk, // 按钮输入 5 | input [3:0] button, // 开关输入 6 | input [7:0] SW, // 按钮输出 7 | output reg [3:0] button_out, // 脉冲输出 8 | output reg [3:0] button_pulse, // 开关输出 9 | output reg [7:0] SW_OK, // button 长按 10 | output reg rst 11 | ); 12 | endmodule 13 | -------------------------------------------------------------------------------- /WbStage.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module WbStage ( 4 | input shouldWriteMemoryElseAluOutputToRegister, // WM2REG 5 | input [31:0] memoryData, 6 | input [31:0] aluOutput, 7 | output [31:0] registerWriteData 8 | ); 9 | 10 | assign registerWriteData = shouldWriteMemoryElseAluOutputToRegister ? memoryData : aluOutput; 11 | endmodule 12 | -------------------------------------------------------------------------------- /Pc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Pc ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input id_shouldStall, 9 | 10 | input [31:0] nextPc, 11 | output reg [31:0] pc = 0 12 | ); 13 | 14 | always @(posedge clock) begin 15 | if (reset) begin 16 | pc <= 0; 17 | end else if (id_shouldStall) begin 18 | pc <= pc; 19 | end else begin 20 | pc <= nextPc; 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /MemStage.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module MemStage ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input [31:0] aluOutput, 9 | input shouldWriteMemory, 10 | input [31:0] registerRtOrZero, 11 | output [31:0] memoryData 12 | ); 13 | 14 | DataMemory dataMemory( 15 | .clka(~clock), 16 | .addra(aluOutput[9:2]), 17 | .douta(memoryData[31:0]), 18 | .wea(shouldWriteMemory), 19 | .dina(registerRtOrZero[31:0]) 20 | ); 21 | endmodule 22 | -------------------------------------------------------------------------------- /IfStage.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IfStage ( 4 | 5 | input clock, 6 | 7 | input [31:0] pc, 8 | 9 | input id_shouldJumpOrBranch, // BRANCH 10 | input [31:0] id_jumpOrBranchPc, 11 | 12 | output [31:0] pc_4, 13 | 14 | output [31:0] instruction, 15 | 16 | output [31:0] nextPc 17 | ); 18 | 19 | assign pc_4 = pc + 4; 20 | 21 | InstructionMemory instructionMemory ( 22 | .clka(~clock), 23 | .addra(pc[9:2]), 24 | .douta(instruction[31:0]) 25 | ); 26 | 27 | assign nextPc = id_shouldJumpOrBranch ? id_jumpOrBranchPc : pc_4; 28 | endmodule 29 | -------------------------------------------------------------------------------- /IfIdRegisters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IfIdRegisters ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input id_shouldStall, 9 | 10 | input [31:0] if_pc_4, 11 | 12 | input [31:0] if_instruction, 13 | 14 | output reg [31:0] id_pc_4 = 0, 15 | 16 | output reg [31:0] id_instruction = 0 17 | ); 18 | 19 | always @(posedge clock) begin 20 | 21 | if (reset) begin 22 | 23 | id_pc_4 <= 0; 24 | 25 | id_instruction <= 0; 26 | 27 | end else if (id_shouldStall) begin 28 | 29 | id_pc_4 <= id_pc_4; 30 | 31 | id_instruction <= id_instruction; 32 | 33 | end else begin 34 | 35 | id_pc_4 <= if_pc_4; 36 | 37 | id_instruction <= if_instruction; 38 | end 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /Alu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | `include "Constants.vh" 4 | 5 | module Alu ( 6 | input [31:0] inputA, 7 | input [31:0] inputB, 8 | input [3:0] operation, 9 | output [31:0] output_ 10 | ); 11 | 12 | assign output_ = 13 | operation == `ALU_ADD ? $signed(inputA) + $signed(inputB) 14 | : operation == `ALU_ADDU ? inputA + inputB 15 | : operation == `ALU_SUB ? $signed(inputA) - $signed(inputB) 16 | : operation == `ALU_SUBU ? inputA - inputB 17 | : operation == `ALU_AND ? inputA & inputB 18 | : operation == `ALU_OR ? inputA | inputB 19 | : operation == `ALU_XOR ? inputA ^ inputB 20 | : operation == `ALU_NOR ? ~(inputA | inputB) 21 | : operation == `ALU_SLL ? inputB << inputA 22 | : operation == `ALU_SRL ? inputB >> inputA 23 | : operation == `ALU_SRA ? inputB >>> inputA 24 | : 32'b0; 25 | endmodule 26 | -------------------------------------------------------------------------------- /ExStage.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ExStage ( 4 | 5 | input [31:0] shiftAmount, 6 | input [31:0] immediate, 7 | 8 | input [3:0] aluOperation, // EALUC 9 | input shouldAluUseShiftAmountElseRegisterRsOrPc_4, // ESHIFT 10 | input shouldAluUseImmeidateElseRegisterRtOrZero, // EALUIMM 11 | 12 | input [31:0] registerRsOrPc_4, 13 | input [31:0] registerRtOrZero, 14 | 15 | output [31:0] aluOutput, 16 | 17 | output [31:0] debug_aluInputA, 18 | output [31:0] debug_aluInputB 19 | ); 20 | 21 | wire [31:0] aluInputA = shouldAluUseShiftAmountElseRegisterRsOrPc_4 ? shiftAmount : registerRsOrPc_4; 22 | wire [31:0] aluInputB = shouldAluUseImmeidateElseRegisterRtOrZero ? immediate : registerRtOrZero; 23 | Alu alu ( 24 | .inputA(aluInputA[31:0]), 25 | .inputB(aluInputB[31:0]), 26 | .operation(aluOperation[3:0]), 27 | .output_(aluOutput[31:0]) 28 | ); 29 | 30 | assign debug_aluInputA = aluInputA; 31 | assign debug_aluInputB = aluInputB; 32 | endmodule 33 | -------------------------------------------------------------------------------- /assets/debugger-input.txt: -------------------------------------------------------------------------------- 1 | cpu_if_instruction 2 | cpu_if_pc 3 | cpu_if_nextPc 4 | cpu_id_instruction 5 | cpu_id_shouldStall 6 | cpu_id_shouldForwardRegisterRs 7 | cpu_id_shouldForwardRegisterRt 8 | cpu_id_register0 9 | cpu_id_register1 10 | cpu_id_register2 11 | cpu_id_register3 12 | cpu_id_register4 13 | cpu_id_register5 14 | cpu_id_register6 15 | cpu_id_register7 16 | cpu_id_register8 17 | cpu_id_register9 18 | cpu_id_register10 19 | cpu_id_register11 20 | cpu_id_register12 21 | cpu_id_register13 22 | cpu_id_register14 23 | cpu_id_register15 24 | cpu_id_register16 25 | cpu_id_register17 26 | cpu_id_register18 27 | cpu_id_register19 28 | cpu_id_register20 29 | cpu_id_register21 30 | cpu_id_register22 31 | cpu_id_register23 32 | cpu_id_register24 33 | cpu_id_register25 34 | cpu_id_register26 35 | cpu_id_register27 36 | cpu_id_register28 37 | cpu_id_register29 38 | cpu_id_register30 39 | cpu_id_register31 40 | cpu_ex_instruction 41 | cpu_ex_aluInputA 42 | cpu_ex_aluInputB 43 | cpu_ex_aluOutput 44 | cpu_mem_instruction 45 | cpu_mem_memoryAddress 46 | cpu_mem_memoryReadData 47 | cpu_mem_shouldWriteMemory 48 | cpu_mem_memoryWriteData 49 | cpu_wb_instruction 50 | cpu_wb_shouldWriteRegister 51 | cpu_wb_registerWriteAddress 52 | cpu_wb_registerWriteData 53 | -------------------------------------------------------------------------------- /MemWbRegisters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module MemWbRegisters ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input [31:0] mem_instruction, 9 | 10 | input mem_shouldWriteRegister, 11 | input [4:0] mem_registerWriteAddress, 12 | input mem_shouldWriteMemoryElseAluOutputToRegister, 13 | input [31:0] mem_memoryData, 14 | input [31:0] mem_aluOutput, 15 | 16 | output reg [31:0] wb_instruction = 0, 17 | 18 | output reg wb_shouldWriteRegister = 0, 19 | output reg [4:0] wb_registerWriteAddress = 0, 20 | output reg wb_shouldWriteMemoryElseAluOutputToRegister = 0, 21 | output reg [31:0] wb_memoryData = 0, 22 | output reg [31:0] wb_aluOutput = 0 23 | ); 24 | 25 | always @(posedge clock) begin 26 | 27 | if (reset) begin 28 | 29 | wb_instruction <= 0; 30 | 31 | wb_shouldWriteRegister <= 0; 32 | wb_registerWriteAddress <= 0; 33 | wb_shouldWriteMemoryElseAluOutputToRegister <= 0; 34 | wb_memoryData <= 0; 35 | wb_aluOutput <= 0; 36 | 37 | end else begin 38 | 39 | wb_instruction <= mem_instruction; 40 | 41 | wb_shouldWriteRegister <= mem_shouldWriteRegister; 42 | wb_registerWriteAddress <= mem_registerWriteAddress; 43 | wb_shouldWriteMemoryElseAluOutputToRegister <= mem_shouldWriteMemoryElseAluOutputToRegister; 44 | wb_memoryData <= mem_memoryData; 45 | wb_aluOutput <= mem_aluOutput; 46 | end 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /Terminal.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Terminal ( 4 | 5 | input clock, 6 | 7 | input isVgaActive, 8 | input [9:0] vgaX, 9 | input [8:0] vgaY, 10 | output [7:0] vgaColor, 11 | 12 | input [11:0] textAddress, 13 | output [7:0] textReadData, 14 | input shouldWriteText, 15 | input [7:0] textWriteData 16 | ); 17 | 18 | localparam COLOR_BLACK = 8'b000_000_00; 19 | localparam COLOR_RED = 8'b111_000_00; 20 | localparam COLOR_WHITE = 8'b111_111_11; 21 | 22 | // 640x480, 80x30 23 | // Make synthesizer happy so that it won't mess up. 24 | //reg [15:0] text [0:2399]; 25 | reg [15:0] text [0:4095]; 26 | 27 | wire [11:0] textIndex = vgaX / 8 + (vgaY / 16) * 80; 28 | wire [15:0] textData = text[textIndex]; 29 | wire [7:0] fontIndex = textData[7:0]; 30 | wire [2:0] fontX = vgaX % 8; 31 | wire [3:0] fontY = vgaY % 16; 32 | wire [11:0] fontAddress = fontIndex * 16 + fontY; 33 | wire [7:0] fontData; 34 | Font font ( 35 | .a(fontAddress[11:0]), 36 | .spo(fontData[7:0]) 37 | ); 38 | wire hasPoint = fontData[8 - fontX]; 39 | wire [7:0] textColor = textData[15:8]; 40 | assign vgaColor = isVgaActive ? (hasPoint ? textColor : COLOR_BLACK) : 8'b0; 41 | 42 | always @(posedge clock) begin 43 | if (shouldWriteText) begin 44 | // HACK FOR LOVE! 45 | text[textAddress] <= {textWriteData == "" ? COLOR_RED : COLOR_WHITE, textWriteData}; 46 | end 47 | end 48 | assign textReadData = text[textAddress][7:0]; 49 | endmodule 50 | -------------------------------------------------------------------------------- /VgaController.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module VgaController ( 4 | 5 | input clock25Mhz, 6 | input reset, 7 | 8 | output hSync, 9 | output vSync, 10 | 11 | output isActive, 12 | output [9:0] x, 13 | output [8:0] y 14 | ); 15 | 16 | // SYNC, BPORCH, VIDEO, FPORCH. 17 | localparam H_SYNC = 10'd96; 18 | localparam H_BPORCH = 10'd144; 19 | localparam H_FPORCH = 10'd784; 20 | localparam H_TOTAL = 10'd800; 21 | localparam V_SYNC = 10'd2; 22 | localparam V_BPORCH = 10'd35; 23 | localparam V_FPORCH = 10'd511; 24 | localparam V_TOTAL = 10'd525; 25 | 26 | reg [9:0] hCounter = 0; 27 | reg [9:0] vCounter = 0; 28 | 29 | always @(posedge clock25Mhz) begin 30 | if (reset) begin 31 | hCounter <= 0; 32 | end else if (hCounter == H_TOTAL - 1'b1) begin 33 | hCounter <= 0; 34 | end else begin 35 | hCounter <= hCounter + 1'b1; 36 | end 37 | end 38 | 39 | always @(posedge clock25Mhz) begin 40 | if (reset) begin 41 | vCounter <= 0; 42 | end else if (hCounter == H_TOTAL - 1'b1) begin 43 | if (vCounter == V_TOTAL - 1) begin 44 | vCounter <= 0; 45 | end else begin 46 | vCounter <= vCounter + 1'b1; 47 | end 48 | end 49 | end 50 | 51 | assign hSync = hCounter < H_SYNC ? 1'b0 : 1'b1; 52 | assign vSync = vCounter < V_SYNC ? 1'b0 : 1'b1; 53 | 54 | assign isActive = (hCounter >= H_BPORCH) && (hCounter < H_FPORCH) && (vCounter >= V_BPORCH) && (vCounter < V_FPORCH) ? 1'b1 : 1'b0; 55 | assign x = hCounter - H_BPORCH; 56 | assign y = {vCounter - V_BPORCH}[8:0]; 57 | endmodule 58 | -------------------------------------------------------------------------------- /RegisterFile.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module RegisterFile ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input [4:0] readAddressA, 9 | output [31:0] readDataA, 10 | input [4:0] readAddressB, 11 | output [31:0] readDataB, 12 | 13 | input shouldWrite, 14 | input [4:0] writeAddress, 15 | input [31:0] writeData, 16 | 17 | output [32 * 32 - 1 : 0] debug_registers 18 | ); 19 | 20 | reg [31:0] registers [1:31]; 21 | integer i; 22 | initial begin 23 | for (i = 1; i < 32; i = i + 1) begin 24 | registers[i] = 0; 25 | end 26 | end 27 | 28 | assign readDataA = readAddressA == 0 ? 32'b0 : registers[readAddressA]; 29 | assign readDataB = readAddressB == 0 ? 32'b0 : registers[readAddressB]; 30 | 31 | integer j; 32 | always @(negedge clock) begin 33 | if (reset) begin 34 | for (j = 1; j < 32; j = j + 1) begin 35 | registers[j] <= 0; 36 | end 37 | end else if (shouldWrite && writeAddress != 0) begin 38 | registers[writeAddress] <= writeData; 39 | end 40 | end 41 | 42 | assign debug_registers = {registers[31], registers[30], registers[29], 43 | registers[28], registers[27], registers[26], registers[25], 44 | registers[24], registers[23], registers[22], registers[21], 45 | registers[20], registers[19], registers[18], registers[17], 46 | registers[16], registers[15], registers[14], registers[13], 47 | registers[12], registers[11], registers[10], registers[9], 48 | registers[8], registers[7], registers[6], registers[5], 49 | registers[4], registers[3], registers[2], registers[1], 32'b0}; 50 | endmodule 51 | -------------------------------------------------------------------------------- /ExMemRegisters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ExMemRegisters ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input [31:0] ex_instruction, 9 | 10 | input ex_shouldWriteRegister, 11 | input [4:0] ex_registerWriteAddress, 12 | input ex_shouldWriteMemoryElseAluOutputToRegister, 13 | 14 | input [31:0] ex_aluOutput, 15 | input ex_shouldWriteMemory, 16 | input [31:0] ex_registerRtOrZero, 17 | 18 | output reg [31:0] mem_instruction = 0, 19 | 20 | output reg mem_shouldWriteRegister = 0, 21 | output reg [4:0] mem_registerWriteAddress = 0, 22 | output reg mem_shouldWriteMemoryElseAluOutputToRegister = 0, 23 | 24 | output reg [31:0] mem_aluOutput = 0, 25 | output reg mem_shouldWriteMemory = 0, 26 | output reg [31:0] mem_registerRtOrZero = 0 27 | ); 28 | 29 | always @(posedge clock) begin 30 | 31 | if (reset) begin 32 | 33 | mem_instruction <= 0; 34 | 35 | mem_shouldWriteRegister <= 0; 36 | mem_registerWriteAddress <= 0; 37 | mem_shouldWriteMemoryElseAluOutputToRegister <= 0; 38 | 39 | mem_aluOutput <= 0; 40 | mem_shouldWriteMemory <= 0; 41 | mem_registerRtOrZero <= 0; 42 | 43 | end else begin 44 | 45 | mem_instruction <= ex_instruction; 46 | 47 | mem_shouldWriteRegister <= ex_shouldWriteRegister; 48 | mem_registerWriteAddress <= ex_registerWriteAddress; 49 | mem_shouldWriteMemoryElseAluOutputToRegister <= ex_shouldWriteMemoryElseAluOutputToRegister; 50 | 51 | mem_aluOutput <= ex_aluOutput; 52 | mem_shouldWriteMemory <= ex_shouldWriteMemory; 53 | mem_registerRtOrZero <= ex_registerRtOrZero; 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /assets/debugger-design.txt: -------------------------------------------------------------------------------- 1 | Pipelined CPU Debugger Made by Zhang Hai with  2 | ================================================================================ 3 | IF Stage: nop 4 | PC: 0xFFFFFFFF Next PC: 0xFFFFFFFF 5 | ================================================================================ 6 | ID Stage: nop 7 | Stall: True 8 | Forward Rs: True Forward Rt: True 9 | Registers: 10 | 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 11 | 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 12 | 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 13 | 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 14 | 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 15 | 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 16 | 0xFFFFFFFF 0xFFFFFFFF 17 | ================================================================================ 18 | EX Stage: nop 19 | ALU Input A: 0xFFFFFFFF ALU Input B: 0xFFFFFFFF 20 | ALU Output: 0xFFFFFFFF 21 | ================================================================================ 22 | MEM Stage: nop 23 | Memory Address: 0xFFFFFFFF Memory Read Data: 0xFFFFFFFF 24 | Memory Write Enabled: True Memory Write Data: 0xFFFFFFFF 25 | ================================================================================ 26 | WB Stage: nop 27 | Register Write Enabled: True Register Write Address: 0xAA 28 | Register Write Data: 0xFFFFFFFF 29 | 30 | 31 | -------------------------------------------------------------------------------- /assets/generate-stage-instantiation.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from itertools import groupby 4 | from collections import namedtuple 5 | import re 6 | 7 | stageName = input('Stage name: ').lower() 8 | 9 | Port = namedtuple('Port', ['direction', 'width', 'name']) 10 | portRe = re.compile('(?P(input|output))(\s+(?P\[\d+:\d+\]))?\s+(?P\w+),?.*') 11 | portList = [] 12 | print('Port list:') 13 | while True: 14 | try: 15 | line = input().strip() 16 | if line: 17 | portMatch = portRe.match(line) 18 | port = Port(**portMatch.groupdict()) 19 | portList.append(port) 20 | else: 21 | portList.append(None) 22 | except EOFError: 23 | break 24 | portList = [key for key, group in groupby(portList)] 25 | 26 | print('-' * 80) 27 | 28 | for port in portList: 29 | if port and port.direction == 'output': 30 | print(' wire', end='') 31 | if port.width: 32 | print(' {}'.format(port.width), end='') 33 | print(' {}_{};'.format(stageName, port.name)) 34 | 35 | print('-' * 80) 36 | 37 | print(''' {}Stage {}Stage ( 38 | '''.format(stageName.capitalize(), stageName)) 39 | 40 | precedingIsPort = False 41 | for port in portList: 42 | if precedingIsPort: 43 | print(',') 44 | if port: 45 | print(' .{}('.format(port.name), end='') 46 | if (port.name not in ('clock', 'reset')) and ('_' not in port.name or 'pc_4' in port.name.lower()): 47 | print('{}_'.format(stageName), end='') 48 | print(port.name, end='') 49 | if port.width: 50 | print(port.width, end='') 51 | print(')', end='') 52 | precedingIsPort = True 53 | else: 54 | print() 55 | precedingIsPort = False 56 | print(''' 57 | );''') 58 | -------------------------------------------------------------------------------- /ipcore_dir/Font.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Sat Apr 16 02:48:10 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:dist_mem_gen:7.2 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx16 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = csg324 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -3 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2 40 | # END Select 41 | # BEGIN Parameters 42 | CSET ce_overrides=ce_overrides_sync_controls 43 | CSET coefficient_file=./Font.coe 44 | CSET common_output_ce=false 45 | CSET common_output_clk=false 46 | CSET component_name=Font 47 | CSET data_width=8 48 | CSET default_data=0 49 | CSET default_data_radix=16 50 | CSET depth=4096 51 | CSET dual_port_address=non_registered 52 | CSET dual_port_output_clock_enable=false 53 | CSET input_clock_enable=false 54 | CSET input_options=non_registered 55 | CSET memory_type=rom 56 | CSET output_options=non_registered 57 | CSET pipeline_stages=0 58 | CSET qualify_we_with_i_ce=false 59 | CSET reset_qdpo=false 60 | CSET reset_qsdpo=false 61 | CSET reset_qspo=false 62 | CSET simple_dual_port_address=non_registered 63 | CSET simple_dual_port_output_clock_enable=false 64 | CSET single_port_output_clock_enable=false 65 | CSET sync_reset_qdpo=false 66 | CSET sync_reset_qsdpo=false 67 | CSET sync_reset_qspo=false 68 | # END Parameters 69 | # BEGIN Extra information 70 | MISC pkg_timestamp=2012-11-21T20:07:40Z 71 | # END Extra information 72 | GENERATE 73 | # CRC: f55ee3b5 74 | -------------------------------------------------------------------------------- /ipcore_dir/Background.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Thu Apr 28 08:24:53 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:dist_mem_gen:7.2 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx16 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = csg324 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -3 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2 40 | # END Select 41 | # BEGIN Parameters 42 | CSET ce_overrides=ce_overrides_sync_controls 43 | CSET coefficient_file=./Background.coe 44 | CSET common_output_ce=false 45 | CSET common_output_clk=false 46 | CSET component_name=Background 47 | CSET data_width=8 48 | CSET default_data=0 49 | CSET default_data_radix=16 50 | CSET depth=2400 51 | CSET dual_port_address=non_registered 52 | CSET dual_port_output_clock_enable=false 53 | CSET input_clock_enable=false 54 | CSET input_options=non_registered 55 | CSET memory_type=rom 56 | CSET output_options=non_registered 57 | CSET pipeline_stages=0 58 | CSET qualify_we_with_i_ce=false 59 | CSET reset_qdpo=false 60 | CSET reset_qsdpo=false 61 | CSET reset_qspo=false 62 | CSET simple_dual_port_address=non_registered 63 | CSET simple_dual_port_output_clock_enable=false 64 | CSET single_port_output_clock_enable=false 65 | CSET sync_reset_qdpo=false 66 | CSET sync_reset_qsdpo=false 67 | CSET sync_reset_qspo=false 68 | # END Parameters 69 | # BEGIN Extra information 70 | MISC pkg_timestamp=2012-11-21T20:07:40Z 71 | # END Extra information 72 | GENERATE 73 | # CRC: 6b45b84e 74 | -------------------------------------------------------------------------------- /CpuTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module CpuTest (); 4 | 5 | // Inputs 6 | reg clock; 7 | reg reset; 8 | 9 | // Outputs 10 | wire [31:0] debug_if_pc; 11 | wire [31:0] debug_if_nextPc; 12 | wire [31:0] debug_if_instruction; 13 | wire [31:0] debug_id_instruction; 14 | wire debug_id_shouldStall; 15 | wire debug_id_shouldForwardRegisterRs; 16 | wire debug_id_shouldForwardRegisterRt; 17 | wire [1023:0] debug_id_registers; 18 | wire [31:0] debug_ex_instruction; 19 | wire [31:0] debug_ex_aluInputA; 20 | wire [31:0] debug_ex_aluInputB; 21 | wire [31:0] debug_ex_aluOutput; 22 | wire [31:0] debug_mem_instruction; 23 | wire [31:0] debug_mem_memoryAddress; 24 | wire [31:0] debug_mem_memoryReadData; 25 | wire debug_mem_shouldWriteMemory; 26 | wire [31:0] debug_mem_memoryWriteData; 27 | wire [31:0] debug_wb_instruction; 28 | wire debug_wb_shouldWriteRegister; 29 | wire [4:0] debug_wb_registerWriteAddress; 30 | wire [31:0] debug_wb_registerWriteData; 31 | 32 | // Instantiate the Unit Under Test (UUT) 33 | Cpu uut ( 34 | .clock(clock), 35 | .reset(reset), 36 | .debug_if_pc(debug_if_pc), 37 | .debug_if_nextPc(debug_if_nextPc), 38 | .debug_if_instruction(debug_if_instruction), 39 | .debug_id_instruction(debug_id_instruction), 40 | .debug_id_shouldStall(debug_id_shouldStall), 41 | .debug_id_shouldForwardRegisterRs(debug_id_shouldForwardRegisterRs), 42 | .debug_id_shouldForwardRegisterRt(debug_id_shouldForwardRegisterRt), 43 | .debug_id_registers(debug_id_registers), 44 | .debug_ex_instruction(debug_ex_instruction), 45 | .debug_ex_aluInputA(debug_ex_aluInputA), 46 | .debug_ex_aluInputB(debug_ex_aluInputB), 47 | .debug_ex_aluOutput(debug_ex_aluOutput), 48 | .debug_mem_instruction(debug_mem_instruction), 49 | .debug_mem_memoryAddress(debug_mem_memoryAddress), 50 | .debug_mem_memoryReadData(debug_mem_memoryReadData), 51 | .debug_mem_shouldWriteMemory(debug_mem_shouldWriteMemory), 52 | .debug_mem_memoryWriteData(debug_mem_memoryWriteData), 53 | .debug_wb_instruction(debug_wb_instruction), 54 | .debug_wb_shouldWriteRegister(debug_wb_shouldWriteRegister), 55 | .debug_wb_registerWriteAddress(debug_wb_registerWriteAddress), 56 | .debug_wb_registerWriteData(debug_wb_registerWriteData) 57 | ); 58 | 59 | initial begin 60 | 61 | // Initialize Inputs 62 | clock = 0; 63 | reset = 0; 64 | 65 | // Wait 100 ns for global reset to finish 66 | #100; 67 | 68 | // Add stimulus here 69 | forever begin 70 | #5; 71 | clock = ~clock; 72 | end 73 | end 74 | endmodule 75 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 浙江大学计算机体系结构课程实验 2 | 3 | 张海 4 | 5 | 本项目是我按照课程要求独立完成的 MIPS 流水线 CPU 实现。目前已实现 31 条指令和 Stall/Forwarding。 6 | 7 | 本项目的开发使用 Nexys 3 开发板进行，但应当可以很简单地移植到其他开发板。 8 | 9 | 本项目的二进制 .bit 文件可以在 [Releases](https://github.com/DreaminginCodeZH/archexp/releases/) 中下载。 10 | 11 | ## 原因 12 | 13 | 课程提供的代码在结构、命名和排版上都有诸多不清晰和不一致之处，使得编码和调试时很不舒服。 14 | 15 | - 命名不统一：大部分线路名采用模块名作为前缀以指示归属，但仍有部分代码存在问题。线路名称中有些前缀后加`_`区别，有些不加，命名不一致。模块对内和对外的线路命名可以不同，但有时加前缀，有时不加，难以一眼确定线路归属，令人困惑。 16 | 17 | - 结构不清晰：流水线寄存器本来应当与各个执行阶段在同一个级别之上，按顺序依次传递数据。但是，代码中将流水线寄存器放在执行阶段模块的代码之中，这正是使得变量命名混乱和代码逻辑不清晰的根源。同时，甚至有将某个多路选择器逻辑放置在流水线寄存器模块代码之中的做法，这令我很难接受。 18 | 19 | 因此，我选择了自己重新实现。 20 | 21 | 至于选择开源，是想要给这门课程的实验提供一份清晰且一致的代码实现，也希望能够有助于同学们更加直观地理解流水线 CPU 的具体实现。 22 | 23 | > 希望前人所走过的弯路后人都不必再走，这是我对开源的信念之一。 24 | 25 | ## 特点 26 | 27 | - 基于课程提供的电路原理图，符合课程要求和实践。原线路命名与项目中线路命名对应关系在执行阶段模块的声明中以注释的方式给出。 28 | 29 | ![流水线 CPU 原理图](assets/readme/schematic.png) 30 | 31 | - 使用 VGA 显示大量调试信息。 32 | 33 | 得益于 VGA 较大的信息量，可以将许多有利于调试或教学的信息都打印在屏幕上实时更新。利用一个组合电路的反汇编器，可以看到当前阶段正在执行指令的汇编源代码。VGA 模块中控制显示相关的长段代码也由 Python 脚本生成，可以通过读取用文本文档记录的设计，快速进行修改。 34 | 35 | ![VGA 调试设计图](assets/readme/debugger-design.png) 36 | 37 | ![VGA 调试实现效果](assets/readme/debugger.jpg) 38 | 39 | - 合理的代码组织方式。 40 | 41 | 在 CPU 模块之下，PC、各个流水线寄存器和各个执行阶段模块依次连接，尽力实现代码组织的合理和明确。 42 | 43 | ![CPU 代码组织结构](assets/readme/organization.png) 44 | 45 | - 统一的代码风格和排版。 46 | 47 | 经过权衡，项目代码采用了较长的命名，是为了将原本意义不明显、需要常常查看注释或原理图的变量名称，转变为清晰、不容易出错的名称，由此项目编码过程中未出现过代码逻辑错误。 48 | 49 | 命名规则的统一使得线路功能和归属清晰可靠，而代码中的缩进、空行分块和前后顺序等排版也尽量追寻体现代码之间的逻辑关系，便于阅读和维护。 50 | 51 | 项目代码始终尽量采用推荐的 Verilog 实践，例如新的模块声明方式。 52 | 53 | - 自动生成部分模块和模块连线代码。 54 | 55 | 得益于统一的命名风格和代码组织，流水线寄存器模块和各模块之间连线的代码可以按照特定规则生成。本项目采用 Python 脚本完成了数百行的代码生成，避免大量繁杂和容易出错的工作，同时由此以后修改接口时也可以更为简单。 56 | 57 | ![流水线寄存器代码生成脚本](assets/readme/code-generation.png) 58 | 59 | 本项目中大部分代码逻辑都在 `*Stage.v` 中，而 `*Registers.v` 和 `Cpu.v` 均为生成的代码。 60 | 61 | ## 许可 62 | 63 | ``` 64 | Copyright (c) 2016 Zhang Hai 65 | 66 | This program is free software: you can redistribute it and/or modify 67 | it under the terms of the GNU General Public License as published by 68 | the Free Software Foundation, either version 3 of the License, or 69 | (at your option) any later version. 70 | 71 | This program is distributed in the hope that it will be useful, but 72 | WITHOUT ANY WARRANTY; without even the implied warranty of 73 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 74 | General Public License for more details. 75 | 76 | You should have received a copy of the GNU General Public License 77 | along with this program. If not, see 78 | . 79 | ``` 80 | -------------------------------------------------------------------------------- /IdExRegisters.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IdExRegisters ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input id_shouldStall, 9 | 10 | input [31:0] id_instruction, 11 | 12 | input [31:0] id_shiftAmount, 13 | input [31:0] id_immediate, 14 | 15 | input [31:0] id_registerRsOrPc_4, 16 | input [31:0] id_registerRtOrZero, 17 | 18 | input [3:0] id_aluOperation, 19 | input id_shouldAluUseShiftAmountElseRegisterRsOrPc_4, 20 | input id_shouldAluUseImmeidateElseRegisterRtOrZero, 21 | 22 | input id_shouldWriteRegister, 23 | input [4:0] id_registerWriteAddress, 24 | input id_shouldWriteMemoryElseAluOutputToRegister, 25 | 26 | input id_shouldWriteMemory, 27 | 28 | output reg [31:0] ex_instruction = 0, 29 | 30 | output reg [31:0] ex_shiftAmount = 0, 31 | output reg [31:0] ex_immediate = 0, 32 | 33 | output reg [31:0] ex_registerRsOrPc_4 = 0, 34 | output reg [31:0] ex_registerRtOrZero = 0, 35 | 36 | output reg [3:0] ex_aluOperation = 0, 37 | output reg ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4 = 0, 38 | output reg ex_shouldAluUseImmeidateElseRegisterRtOrZero = 0, 39 | 40 | output reg ex_shouldWriteRegister = 0, 41 | output reg [4:0] ex_registerWriteAddress = 0, 42 | output reg ex_shouldWriteMemoryElseAluOutputToRegister = 0, 43 | 44 | output reg ex_shouldWriteMemory = 0 45 | ); 46 | 47 | always @(posedge clock) begin 48 | 49 | if (reset || id_shouldStall) begin 50 | 51 | ex_instruction <= 0; 52 | 53 | ex_shiftAmount <= 0; 54 | ex_immediate <= 0; 55 | 56 | ex_registerRsOrPc_4 <= 0; 57 | ex_registerRtOrZero <= 0; 58 | 59 | ex_aluOperation <= 0; 60 | ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4 <= 0; 61 | ex_shouldAluUseImmeidateElseRegisterRtOrZero <= 0; 62 | 63 | ex_shouldWriteRegister <= 0; 64 | ex_registerWriteAddress <= 0; 65 | ex_shouldWriteMemoryElseAluOutputToRegister <= 0; 66 | 67 | ex_shouldWriteMemory <= 0; 68 | 69 | end else begin 70 | 71 | ex_instruction <= id_instruction; 72 | 73 | ex_shiftAmount <= id_shiftAmount; 74 | ex_immediate <= id_immediate; 75 | 76 | ex_registerRsOrPc_4 <= id_registerRsOrPc_4; 77 | ex_registerRtOrZero <= id_registerRtOrZero; 78 | 79 | ex_aluOperation <= id_aluOperation; 80 | ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4 <= id_shouldAluUseShiftAmountElseRegisterRsOrPc_4; 81 | ex_shouldAluUseImmeidateElseRegisterRtOrZero <= id_shouldAluUseImmeidateElseRegisterRtOrZero; 82 | 83 | ex_shouldWriteRegister <= id_shouldWriteRegister; 84 | ex_registerWriteAddress <= id_registerWriteAddress; 85 | ex_shouldWriteMemoryElseAluOutputToRegister <= id_shouldWriteMemoryElseAluOutputToRegister; 86 | 87 | ex_shouldWriteMemory <= id_shouldWriteMemory; 88 | end 89 | end 90 | endmodule 91 | -------------------------------------------------------------------------------- /ipcore_dir/DataMemory.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Fri Apr 15 09:46:57 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:blk_mem_gen:7.3 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx16 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = csg324 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -3 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 40 | # END Select 41 | # BEGIN Parameters 42 | CSET additional_inputs_for_power_estimation=false 43 | CSET algorithm=Minimum_Area 44 | CSET assume_synchronous_clk=false 45 | CSET axi_id_width=4 46 | CSET axi_slave_type=Memory_Slave 47 | CSET axi_type=AXI4_Full 48 | CSET byte_size=9 49 | CSET coe_file=./DataMemory.coe 50 | CSET collision_warnings=ALL 51 | CSET component_name=DataMemory 52 | CSET disable_collision_warnings=false 53 | CSET disable_out_of_range_warnings=false 54 | CSET ecc=false 55 | CSET ecctype=No_ECC 56 | CSET enable_32bit_address=false 57 | CSET enable_a=Always_Enabled 58 | CSET enable_b=Always_Enabled 59 | CSET error_injection_type=Single_Bit_Error_Injection 60 | CSET fill_remaining_memory_locations=false 61 | CSET interface_type=Native 62 | CSET load_init_file=true 63 | CSET mem_file=no_Mem_file_loaded 64 | CSET memory_type=Single_Port_RAM 65 | CSET operating_mode_a=WRITE_FIRST 66 | CSET operating_mode_b=WRITE_FIRST 67 | CSET output_reset_value_a=0 68 | CSET output_reset_value_b=0 69 | CSET pipeline_stages=0 70 | CSET port_a_clock=100 71 | CSET port_a_enable_rate=100 72 | CSET port_a_write_rate=50 73 | CSET port_b_clock=0 74 | CSET port_b_enable_rate=0 75 | CSET port_b_write_rate=0 76 | CSET primitive=8kx2 77 | CSET read_width_a=32 78 | CSET read_width_b=32 79 | CSET register_porta_input_of_softecc=false 80 | CSET register_porta_output_of_memory_core=false 81 | CSET register_porta_output_of_memory_primitives=false 82 | CSET register_portb_output_of_memory_core=false 83 | CSET register_portb_output_of_memory_primitives=false 84 | CSET register_portb_output_of_softecc=false 85 | CSET remaining_memory_locations=0 86 | CSET reset_memory_latch_a=false 87 | CSET reset_memory_latch_b=false 88 | CSET reset_priority_a=CE 89 | CSET reset_priority_b=CE 90 | CSET reset_type=SYNC 91 | CSET softecc=false 92 | CSET use_axi_id=false 93 | CSET use_bram_block=Stand_Alone 94 | CSET use_byte_write_enable=false 95 | CSET use_error_injection_pins=false 96 | CSET use_regcea_pin=false 97 | CSET use_regceb_pin=false 98 | CSET use_rsta_pin=false 99 | CSET use_rstb_pin=false 100 | CSET write_depth_a=256 101 | CSET write_width_a=32 102 | CSET write_width_b=32 103 | # END Parameters 104 | # BEGIN Extra information 105 | MISC pkg_timestamp=2012-11-19T16:22:25Z 106 | # END Extra information 107 | GENERATE 108 | # CRC: f8b9b2ef 109 | -------------------------------------------------------------------------------- /ipcore_dir/InstructionMemory.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Sun May 1 07:40:10 2016 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:blk_mem_gen:7.3 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx16 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = csg324 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -3 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 40 | # END Select 41 | # BEGIN Parameters 42 | CSET additional_inputs_for_power_estimation=false 43 | CSET algorithm=Minimum_Area 44 | CSET assume_synchronous_clk=false 45 | CSET axi_id_width=4 46 | CSET axi_slave_type=Memory_Slave 47 | CSET axi_type=AXI4_Full 48 | CSET byte_size=9 49 | CSET coe_file=./InstructionMemory.coe 50 | CSET collision_warnings=ALL 51 | CSET component_name=InstructionMemory 52 | CSET disable_collision_warnings=false 53 | CSET disable_out_of_range_warnings=false 54 | CSET ecc=false 55 | CSET ecctype=No_ECC 56 | CSET enable_32bit_address=false 57 | CSET enable_a=Always_Enabled 58 | CSET enable_b=Always_Enabled 59 | CSET error_injection_type=Single_Bit_Error_Injection 60 | CSET fill_remaining_memory_locations=false 61 | CSET interface_type=Native 62 | CSET load_init_file=true 63 | CSET mem_file=no_Mem_file_loaded 64 | CSET memory_type=Single_Port_ROM 65 | CSET operating_mode_a=WRITE_FIRST 66 | CSET operating_mode_b=WRITE_FIRST 67 | CSET output_reset_value_a=0 68 | CSET output_reset_value_b=0 69 | CSET pipeline_stages=0 70 | CSET port_a_clock=100 71 | CSET port_a_enable_rate=100 72 | CSET port_a_write_rate=0 73 | CSET port_b_clock=0 74 | CSET port_b_enable_rate=0 75 | CSET port_b_write_rate=0 76 | CSET primitive=8kx2 77 | CSET read_width_a=32 78 | CSET read_width_b=32 79 | CSET register_porta_input_of_softecc=false 80 | CSET register_porta_output_of_memory_core=false 81 | CSET register_porta_output_of_memory_primitives=false 82 | CSET register_portb_output_of_memory_core=false 83 | CSET register_portb_output_of_memory_primitives=false 84 | CSET register_portb_output_of_softecc=false 85 | CSET remaining_memory_locations=0 86 | CSET reset_memory_latch_a=false 87 | CSET reset_memory_latch_b=false 88 | CSET reset_priority_a=CE 89 | CSET reset_priority_b=CE 90 | CSET reset_type=SYNC 91 | CSET softecc=false 92 | CSET use_axi_id=false 93 | CSET use_bram_block=Stand_Alone 94 | CSET use_byte_write_enable=false 95 | CSET use_error_injection_pins=false 96 | CSET use_regcea_pin=false 97 | CSET use_regceb_pin=false 98 | CSET use_rsta_pin=false 99 | CSET use_rstb_pin=false 100 | CSET write_depth_a=256 101 | CSET write_width_a=32 102 | CSET write_width_b=32 103 | # END Parameters 104 | # BEGIN Extra information 105 | MISC pkg_timestamp=2012-11-19T16:22:25Z 106 | # END Extra information 107 | GENERATE 108 | # CRC: 7515efc 109 | -------------------------------------------------------------------------------- /assets/generate-pipeline-registers.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from itertools import groupby 4 | from collections import namedtuple 5 | import re 6 | 7 | inputStageName = input('Input stage name: ').lower() 8 | outputStageName = input('Output stage name: ').lower() 9 | 10 | Port = namedtuple('Port', ['direction', 'width', 'name']) 11 | portRe = re.compile('(?P(input|output))(\s+(?P\[\d+:\d+\]))?\s+(?P\w+),?.*') 12 | portList = [] 13 | print('Port list:') 14 | while True: 15 | try: 16 | line = input().strip() 17 | if line: 18 | portMatch = portRe.match(line) 19 | port = Port(**portMatch.groupdict()) 20 | if port.direction == 'output': 21 | portList.append(port) 22 | else: 23 | portList.append(None) 24 | except EOFError: 25 | break 26 | portList = [key for key, group in groupby(portList)] 27 | 28 | print('-' * 80) 29 | 30 | print('''module {}{}Registers ( 31 | 32 | input clock, 33 | input reset, 34 | '''.format(inputStageName.capitalize(), outputStageName.capitalize())) 35 | 36 | precedingIsPort = False 37 | for port in portList: 38 | if precedingIsPort: 39 | print(',') 40 | if port: 41 | print(' input', end='') 42 | if port.width: 43 | print(" {}".format(port.width), end='') 44 | print(" {}_{}".format(inputStageName, port.name), end='') 45 | precedingIsPort = True 46 | else: 47 | print() 48 | precedingIsPort = False 49 | print(''', 50 | ''') 51 | 52 | precedingIsPort = False 53 | for port in portList: 54 | if precedingIsPort: 55 | print(',') 56 | if port: 57 | print(' output reg', end='') 58 | if port.width: 59 | print(" {}".format(port.width), end='') 60 | print(" {}_{} = 0".format(outputStageName, port.name), end='') 61 | precedingIsPort = True 62 | else: 63 | print() 64 | precedingIsPort = False 65 | 66 | print(''' 67 | ); 68 | 69 | always @(posedge clock) begin 70 | 71 | if (reset) begin 72 | ''') 73 | 74 | for port in portList: 75 | if port: 76 | print(' {}_{} <= 0;'.format(outputStageName, port.name)) 77 | else: 78 | print() 79 | 80 | print(''' 81 | end else begin 82 | ''') 83 | 84 | for port in portList: 85 | if port: 86 | print(' {}_{} <= {}_{};'.format(outputStageName, port.name, inputStageName, port.name)) 87 | else: 88 | print() 89 | 90 | print(''' end 91 | end 92 | endmodule''') 93 | 94 | print('-' * 80) 95 | 96 | for port in portList: 97 | if port: 98 | print(' wire', end='') 99 | if port.width: 100 | print(' {}'.format(port.width), end='') 101 | print(' {}_{};'.format(inputStageName, port.name)) 102 | print() 103 | for port in portList: 104 | if port: 105 | print(' wire', end='') 106 | if port.width: 107 | print(' {}'.format(port.width), end='') 108 | print(' {}_{};'.format(outputStageName, port.name)) 109 | 110 | print('-' * 80) 111 | 112 | print(''' {}{}Registers {}{}Registers ( 113 | 114 | .clock(clock), 115 | .reset(reset), 116 | '''.format(inputStageName.capitalize(), outputStageName.capitalize(), inputStageName, outputStageName.capitalize())) 117 | precedingIsPort = False 118 | for port in portList: 119 | if precedingIsPort: 120 | print(',') 121 | if port: 122 | print(' .{}_{}({}_{}'.format(inputStageName, port.name, inputStageName, port.name), end='') 123 | if port.width: 124 | print(port.width, end='') 125 | print(')', end='') 126 | precedingIsPort = True 127 | else: 128 | print() 129 | precedingIsPort = False 130 | print(''', 131 | ''') 132 | precedingIsPort = False 133 | for port in portList: 134 | if precedingIsPort: 135 | print(',') 136 | if port: 137 | print(' .{}_{}({}_{}'.format(outputStageName, port.name, outputStageName, port.name), end='') 138 | if port.width: 139 | print(port.width, end='') 140 | print(')', end='') 141 | precedingIsPort = True 142 | else: 143 | print() 144 | precedingIsPort = False 145 | print(''' 146 | );''') 147 | -------------------------------------------------------------------------------- /ipcore_dir/Font.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /ipcore_dir/Background.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /ipcore_dir/DataMemory.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /ipcore_dir/InstructionMemory.xise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 |
14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | -------------------------------------------------------------------------------- /archexp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module archexp( 4 | 5 | input clock50Mhz, 6 | 7 | input [3:0] BTN, 8 | input [7:0] SW, 9 | output [3:0] AN, 10 | output [7:0] SEGMENT, 11 | output [7:0] LED, 12 | 13 | output vgaHSync, 14 | output vgaVSync, 15 | output [2:0] vgaRed, 16 | output [2:0] vgaGreen, 17 | output [1:0] vgaBlue 18 | ); 19 | 20 | wire [3:0] button_out; 21 | wire reset; 22 | wire [7:0] SW_OK; 23 | 24 | wire [31:0] clockCounter; 25 | 26 | wire [31:0] cpu_if_pc; 27 | wire [31:0] cpu_if_nextPc; 28 | wire [31:0] cpu_if_instruction; 29 | wire [31:0] cpu_id_instruction; 30 | wire cpu_id_shouldStall; 31 | wire cpu_id_shouldForwardRegisterRs; 32 | wire cpu_id_shouldForwardRegisterRt; 33 | wire [32 * 32 - 1 : 0] cpu_id_registers; 34 | wire [31:0] cpu_ex_instruction; 35 | wire [31:0] cpu_ex_aluInputA; 36 | wire [31:0] cpu_ex_aluInputB; 37 | wire [31:0] cpu_ex_aluOutput; 38 | wire [31:0] cpu_mem_instruction; 39 | wire [31:0] cpu_mem_memoryAddress; 40 | wire [31:0] cpu_mem_memoryReadData; 41 | wire cpu_mem_shouldWriteMemory; 42 | wire [31:0] cpu_mem_memoryWriteData; 43 | wire [31:0] cpu_wb_instruction; 44 | wire cpu_wb_shouldWriteRegister; 45 | wire [4:0] cpu_wb_registerWriteAddress; 46 | wire [31:0] cpu_wb_registerWriteData; 47 | 48 | wire [9:0] vgaX; 49 | wire [8:0] vgaY; 50 | wire isVgaActive; 51 | wire [7:0] vgaColor; 52 | 53 | wire [11:0] terminalAddress; 54 | wire shouldWriteTerminal; 55 | wire [7:0] terminalWriteData; 56 | wire [7:0] terminalReadData; 57 | 58 | Anti_jitter U9 ( 59 | .clk(clock50Mhz), 60 | .button(BTN[3:0]), 61 | .SW(SW[7:0]), 62 | .button_out(button_out[3:0]), 63 | .rst(reset), 64 | .button_pulse(), 65 | .SW_OK(SW_OK[7:0]) 66 | ); 67 | 68 | ClockDivider clockDivider ( 69 | .clock(clock50Mhz), 70 | .reset(reset), 71 | .counter(clockCounter[31:0]) 72 | ); 73 | 74 | wire cpuClock = !button_out[1]; // So that memory read operates before CPU. 75 | Cpu cpu ( 76 | 77 | .clock(cpuClock), 78 | .reset(reset), 79 | 80 | .debug_if_pc(cpu_if_pc[31:0]), 81 | .debug_if_nextPc(cpu_if_nextPc[31:0]), 82 | .debug_if_instruction(cpu_if_instruction[31:0]), 83 | .debug_id_instruction(cpu_id_instruction[31:0]), 84 | .debug_id_shouldStall(cpu_id_shouldStall), 85 | .debug_id_shouldForwardRegisterRs(cpu_id_shouldForwardRegisterRs), 86 | .debug_id_shouldForwardRegisterRt(cpu_id_shouldForwardRegisterRt), 87 | .debug_id_registers(cpu_id_registers[32 * 32 - 1 : 0]), 88 | .debug_ex_instruction(cpu_ex_instruction[31:0]), 89 | .debug_ex_aluInputA(cpu_ex_aluInputA[31:0]), 90 | .debug_ex_aluInputB(cpu_ex_aluInputB[31:0]), 91 | .debug_ex_aluOutput(cpu_ex_aluOutput[31:0]), 92 | .debug_mem_instruction(cpu_mem_instruction[31:0]), 93 | .debug_mem_memoryAddress(cpu_mem_memoryAddress[31:0]), 94 | .debug_mem_memoryReadData(cpu_mem_memoryReadData[31:0]), 95 | .debug_mem_shouldWriteMemory(cpu_mem_shouldWriteMemory), 96 | .debug_mem_memoryWriteData(cpu_mem_memoryWriteData[31:0]), 97 | .debug_wb_instruction(cpu_wb_instruction[31:0]), 98 | .debug_wb_shouldWriteRegister(cpu_wb_shouldWriteRegister), 99 | .debug_wb_registerWriteAddress(cpu_wb_registerWriteAddress[4:0]), 100 | .debug_wb_registerWriteData(cpu_wb_registerWriteData[31:0]) 101 | ); 102 | 103 | wire clock25Mhz = clockCounter[1]; 104 | VgaController vgaController ( 105 | .clock25Mhz(clock25Mhz), 106 | .reset(reset), 107 | .hSync(vgaHSync), 108 | .vSync(vgaVSync), 109 | .isActive(isVgaActive), 110 | .x(vgaX[9:0]), 111 | .y(vgaY[8:0]) 112 | ); 113 | 114 | Terminal terminal ( 115 | 116 | .clock(clock50Mhz), 117 | 118 | .isVgaActive(isVgaActive), 119 | .vgaX(vgaX[9:0]), 120 | .vgaY(vgaY[8:0]), 121 | .vgaColor(vgaColor[7:0]), 122 | 123 | .textAddress(terminalAddress[11:0]), 124 | .textReadData(terminalReadData[7:0]), 125 | .shouldWriteText(shouldWriteTerminal), 126 | .textWriteData(terminalWriteData[7:0]) 127 | ); 128 | assign vgaRed = vgaColor[7:5]; 129 | assign vgaGreen = vgaColor[4:2]; 130 | assign vgaBlue = vgaColor[1:0]; 131 | 132 | Debugger debugger ( 133 | 134 | .clock(clock25Mhz), 135 | 136 | .cpu_if_pc(cpu_if_pc[31:0]), 137 | .cpu_if_nextPc(cpu_if_nextPc[31:0]), 138 | .cpu_if_instruction(cpu_if_instruction[31:0]), 139 | .cpu_id_instruction(cpu_id_instruction[31:0]), 140 | .cpu_id_shouldStall(cpu_id_shouldStall), 141 | .cpu_id_shouldForwardRegisterRs(cpu_id_shouldForwardRegisterRs), 142 | .cpu_id_shouldForwardRegisterRt(cpu_id_shouldForwardRegisterRt), 143 | .cpu_id_registers(cpu_id_registers[32 * 32 - 1 : 0]), 144 | .cpu_ex_instruction(cpu_ex_instruction[31:0]), 145 | .cpu_ex_aluInputA(cpu_ex_aluInputA[31:0]), 146 | .cpu_ex_aluInputB(cpu_ex_aluInputB[31:0]), 147 | .cpu_ex_aluOutput(cpu_ex_aluOutput[31:0]), 148 | .cpu_mem_instruction(cpu_mem_instruction[31:0]), 149 | .cpu_mem_memoryAddress(cpu_mem_memoryAddress[31:0]), 150 | .cpu_mem_memoryReadData(cpu_mem_memoryReadData[31:0]), 151 | .cpu_mem_shouldWriteMemory(cpu_mem_shouldWriteMemory), 152 | .cpu_mem_memoryWriteData(cpu_mem_memoryWriteData[31:0]), 153 | .cpu_wb_instruction(cpu_wb_instruction[31:0]), 154 | .cpu_wb_shouldWriteRegister(cpu_wb_shouldWriteRegister), 155 | .cpu_wb_registerWriteAddress(cpu_wb_registerWriteAddress[4:0]), 156 | .cpu_wb_registerWriteData(cpu_wb_registerWriteData[31:0]), 157 | 158 | .terminalAddress(terminalAddress[11:0]), 159 | .shouldWriteTerminal(shouldWriteTerminal), 160 | .terminalWriteData(terminalWriteData[7:0]) 161 | ); 162 | endmodule 163 | -------------------------------------------------------------------------------- /assets/generate-debugger.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from codecs import encode 4 | from collections import namedtuple 5 | from enum import Enum, unique 6 | 7 | def find_all(a_str, sub): 8 | start = 0 9 | while True: 10 | start = a_str.find(sub, start) 11 | if start == -1: 12 | return 13 | yield start 14 | start += len(sub) # use start += 1 to find overlapping matches 15 | 16 | class AutoEnum(Enum): 17 | def __new__(cls): 18 | value = len(cls.__members__) + 1 19 | obj = object.__new__(cls) 20 | obj._value_ = value 21 | return obj 22 | 23 | class InterpolationType(AutoEnum): 24 | INSTRUCTION = () 25 | HEX_8 = () 26 | HEX_2 = () 27 | BOOLEAN = () 28 | 29 | Interpolation = namedtuple('Interpolation', ['type', 'row', 'column']) 30 | 31 | def getTerminalAddress(interpolation): 32 | return 80 * interpolation.row + interpolation.column 33 | 34 | designLineList = [] 35 | with open('debugger-design.txt') as designFile: 36 | for line in designFile: 37 | if len(line.rstrip()) > 80: 38 | raise AssertionError('Design contains a line more than 80 characters') 39 | designLineList.append(line.rstrip().ljust(80)) 40 | if len(designLineList) != 30: 41 | raise AssertionError('Design does not contain exactly 30 lines') 42 | 43 | inputList = [] 44 | with open('debugger-input.txt') as inputFile: 45 | for line in inputFile: 46 | inputList.append(line.strip()) 47 | 48 | interpolationList = [] 49 | row = 0 50 | for line in designLineList: 51 | for index in find_all(line, 'nop'): 52 | interpolationList.append(Interpolation(InterpolationType.INSTRUCTION, row, index)) 53 | for index in find_all(line, '0xFFFFFFFF'): 54 | interpolationList.append(Interpolation(InterpolationType.HEX_8, row, index + 2)) 55 | for index in find_all(line, '0xAA'): 56 | interpolationList.append(Interpolation(InterpolationType.HEX_2, row, index + 2)) 57 | for index in find_all(line, 'True'): 58 | interpolationList.append(Interpolation(InterpolationType.BOOLEAN, row, index)) 59 | row += 1 60 | interpolationList.sort(key=getTerminalAddress) 61 | 62 | inputIter = iter(inputList) 63 | disassemblerInputList = [] 64 | hexCharacterInputList = [] 65 | booleanTextInputList = [] 66 | dataList = [] 67 | for interpolation in interpolationList: 68 | address = getTerminalAddress(interpolation) 69 | if interpolation.type is InterpolationType.INSTRUCTION: 70 | length = 32 71 | disassemblerInputList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}'.format(address, address + length, next(inputIter))) 72 | source = 'disassemblerOutput' 73 | dataList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}[{} - 8 * (nextTerminalAddress - {}) -: 8]'.format(address, address + length, source, length * 8 - 1, address)) 74 | elif interpolation.type is InterpolationType.HEX_8: 75 | length = 8 76 | hexCharacterInputList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}[31 - 4 * (nextTerminalAddress - {}) -: 4]'.format(address, address + length, next(inputIter), address)) 77 | source = 'hexCharacterOutput' 78 | dataList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}'.format(address, address + length, source)) 79 | elif interpolation.type is InterpolationType.HEX_2: 80 | length = 2 81 | hexCharacterInputList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}[7 - 4 * (nextTerminalAddress - {}) -: 4]'.format(address, address + length, next(inputIter), address)) 82 | source = 'hexCharacterOutput' 83 | dataList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}'.format(address, address + length, source)) 84 | elif interpolation.type is InterpolationType.BOOLEAN: 85 | length = 5 86 | booleanTextInputList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}'.format(address, address + length, next(inputIter))) 87 | source = 'booleanTextOutput' 88 | dataList.append('nextTerminalAddress >= {} && nextTerminalAddress < {} ? {}[{} - 8 * (nextTerminalAddress - {}) -: 8]'.format(address, address + length, source, length * 8 - 1, address)) 89 | 90 | try: 91 | next(inputIter) 92 | raise AssertionError('Input is not fully consumed') 93 | except StopIteration: 94 | pass 95 | 96 | def printLineList(firstLine, lineList, lastLine = None): 97 | print(firstLine) 98 | isFirst = True 99 | for line in lineList: 100 | print(' ', end='') 101 | if isFirst: 102 | isFirst = False 103 | else: 104 | print(': ', end='') 105 | print(line) 106 | if lastLine: 107 | print(' : {};'.format(lastLine)) 108 | 109 | printLineList('wire [31:0] disassemblerInput =', disassemblerInputList, '32\'hFFFFFFFF') 110 | print() 111 | printLineList('wire [3:0] hexCharacterInput =', hexCharacterInputList, '4\'hF') 112 | print() 113 | printLineList('wire booleanTextInput =', booleanTextInputList, '1\'b1') 114 | print() 115 | printLineList('terminalWriteData <=', dataList, 'backgroundCharacter') 116 | 117 | with open('Background.coe', 'w') as backgroundFile: 118 | print('''memory_initialization_radix=16; 119 | memory_initialization_vector=''', file=backgroundFile) 120 | isFirst = True 121 | for line in designLineList: 122 | for character in line: 123 | if isFirst: 124 | isFirst = False 125 | else: 126 | print(', ', end='', file=backgroundFile) 127 | print("{:02x}".format(ord(character)), end='', file=backgroundFile) 128 | print(';', file=backgroundFile) 129 | 130 | print() 131 | print('NOTICE: Please copy Background.coe to ipcore_dir/ and regenerate core.') 132 | -------------------------------------------------------------------------------- /IdStage.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IdStage ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | input [31:0] pc_4, 9 | 10 | input [31:0] instruction, 11 | 12 | output shouldJumpOrBranch, // BRANCH 13 | output [31:0] jumpOrBranchPc, 14 | 15 | output [31:0] shiftAmount, 16 | output [31:0] immediate, 17 | 18 | output [31:0] registerRsOrPc_4, 19 | output [31:0] registerRtOrZero, 20 | 21 | output [3:0] aluOperation, // ALUC 22 | output shouldAluUseShiftAmountElseRegisterRsOrPc_4, // SHIFT 23 | output shouldAluUseImmeidateElseRegisterRtOrZero, // ALUIMM 24 | 25 | output shouldWriteRegister, // WREG 26 | output [4:0] registerWriteAddress, 27 | output shouldWriteMemoryElseAluOutputToRegister, // M2REG 28 | 29 | output shouldWriteMemory, // WMEM 30 | 31 | input wb_shouldWriteRegister, 32 | input [4:0] wb_registerWriteAddress, 33 | input [31:0] wb_registerWriteData, 34 | 35 | input ex_shouldWriteRegister, 36 | input [4:0] ex_registerWriteAddress, 37 | input ex_shouldWriteMemoryElseAluOutputToRegister, 38 | input [31:0] ex_aluOutput, 39 | input mem_shouldWriteRegister, 40 | input [4:0] mem_registerWriteAddress, 41 | input mem_shouldWriteMemoryElseAluOutputToRegister, 42 | input [31:0] mem_aluOutput, 43 | input [31:0] mem_memoryData, 44 | output shouldStall, // WPCIR 45 | 46 | output debug_shouldForwardRegisterRs, 47 | output debug_shouldForwardRegisterRt, 48 | output [32 * 32 - 1 : 0] debug_registers 49 | ); 50 | 51 | wire isJumpIndex; // JUMP 52 | wire [25:0] jumpIndex; // address 53 | wire isJumpRegister; // JR 54 | wire isRegisterRsRtEqual; // RSRTEQU 55 | wire isJumpAndLink; // JAL 56 | wire shouldSignElseZeroExtendImmediate; // SEXT 57 | wire shouldWriteToRegisterRtElseRd; // REGRT 58 | wire shouldForwardRegisterRsWithExStageAluOutput; 59 | wire shouldForwardRegisterRsWithMemStageAluOutput; 60 | wire shouldForwardRegisterRsWithMemStageMemoryData; 61 | wire shouldForwardRegisterRtWithExStageAluOutput; 62 | wire shouldForwardRegisterRtWithMemStageAluOutput; 63 | wire shouldForwardRegisterRtWithMemStageMemoryData; 64 | ControlUnit controlUnit ( 65 | 66 | .instruction(instruction[31:0]), 67 | 68 | .isJumpIndex(isJumpIndex), 69 | .jumpIndex(jumpIndex[25:0]), 70 | .isJumpRegister(isJumpRegister), 71 | .isRegisterRsRtEqual(isRegisterRsRtEqual), 72 | .shouldJumpOrBranch(shouldJumpOrBranch), 73 | .isJumpAndLink(isJumpAndLink), 74 | 75 | .shouldSignElseZeroExtendImmediate(shouldSignElseZeroExtendImmediate), 76 | 77 | .aluOperation(aluOperation[3:0]), 78 | .shouldAluUseShiftAmountElseRegisterRsOrPc_4(shouldAluUseShiftAmountElseRegisterRsOrPc_4), 79 | .shouldAluUseImmeidateElseRegisterRtOrZero(shouldAluUseImmeidateElseRegisterRtOrZero), 80 | 81 | .shouldWriteRegister(shouldWriteRegister), 82 | .shouldWriteToRegisterRtElseRd(shouldWriteToRegisterRtElseRd), 83 | .shouldWriteMemoryElseAluOutputToRegister(shouldWriteMemoryElseAluOutputToRegister), 84 | 85 | .shouldWriteMemory(shouldWriteMemory), 86 | 87 | .ex_shouldWriteRegister(ex_shouldWriteRegister), 88 | .ex_registerWriteAddress(ex_registerWriteAddress[4:0]), 89 | .ex_shouldWriteMemoryElseAluOutputToRegister(ex_shouldWriteMemoryElseAluOutputToRegister), 90 | .mem_shouldWriteRegister(mem_shouldWriteRegister), 91 | .mem_registerWriteAddress(mem_registerWriteAddress[4:0]), 92 | .mem_shouldWriteMemoryElseAluOutputToRegister(mem_shouldWriteMemoryElseAluOutputToRegister), 93 | .shouldStall(shouldStall), 94 | .shouldForwardRegisterRsWithExStageAluOutput(shouldForwardRegisterRsWithExStageAluOutput), 95 | .shouldForwardRegisterRsWithMemStageAluOutput(shouldForwardRegisterRsWithMemStageAluOutput), 96 | .shouldForwardRegisterRsWithMemStageMemoryData(shouldForwardRegisterRsWithMemStageMemoryData), 97 | .shouldForwardRegisterRtWithExStageAluOutput(shouldForwardRegisterRtWithExStageAluOutput), 98 | .shouldForwardRegisterRtWithMemStageAluOutput(shouldForwardRegisterRtWithMemStageAluOutput), 99 | .shouldForwardRegisterRtWithMemStageMemoryData(shouldForwardRegisterRtWithMemStageMemoryData) 100 | ); 101 | 102 | assign shiftAmount = {27'b0, instruction[10:6]}; 103 | wire [15:0] instructionImmediate = instruction[15:0]; 104 | assign immediate = { 105 | shouldSignElseZeroExtendImmediate ? {16{instructionImmediate[15]}} : 16'b0, 106 | instructionImmediate 107 | }; 108 | 109 | wire [4:0] rs = instruction[25:21]; 110 | wire [4:0] rt = instruction[20:16]; 111 | wire [4:0] rd = instruction[15:11]; 112 | 113 | assign registerWriteAddress = 114 | isJumpAndLink ? 5'd31 115 | : shouldWriteToRegisterRtElseRd ? rt : rd; 116 | 117 | wire [31:0] localRegisterRs; 118 | wire [31:0] localRegisterRt; 119 | RegisterFile registerFile ( 120 | 121 | .clock(clock), 122 | .reset(reset), 123 | 124 | .readAddressA(rs[4:0]), 125 | .readDataA(localRegisterRs[31:0]), 126 | .readAddressB(rt[4:0]), 127 | .readDataB(localRegisterRt[31:0]), 128 | 129 | .shouldWrite(wb_shouldWriteRegister), 130 | .writeAddress(wb_registerWriteAddress[4:0]), 131 | .writeData(wb_registerWriteData[31:0]), 132 | 133 | .debug_registers(debug_registers[32 * 32 - 1 : 0]) 134 | ); 135 | 136 | wire [31:0] registerRs = 137 | shouldForwardRegisterRsWithExStageAluOutput ? ex_aluOutput 138 | : shouldForwardRegisterRsWithMemStageAluOutput ? mem_aluOutput 139 | : shouldForwardRegisterRsWithMemStageMemoryData ? mem_memoryData 140 | : localRegisterRs; 141 | wire [31:0] registerRt = 142 | shouldForwardRegisterRtWithExStageAluOutput ? ex_aluOutput 143 | : shouldForwardRegisterRtWithMemStageAluOutput ? mem_aluOutput 144 | : shouldForwardRegisterRtWithMemStageMemoryData ? mem_memoryData 145 | : localRegisterRt; 146 | assign debug_shouldForwardRegisterRs = shouldForwardRegisterRsWithExStageAluOutput || shouldForwardRegisterRsWithMemStageAluOutput || shouldForwardRegisterRsWithMemStageMemoryData; 147 | assign debug_shouldForwardRegisterRt = shouldForwardRegisterRtWithExStageAluOutput || shouldForwardRegisterRtWithMemStageAluOutput || shouldForwardRegisterRtWithMemStageMemoryData; 148 | 149 | assign registerRsOrPc_4 = isJumpAndLink ? pc_4 : registerRs; 150 | assign registerRtOrZero = isJumpAndLink ? 32'b0 : registerRt; 151 | 152 | assign isRegisterRsRtEqual = registerRs == registerRt; 153 | wire [31:0] jumpIndexPc = {pc_4[31:28], jumpIndex, 2'b0}; 154 | wire [31:0] branchPc = pc_4 + {immediate[29:0], 2'b0}; 155 | assign jumpOrBranchPc = 156 | isJumpRegister ? registerRs 157 | : isJumpIndex ? jumpIndexPc 158 | : branchPc; 159 | endmodule 160 | -------------------------------------------------------------------------------- /Disassembler.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | `include "Constants.vh" 4 | 5 | module Disassembler ( 6 | 7 | input [31:0] instruction, 8 | 9 | output [32 * 8 - 1 : 0] text 10 | ); 11 | 12 | wire [5:0] code = instruction[31:26]; 13 | wire [4:0] rs = instruction[25:21]; 14 | wire [4:0] rt = instruction[20:16]; 15 | wire [4:0] rd = instruction[15:11]; 16 | wire [4:0] shiftAmount = instruction[10:6]; 17 | wire [5:0] function_ = instruction[5:0]; 18 | wire [15:0] immediate = instruction[15:0]; 19 | //wire [15:0] offset = immediate; 20 | wire [4:0] base = rs; 21 | wire [25:0] index = instruction[25:0]; 22 | 23 | function [7:0] getDecimalFirstCharacter ( 24 | input [4:0] decimal 25 | ); 26 | getDecimalFirstCharacter = 27 | decimal < 5'd10 ? decimal + "0" 28 | : decimal < 5'd20 ? "1" 29 | : decimal < 5'd30 ? "2" 30 | : "3"; 31 | endfunction 32 | 33 | function [7:0] getDecimalSecondCharacter ( 34 | input [4:0] decimal 35 | ); 36 | getDecimalSecondCharacter = 37 | decimal < 5'd10 ? 8'b0 38 | : decimal < 5'd20 ? (decimal - 5'd10) + "0" 39 | : decimal < 5'd30 ? (decimal - 5'd20) + "0" 40 | : (decimal - 5'd30) + "0"; 41 | endfunction 42 | 43 | function [8 * 8 - 1 : 0] getRegisterText ( 44 | input [4:0] register, 45 | input [7:0] terminator 46 | ); 47 | getRegisterText = 48 | register < 5'd10 ? {"$", getDecimalFirstCharacter(register[4:0]), terminator, " "} 49 | : {"$", getDecimalFirstCharacter(register[4:0]), getDecimalSecondCharacter(register[4:0]), terminator, " "}; 50 | endfunction 51 | 52 | function [8 * 8 - 1 : 0] getShiftAmountText ( 53 | input [4:0] shiftAmount 54 | ); 55 | getShiftAmountText = 56 | shiftAmount < 5'd10 ? {getDecimalFirstCharacter(shiftAmount[4:0]), " "} 57 | : {getDecimalFirstCharacter(shiftAmount[4:0]), getDecimalSecondCharacter(shiftAmount[4:0]), " "}; 58 | endfunction 59 | 60 | function [7:0] getHexCharacter ( 61 | input [3:0] hex 62 | ); 63 | getHexCharacter = hex < 4'd10 ? hex + "0" : (hex - 4'd10) + "A"; 64 | endfunction 65 | 66 | function [8 * 8 - 1 : 0] getImmediateText ( 67 | input [15:0] immediate 68 | ); 69 | getImmediateText = {"0x", getHexCharacter(immediate[15:12]), getHexCharacter(immediate[11:8]), getHexCharacter(immediate[7:4]), getHexCharacter(immediate[3:0]), " "}; 70 | endfunction 71 | 72 | function [8 * 8 - 1 : 0] getBaseText ( 73 | input [4:0] base 74 | ); 75 | getBaseText = 76 | base < 5'd10 ? {"($", getDecimalFirstCharacter(base[4:0]), ") "} 77 | : {"($", getDecimalFirstCharacter(base[4:0]), getDecimalSecondCharacter(base[4:0]), ") "}; 78 | endfunction 79 | 80 | function [16 * 8 - 1 : 0] getIndexText ( 81 | input [25:0] index 82 | ); 83 | getIndexText = {"0x", getHexCharacter({2'b0, index[25:24]}), getHexCharacter(index[23:20]), getHexCharacter(index[19:16]), getHexCharacter(index[15:12]), getHexCharacter(index[11:8]), getHexCharacter(index[7:4]), getHexCharacter(index[3:0]), " "}; 84 | endfunction 85 | 86 | wire [8 * 8 - 1 : 0] spaceText = {8{" "}}; 87 | wire [8 * 8 - 1 : 0] rsText = getRegisterText(rs[4:0], " "); 88 | wire [8 * 8 - 1 : 0] rsCommaText = getRegisterText(rs[4:0], ","); 89 | wire [8 * 8 - 1 : 0] rtText = getRegisterText(rt[4:0], " "); 90 | wire [8 * 8 - 1 : 0] rtCommaText = getRegisterText(rt[4:0], ","); 91 | wire [8 * 8 - 1 : 0] rdText = getRegisterText(rd[4:0], " "); 92 | wire [8 * 8 - 1 : 0] rdCommaText = getRegisterText(rd[4:0], ","); 93 | wire [8 * 8 - 1 : 0] shiftAmountText = getShiftAmountText(shiftAmount[4:0]); 94 | wire [8 * 8 - 1 : 0] immediateText = getImmediateText(immediate[15:0]); 95 | wire [8 * 8 - 1 : 0] offsetText = immediateText; 96 | wire [8 * 8 - 1 : 0] baseText = getBaseText(base[4:0]); 97 | wire [16 * 8 - 1 : 0] indexText = getIndexText(index[25:0]); 98 | wire [32 * 8 - 1 : 0] unknownText = {" ", spaceText, spaceText}; 99 | 100 | assign text = 101 | instruction == 32'b0 ? {"nop ", spaceText, spaceText, spaceText} 102 | : code == `CODE_R_TYPE ? ( 103 | function_ == `FUNCTION_ADD ? {"add ", rdCommaText, rsCommaText, rtText} 104 | : function_ == `FUNCTION_ADDU ? {"addu ", rdCommaText, rsCommaText, rtText} 105 | : function_ == `FUNCTION_SUB ? {"sub ", rdCommaText, rsCommaText, rtText} 106 | : function_ == `FUNCTION_SUBU ? {"subu ", rdCommaText, rsCommaText, rtText} 107 | : function_ == `FUNCTION_AND ? {"and ", rdCommaText, rsCommaText, rtText} 108 | : function_ == `FUNCTION_OR ? {"or ", rdCommaText, rsCommaText, rtText} 109 | : function_ == `FUNCTION_XOR ? {"xor ", rdCommaText, rsCommaText, rtText} 110 | : function_ == `FUNCTION_NOR ? {"nor ", rdCommaText, rsCommaText, rtText} 111 | : function_ == `FUNCTION_SLT ? {"slt ", rdCommaText, rsCommaText, rtText} 112 | : function_ == `FUNCTION_SLTU ? {"sltu ", rdCommaText, rsCommaText, rtText} 113 | : function_ == `FUNCTION_SLL ? {"sll ", rdCommaText, rtCommaText, shiftAmountText} 114 | : function_ == `FUNCTION_SRL ? {"srl ", rdCommaText, rtCommaText, shiftAmountText} 115 | : function_ == `FUNCTION_SRA ? {"sra ", rdCommaText, rtCommaText, shiftAmountText} 116 | : function_ == `FUNCTION_SLLV ? {"sllv ", rdCommaText, rtCommaText, rsText} 117 | : function_ == `FUNCTION_SRLV ? {"srlv ", rdCommaText, rtCommaText, rsText} 118 | : function_ == `FUNCTION_SRAV ? {"srav ", rdCommaText, rtCommaText, rsText} 119 | : function_ == `FUNCTION_JR ? {"jr ", spaceText, spaceText, spaceText} 120 | : unknownText 121 | ) 122 | : code == `CODE_ADDI ? {"addi ", rtCommaText, rsCommaText, immediateText} 123 | : code == `CODE_ADDIU ? {"addiu ", rtCommaText, rsCommaText, immediateText} 124 | : code == `CODE_ANDI ? {"andi ", rtCommaText, rsCommaText, immediateText} 125 | : code == `CODE_ORI ? {"ori ", rtCommaText, rsCommaText, immediateText} 126 | : code == `CODE_XORI ? {"xori ", rtCommaText, rsCommaText, immediateText} 127 | : code == `CODE_LUI ? {"lui ", rtCommaText, immediateText, spaceText} 128 | : code == `CODE_LW ? {"lw ", rtCommaText, offsetText, baseText} 129 | : code == `CODE_SW ? {"sw ", rtCommaText, offsetText, baseText} 130 | : code == `CODE_BEQ ? {"beq ", rsCommaText, rtCommaText, offsetText} 131 | : code == `CODE_BNE ? {"bne ", rsCommaText, rtCommaText, offsetText} 132 | : code == `CODE_SLTI ? {"slti ", rtCommaText, rsCommaText, immediateText} 133 | : code == `CODE_SLTIU ? {"sltiu ", rtCommaText, rsCommaText, immediateText} 134 | : code == `CODE_J ? {"j ", indexText, spaceText} 135 | : code == `CODE_JAL ? {"jal ", indexText, spaceText} 136 | : unknownText; 137 | endmodule 138 | -------------------------------------------------------------------------------- /ControlUnit.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | `include "Constants.vh" 4 | 5 | module ControlUnit ( 6 | 7 | input [31:0] instruction, 8 | 9 | output isJumpIndex, // JUMP 10 | output [25:0] jumpIndex, // address 11 | output isJumpRegister, // JR, but not JALR yet 12 | input isRegisterRsRtEqual, // RSRTEQU 13 | output shouldJumpOrBranch, // BRANCH 14 | output isJumpAndLink, // JAL 15 | 16 | output shouldSignElseZeroExtendImmediate, // SEXT 17 | 18 | output [3:0] aluOperation, // ALUC 19 | output shouldAluUseShiftAmountElseRegisterRsOrPc_4, // SHIFT 20 | output shouldAluUseImmeidateElseRegisterRtOrZero, // ALUIMM 21 | 22 | output shouldWriteRegister, // WREG 23 | output shouldWriteToRegisterRtElseRd, // REGRT 24 | output shouldWriteMemoryElseAluOutputToRegister, // M2REG 25 | 26 | output shouldWriteMemory, // WMEM 27 | 28 | input ex_shouldWriteRegister, 29 | input [4:0] ex_registerWriteAddress, 30 | input ex_shouldWriteMemoryElseAluOutputToRegister, 31 | input mem_shouldWriteRegister, 32 | input [4:0] mem_registerWriteAddress, 33 | input mem_shouldWriteMemoryElseAluOutputToRegister, 34 | output shouldStall, // WPCIR 35 | output shouldForwardRegisterRsWithExStageAluOutput, 36 | output shouldForwardRegisterRsWithMemStageAluOutput, 37 | output shouldForwardRegisterRsWithMemStageMemoryData, 38 | output shouldForwardRegisterRtWithExStageAluOutput, 39 | output shouldForwardRegisterRtWithMemStageAluOutput, 40 | output shouldForwardRegisterRtWithMemStageMemoryData 41 | ); 42 | 43 | wire [5:0] code = instruction[31:26]; 44 | wire [5:0] function_ = instruction[5:0]; 45 | 46 | assign isJumpIndex = code == `CODE_J || code == `CODE_JAL; 47 | assign jumpIndex = instruction[25:0]; 48 | // TODO: JALR 49 | assign isJumpAndLink = code == `CODE_JAL; 50 | wire isRType = code == `CODE_R_TYPE; 51 | // TODO: JALR 52 | assign isJumpRegister = isRType && function_ == `FUNCTION_JR; 53 | wire isBeq = code == `CODE_BEQ; 54 | wire isBranch = isBeq || code == `CODE_BNE; 55 | wire shouldBranch = isBranch && (isBeq == isRegisterRsRtEqual); 56 | assign shouldJumpOrBranch = isJumpIndex || isJumpRegister || shouldBranch; 57 | 58 | assign shouldSignElseZeroExtendImmediate = 59 | code == `CODE_ADDI 60 | || code == `CODE_ADDIU 61 | || code == `CODE_LW 62 | || code == `CODE_SW 63 | || code == `CODE_BEQ 64 | || code == `CODE_BNE 65 | || code == `CODE_SLTI; 66 | assign aluOperation = 67 | isJumpAndLink ? `ALU_ADD // pc_4 + 0 68 | : isRType ? ( 69 | function_ == `FUNCTION_ADD ? `ALU_ADD 70 | : function_ == `FUNCTION_ADDU ? `ALU_ADDU 71 | : function_ == `FUNCTION_SUB ? `ALU_SUB 72 | : function_ == `FUNCTION_SUBU ? `ALU_SUBU 73 | : function_ == `FUNCTION_AND ? `ALU_AND 74 | : function_ == `FUNCTION_OR ? `ALU_OR 75 | : function_ == `FUNCTION_XOR ? `ALU_XOR 76 | : function_ == `FUNCTION_NOR ? `ALU_NOR 77 | : function_ == `FUNCTION_SLT ? `ALU_SUB 78 | : function_ == `FUNCTION_SLTU ? `ALU_SUBU 79 | : function_ == `FUNCTION_SLL ? `ALU_SLL 80 | : function_ == `FUNCTION_SRL ? `ALU_SRL 81 | : function_ == `FUNCTION_SRA ? `ALU_SRA 82 | : function_ == `FUNCTION_SLLV ? `ALU_SLL 83 | : function_ == `FUNCTION_SRLV ? `ALU_SRL 84 | : function_ == `FUNCTION_SRAV ? `ALU_SRA 85 | : `ALU_NONE 86 | ) 87 | : code == `CODE_ADDI ? `ALU_ADD 88 | : code == `CODE_ADDIU ? `ALU_ADDU 89 | : code == `CODE_ANDI ? `ALU_AND 90 | : code == `CODE_ORI ? `ALU_OR 91 | : code == `CODE_XORI ? `ALU_XOR 92 | : code == `CODE_LUI ? `ALU_SLL // HIGHLIGHT 93 | : code == `CODE_LW ? `ALU_ADD 94 | : code == `CODE_SW ? `ALU_ADD 95 | : code == `CODE_BEQ ? `ALU_SUB 96 | : code == `CODE_BNE ? `ALU_SUB 97 | : code == `CODE_SLTI ? `ALU_SUB 98 | : code == `CODE_SLTIU ? `ALU_SUBU 99 | : `ALU_NONE; 100 | assign shouldAluUseShiftAmountElseRegisterRsOrPc_4 = 101 | !isJumpAndLink // pc_4 102 | && (isRType && ( 103 | function_ == `FUNCTION_SLL 104 | || function_ == `FUNCTION_SRL 105 | || function_ == `FUNCTION_SRA 106 | )); 107 | assign shouldAluUseImmeidateElseRegisterRtOrZero = 108 | !isJumpAndLink // 0 109 | && ( 110 | code == `CODE_ADDI 111 | || code == `CODE_ADDIU 112 | || code == `CODE_ANDI 113 | || code == `CODE_ORI 114 | || code == `CODE_XORI 115 | || code == `CODE_LUI // TODO: Correct? 116 | || code == `CODE_LW 117 | || code == `CODE_SW 118 | || code == `CODE_SLTI 119 | || code == `CODE_SLTIU 120 | ); 121 | 122 | assign shouldWriteToRegisterRtElseRd = 123 | code == `CODE_ADDI 124 | || code == `CODE_ADDIU 125 | || code == `CODE_ANDI 126 | || code == `CODE_ORI 127 | || code == `CODE_XORI 128 | || code == `CODE_LUI 129 | || code == `CODE_LW 130 | || code == `CODE_SLTI 131 | || code == `CODE_SLTIU; 132 | assign shouldWriteRegister = 133 | (isRType && ( 134 | function_ == `FUNCTION_ADD 135 | || function_ == `FUNCTION_ADDU 136 | || function_ == `FUNCTION_SUB 137 | || function_ == `FUNCTION_SUBU 138 | || function_ == `FUNCTION_AND 139 | || function_ == `FUNCTION_OR 140 | || function_ == `FUNCTION_XOR 141 | || function_ == `FUNCTION_NOR 142 | || function_ == `FUNCTION_SLT 143 | || function_ == `FUNCTION_SLTU 144 | || function_ == `FUNCTION_SLL 145 | || function_ == `FUNCTION_SRL 146 | || function_ == `FUNCTION_SRA 147 | || function_ == `FUNCTION_SLLV 148 | || function_ == `FUNCTION_SRLV 149 | || function_ == `FUNCTION_SRAV 150 | )) 151 | || shouldWriteToRegisterRtElseRd 152 | || isJumpAndLink; 153 | assign shouldWriteMemoryElseAluOutputToRegister = code == `CODE_LW; 154 | 155 | assign shouldWriteMemory = code == `CODE_SW; 156 | 157 | wire [4:0] rs = instruction[25:21]; 158 | wire [4:0] rt = instruction[20:16]; 159 | wire willExStageWriteRegisterRs = ex_shouldWriteRegister && ex_registerWriteAddress == rs; 160 | wire willExStageWriteRegisterRt = ex_shouldWriteRegister && ex_registerWriteAddress == rt; 161 | wire willMemStageWriteRegisterRs = mem_shouldWriteRegister && mem_registerWriteAddress == rs; 162 | wire willMemStageWriteRegisterRt = mem_shouldWriteRegister && mem_registerWriteAddress == rt; 163 | assign shouldStall = (willExStageWriteRegisterRs || willExStageWriteRegisterRt) && ex_shouldWriteMemoryElseAluOutputToRegister; 164 | assign shouldForwardRegisterRsWithExStageAluOutput = willExStageWriteRegisterRs && !ex_shouldWriteMemoryElseAluOutputToRegister; 165 | assign shouldForwardRegisterRsWithMemStageAluOutput = willMemStageWriteRegisterRs && !mem_shouldWriteMemoryElseAluOutputToRegister; 166 | assign shouldForwardRegisterRsWithMemStageMemoryData = willMemStageWriteRegisterRs && mem_shouldWriteMemoryElseAluOutputToRegister; 167 | assign shouldForwardRegisterRtWithExStageAluOutput = willExStageWriteRegisterRt && !ex_shouldWriteMemoryElseAluOutputToRegister; 168 | assign shouldForwardRegisterRtWithMemStageAluOutput = willMemStageWriteRegisterRt && !mem_shouldWriteMemoryElseAluOutputToRegister; 169 | assign shouldForwardRegisterRtWithMemStageMemoryData = willMemStageWriteRegisterRt && mem_shouldWriteMemoryElseAluOutputToRegister; 170 | endmodule 171 | -------------------------------------------------------------------------------- /ipcore_dir/Background.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 50, 69, 70, 65, 6c, 69, 6e, 65, 64, 20, 43, 50, 55, 20, 44, 65, 62, 75, 67, 67, 65, 72, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 4d, 61, 64, 65, 20, 62, 79, 20, 5a, 68, 61, 6e, 67, 20, 48, 61, 69, 20, 77, 69, 74, 68, 20, 03, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 49, 46, 20, 53, 74, 61, 67, 65, 3a, 20, 6e, 6f, 70, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 50, 43, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 4e, 65, 78, 74, 20, 50, 43, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 49, 44, 20, 53, 74, 61, 67, 65, 3a, 20, 6e, 6f, 70, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 53, 74, 61, 6c, 6c, 3a, 20, 54, 72, 75, 65, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 46, 6f, 72, 77, 61, 72, 64, 20, 52, 73, 3a, 20, 54, 72, 75, 65, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 46, 6f, 72, 77, 61, 72, 64, 20, 52, 74, 3a, 20, 54, 72, 75, 65, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 52, 65, 67, 69, 73, 74, 65, 72, 73, 3a, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 45, 58, 20, 53, 74, 61, 67, 65, 3a, 20, 6e, 6f, 70, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 41, 4c, 55, 20, 49, 6e, 70, 75, 74, 20, 41, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 41, 4c, 55, 20, 49, 6e, 70, 75, 74, 20, 42, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 41, 4c, 55, 20, 4f, 75, 74, 70, 75, 74, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 4d, 45, 4d, 20, 53, 74, 61, 67, 65, 3a, 20, 6e, 6f, 70, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 4d, 65, 6d, 6f, 72, 79, 20, 41, 64, 64, 72, 65, 73, 73, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 4d, 65, 6d, 6f, 72, 79, 20, 52, 65, 61, 64, 20, 44, 61, 74, 61, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 4d, 65, 6d, 6f, 72, 79, 20, 57, 72, 69, 74, 65, 20, 45, 6e, 61, 62, 6c, 65, 64, 3a, 20, 54, 72, 75, 65, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 4d, 65, 6d, 6f, 72, 79, 20, 57, 72, 69, 74, 65, 20, 44, 61, 74, 61, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 3d, 57, 42, 20, 53, 74, 61, 67, 65, 3a, 20, 6e, 6f, 70, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 52, 65, 67, 69, 73, 74, 65, 72, 20, 57, 72, 69, 74, 65, 20, 45, 6e, 61, 62, 6c, 65, 64, 3a, 20, 54, 72, 75, 65, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 52, 65, 67, 69, 73, 74, 65, 72, 20, 57, 72, 69, 74, 65, 20, 41, 64, 64, 72, 65, 73, 73, 3a, 20, 30, 78, 41, 41, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 52, 65, 67, 69, 73, 74, 65, 72, 20, 57, 72, 69, 74, 65, 20, 44, 61, 74, 61, 3a, 20, 30, 78, 46, 46, 46, 46, 46, 46, 46, 46, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20; 4 | -------------------------------------------------------------------------------- /Cpu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Cpu ( 4 | 5 | input clock, 6 | input reset, 7 | 8 | output [31:0] debug_if_pc, 9 | output [31:0] debug_if_nextPc, 10 | output [31:0] debug_if_instruction, 11 | output [31:0] debug_id_instruction, 12 | output debug_id_shouldStall, 13 | output debug_id_shouldForwardRegisterRs, 14 | output debug_id_shouldForwardRegisterRt, 15 | output [32 * 32 - 1 : 0] debug_id_registers, 16 | output [31:0] debug_ex_instruction, 17 | output [31:0] debug_ex_aluInputA, 18 | output [31:0] debug_ex_aluInputB, 19 | output [31:0] debug_ex_aluOutput, 20 | output [31:0] debug_mem_instruction, 21 | output [31:0] debug_mem_memoryAddress, 22 | output [31:0] debug_mem_memoryReadData, 23 | output debug_mem_shouldWriteMemory, 24 | output [31:0] debug_mem_memoryWriteData, 25 | output [31:0] debug_wb_instruction, 26 | output debug_wb_shouldWriteRegister, 27 | output [4:0] debug_wb_registerWriteAddress, 28 | output [31:0] debug_wb_registerWriteData 29 | ); 30 | 31 | wire [31:0] if_pc; 32 | 33 | wire [31:0] if_pc_4; 34 | wire [31:0] if_instruction; 35 | wire [31:0] if_nextPc; 36 | 37 | wire [31:0] id_pc_4; 38 | wire [31:0] id_instruction; 39 | 40 | wire id_shouldJumpOrBranch; 41 | wire [31:0] id_jumpOrBranchPc; 42 | wire [31:0] id_shiftAmount; 43 | wire [31:0] id_immediate; 44 | wire [31:0] id_registerRsOrPc_4; 45 | wire [31:0] id_registerRtOrZero; 46 | wire [3:0] id_aluOperation; 47 | wire id_shouldAluUseShiftAmountElseRegisterRsOrPc_4; 48 | wire id_shouldAluUseImmeidateElseRegisterRtOrZero; 49 | wire id_shouldWriteRegister; 50 | wire [4:0] id_registerWriteAddress; 51 | wire id_shouldWriteMemoryElseAluOutputToRegister; 52 | wire id_shouldWriteMemory; 53 | wire id_shouldStall; 54 | 55 | wire [31:0] ex_instruction; 56 | wire [31:0] ex_shiftAmount; 57 | wire [31:0] ex_immediate; 58 | wire [31:0] ex_registerRsOrPc_4; 59 | wire [31:0] ex_registerRtOrZero; 60 | wire [3:0] ex_aluOperation; 61 | wire ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4; 62 | wire ex_shouldAluUseImmeidateElseRegisterRtOrZero; 63 | wire ex_shouldWriteRegister; 64 | wire [4:0] ex_registerWriteAddress; 65 | wire ex_shouldWriteMemoryElseAluOutputToRegister; 66 | wire ex_shouldWriteMemory; 67 | 68 | wire [31:0] ex_aluOutput; 69 | 70 | wire [31:0] mem_instruction; 71 | wire mem_shouldWriteRegister; 72 | wire [4:0] mem_registerWriteAddress; 73 | wire mem_shouldWriteMemoryElseAluOutputToRegister; 74 | wire [31:0] mem_aluOutput; 75 | wire mem_shouldWriteMemory; 76 | wire [31:0] mem_registerRtOrZero; 77 | 78 | wire [31:0] mem_memoryData; 79 | 80 | wire [31:0] wb_instruction; 81 | wire wb_shouldWriteRegister; 82 | wire [4:0] wb_registerWriteAddress; 83 | wire wb_shouldWriteMemoryElseAluOutputToRegister; 84 | wire [31:0] wb_memoryData; 85 | wire [31:0] wb_aluOutput; 86 | 87 | wire [31:0] wb_registerWriteData; 88 | 89 | Pc pc ( 90 | 91 | .clock(clock), 92 | .reset(reset), 93 | 94 | .id_shouldStall(id_shouldStall), 95 | 96 | .nextPc(if_nextPc[31:0]), 97 | .pc(if_pc[31:0]) 98 | ); 99 | 100 | IfStage ifStage ( 101 | 102 | .clock(clock), 103 | 104 | .pc(if_pc[31:0]), 105 | 106 | .id_shouldJumpOrBranch(id_shouldJumpOrBranch), 107 | .id_jumpOrBranchPc(id_jumpOrBranchPc[31:0]), 108 | 109 | .pc_4(if_pc_4[31:0]), 110 | 111 | .instruction(if_instruction[31:0]), 112 | 113 | .nextPc(if_nextPc[31:0]) 114 | ); 115 | 116 | IfIdRegisters ifIdRegisters ( 117 | 118 | .clock(clock), 119 | .reset(reset), 120 | 121 | .id_shouldStall(id_shouldStall), 122 | 123 | .if_pc_4(if_pc_4[31:0]), 124 | 125 | .if_instruction(if_instruction[31:0]), 126 | 127 | .id_pc_4(id_pc_4[31:0]), 128 | 129 | .id_instruction(id_instruction[31:0]) 130 | ); 131 | 132 | IdStage idStage ( 133 | 134 | .clock(clock), 135 | .reset(reset), 136 | 137 | .pc_4(id_pc_4[31:0]), 138 | 139 | .instruction(id_instruction[31:0]), 140 | 141 | .shouldJumpOrBranch(id_shouldJumpOrBranch), 142 | .jumpOrBranchPc(id_jumpOrBranchPc[31:0]), 143 | 144 | .shiftAmount(id_shiftAmount[31:0]), 145 | .immediate(id_immediate[31:0]), 146 | 147 | .registerRsOrPc_4(id_registerRsOrPc_4[31:0]), 148 | .registerRtOrZero(id_registerRtOrZero[31:0]), 149 | 150 | .aluOperation(id_aluOperation[3:0]), 151 | .shouldAluUseShiftAmountElseRegisterRsOrPc_4(id_shouldAluUseShiftAmountElseRegisterRsOrPc_4), 152 | .shouldAluUseImmeidateElseRegisterRtOrZero(id_shouldAluUseImmeidateElseRegisterRtOrZero), 153 | 154 | .shouldWriteRegister(id_shouldWriteRegister), 155 | .registerWriteAddress(id_registerWriteAddress[4:0]), 156 | .shouldWriteMemoryElseAluOutputToRegister(id_shouldWriteMemoryElseAluOutputToRegister), 157 | 158 | .shouldWriteMemory(id_shouldWriteMemory), 159 | 160 | .wb_shouldWriteRegister(wb_shouldWriteRegister), 161 | .wb_registerWriteAddress(wb_registerWriteAddress[4:0]), 162 | .wb_registerWriteData(wb_registerWriteData[31:0]), 163 | 164 | .ex_shouldWriteRegister(ex_shouldWriteRegister), 165 | .ex_registerWriteAddress(ex_registerWriteAddress[4:0]), 166 | .ex_shouldWriteMemoryElseAluOutputToRegister(ex_shouldWriteMemoryElseAluOutputToRegister), 167 | .ex_aluOutput(ex_aluOutput[31:0]), 168 | .mem_shouldWriteRegister(mem_shouldWriteRegister), 169 | .mem_registerWriteAddress(mem_registerWriteAddress[4:0]), 170 | .mem_shouldWriteMemoryElseAluOutputToRegister(mem_shouldWriteMemoryElseAluOutputToRegister), 171 | .mem_aluOutput(mem_aluOutput[31:0]), 172 | .mem_memoryData(mem_memoryData[31:0]), 173 | .shouldStall(id_shouldStall), 174 | 175 | .debug_shouldForwardRegisterRs(debug_id_shouldForwardRegisterRs), 176 | .debug_shouldForwardRegisterRt(debug_id_shouldForwardRegisterRt), 177 | .debug_registers(debug_id_registers[32 * 32 - 1 : 0]) 178 | ); 179 | 180 | IdExRegisters idExRegisters ( 181 | 182 | .clock(clock), 183 | .reset(reset), 184 | 185 | .id_shouldStall(id_shouldStall), 186 | 187 | .id_instruction(id_instruction[31:0]), 188 | 189 | .id_shiftAmount(id_shiftAmount[31:0]), 190 | .id_immediate(id_immediate[31:0]), 191 | 192 | .id_registerRsOrPc_4(id_registerRsOrPc_4[31:0]), 193 | .id_registerRtOrZero(id_registerRtOrZero[31:0]), 194 | 195 | .id_aluOperation(id_aluOperation[3:0]), 196 | .id_shouldAluUseShiftAmountElseRegisterRsOrPc_4(id_shouldAluUseShiftAmountElseRegisterRsOrPc_4), 197 | .id_shouldAluUseImmeidateElseRegisterRtOrZero(id_shouldAluUseImmeidateElseRegisterRtOrZero), 198 | 199 | .id_shouldWriteRegister(id_shouldWriteRegister), 200 | .id_registerWriteAddress(id_registerWriteAddress[4:0]), 201 | .id_shouldWriteMemoryElseAluOutputToRegister(id_shouldWriteMemoryElseAluOutputToRegister), 202 | 203 | .id_shouldWriteMemory(id_shouldWriteMemory), 204 | 205 | .ex_instruction(ex_instruction[31:0]), 206 | 207 | .ex_shiftAmount(ex_shiftAmount[31:0]), 208 | .ex_immediate(ex_immediate[31:0]), 209 | 210 | .ex_registerRsOrPc_4(ex_registerRsOrPc_4[31:0]), 211 | .ex_registerRtOrZero(ex_registerRtOrZero[31:0]), 212 | 213 | .ex_aluOperation(ex_aluOperation[3:0]), 214 | .ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4(ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4), 215 | .ex_shouldAluUseImmeidateElseRegisterRtOrZero(ex_shouldAluUseImmeidateElseRegisterRtOrZero), 216 | 217 | .ex_shouldWriteRegister(ex_shouldWriteRegister), 218 | .ex_registerWriteAddress(ex_registerWriteAddress[4:0]), 219 | .ex_shouldWriteMemoryElseAluOutputToRegister(ex_shouldWriteMemoryElseAluOutputToRegister), 220 | 221 | .ex_shouldWriteMemory(ex_shouldWriteMemory) 222 | ); 223 | 224 | ExStage exStage ( 225 | 226 | .shiftAmount(ex_shiftAmount[31:0]), 227 | .immediate(ex_immediate[31:0]), 228 | 229 | .aluOperation(ex_aluOperation[3:0]), 230 | .shouldAluUseShiftAmountElseRegisterRsOrPc_4(ex_shouldAluUseShiftAmountElseRegisterRsOrPc_4), 231 | .shouldAluUseImmeidateElseRegisterRtOrZero(ex_shouldAluUseImmeidateElseRegisterRtOrZero), 232 | 233 | .registerRsOrPc_4(ex_registerRsOrPc_4[31:0]), 234 | .registerRtOrZero(ex_registerRtOrZero[31:0]), 235 | 236 | .aluOutput(ex_aluOutput[31:0]), 237 | 238 | .debug_aluInputA(debug_ex_aluInputA[31:0]), 239 | .debug_aluInputB(debug_ex_aluInputB[31:0]) 240 | ); 241 | 242 | ExMemRegisters exMemRegisters ( 243 | 244 | .clock(clock), 245 | .reset(reset), 246 | 247 | .ex_instruction(ex_instruction[31:0]), 248 | 249 | .ex_shouldWriteRegister(ex_shouldWriteRegister), 250 | .ex_registerWriteAddress(ex_registerWriteAddress[4:0]), 251 | .ex_shouldWriteMemoryElseAluOutputToRegister(ex_shouldWriteMemoryElseAluOutputToRegister), 252 | 253 | .ex_aluOutput(ex_aluOutput[31:0]), 254 | .ex_shouldWriteMemory(ex_shouldWriteMemory), 255 | .ex_registerRtOrZero(ex_registerRtOrZero[31:0]), 256 | 257 | .mem_instruction(mem_instruction[31:0]), 258 | 259 | .mem_shouldWriteRegister(mem_shouldWriteRegister), 260 | .mem_registerWriteAddress(mem_registerWriteAddress[4:0]), 261 | .mem_shouldWriteMemoryElseAluOutputToRegister(mem_shouldWriteMemoryElseAluOutputToRegister), 262 | 263 | .mem_aluOutput(mem_aluOutput[31:0]), 264 | .mem_shouldWriteMemory(mem_shouldWriteMemory), 265 | .mem_registerRtOrZero(mem_registerRtOrZero[31:0]) 266 | ); 267 | 268 | MemStage memStage ( 269 | 270 | .clock(clock), 271 | .reset(reset), 272 | 273 | .aluOutput(mem_aluOutput[31:0]), 274 | .shouldWriteMemory(mem_shouldWriteMemory), 275 | .registerRtOrZero(mem_registerRtOrZero[31:0]), 276 | .memoryData(mem_memoryData[31:0]) 277 | ); 278 | 279 | MemWbRegisters memWbRegisters ( 280 | 281 | .clock(clock), 282 | .reset(reset), 283 | 284 | .mem_instruction(mem_instruction[31:0]), 285 | 286 | .mem_shouldWriteRegister(mem_shouldWriteRegister), 287 | .mem_registerWriteAddress(mem_registerWriteAddress[4:0]), 288 | .mem_shouldWriteMemoryElseAluOutputToRegister(mem_shouldWriteMemoryElseAluOutputToRegister), 289 | .mem_memoryData(mem_memoryData[31:0]), 290 | .mem_aluOutput(mem_aluOutput[31:0]), 291 | 292 | .wb_instruction(wb_instruction[31:0]), 293 | 294 | .wb_shouldWriteRegister(wb_shouldWriteRegister), 295 | .wb_registerWriteAddress(wb_registerWriteAddress[4:0]), 296 | .wb_shouldWriteMemoryElseAluOutputToRegister(wb_shouldWriteMemoryElseAluOutputToRegister), 297 | .wb_memoryData(wb_memoryData[31:0]), 298 | .wb_aluOutput(wb_aluOutput[31:0]) 299 | ); 300 | 301 | WbStage wbStage ( 302 | .shouldWriteMemoryElseAluOutputToRegister(wb_shouldWriteMemoryElseAluOutputToRegister), 303 | .memoryData(wb_memoryData[31:0]), 304 | .aluOutput(wb_aluOutput[31:0]), 305 | .registerWriteData(wb_registerWriteData[31:0]) 306 | ); 307 | 308 | assign debug_if_pc = if_pc[31:0]; 309 | assign debug_if_nextPc = if_nextPc[31:0]; 310 | assign debug_if_instruction = if_instruction[31:0]; 311 | assign debug_id_instruction = id_instruction[31:0]; 312 | assign debug_id_shouldStall = id_shouldStall; 313 | assign debug_ex_instruction = ex_instruction[31:0]; 314 | assign debug_ex_aluOutput = ex_aluOutput[31:0]; 315 | assign debug_mem_instruction = mem_instruction[31:0]; 316 | assign debug_mem_memoryAddress = mem_aluOutput[31:0]; 317 | assign debug_mem_memoryReadData = mem_memoryData[31:0]; 318 | assign debug_mem_shouldWriteMemory = mem_shouldWriteMemory; 319 | assign debug_mem_memoryWriteData = mem_registerRtOrZero[31:0]; 320 | assign debug_wb_instruction = wb_instruction[31:0]; 321 | assign debug_wb_shouldWriteRegister = wb_shouldWriteRegister; 322 | assign debug_wb_registerWriteAddress = wb_registerWriteAddress[4:0]; 323 | assign debug_wb_registerWriteData = wb_registerWriteData[31:0]; 324 | endmodule 325 | -------------------------------------------------------------------------------- /assets/Font.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 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4 | -------------------------------------------------------------------------------- /ipcore_dir/Font.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix=16; 2 | memory_initialization_vector= 3 | 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6,36,ff,00,00,00,00,00,00,00,00,00,00,00,00,00,ff,00,ff,18,18,18,18,18,18,18,18,00,00,00,00,00,00,00,ff,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,3f,00,00,00,00,00,00,00,00,18,18,18,18,18,1f,18,1f,00,00,00,00,00,00,00,00,00,00,00,00,00,1f,18,1f,18,18,18,18,18,18,18,18,00,00,00,00,00,00,00,3f,36,36,36,36,36,36,36,36,36,36,36,36,36,36,36,ff,36,36,36,36,36,36,36,36,18,18,18,18,18,ff,18,ff,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,f8,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,1f,18,18,18,18,18,18,18,18,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,ff,00,00,00,00,00,00,00,ff,ff,ff,ff,ff,ff,ff,ff,ff,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,f0,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,0f,ff,ff,ff,ff,ff,ff,ff,00,00,00,00,00,00,00,00,00,00,00,00,00,00,76,dc,d8,d8,d8,dc,76,00,00,00,00,00,00,78,cc,cc,cc,d8,cc,c6,c6,c6,cc,00,00,00,00,00,00,fe,c6,c6,c0,c0,c0,c0,c0,c0,c0,00,00,00,00,00,00,00,00,fe,6c,6c,6c,6c,6c,6c,6c,00,00,00,00,00,00,00,fe,c6,60,30,18,30,60,c6,fe,00,00,00,00,00,00,00,00,00,7e,d8,d8,d8,d8,d8,70,00,00,00,00,00,00,00,00,66,66,66,66,66,7c,60,60,c0,00,00,00,00,00,00,00,76,dc,18,18,18,18,18,18,00,00,00,00,00,00,00,7e,18,3c,66,66,66,3c,18,7e,00,00,00,00,00,00,00,38,6c,c6,c6,fe,c6,c6,6c,38,00,00,00,00,00,00,38,6c,c6,c6,c6,6c,6c,6c,6c,ee,00,00,00,00,00,00,1e,30,18,0c,3e,66,66,66,66,3c,00,00,00,00,00,00,00,00,00,7e,db,db,db,7e,00,00,00,00,00,00,00,00,00,03,06,7e,db,db,f3,7e,60,c0,00,00,00,00,00,00,1c,30,60,60,7c,60,60,60,30,1c,00,00,00,00,00,00,00,7c,c6,c6,c6,c6,c6,c6,c6,c6,00,00,00,00,00,00,00,00,fe,00,00,fe,00,00,fe,00,00,00,00,00,00,00,00,00,18,18,7e,18,18,00,00,ff,00,00,00,00,00,00,00,30,18,0c,06,0c,18,30,00,7e,00,00,00,00,00,00,00,0c,18,30,60,30,18,0c,00,7e,00,00,00,00,00,00,0e,1b,1b,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,d8,d8,d8,70,00,00,00,00,00,00,00,00,18,18,00,7e,00,18,18,00,00,00,00,00,00,00,00,00,00,76,dc,00,76,dc,00,00,00,00,00,00,00,38,6c,6c,38,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,18,18,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,18,00,00,00,00,00,00,00,00,0f,0c,0c,0c,0c,0c,ec,6c,6c,3c,1c,00,00,00,00,00,d8,6c,6c,6c,6c,6c,00,00,00,00,00,00,00,00,00,00,70,d8,30,60,c8,f8,00,00,00,00,00,00,00,00,00,00,00,00,00,7c,7c,7c,7c,7c,7c,7c,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00,00; 4 | -------------------------------------------------------------------------------- /Debugger.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Debugger ( 4 | 5 | input clock, 6 | 7 | input [31:0] cpu_if_pc, 8 | input [31:0] cpu_if_nextPc, 9 | input [31:0] cpu_if_instruction, 10 | input [31:0] cpu_id_instruction, 11 | input cpu_id_shouldStall, 12 | input cpu_id_shouldForwardRegisterRs, 13 | input cpu_id_shouldForwardRegisterRt, 14 | input [32 * 32 - 1 : 0] cpu_id_registers, 15 | input [31:0] cpu_ex_instruction, 16 | input [31:0] cpu_ex_aluInputA, 17 | input [31:0] cpu_ex_aluInputB, 18 | input [31:0] cpu_ex_aluOutput, 19 | input [31:0] cpu_mem_instruction, 20 | input [31:0] cpu_mem_memoryAddress, 21 | input [31:0] cpu_mem_memoryReadData, 22 | input cpu_mem_shouldWriteMemory, 23 | input [31:0] cpu_mem_memoryWriteData, 24 | input [31:0] cpu_wb_instruction, 25 | input cpu_wb_shouldWriteRegister, 26 | input [4:0] cpu_wb_registerWriteAddress, 27 | input [31:0] cpu_wb_registerWriteData, 28 | 29 | output reg [11:0] terminalAddress = 0, 30 | output shouldWriteTerminal, 31 | output reg [7:0] terminalWriteData = 0 32 | ); 33 | 34 | localparam TERMINAL_ADDRESS_MAX = 2399; 35 | 36 | assign shouldWriteTerminal = 1; 37 | 38 | wire [11:0] nextTerminalAddress = terminalAddress < TERMINAL_ADDRESS_MAX ? terminalAddress + 1'b1 : 0; 39 | 40 | wire [31:0] disassemblerInput = 41 | nextTerminalAddress >= 170 && nextTerminalAddress < 202 ? cpu_if_instruction 42 | : nextTerminalAddress >= 410 && nextTerminalAddress < 442 ? cpu_id_instruction 43 | : nextTerminalAddress >= 1370 && nextTerminalAddress < 1402 ? cpu_ex_instruction 44 | : nextTerminalAddress >= 1691 && nextTerminalAddress < 1723 ? cpu_mem_instruction 45 | : nextTerminalAddress >= 2010 && nextTerminalAddress < 2042 ? cpu_wb_instruction 46 | : 32'hFFFFFFFF; 47 | wire [32 * 8 - 1 : 0] disassemblerOutput; 48 | Disassembler disassembler ( 49 | .instruction(disassemblerInput[31:0]), 50 | .text(disassemblerOutput[32 * 8 - 1 : 0]) 51 | ); 52 | 53 | // XST doesn't accept {cpu_id_registers[32 * 32 - 1 : 31 * 32]}[31 - 4 * (nextTerminalAddress - 560) -: 4] 54 | wire [31:0] cpu_id_register0 = cpu_id_registers[1 * 32 - 1 : 0 * 32]; 55 | wire [31:0] cpu_id_register1 = cpu_id_registers[2 * 32 - 1 : 1 * 32]; 56 | wire [31:0] cpu_id_register2 = cpu_id_registers[3 * 32 - 1 : 2 * 32]; 57 | wire [31:0] cpu_id_register3 = cpu_id_registers[4 * 32 - 1 : 3 * 32]; 58 | wire [31:0] cpu_id_register4 = cpu_id_registers[5 * 32 - 1 : 4 * 32]; 59 | wire [31:0] cpu_id_register5 = cpu_id_registers[6 * 32 - 1 : 5 * 32]; 60 | wire [31:0] cpu_id_register6 = cpu_id_registers[7 * 32 - 1 : 6 * 32]; 61 | wire [31:0] cpu_id_register7 = cpu_id_registers[8 * 32 - 1 : 7 * 32]; 62 | wire [31:0] cpu_id_register8 = cpu_id_registers[9 * 32 - 1 : 8 * 32]; 63 | wire [31:0] cpu_id_register9 = cpu_id_registers[10 * 32 - 1 : 9 * 32]; 64 | wire [31:0] cpu_id_register10 = cpu_id_registers[11 * 32 - 1 : 10 * 32]; 65 | wire [31:0] cpu_id_register11 = cpu_id_registers[12 * 32 - 1 : 11 * 32]; 66 | wire [31:0] cpu_id_register12 = cpu_id_registers[13 * 32 - 1 : 12 * 32]; 67 | wire [31:0] cpu_id_register13 = cpu_id_registers[14 * 32 - 1 : 13 * 32]; 68 | wire [31:0] cpu_id_register14 = cpu_id_registers[15 * 32 - 1 : 14 * 32]; 69 | wire [31:0] cpu_id_register15 = cpu_id_registers[16 * 32 - 1 : 15 * 32]; 70 | wire [31:0] cpu_id_register16 = cpu_id_registers[17 * 32 - 1 : 16 * 32]; 71 | wire [31:0] cpu_id_register17 = cpu_id_registers[18 * 32 - 1 : 17 * 32]; 72 | wire [31:0] cpu_id_register18 = cpu_id_registers[19 * 32 - 1 : 18 * 32]; 73 | wire [31:0] cpu_id_register19 = cpu_id_registers[20 * 32 - 1 : 19 * 32]; 74 | wire [31:0] cpu_id_register20 = cpu_id_registers[21 * 32 - 1 : 20 * 32]; 75 | wire [31:0] cpu_id_register21 = cpu_id_registers[22 * 32 - 1 : 21 * 32]; 76 | wire [31:0] cpu_id_register22 = cpu_id_registers[23 * 32 - 1 : 22 * 32]; 77 | wire [31:0] cpu_id_register23 = cpu_id_registers[24 * 32 - 1 : 23 * 32]; 78 | wire [31:0] cpu_id_register24 = cpu_id_registers[25 * 32 - 1 : 24 * 32]; 79 | wire [31:0] cpu_id_register25 = cpu_id_registers[26 * 32 - 1 : 25 * 32]; 80 | wire [31:0] cpu_id_register26 = cpu_id_registers[27 * 32 - 1 : 26 * 32]; 81 | wire [31:0] cpu_id_register27 = cpu_id_registers[28 * 32 - 1 : 27 * 32]; 82 | wire [31:0] cpu_id_register28 = cpu_id_registers[29 * 32 - 1 : 28 * 32]; 83 | wire [31:0] cpu_id_register29 = cpu_id_registers[30 * 32 - 1 : 29 * 32]; 84 | wire [31:0] cpu_id_register30 = cpu_id_registers[31 * 32 - 1 : 30 * 32]; 85 | wire [31:0] cpu_id_register31 = cpu_id_registers[32 * 32 - 1 : 31 * 32]; 86 | 87 | // FIXME: XST inferred these indexed part-select as shifters instead of multiplexers. 88 | wire [3:0] hexCharacterInput = 89 | nextTerminalAddress >= 246 && nextTerminalAddress < 254 ? cpu_if_pc[31 - 4 * (nextTerminalAddress - 246) -: 4] 90 | : nextTerminalAddress >= 291 && nextTerminalAddress < 299 ? cpu_if_nextPc[31 - 4 * (nextTerminalAddress - 291) -: 4] 91 | : nextTerminalAddress >= 722 && nextTerminalAddress < 730 ? cpu_id_register0[31 - 4 * (nextTerminalAddress - 722) -: 4] 92 | : nextTerminalAddress >= 739 && nextTerminalAddress < 747 ? cpu_id_register1[31 - 4 * (nextTerminalAddress - 739) -: 4] 93 | : nextTerminalAddress >= 756 && nextTerminalAddress < 764 ? cpu_id_register2[31 - 4 * (nextTerminalAddress - 756) -: 4] 94 | : nextTerminalAddress >= 773 && nextTerminalAddress < 781 ? cpu_id_register3[31 - 4 * (nextTerminalAddress - 773) -: 4] 95 | : nextTerminalAddress >= 790 && nextTerminalAddress < 798 ? cpu_id_register4[31 - 4 * (nextTerminalAddress - 790) -: 4] 96 | : nextTerminalAddress >= 802 && nextTerminalAddress < 810 ? cpu_id_register5[31 - 4 * (nextTerminalAddress - 802) -: 4] 97 | : nextTerminalAddress >= 819 && nextTerminalAddress < 827 ? cpu_id_register6[31 - 4 * (nextTerminalAddress - 819) -: 4] 98 | : nextTerminalAddress >= 836 && nextTerminalAddress < 844 ? cpu_id_register7[31 - 4 * (nextTerminalAddress - 836) -: 4] 99 | : nextTerminalAddress >= 853 && nextTerminalAddress < 861 ? cpu_id_register8[31 - 4 * (nextTerminalAddress - 853) -: 4] 100 | : nextTerminalAddress >= 870 && nextTerminalAddress < 878 ? cpu_id_register9[31 - 4 * (nextTerminalAddress - 870) -: 4] 101 | : nextTerminalAddress >= 882 && nextTerminalAddress < 890 ? cpu_id_register10[31 - 4 * (nextTerminalAddress - 882) -: 4] 102 | : nextTerminalAddress >= 899 && nextTerminalAddress < 907 ? cpu_id_register11[31 - 4 * (nextTerminalAddress - 899) -: 4] 103 | : nextTerminalAddress >= 916 && nextTerminalAddress < 924 ? cpu_id_register12[31 - 4 * (nextTerminalAddress - 916) -: 4] 104 | : nextTerminalAddress >= 933 && nextTerminalAddress < 941 ? cpu_id_register13[31 - 4 * (nextTerminalAddress - 933) -: 4] 105 | : nextTerminalAddress >= 950 && nextTerminalAddress < 958 ? cpu_id_register14[31 - 4 * (nextTerminalAddress - 950) -: 4] 106 | : nextTerminalAddress >= 962 && nextTerminalAddress < 970 ? cpu_id_register15[31 - 4 * (nextTerminalAddress - 962) -: 4] 107 | : nextTerminalAddress >= 979 && nextTerminalAddress < 987 ? cpu_id_register16[31 - 4 * (nextTerminalAddress - 979) -: 4] 108 | : nextTerminalAddress >= 996 && nextTerminalAddress < 1004 ? cpu_id_register17[31 - 4 * (nextTerminalAddress - 996) -: 4] 109 | : nextTerminalAddress >= 1013 && nextTerminalAddress < 1021 ? cpu_id_register18[31 - 4 * (nextTerminalAddress - 1013) -: 4] 110 | : nextTerminalAddress >= 1030 && nextTerminalAddress < 1038 ? cpu_id_register19[31 - 4 * (nextTerminalAddress - 1030) -: 4] 111 | : nextTerminalAddress >= 1042 && nextTerminalAddress < 1050 ? cpu_id_register20[31 - 4 * (nextTerminalAddress - 1042) -: 4] 112 | : nextTerminalAddress >= 1059 && nextTerminalAddress < 1067 ? cpu_id_register21[31 - 4 * (nextTerminalAddress - 1059) -: 4] 113 | : nextTerminalAddress >= 1076 && nextTerminalAddress < 1084 ? cpu_id_register22[31 - 4 * (nextTerminalAddress - 1076) -: 4] 114 | : nextTerminalAddress >= 1093 && nextTerminalAddress < 1101 ? cpu_id_register23[31 - 4 * (nextTerminalAddress - 1093) -: 4] 115 | : nextTerminalAddress >= 1110 && nextTerminalAddress < 1118 ? cpu_id_register24[31 - 4 * (nextTerminalAddress - 1110) -: 4] 116 | : nextTerminalAddress >= 1122 && nextTerminalAddress < 1130 ? cpu_id_register25[31 - 4 * (nextTerminalAddress - 1122) -: 4] 117 | : nextTerminalAddress >= 1139 && nextTerminalAddress < 1147 ? cpu_id_register26[31 - 4 * (nextTerminalAddress - 1139) -: 4] 118 | : nextTerminalAddress >= 1156 && nextTerminalAddress < 1164 ? cpu_id_register27[31 - 4 * (nextTerminalAddress - 1156) -: 4] 119 | : nextTerminalAddress >= 1173 && nextTerminalAddress < 1181 ? cpu_id_register28[31 - 4 * (nextTerminalAddress - 1173) -: 4] 120 | : nextTerminalAddress >= 1190 && nextTerminalAddress < 1198 ? cpu_id_register29[31 - 4 * (nextTerminalAddress - 1190) -: 4] 121 | : nextTerminalAddress >= 1202 && nextTerminalAddress < 1210 ? cpu_id_register30[31 - 4 * (nextTerminalAddress - 1202) -: 4] 122 | : nextTerminalAddress >= 1219 && nextTerminalAddress < 1227 ? cpu_id_register31[31 - 4 * (nextTerminalAddress - 1219) -: 4] 123 | : nextTerminalAddress >= 1455 && nextTerminalAddress < 1463 ? cpu_ex_aluInputA[31 - 4 * (nextTerminalAddress - 1455) -: 4] 124 | : nextTerminalAddress >= 1495 && nextTerminalAddress < 1503 ? cpu_ex_aluInputB[31 - 4 * (nextTerminalAddress - 1495) -: 4] 125 | : nextTerminalAddress >= 1534 && nextTerminalAddress < 1542 ? cpu_ex_aluOutput[31 - 4 * (nextTerminalAddress - 1534) -: 4] 126 | : nextTerminalAddress >= 1778 && nextTerminalAddress < 1786 ? cpu_mem_memoryAddress[31 - 4 * (nextTerminalAddress - 1778) -: 4] 127 | : nextTerminalAddress >= 1820 && nextTerminalAddress < 1828 ? cpu_mem_memoryReadData[31 - 4 * (nextTerminalAddress - 1820) -: 4] 128 | : nextTerminalAddress >= 1901 && nextTerminalAddress < 1909 ? cpu_mem_memoryWriteData[31 - 4 * (nextTerminalAddress - 1901) -: 4] 129 | : nextTerminalAddress >= 2146 && nextTerminalAddress < 2148 ? cpu_wb_registerWriteAddress[7 - 4 * (nextTerminalAddress - 2146) -: 4] 130 | : nextTerminalAddress >= 2183 && nextTerminalAddress < 2191 ? cpu_wb_registerWriteData[31 - 4 * (nextTerminalAddress - 2183) -: 4] 131 | : 4'hF; 132 | wire [7:0] hexCharacterOutput; 133 | HexCharacterConverter hexCharacterConverter ( 134 | .hex(hexCharacterInput[3:0]), 135 | .character(hexCharacterOutput[7:0]) 136 | ); 137 | 138 | wire booleanTextInput = 139 | nextTerminalAddress >= 487 && nextTerminalAddress < 492 ? cpu_id_shouldStall 140 | : nextTerminalAddress >= 572 && nextTerminalAddress < 577 ? cpu_id_shouldForwardRegisterRs 141 | : nextTerminalAddress >= 612 && nextTerminalAddress < 617 ? cpu_id_shouldForwardRegisterRt 142 | : nextTerminalAddress >= 1862 && nextTerminalAddress < 1867 ? cpu_mem_shouldWriteMemory 143 | : nextTerminalAddress >= 2104 && nextTerminalAddress < 2109 ? cpu_wb_shouldWriteRegister 144 | : 1'b1; 145 | wire [5 * 8 - 1 : 0] booleanTextOutput; 146 | BooleanTextConverter booleanTextConverter ( 147 | .boolean(booleanTextInput), 148 | .text(booleanTextOutput[5 * 8 - 1 : 0]) 149 | ); 150 | 151 | wire [11:0] backgroundAddress = nextTerminalAddress; 152 | wire [7:0] backgroundCharacter; 153 | Background background ( 154 | .a(backgroundAddress[11:0]), 155 | .spo(backgroundCharacter[7:0]) 156 | ); 157 | 158 | always @(posedge clock) begin 159 | 160 | terminalAddress <= nextTerminalAddress; 161 | 162 | terminalWriteData <= 163 | nextTerminalAddress >= 170 && nextTerminalAddress < 202 ? disassemblerOutput[255 - 8 * (nextTerminalAddress - 170) -: 8] 164 | : nextTerminalAddress >= 246 && nextTerminalAddress < 254 ? hexCharacterOutput 165 | : nextTerminalAddress >= 291 && nextTerminalAddress < 299 ? hexCharacterOutput 166 | : nextTerminalAddress >= 410 && nextTerminalAddress < 442 ? disassemblerOutput[255 - 8 * (nextTerminalAddress - 410) -: 8] 167 | : nextTerminalAddress >= 487 && nextTerminalAddress < 492 ? booleanTextOutput[39 - 8 * (nextTerminalAddress - 487) -: 8] 168 | : nextTerminalAddress >= 572 && nextTerminalAddress < 577 ? booleanTextOutput[39 - 8 * (nextTerminalAddress - 572) -: 8] 169 | : nextTerminalAddress >= 612 && nextTerminalAddress < 617 ? booleanTextOutput[39 - 8 * (nextTerminalAddress - 612) -: 8] 170 | : nextTerminalAddress >= 722 && nextTerminalAddress < 730 ? hexCharacterOutput 171 | : nextTerminalAddress >= 739 && nextTerminalAddress < 747 ? hexCharacterOutput 172 | : nextTerminalAddress >= 756 && nextTerminalAddress < 764 ? hexCharacterOutput 173 | : nextTerminalAddress >= 773 && nextTerminalAddress < 781 ? hexCharacterOutput 174 | : nextTerminalAddress >= 790 && nextTerminalAddress < 798 ? hexCharacterOutput 175 | : nextTerminalAddress >= 802 && nextTerminalAddress < 810 ? hexCharacterOutput 176 | : nextTerminalAddress >= 819 && nextTerminalAddress < 827 ? hexCharacterOutput 177 | : nextTerminalAddress >= 836 && nextTerminalAddress < 844 ? hexCharacterOutput 178 | : nextTerminalAddress >= 853 && nextTerminalAddress < 861 ? hexCharacterOutput 179 | : nextTerminalAddress >= 870 && nextTerminalAddress < 878 ? hexCharacterOutput 180 | : nextTerminalAddress >= 882 && nextTerminalAddress < 890 ? hexCharacterOutput 181 | : nextTerminalAddress >= 899 && nextTerminalAddress < 907 ? hexCharacterOutput 182 | : nextTerminalAddress >= 916 && nextTerminalAddress < 924 ? hexCharacterOutput 183 | : nextTerminalAddress >= 933 && nextTerminalAddress < 941 ? hexCharacterOutput 184 | : nextTerminalAddress >= 950 && nextTerminalAddress < 958 ? hexCharacterOutput 185 | : nextTerminalAddress >= 962 && nextTerminalAddress < 970 ? hexCharacterOutput 186 | : nextTerminalAddress >= 979 && nextTerminalAddress < 987 ? hexCharacterOutput 187 | : nextTerminalAddress >= 996 && nextTerminalAddress < 1004 ? hexCharacterOutput 188 | : nextTerminalAddress >= 1013 && nextTerminalAddress < 1021 ? hexCharacterOutput 189 | : nextTerminalAddress >= 1030 && nextTerminalAddress < 1038 ? hexCharacterOutput 190 | : nextTerminalAddress >= 1042 && nextTerminalAddress < 1050 ? hexCharacterOutput 191 | : nextTerminalAddress >= 1059 && nextTerminalAddress < 1067 ? hexCharacterOutput 192 | : nextTerminalAddress >= 1076 && nextTerminalAddress < 1084 ? hexCharacterOutput 193 | : nextTerminalAddress >= 1093 && nextTerminalAddress < 1101 ? hexCharacterOutput 194 | : nextTerminalAddress >= 1110 && nextTerminalAddress < 1118 ? hexCharacterOutput 195 | : nextTerminalAddress >= 1122 && nextTerminalAddress < 1130 ? hexCharacterOutput 196 | : nextTerminalAddress >= 1139 && nextTerminalAddress < 1147 ? hexCharacterOutput 197 | : nextTerminalAddress >= 1156 && nextTerminalAddress < 1164 ? hexCharacterOutput 198 | : nextTerminalAddress >= 1173 && nextTerminalAddress < 1181 ? hexCharacterOutput 199 | : nextTerminalAddress >= 1190 && nextTerminalAddress < 1198 ? hexCharacterOutput 200 | : nextTerminalAddress >= 1202 && nextTerminalAddress < 1210 ? hexCharacterOutput 201 | : nextTerminalAddress >= 1219 && nextTerminalAddress < 1227 ? hexCharacterOutput 202 | : nextTerminalAddress >= 1370 && nextTerminalAddress < 1402 ? disassemblerOutput[255 - 8 * (nextTerminalAddress - 1370) -: 8] 203 | : nextTerminalAddress >= 1455 && nextTerminalAddress < 1463 ? hexCharacterOutput 204 | : nextTerminalAddress >= 1495 && nextTerminalAddress < 1503 ? hexCharacterOutput 205 | : nextTerminalAddress >= 1534 && nextTerminalAddress < 1542 ? hexCharacterOutput 206 | : nextTerminalAddress >= 1691 && nextTerminalAddress < 1723 ? disassemblerOutput[255 - 8 * (nextTerminalAddress - 1691) -: 8] 207 | : nextTerminalAddress >= 1778 && nextTerminalAddress < 1786 ? hexCharacterOutput 208 | : nextTerminalAddress >= 1820 && nextTerminalAddress < 1828 ? hexCharacterOutput 209 | : nextTerminalAddress >= 1862 && nextTerminalAddress < 1867 ? booleanTextOutput[39 - 8 * (nextTerminalAddress - 1862) -: 8] 210 | : nextTerminalAddress >= 1901 && nextTerminalAddress < 1909 ? hexCharacterOutput 211 | : nextTerminalAddress >= 2010 && nextTerminalAddress < 2042 ? disassemblerOutput[255 - 8 * (nextTerminalAddress - 2010) -: 8] 212 | : nextTerminalAddress >= 2104 && nextTerminalAddress < 2109 ? booleanTextOutput[39 - 8 * (nextTerminalAddress - 2104) -: 8] 213 | : nextTerminalAddress >= 2146 && nextTerminalAddress < 2148 ? hexCharacterOutput 214 | : nextTerminalAddress >= 2183 && nextTerminalAddress < 2191 ? hexCharacterOutput 215 | : backgroundCharacter; 216 | end 217 | endmodule 218 | -------------------------------------------------------------------------------- /nexys3.ucf: -------------------------------------------------------------------------------- 1 | ## This file is a general .ucf for Nexys3 rev B board 2 | ## To use it in a project: 3 | ## - remove or comment the lines corresponding to unused pins 4 | ## - rename the used signals according to the project 5 | 6 | ##Clock signal 7 | Net "clock50Mhz" LOC = V10 | IOSTANDARD = LVCMOS33; 8 | #Net "clock50Mhz" TNM_NET = sys_clk_pin; 9 | #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz; 10 | 11 | ## onBoard USB controller 12 | #Net "EppAstb" LOC = H1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA 13 | #Net "EppDstb" LOC = K4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB 14 | #Net "EppWait" LOC = C2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD 15 | #Net "EppDB<0>" LOC = E1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0 16 | #Net "EppDB<1>" LOC = F4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1 17 | #Net "EppDB<2>" LOC = F3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2 18 | #Net "EppDB<3>" LOC = D2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3 19 | #Net "EppDB<4>" LOC = D1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4 20 | #Net "EppDB<5>" LOC = H7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5 21 | #Net "EppDB<6>" LOC = G6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6 22 | #Net "EppDB<7>" LOC = E4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7 23 | 24 | #Net "UsbClk" LOC = H2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41P_GCLK27_M3DQ4, Sch name = U-IFCLK 25 | #Net "UsbDir" LOC = F6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55P_M3A13, Sch name = U-SLCS 26 | 27 | #Net "UsbWR" LOC = C1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83N_VREF, Sch name = U-SLWR 28 | #Net "UsbOE" LOC = H6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49P_M3A7, Sch name = U-SLOE 29 | 30 | #Net "UsbAdr<1>" LOC = E3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50P_M3WE, Sch name = U-FIFOAD1 31 | #Net "UsbAdr<0>" LOC = H5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49N_M3A2, Sch name = U-FIFOAD0 32 | 33 | #Net "UsbPktend" LOC = D3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54N_M3A11, Sch name = U-PKTEND 34 | 35 | #Net "UsbFlag" LOC = F5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC 36 | #Net "UsbMode" LOC = F1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48N_M3BA1, Sch name = U-INT0# 37 | 38 | ## onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash 39 | #Net "MemOE" LOC = L18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46N_FOE_B_M1DQ3, Sch name = P30-OE 40 | #Net "MemWR" LOC = M16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47P_FWE_B_M1DQ0, Sch name = P30-WE 41 | #Net "MemAdv" LOC = H18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43N_GCLK4_M1DQ5, Sch name = P30-ADV 42 | #Net "MemWait" LOC = V4 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63N, Sch name = P30-WAIT 43 | #Net "MemClk" LOC = R10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29P_GCLK3, Sch name = P30-CLK 44 | 45 | #Net "RamCS" LOC = L15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42P_GCLK7_M1UDM, Sch name = MT-CE 46 | #Net "RamCRE" LOC = M18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47N_LDC_M1DQ1, Sch name = MT-CRE 47 | #Net "RamUB" LOC = K15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = MT-UB 48 | #Net "RamLB" LOC = K16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41N_GCLK8_M1CASN, Sch name = MT-LB 49 | 50 | #Net "FlashCS" LOC = L17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46P_FCS_B_M1DQ2, Sch name = P30-CE 51 | #Net "FlashRp" LOC = T4 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63P, Sch name = P30-RST 52 | 53 | #Net "QuadSpiFlashCS" LOC = V3 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L65N_CSO_B_2, Sch name = CS 54 | #Net "QuadSpiFlashSck" LOC = R15 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L1P_CCLK_2, Sch name = SCK 55 | 56 | #Net "MemAdr<1>" LOC = K18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45N_A0_M1LDQSN, Sch name = P30-A0 57 | #Net "MemAdr<2>" LOC = K17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45P_A1_M1LDQS, Sch name = P30-A1 58 | #Net "MemAdr<3>" LOC = J18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44N_A2_M1DQ7, Sch name = P30-A2 59 | #Net "MemAdr<4>" LOC = J16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44P_A3_M1DQ6, Sch name = P30-A3 60 | #Net "MemAdr<5>" LOC = G18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38N_A4_M1CLKN, Sch name = P30-A4 61 | #Net "MemAdr<6>" LOC = G16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38P_A5_M1CLK, Sch name = P30-A5 62 | #Net "MemAdr<7>" LOC = H16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37N_A6_M1A1, Sch name = P30-A6 63 | #Net "MemAdr<8>" LOC = H15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37P_A7_M1A0, Sch name = P30-A7 64 | #Net "MemAdr<9>" LOC = H14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36N_A8_M1BA1, Sch name = P30-A8 65 | #Net "MemAdr<10>" LOC = H13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36P_A9_M1BA0, Sch name = P30-A9 66 | #Net "MemAdr<11>" LOC = F18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35N_A10_M1A2, Sch name = P30-A10 67 | #Net "MemAdr<12>" LOC = F17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35P_A11_M1A7, Sch name = P30-A11 68 | #Net "MemAdr<13>" LOC = K13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34N_A12_M1BA2, Sch name = P30-A12 69 | #Net "MemAdr<14>" LOC = K12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34P_A13_M1WE, Sch name = P30-A13 70 | #Net "MemAdr<15>" LOC = E18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33N_A14_M1A4, Sch name = P30-A14 71 | #Net "MemAdr<16>" LOC = E16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33P_A15_M1A10, Sch name = P30-A15 72 | #Net "MemAdr<17>" LOC = G13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32N_A16_M1A9, Sch name = P30-A16 73 | #Net "MemAdr<18>" LOC = H12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32P_A17_M1A8, Sch name = P30-A17 74 | #Net "MemAdr<19>" LOC = D18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31N_A18_M1A12, Sch name = P30-A18 75 | #Net "MemAdr<20>" LOC = D17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31P_A19_M1CKE, Sch name = P30-A19 76 | #Net "MemAdr<21>" LOC = G14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30N_A20_M1A11, Sch name = P30-A20 77 | #Net "MemAdr<22>" LOC = F14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30P_A21_M1RESET Sch name = P30-A21 78 | #Net "MemAdr<23>" LOC = C18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29N_A22_M1A14, Sch name = P30-A22 79 | #Net "MemAdr<24>" LOC = C17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29P_A23_M1A13, Sch name = P30-A23 80 | #Net "MemAdr<25>" LOC = F16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1N_A24_VREF, Sch name = P30-A24 81 | #Net "MemAdr<26>" LOC = F15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1P_A25, Sch name = P30-A25 82 | 83 | #Net "QuadSpiFlashDB<0>" LOC = T13 | IOSTANDARD = LVCMOS33; #Dual/Quad SPI Flash DB<0>, Bank = MISC, pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI 84 | #Net "MemDB<0>" LOC = R13 | IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<0>, or Dual/Quad SPI Flash DB<1>, Bank = MISC, pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = P30-DQ0 85 | #Net "MemDB<1>" LOC = T14 | IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<1>, or Quad SPI Flash DB<2>, Bank = MISC, pin name = IO_L12P_D1_MISO2_2, Sch name = P30-DQ1 86 | #Net "MemDB<2>" LOC = V14 | IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<2>, or Quad SPI Flash DB<3>, Bank = MISC, pin name = IO_L12N_D2_MISO3_2, Sch name = P30-DQ2 87 | #Net "MemDB<3>" LOC = U5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49P_D3, Sch name = P30-DQ3 88 | #Net "MemDB<4>" LOC = V5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49N_D4, Sch name = P30-DQ4 89 | #Net "MemDB<5>" LOC = R3 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62P_D5, Sch name = P30-DQ5 90 | #Net "MemDB<6>" LOC = T3 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62N_D6, Sch name = P30-DQ6 91 | #Net "MemDB<7>" LOC = R5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L48P_D7, Sch name = P30-DQ7 92 | #Net "MemDB<8>" LOC = N5 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64P_D8, Sch name = P30-DQ8 93 | #Net "MemDB<9>" LOC = P6 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64N_D9, Sch name = P30-DQ9 94 | #Net "MemDB<10>" LOC = P12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L13N_D10, Sch name = P30-DQ10 95 | #Net "MemDB<11>" LOC = U13 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14P_D11, Sch name = P30-DQ11 96 | #Net "MemDB<12>" LOC = V13 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14N_D12, Sch name = P30-DQ12 97 | #Net "MemDB<13>" LOC = U10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L30P_GCLK1_D13, Sch name = P30-DQ13 98 | #Net "MemDB<14>" LOC = R8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31P_GCLK31_D14, Sch name = P30-DQ14 99 | #Net "MemDB<15>" LOC = T8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31N_GCLK30_D15, Sch name = P30-DQ15 100 | 101 | ## SMSC ethernet PHY 102 | #Net "PhyRstn" LOC = P3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2N, Sch name = ETH-RST 103 | #Net "PhyCrs" LOC = N3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L1N_VREF, Sch name = ETH-CRS 104 | #Net "PhyCol" LOC = P4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2P, Sch name = ETH-COL 105 | #Net "PhyClk25Mhz" LOC = N4 | IOSTANDARD = LVCMOS33; #Unconnected if R172 is not loaded, Bank = 3, pin name = IO_L1P, Sch name = ETH-CLK25MHZ 106 | 107 | #Net "PhyTxd<3>" LOC = T1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33N_M3DQ13, Sch name = ETH-TXD3 108 | #Net "PhyTxd<2>" LOC = T2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33P_M3DQ12, Sch name = ETH-TXD2 109 | #Net "PhyTxd<1>" LOC = U1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32N_M3DQ15, Sch name = ETH-TXD1 110 | #Net "PhyTxd<0>" LOC = U2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32P_M3DQ14, Sch name = ETH-TXD0 111 | #Net "PhyTxEn" LOC = L2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37P_M3DQ0, Sch name = ETH-TX_EN 112 | #Net "PhyTxClk" LOC = L5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43P_GCLK23_M3RASN, Sch name = ETH-TX_CLK 113 | #Net "PhyTxEr" LOC = P2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34P_M3UDQS, Sch name = ETH-TXD4 114 | 115 | #Net "PhyRxd<3>" LOC = M3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36P_M3DQ8, Sch name = ETH-RXD3 116 | #Net "PhyRxd<2>" LOC = N1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35N_M3DQ11, Sch name = ETH-RXD2 117 | #Net "PhyRxd<1>" LOC = N2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35P_M3DQ10, Sch name = ETH-RXD1 118 | #Net "PhyRxd<0>" LOC = P1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34N_M3UDQSN, Sch name = ETH-RXD0 119 | #Net "PhyRxDv" LOC = L1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37N_M3DQ1, Sch name = ETH-RX_DV 120 | #Net "PhyRxEr" LOC = M1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36N_M3DQ9, Sch name = ETH-RXD4 121 | #Net "PhyRxClk" LOC = H4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44P_GCLK21_M3A5, Sch name = ETH-RX_CLK 122 | 123 | #Net "PhyMdc" LOC = M5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31N_VREF, Sch name = ETH-MDC 124 | #Net "PhyMdio" LOC = L6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31P, Sch name = ETH-MDIO 125 | 126 | ## Pic USB-HID interface 127 | #Net "PS2_Data" LOC = J13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39P_M1A3, Sch name = PIC-SDI1 128 | #Net "PS2_clk" LOC = L12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5, Sch name = PIC-SCK1 129 | 130 | #NET "PS2MouseData" LOC = K14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39N_M1ODT, Sch name = PIC-SDO1 131 | #NET "PS2MouseClk" LOC = L13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6, Sch name = PIC-SS1 132 | 133 | #Net "PicGpio<0>" LOC = L16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = PIC-GPIO0 134 | #NET "PicGpio<1>" LOC = H17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43P_GCLK5_M1DQ4, Sch name = PIC-GPIO1 135 | 136 | ## Usb-RS232 interface 137 | #Net "RxD" LOC = N17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX 138 | #Net "TxD" LOC = N18 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48N_M1DQ9, Sch name = MCU-TX 139 | 140 | ## 7 segment display 141 | #Net "SEGMENT<0>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA 142 | #Net "SEGMENT<1>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB 143 | #Net "SEGMENT<2>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC 144 | #Net "SEGMENT<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD 145 | #Net "SEGMENT<4>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE 146 | #Net "SEGMENT<5>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF 147 | #Net "SEGMENT<6>" LOC = L14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG 148 | #Net "SEGMENT<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP 149 | # 150 | #Net "AN<0>" LOC = N16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0 151 | #Net "AN<1>" LOC = N15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1 152 | #Net "AN<2>" LOC = P18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2 153 | #Net "AN<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3 154 | 155 | ## Leds 156 | #Net "LED<0>" LOC = U16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0 157 | #Net "LED<1>" LOC = V16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1 158 | #Net "LED<2>" LOC = U15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2 159 | #Net "LED<3>" LOC = V15 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5N, Sch name = LD3 160 | #Net "LED<4>" LOC = M11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15P, Sch name = LD4 161 | #Net "LED<5>" LOC = N11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15N, Sch name = LD5 162 | #Net "LED<6>" LOC = R11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16P, Sch name = LD6 163 | #Net "LED<7>" LOC = T11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16N_VREF, Sch name = LD7 164 | 165 | ## Switches 166 | Net "SW<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0 167 | Net "SW<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1 168 | Net "SW<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2 169 | Net "SW<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3 170 | Net "SW<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4 171 | Net "SW<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5 172 | Net "SW<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6 173 | Net "SW<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7 174 | 175 | ## Buttons 176 | Net "BTN<0>" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS 177 | Net "BTN<1>" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU 178 | Net "BTN<2>" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL 179 | Net "BTN<3>" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND 180 | #Net "BTN<4>" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR 181 | 182 | ## VGA Connector 183 | NET "vgaRed<0>" LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0 184 | NET "vgaRed<1>" LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED1 185 | NET "vgaRed<2>" LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2 186 | NET "vgaGreen<0>" LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN0 187 | NET "vgaGreen<1>" LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN1 188 | NET "vgaGreen<2>" LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2 189 | NET "vgaBlue<0>" LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1 190 | NET "vgaBlue<1>" LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU2 191 | NET "vgaHSync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC 192 | NET "vgaVSync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC 193 | 194 | ## 12 pin connectors 195 | 196 | ##JA 197 | #Net "JA<0>" LOC = T12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19P, Sch name = JA1 198 | #Net "JA<1>" LOC = V12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19N, Sch name = JA2 199 | #Net "JA<2>" LOC = N10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20P, Sch name = JA3 200 | #Net "JA<3>" LOC = P11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20N, Sch name = JA4 201 | #Net "JA<4>" LOC = M10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22P, Sch name = JA7 202 | #Net "JA<5>" LOC = N9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22N, Sch name = JA8 203 | #Net "JA<6>" LOC = U11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23P, Sch name = JA9 204 | #Net "JA<7>" LOC = V11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23N, Sch name = JA10 205 | 206 | ##JB 207 | #Net "JB<0>" LOC = K2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38P_M3DQ2, Sch name = JB1 208 | #Net "JB<1>" LOC = K1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38N_M3DQ3, Sch name = JB2 209 | #Net "JB<2>" LOC = L4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39P_M3LDQS, Sch name = JB3 210 | #Net "JB<3>" LOC = L3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39N_M3LDQSN, Sch name = JB4 211 | #Net "JB<4>" LOC = J3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P_M3DQ6, Sch name = JB7 212 | #Net "JB<5>" LOC = J1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N_M3DQ7, Sch name = JB8 213 | #Net "JB<6>" LOC = K3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N_GCLK24_M3LDM, Sch name = JB9 214 | #Net "JB<7>" LOC = K5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = JB10 215 | 216 | ##JC 217 | #Net "JC<0>" LOC = H3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44N_GCLK20_M3A6, Sch name = JC1 218 | #Net "JC<1>" LOC = L7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45P_M3A3, Sch name = JC2 219 | #Net "JC<2>" LOC = K6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45N_M3ODT, Sch name = JC3 220 | #Net "JC<3>" LOC = G3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46P_M3CLK, Sch name = JC4 221 | #Net "JC<4>" LOC = G1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46N_M3CLKN, Sch name = JC7 222 | #Net "JC<5>" LOC = J7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P_M3A0, Sch name = JC8 223 | #Net "JC<6>" LOC = J6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N_M3A1, Sch name = JC9 224 | #Net "JC<7>" LOC = F2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48P_M3BA0, Sch name = JC10 225 | 226 | ##JD, LX16 Die only 227 | #Net "JD<0>" LOC = G11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P, Sch name = JD1 228 | #Net "JD<1>" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N, Sch name = JD2 229 | #Net "JD<2>" LOC = F11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P, Sch name = JD3 230 | #Net "JD<3>" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N, Sch name = JD4 231 | #Net "JD<4>" LOC = D12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P, Sch name = JD7 232 | #Net "JD<5>" LOC = C12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N, Sch name = JD8 233 | #Net "JD<6>" LOC = F12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P, Sch name = JD9 234 | #Net "JD<7>" LOC = E12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N, Sch name = JD10 235 | 236 | ## VHDCI Connector 237 | #Net "EXP-IO_P<0>" LOC = B2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2P, Sch name = EXP_IO1_P 238 | #Net "EXP-IO_N<0>" LOC = A2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2N, Sch name = EXP_IO1_N 239 | #Net "EXP-IO_P<1>" LOC = D6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3P, Sch name = EXP_IO2_P 240 | #Net "EXP-IO_N<1>" LOC = C6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3N, Sch name = EXP_IO2_N 241 | #Net "EXP-IO_P<2>" LOC = B3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4P, Sch name = EXP_IO3_P 242 | #Net "EXP-IO_N<2>" LOC = A3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4N, Sch name = EXP_IO3_N 243 | #Net "EXP-IO_P<3>" LOC = B4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5P, Sch name = EXP_IO4_P 244 | #Net "EXP-IO_N<3>" LOC = A4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5N, Sch name = EXP_IO4_N 245 | #Net "EXP-IO_P<4>" LOC = C5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6P, Sch name = EXP_IO5_P 246 | #Net "EXP-IO_N<4>" LOC = A5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6N, Sch name = EXP_IO5_N 247 | #Net "EXP-IO_P<5>" LOC = B6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8P, Sch name = EXP_IO6_P 248 | #Net "EXP-IO_N<5>" LOC = A6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8N_VREF, Sch name = EXP_IO6_N 249 | #Net "EXP-IO_P<6>" LOC = C7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10P, Sch name = EXP_IO7_P 250 | #Net "EXP-IO_N<6>" LOC = A7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10N, Sch name = EXP_IO7_N 251 | #Net "EXP-IO_P<7>" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11P, Sch name = EXP_IO8_P 252 | #Net "EXP-IO_N<7>" LOC = C8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11N, Sch name = EXP_IO8_N 253 | #Net "EXP-IO_P<8>" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35P_GCLK17, Sch name = EXP_IO9_P 254 | #Net "EXP-IO_N<8>" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35N_GCLK16, Sch name = EXP_IO9_N 255 | #Net "EXP-IO_P<9>" LOC = D11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36P_GCLK15, Sch name = EXP_IO10_P 256 | #Net "EXP-IO_N<9>" LOC = C11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36N_GCLK14, Sch name = EXP_IO10_N 257 | #Net "EXP-IO_P<10>" LOC = C10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37P_GCLK13, Sch name = EXP_IO11_P 258 | #Net "EXP-IO_N<10>" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37N_GCLK12, Sch name = EXP_IO11_N 259 | #Net "EXP-IO_P<11>" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38P, Sch name = EXP_IO12_P 260 | #Net "EXP-IO_N<11>" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38N_VREF, Sch name = EXP_IO12_N 261 | #Net "EXP-IO_P<12>" LOC = B11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39P, Sch name = EXP_IO13_P 262 | #Net "EXP-IO_N<12>" LOC = A11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39N, Sch name = EXP_IO13_N 263 | #Net "EXP-IO_P<13>" LOC = B12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41P, Sch name = EXP_IO14_P 264 | #Net "EXP-IO_N<13>" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41N, Sch name = EXP_IO14_N 265 | #Net "EXP-IO_P<14>" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50P, Sch name = EXP_IO15_P 266 | #Net "EXP-IO_N<14>" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50N, Sch name = EXP_IO15_N 267 | #Net "EXP-IO_P<15>" LOC = B14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62P, Sch name = EXP_IO16_P 268 | #Net "EXP-IO_N<15>" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62N_VREF, Sch name = EXP_IO16_N 269 | #Net "EXP-IO_P<16>" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63P_SCP7, Sch name = EXP_IO17_P 270 | #Net "EXP-IO_N<16>" LOC = E13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63N_SCP6, Sch name = EXP_IO17_N 271 | #Net "EXP-IO_P<17>" LOC = C15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64P_SCP5, Sch name = EXP_IO18_P 272 | #Net "EXP-IO_N<17>" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64N_SCP4, Sch name = EXP_IO18_N 273 | #Net "EXP-IO_P<18>" LOC = D14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65P_SCP3, Sch name = EXP_IO19_P 274 | #Net "EXP-IO_N<18>" LOC = C14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65N_SCP2, Sch name = EXP_IO19_N 275 | #Net "EXP-IO_P<19>" LOC = B16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66P_SCP1, Sch name = EXP_IO20_P 276 | #Net "EXP-IO_N<19>" LOC = A16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66N_SCP0, Sch name = EXP_IO20_N 277 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. By contrast, 15 | the GNU General Public License is intended to guarantee your freedom to 16 | share and change all versions of a program--to make sure it remains free 17 | software for all its users. We, the Free Software Foundation, use the 18 | GNU General Public License for most of our software; it applies also to 19 | any other work released this way by its authors. You can apply it to 20 | your programs, too. 21 | 22 | When we speak of free software, we are referring to freedom, not 23 | price. Our General Public Licenses are designed to make sure that you 24 | have the freedom to distribute copies of free software (and charge for 25 | them if you wish), that you receive source code or can get it if you 26 | want it, that you can change the software or use pieces of it in new 27 | free programs, and that you know you can do these things. 28 | 29 | To protect your rights, we need to prevent others from denying you 30 | these rights or asking you to surrender the rights. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | {one line to give the program's name and a brief idea of what it does.} 635 | Copyright (C) {year} {name of author} 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | {project} Copyright (C) {year} {fullname} 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | --------------------------------------------------------------------------------