├── README.md ├── doc&paper ├── 跨时钟域设计与验证.docx ├── ClockCrossing.pdf ├── CummingsSNUG2002SJ_FIFO1.pdf ├── CummingsSNUG2008Boston_CDC.pdf └── Metastability-and-Synchronizers.IEEEDToct2011.pdf └── src ├── sync2FF.v ├── src2dest.v ├── dest_domain.v ├── src_domain.v └── src2dest_tb.v /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhangzek/Clock-Domain-Crossing-Design/HEAD/README.md -------------------------------------------------------------------------------- /doc&paper/跨时钟域设计与验证.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhangzek/Clock-Domain-Crossing-Design/HEAD/doc&paper/跨时钟域设计与验证.docx -------------------------------------------------------------------------------- /doc&paper/ClockCrossing.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhangzek/Clock-Domain-Crossing-Design/HEAD/doc&paper/ClockCrossing.pdf -------------------------------------------------------------------------------- /doc&paper/CummingsSNUG2002SJ_FIFO1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhangzek/Clock-Domain-Crossing-Design/HEAD/doc&paper/CummingsSNUG2002SJ_FIFO1.pdf -------------------------------------------------------------------------------- /doc&paper/CummingsSNUG2008Boston_CDC.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhangzek/Clock-Domain-Crossing-Design/HEAD/doc&paper/CummingsSNUG2008Boston_CDC.pdf -------------------------------------------------------------------------------- /doc&paper/Metastability-and-Synchronizers.IEEEDToct2011.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhangzek/Clock-Domain-Crossing-Design/HEAD/doc&paper/Metastability-and-Synchronizers.IEEEDToct2011.pdf -------------------------------------------------------------------------------- /src/sync2FF.v: -------------------------------------------------------------------------------- 1 | //两级寄存 2 | module sync2FF#( 3 | parameter DATAWIDTH = 8 4 | ) 5 | ( 6 | input CLK, 7 | input RSTn, 8 | input D, 9 | output reg Q 10 | ); 11 | 12 | reg Q1; 13 | 14 | always @(posedge CLK or negedge RSTn) begin 15 | if (!RSTn) begin 16 | // reset 17 | Q <= 0; 18 | Q1 <= 0; 19 | end 20 | else begin 21 | Q1 <= D; 22 | Q <= Q1; 23 | end 24 | end 25 | 26 | endmodule -------------------------------------------------------------------------------- /src/src2dest.v: -------------------------------------------------------------------------------- 1 | //top module 2 | module src2dest#( 3 | parameter DATAWIDTH = 8 4 | ) 5 | ( 6 | input src_CLK , 7 | input dest_CLK , 8 | input RSTn , 9 | input [ DATAWIDTH - 1 : 0 ] src_data_in , 10 | output [ DATAWIDTH - 1 : 0 ] dest_data_out , 11 | output src_data_valid , 12 | output dest_data_valid 13 | 14 | ); 15 | 16 | wire [ DATAWIDTH - 1 : 0 ] src2dest_data; 17 | wire [ DATAWIDTH - 1 :0 ] src2dest_load; 18 | 19 | src_domain src_domain_inst( .CLK (src_CLK ) , 20 | .RSTn (RSTn ) , 21 | .src_data_in (src_data_in ) , 22 | .src2dest_data (src2dest_data ) , 23 | .src2dest_load (src2dest_load ) , 24 | .src_data_valid (src_data_valid )) ; 25 | dest_domain dest_domain_inst(.CLK (dest_CLK ) , 26 | .RSTn (RSTn ) , 27 | .src2dest_data (src2dest_data ) , 28 | .src2dest_load (src2dest_load ) , 29 | .dest_data_valid (dest_data_valid) , 30 | .dest_data_out (dest_data_out )) ; 31 | 32 | endmodule -------------------------------------------------------------------------------- /src/dest_domain.v: -------------------------------------------------------------------------------- 1 | module dest_domain#( 2 | parameter DATAWIDTH = 8 3 | ) 4 | ( 5 | input CLK , 6 | input RSTn , 7 | input [ DATAWIDTH - 1 : 0 ] src2dest_data , 8 | input src2dest_load , 9 | output reg dest_data_valid , 10 | output reg [ DATAWIDTH - 1 : 0 ] dest_data_out 11 | ); 12 | wire dest_valid; 13 | wire ldtoggle_sy; 14 | reg ldtoggle_sy_dl; 15 | 16 | always @(posedge CLK or negedge RSTn) 17 | begin 18 | if (!RSTn) 19 | begin 20 | dest_data_valid <= 0; 21 | dest_data_out <= 0; 22 | ldtoggle_sy_dl <= 0; 23 | end 24 | else 25 | begin 26 | ldtoggle_sy_dl <= ldtoggle_sy; 27 | dest_data_valid <= dest_valid; 28 | end 29 | end 30 | 31 | assign dest_valid = ldtoggle_sy ^ ldtoggle_sy_dl; 32 | 33 | always @(posedge CLK or negedge RSTn) 34 | begin 35 | if (dest_valid) 36 | begin 37 | dest_data_out <= src2dest_data; 38 | end 39 | end 40 | sync2FF sync2FF_inst( .CLK (CLK ) , 41 | .RSTn (RSTn ) , 42 | .D (src2dest_load ) , 43 | .Q (ldtoggle_sy )) ; 44 | 45 | endmodule -------------------------------------------------------------------------------- /src/src_domain.v: -------------------------------------------------------------------------------- 1 | //source domain 2 | module src_domain#( 3 | parameter DATAWIDTH = 8 4 | ) 5 | ( 6 | input CLK , 7 | input RSTn , 8 | input [ DATAWIDTH - 1 : 0 ] src_data_in , 9 | output reg [ DATAWIDTH - 1 : 0 ] src2dest_data , 10 | output reg src2dest_load , 11 | output reg src_data_valid 12 | ); 13 | 14 | reg [ DATAWIDTH - 1 : 0 ] src_data_in_reg; 15 | 16 | always @(posedge CLK or negedge RSTn) begin 17 | if (!RSTn) begin 18 | // reset 19 | src2dest_data <= 0; 20 | src2dest_load <= 0; 21 | src_data_in_reg <= 0; 22 | end 23 | else begin 24 | src2dest_load <= src2dest_load ^ src_data_valid; 25 | src_data_in_reg <= src_data_in; 26 | end 27 | if (src_data_valid) begin 28 | src2dest_data <= src_data_in; 29 | end 30 | end 31 | 32 | 33 | 34 | /**********src_data_in changed signal**********/ 35 | always @(posedge CLK or negedge RSTn) begin 36 | 37 | if (!RSTn) begin 38 | // reset 39 | src_data_valid <= 0; 40 | end 41 | else if (src_data_in!=src_data_in_reg) 42 | begin 43 | src_data_valid <= 1; 44 | end 45 | else 46 | src_data_valid <= 0; 47 | end 48 | 49 | endmodule -------------------------------------------------------------------------------- /src/src2dest_tb.v: -------------------------------------------------------------------------------- 1 | //testbench 2 | module src2dest_tb(); 3 | parameter DATAWIDTH = 8; 4 | 5 | reg src_CLK ; 6 | reg dest_CLK ; 7 | reg RSTn ; 8 | reg [ DATAWIDTH - 1 : 0 ] src_data_in ; 9 | wire [ DATAWIDTH - 1 : 0 ] dest_data_out ; 10 | wire src_data_valid ; 11 | wire dest_data_valid ; 12 | 13 | 14 | initial 15 | begin 16 | src_CLK = 0; 17 | forever #20 src_CLK <= ~src_CLK; 18 | 19 | end 20 | initial 21 | begin 22 | dest_CLK = 0; 23 | forever #30 dest_CLK <= ~dest_CLK; 24 | end 25 | initial 26 | begin 27 | RSTn = 0; 28 | #10 29 | RSTn = 1; 30 | end 31 | 32 | initial 33 | begin 34 | src_data_in <= 0; 35 | #200 src_data_in <= 8'd2; 36 | #240 src_data_in <= 8'd20; 37 | #200 src_data_in <= 8'd22; 38 | #280 src_data_in <= 8'd11; 39 | #300 src_data_in <= 8'd3; 40 | #340 src_data_in <= 8'd6; 41 | #300 src_data_in <= 8'd7; 42 | #240 src_data_in <= 8'd8; 43 | #240 src_data_in <= 8'd13; 44 | #300 src_data_in <= 8'd24; 45 | #300 src_data_in <= 8'd35; 46 | #240 src_data_in <= 8'd17; 47 | #400 src_data_in <= 8'd18; 48 | #260 src_data_in <= 8'd21; 49 | #240 src_data_in <= 8'd13; 50 | #300 src_data_in <= 8'd25; 51 | #240 src_data_in <= 8'd36; 52 | #280 src_data_in <= 8'd47; 53 | #400 src_data_in <= 8'd63; 54 | #440 src_data_in <= 8'd32; 55 | #800 56 | $stop; 57 | 58 | end 59 | 60 | src2dest src2deat_inst( .src_CLK (src_CLK ) , 61 | .dest_CLK (dest_CLK ) , 62 | .RSTn (RSTn ) , 63 | .src_data_in (src_data_in ) , 64 | .dest_data_out (dest_data_out ) , 65 | .src_data_valid (src_data_valid ) , 66 | .dest_data_valid (dest_data_valid)) ; 67 | 68 | endmodule --------------------------------------------------------------------------------