├── divider ├── layout │ ├── run │ ├── clean │ ├── scripts │ │ ├── mmc.view │ │ ├── mmc2.view │ │ ├── divider.ioc │ │ └── top.tcl │ └── designs │ │ ├── divider.mapped.sdc │ │ └── divider.mapped.v ├── syn │ ├── run │ ├── clean │ ├── divider.constraints.tcl │ └── run.tcl ├── behav_sim │ ├── clean │ ├── run │ └── divider_tb.v ├── layout_sim │ ├── clean │ ├── run │ └── divider_tb.v ├── syn_sim │ ├── clean │ ├── run │ ├── divider_tb.v │ └── divider.mapped.v └── rtl │ └── divider.v ├── divider_layout.png ├── document ├── divider.pdf ├── linux command.pdf ├── tutorial_slides.pdf └── EDI13.1workshoplab1.pdf └── README.md /divider/layout/run: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | encounter -init scripts/top.tcl -win 4 | -------------------------------------------------------------------------------- /divider/syn/run: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | dc_shell -f run.tcl | tee -i run.log 4 | -------------------------------------------------------------------------------- /divider/syn/clean: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -fr reports results alib* WORK 4 | rm *.log *.svf 5 | -------------------------------------------------------------------------------- /divider_layout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhujingyang520/vlsi_project/HEAD/divider_layout.png -------------------------------------------------------------------------------- /document/divider.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhujingyang520/vlsi_project/HEAD/document/divider.pdf -------------------------------------------------------------------------------- /divider/behav_sim/clean: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -fr csrc DVEfiles simv.daidir 4 | rm -f *.vpd *.key 5 | rm -f simv 6 | -------------------------------------------------------------------------------- /divider/layout_sim/clean: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -fr csrc DVEfiles simv.daidir 4 | rm -f *.vpd *.key 5 | rm -f simv 6 | -------------------------------------------------------------------------------- /divider/syn_sim/clean: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -fr csrc DVEfiles simv.daidir 4 | rm -f *.vpd *.key 5 | rm -f simv 6 | -------------------------------------------------------------------------------- /document/linux command.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhujingyang520/vlsi_project/HEAD/document/linux command.pdf -------------------------------------------------------------------------------- /document/tutorial_slides.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhujingyang520/vlsi_project/HEAD/document/tutorial_slides.pdf -------------------------------------------------------------------------------- /document/EDI13.1workshoplab1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhujingyang520/vlsi_project/HEAD/document/EDI13.1workshoplab1.pdf -------------------------------------------------------------------------------- /divider/behav_sim/run: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | vcs -full64 ../rtl/divider.v divider_tb.v +v2k -debug_all -top divider_tb \ 4 | -timescale=1ns/1ps 5 | -------------------------------------------------------------------------------- /divider/layout/clean: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | rm -fr db reports results clock_report 4 | rm -f encounter.* *.cts_trace *.rguide *.txt 5 | rm -f *.map *.mtarpt *.ctstch 6 | rm -fr celtic extLogDir .cadence 7 | -------------------------------------------------------------------------------- /divider/syn_sim/run: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ################################################################################ 4 | # Specify the filepath of the verilog library file of standard cell 5 | ################################################################################ 6 | VERILOG_LIB=/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Verilog/NangateOpenCellLibrary.v 7 | 8 | vcs -full64 divider.mapped.v divider_tb.v +v2k -debug_all -top divider_tb \ 9 | -timescale=1ns/1ps +neg_tchk +warn=noTFIPC -v $VERILOG_LIB 10 | -------------------------------------------------------------------------------- /divider/layout_sim/run: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ################################################################################ 4 | # Specify the filepath of the verilog library file of standard cell 5 | ################################################################################ 6 | VERILOG_LIB=/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Verilog/NangateOpenCellLibrary.v 7 | 8 | vcs -full64 divider.routed.v divider_tb.v +v2k -debug_all -top divider_tb \ 9 | -timescale=1ns/1ps +neg_tchk +warn=noTFIPC,noSDFCOM_UHICD -v $VERILOG_LIB 10 | -------------------------------------------------------------------------------- /divider/syn/divider.constraints.tcl: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Filename: divider.constraints.tcl 3 | # Author: ZHU Jingyang 4 | # Email: jzhuak@connect.ust.hk 5 | # Affiliation: Hong Kong University of Science and Technology 6 | # ------------------------------------------------------------------------------- 7 | # This is the template constraint script for ELEC5160/EESM5020. 8 | ################################################################################ 9 | 10 | ################################################################################ 11 | # Timing constraint 12 | ################################################################################ 13 | # Critical path constraint: set the desired clock frequency 14 | create_clock -period 5.0 [get_ports clk] 15 | 16 | # Input delay and output delay 17 | set_input_delay -max 1.0 -clock clk \ 18 | [remove_from_collection [all_inputs] [get_ports clk]] 19 | set_output_delay -max 1.0 -clock clk [all_outputs] 20 | 21 | ################################################################################ 22 | # Enviornement attribute constraint 23 | ################################################################################ 24 | # Load on the output ports 25 | set_load 1 [all_outputs] 26 | 27 | # Input transition time on all inputs except clock 28 | set_input_transition 0.1 \ 29 | [remove_from_collection [all_inputs] [get_ports clk]] 30 | -------------------------------------------------------------------------------- /divider/layout/scripts/mmc.view: -------------------------------------------------------------------------------- 1 | # Version:1.0 MMMC View Definition File 2 | # Do Not Remove Above Line 3 | create_rc_corner -name rc_best -cap_table {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/captables/NCSU_FreePDK_45nm.capTbl} -T {0} -preRoute_res {1.34236} -preRoute_cap {1.110066} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.34236} -postRoute_cap {0.960234} -postRoute_xcap {1.22327} -postRoute_clkres {0.0} -postRoute_clkcap {0.969117 0 0} 4 | create_rc_corner -name rc_worst -cap_table {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/captables/NCSU_FreePDK_45nm.capTbl} -T {125} -preRoute_res {1.34236} -preRoute_cap {1.10066} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.34236} -postRoute_cap {0.960234} -postRoute_xcap {1.22327} -postRoute_clkres {0.0} -postRoute_clkcap {0.969117 0 0} 5 | create_library_set -name lib_slow -timing {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM/NangateOpenCellLibrary_slow.lib} 6 | create_library_set -name lib_fast -timing {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM/NangateOpenCellLibrary_fast.lib} 7 | create_constraint_mode -name constraint_slow -sdc_files {designs/divider.mapped.sdc} 8 | create_delay_corner -name delay_corner_slow -library_set {lib_slow} -rc_corner {rc_worst} 9 | create_delay_corner -name delay_corner_fast -library_set {lib_fast} -rc_corner {rc_best} 10 | create_analysis_view -name analysis_slow -constraint_mode {constraint_slow} -delay_corner {delay_corner_slow} 11 | create_analysis_view -name analysis_fast -constraint_mode {constraint_slow} -delay_corner {delay_corner_fast} 12 | set_analysis_view -setup {analysis_slow} -hold {analysis_fast} 13 | -------------------------------------------------------------------------------- /divider/layout/scripts/mmc2.view: -------------------------------------------------------------------------------- 1 | # Version:1.0 MMMC View Definition File 2 | # Do Not Remove Above Line 3 | create_rc_corner -name rc_best -cap_table {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/fireice/best.captbl} -T {0} -preRoute_res {1.34236} -preRoute_cap {1.10066} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.34236} -postRoute_cap {0.960234} -postRoute_xcap {1.22327} -postRoute_clkres {0.0} -postRoute_clkcap {0.969117 0 0} -qx_tech_file {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/fireice/best.tch} 4 | create_rc_corner -name rc_worst -cap_table {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/fireice/worst.captbl} -T {125} -preRoute_res {1.34236} -preRoute_cap {1.10066} -preRoute_clkres {0.0} -preRoute_clkcap {0.0} -postRoute_res {1.34236} -postRoute_cap {0.960234} -postRoute_xcap {1.22327} -postRoute_clkres {0.0} -postRoute_clkcap {0.969117 0 0} -qx_tech_file {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/fireice/worst.tch} 5 | create_library_set -name lib_slow -timing {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM/NangateOpenCellLibrary_slow.lib} -si {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/celtic/slow.cdb} 6 | create_library_set -name lib_fast -timing {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM/NangateOpenCellLibrary_fast.lib} -si {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/celtic/fast.cdb} 7 | create_constraint_mode -name constraint_slow -sdc_files {designs/divider.mapped.sdc} 8 | create_delay_corner -name delay_corner_slow -library_set {lib_slow} -rc_corner {rc_worst} 9 | create_delay_corner -name delay_corner_fast -library_set {lib_fast} -rc_corner {rc_best} 10 | create_analysis_view -name analysis_slow -constraint_mode {constraint_slow} -delay_corner {delay_corner_slow} 11 | create_analysis_view -name analysis_fast -constraint_mode {constraint_slow} -delay_corner {delay_corner_fast} 12 | set_analysis_view -setup {analysis_slow} -hold {analysis_fast} 13 | -------------------------------------------------------------------------------- /divider/behav_sim/divider_tb.v: -------------------------------------------------------------------------------- 1 | // ============================================================================= 2 | // Filename: divider_tb.v 3 | // Author: ZHU, Jingyang 4 | // Email: jzhuak@connect.ust.hk 5 | // Affiliation: Hong Kong University of Science and Technology 6 | // ----------------------------------------------------------------------------- 7 | // 8 | // This file exports the testbench for divider module. 9 | // It generates the adhoc input stimulus for the divider. 10 | // ============================================================================= 11 | 12 | `timescale 1 ns / 1 ps 13 | 14 | module divider_tb; 15 | 16 | // ---------------------------------- 17 | // Local parameter declaration 18 | // ---------------------------------- 19 | localparam CLK_PERIOD = 5.0; // clock period: 5ns 20 | 21 | // ---------------------------------- 22 | // Interface of the divider module 23 | // ---------------------------------- 24 | reg clk, rst, start; 25 | reg [31:0] dividend, divisor; 26 | wire done; 27 | wire [31:0] quotient, remainder; 28 | 29 | // ---------------------------------- 30 | // Instantiate the divider 31 | // ---------------------------------- 32 | divider uut ( 33 | .clk (clk), // system clock 34 | .rst (rst), // system reset (active high) 35 | 36 | .start (start), // flag for starting division 37 | .dividend (dividend), // operand 1: dividend 38 | .divisor (divisor), // operand 2: divisor 39 | 40 | .done (done), // flag for finishing division 41 | .quotient (quotient), // result 1: quotient 42 | .remainder (remainder) // result 2: remainder 43 | ); 44 | 45 | // ---------------------------------- 46 | // Clock generation 47 | // ---------------------------------- 48 | initial begin 49 | clk = 1'b0; 50 | forever #(CLK_PERIOD/2.0) clk = ~clk; 51 | end 52 | 53 | // ---------------------------------- 54 | // Input stimulus 55 | // Generate the ad-hoc stimulus 56 | // ---------------------------------- 57 | initial begin 58 | // Reset 59 | rst = 1'b1; 60 | start = 1'b0; 61 | dividend = 32'd0; 62 | divisor = 32'd0; 63 | #(2*CLK_PERIOD) rst = 1'b0; 64 | 65 | // Input stimulus 1: 10/7 66 | @(negedge clk); 67 | start = 1'b1; 68 | dividend = 32'd10; 69 | divisor = 32'd7; 70 | #CLK_PERIOD; 71 | start = 1'b0; 72 | 73 | // Input stimulus 2: 100/100 74 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 75 | start = 1'b1; 76 | dividend = 32'd100; 77 | divisor = 32'd100; 78 | #CLK_PERIOD; 79 | start = 1'b0; 80 | 81 | // Input stimulus 3: 100/7 82 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 83 | start = 1'b1; 84 | dividend = 32'd100; 85 | divisor = 32'd7; 86 | #CLK_PERIOD; 87 | start = 1'b0; 88 | 89 | // Input stimulus 4: 100/0 90 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 91 | start = 1'b1; 92 | dividend = 32'd100; 93 | divisor = 32'd0; 94 | #CLK_PERIOD; 95 | start = 1'b0; 96 | 97 | // Input stimulus 4: i70/150 98 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 99 | start = 1'b1; 100 | dividend = 32'd70; 101 | divisor = 32'd150; 102 | #CLK_PERIOD; 103 | start = 1'b0; 104 | 105 | // Finish the testbench 106 | wait(done == 1'b1); #(CLK_PERIOD*2); 107 | $finish; 108 | end 109 | 110 | // ---------------------------------- 111 | // Output monitor 112 | // ---------------------------------- 113 | always @(posedge clk) begin 114 | if (done) begin 115 | $display("%0d / %0d: quotient = %0d, remainder = %0d", dividend, divisor, 116 | quotient, remainder); 117 | end 118 | end 119 | 120 | endmodule 121 | -------------------------------------------------------------------------------- /divider/layout_sim/divider_tb.v: -------------------------------------------------------------------------------- 1 | // ============================================================================= 2 | // Filename: divider_tb.v 3 | // Author: ZHU, Jingyang 4 | // Email: jzhuak@connect.ust.hk 5 | // Affiliation: Hong Kong University of Science and Technology 6 | // ----------------------------------------------------------------------------- 7 | // 8 | // This file exports the testbench for divider module. 9 | // It generates the adhoc input stimulus for the divider. 10 | // ============================================================================= 11 | 12 | `timescale 1 ns / 1 ps 13 | 14 | module divider_tb; 15 | 16 | // ---------------------------------- 17 | // Local parameter declaration 18 | // ---------------------------------- 19 | localparam CLK_PERIOD = 5.0; // clock period: 5ns 20 | 21 | // ---------------------------------- 22 | // Interface of the divider module 23 | // ---------------------------------- 24 | reg clk, rst, start; 25 | reg [31:0] dividend, divisor; 26 | wire done; 27 | wire [31:0] quotient, remainder; 28 | 29 | // ---------------------------------- 30 | // Instantiate the divider 31 | // ---------------------------------- 32 | divider uut ( 33 | .clk (clk), // system clock 34 | .rst (rst), // system reset (active high) 35 | 36 | .start (start), // flag for starting division 37 | .dividend (dividend), // operand 1: dividend 38 | .divisor (divisor), // operand 2: divisor 39 | 40 | .done (done), // flag for finishing division 41 | .quotient (quotient), // result 1: quotient 42 | .remainder (remainder) // result 2: remainder 43 | ); 44 | 45 | // ---------------------------------- 46 | // For gate-level simulation, we 47 | // should backannotate the SDF file 48 | // ---------------------------------- 49 | initial begin 50 | $sdf_annotate("divider.sdf", uut); 51 | end 52 | 53 | // ---------------------------------- 54 | // Clock generation 55 | // ---------------------------------- 56 | initial begin 57 | clk = 1'b0; 58 | forever #(CLK_PERIOD/2.0) clk = ~clk; 59 | end 60 | 61 | // ---------------------------------- 62 | // Input stimulus 63 | // Generate the ad-hoc stimulus 64 | // ---------------------------------- 65 | initial begin 66 | // Reset 67 | rst = 1'b1; 68 | start = 1'b0; 69 | dividend = 32'd0; 70 | divisor = 32'd0; 71 | #(2*CLK_PERIOD) rst = 1'b0; 72 | 73 | // Input stimulus 1: 10/7 74 | @(negedge clk); 75 | start = 1'b1; 76 | dividend = 32'd10; 77 | divisor = 32'd7; 78 | #CLK_PERIOD; 79 | start = 1'b0; 80 | 81 | // Input stimulus 2: 100/100 82 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 83 | start = 1'b1; 84 | dividend = 32'd100; 85 | divisor = 32'd100; 86 | #CLK_PERIOD; 87 | start = 1'b0; 88 | 89 | // Input stimulus 3: 100/7 90 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 91 | start = 1'b1; 92 | dividend = 32'd100; 93 | divisor = 32'd7; 94 | #CLK_PERIOD; 95 | start = 1'b0; 96 | 97 | // Input stimulus 4: 100/0 98 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 99 | start = 1'b1; 100 | dividend = 32'd100; 101 | divisor = 32'd0; 102 | #CLK_PERIOD; 103 | start = 1'b0; 104 | 105 | // Input stimulus 4: i70/150 106 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 107 | start = 1'b1; 108 | dividend = 32'd70; 109 | divisor = 32'd150; 110 | #CLK_PERIOD; 111 | start = 1'b0; 112 | 113 | // Finish the testbench 114 | wait(done == 1'b1); #(CLK_PERIOD*2); 115 | $finish; 116 | end 117 | 118 | // ---------------------------------- 119 | // Output monitor 120 | // ---------------------------------- 121 | always @(posedge clk) begin 122 | if (done) begin 123 | $display("%0d / %0d: quotient = %0d, remainder = %0d", dividend, divisor, 124 | quotient, remainder); 125 | end 126 | end 127 | 128 | endmodule 129 | -------------------------------------------------------------------------------- /divider/syn_sim/divider_tb.v: -------------------------------------------------------------------------------- 1 | // ============================================================================= 2 | // Filename: divider_tb.v 3 | // Author: ZHU, Jingyang 4 | // Email: jzhuak@connect.ust.hk 5 | // Affiliation: Hong Kong University of Science and Technology 6 | // ----------------------------------------------------------------------------- 7 | // 8 | // This file exports the testbench for divider module. 9 | // It generates the adhoc input stimulus for the divider. 10 | // ============================================================================= 11 | 12 | `timescale 1 ns / 1 ps 13 | 14 | module divider_tb; 15 | 16 | // ---------------------------------- 17 | // Local parameter declaration 18 | // ---------------------------------- 19 | localparam CLK_PERIOD = 5.0; // clock period: 5ns 20 | 21 | // ---------------------------------- 22 | // Interface of the divider module 23 | // ---------------------------------- 24 | reg clk, rst, start; 25 | reg [31:0] dividend, divisor; 26 | wire done; 27 | wire [31:0] quotient, remainder; 28 | 29 | // ---------------------------------- 30 | // Instantiate the divider 31 | // ---------------------------------- 32 | divider uut ( 33 | .clk (clk), // system clock 34 | .rst (rst), // system reset (active high) 35 | 36 | .start (start), // flag for starting division 37 | .dividend (dividend), // operand 1: dividend 38 | .divisor (divisor), // operand 2: divisor 39 | 40 | .done (done), // flag for finishing division 41 | .quotient (quotient), // result 1: quotient 42 | .remainder (remainder) // result 2: remainder 43 | ); 44 | 45 | // ---------------------------------- 46 | // For gate-level simulation, we 47 | // should backannotate the SDF file 48 | // ---------------------------------- 49 | initial begin 50 | $sdf_annotate("divider.mapped.sdf", uut); 51 | end 52 | 53 | // ---------------------------------- 54 | // Clock generation 55 | // ---------------------------------- 56 | initial begin 57 | clk = 1'b0; 58 | forever #(CLK_PERIOD/2.0) clk = ~clk; 59 | end 60 | 61 | // ---------------------------------- 62 | // Input stimulus 63 | // Generate the ad-hoc stimulus 64 | // ---------------------------------- 65 | initial begin 66 | // Reset 67 | rst = 1'b1; 68 | start = 1'b0; 69 | dividend = 32'd0; 70 | divisor = 32'd0; 71 | #(2*CLK_PERIOD) rst = 1'b0; 72 | 73 | // Input stimulus 1: 10/7 74 | @(negedge clk); 75 | start = 1'b1; 76 | dividend = 32'd10; 77 | divisor = 32'd7; 78 | #CLK_PERIOD; 79 | start = 1'b0; 80 | 81 | // Input stimulus 2: 100/100 82 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 83 | start = 1'b1; 84 | dividend = 32'd100; 85 | divisor = 32'd100; 86 | #CLK_PERIOD; 87 | start = 1'b0; 88 | 89 | // Input stimulus 3: 100/7 90 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 91 | start = 1'b1; 92 | dividend = 32'd100; 93 | divisor = 32'd7; 94 | #CLK_PERIOD; 95 | start = 1'b0; 96 | 97 | // Input stimulus 4: 100/0 98 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 99 | start = 1'b1; 100 | dividend = 32'd100; 101 | divisor = 32'd0; 102 | #CLK_PERIOD; 103 | start = 1'b0; 104 | 105 | // Input stimulus 4: i70/150 106 | wait(done == 1'b1); #CLK_PERIOD; @(negedge clk); 107 | start = 1'b1; 108 | dividend = 32'd70; 109 | divisor = 32'd150; 110 | #CLK_PERIOD; 111 | start = 1'b0; 112 | 113 | // Finish the testbench 114 | wait(done == 1'b1); #(CLK_PERIOD*2); 115 | $finish; 116 | end 117 | 118 | // ---------------------------------- 119 | // Output monitor 120 | // ---------------------------------- 121 | always @(posedge clk) begin 122 | if (done) begin 123 | $display("%0d / %0d: quotient = %0d, remainder = %0d", dividend, divisor, 124 | quotient, remainder); 125 | end 126 | end 127 | 128 | endmodule 129 | -------------------------------------------------------------------------------- /divider/syn/run.tcl: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Filename: dc.tcl 3 | # Author: ZHU Jingyang 4 | # Email: jzhuak@connect.ust.hk 5 | # Affiliation: Hong Kong University of Science and Technology 6 | # ------------------------------------------------------------------------------- 7 | # This is the template Design Compiler script for ELEC5160/EESM5020. 8 | ################################################################################ 9 | 10 | ################################################################################ 11 | # Step 0: create directories for results and reports 12 | ################################################################################ 13 | file mkdir reports; # store area, timing, power reports 14 | file mkdir results; # store design 15 | 16 | ################################################################################ 17 | # Step 1: digital standard cell library set up 18 | # You should specify the following paths accordingly: 19 | # - search_path 20 | # - target_library 21 | # - link_library 22 | ################################################################################ 23 | set_app_var search_path ". /mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM ../rtl $search_path" 24 | set_app_var target_library "NangateOpenCellLibrary_slow.db" 25 | set_app_var synthetic_library dw_foundation.sldb 26 | set_app_var link_library "* $target_library $synthetic_library" 27 | 28 | ################################################################################ 29 | # Step 2: import design 30 | # You should specify the HDL files for your design accordingly. 31 | # Note: the HDL files should be located in the search_path you defined above. 32 | # Please do NOT import testbench or behavior memory model here. 33 | ################################################################################ 34 | define_design_lib WORK -path ./WORK 35 | analyze -format verilog {divider.v} 36 | elaborate divider; # top module name 37 | 38 | # store the unmapped results 39 | write -hierarchy -format ddc -output results/divider.unmapped.ddc 40 | 41 | ################################################################################ 42 | # Step 3: constrain your design 43 | # You should specify the critical path, the input & output delay and the 44 | # environment attribute of your design, so that Design Compiler can correctly 45 | # synthesize your design with the required specfication. 46 | ################################################################################ 47 | # All the constraints are written in the following tcl script 48 | source divider.constraints.tcl 49 | 50 | ################################################################################ 51 | # Create default path groups 52 | # 53 | # Seperate these paths can help improve optimization results. 54 | ################################################################################ 55 | set ports_clock_root \ 56 | [filter_collection [get_attribute [get_clocks] sources] object_class==port] 57 | group_path -name REGOUT -to [all_outputs] 58 | group_path -name REGIN -from [remove_from_collection [all_inputs] \ 59 | ${ports_clock_root}] 60 | group_path -name FEEDTHROUGH -from \ 61 | [remove_from_collection [all_inputs] ${ports_clock_root}] -to [all_outputs] 62 | 63 | ################################################################################ 64 | # Apply Additional Optimization Constraints 65 | ################################################################################ 66 | # Prevent assignment statements in the Verilog netlist. 67 | set_fix_multiple_port_nets -all -buffer_constants 68 | 69 | ################################################################################ 70 | # Check for Design Errors. It is a good habit to check the design before you run 71 | # the synthesis. 72 | ################################################################################ 73 | check_design -summary 74 | check_design > reports/divider.check_design.rpt; # dump to the file 75 | 76 | ################################################################################ 77 | # Step 4: compile the design 78 | # There exits lots of option for compile command. Please check the manual of 79 | # compile for further info. 80 | ################################################################################ 81 | compile 82 | 83 | ################################################################################ 84 | # Note: compile_ultra does not work for some open source libraries, i.e. Nangate 85 | # since there are some cells missing for these libraries. 86 | # Sol: use compile instead. You can use compile_ultra for the commerial library 87 | # such TSMC45nm, which has a complete set of gates supported. 88 | # 89 | # compile_ultra -no_autoungroup; # keep hierarchy for the purpose of debug 90 | ################################################################################ 91 | 92 | # High-effort area optimization which improves the area without degrading the 93 | # timing or leakage of the compiled design 94 | optimize_netlist -area 95 | 96 | ################################################################################ 97 | # Step 5: write out final design and reports 98 | # The files include: 99 | # - .ddc: binary format used for subsequent Design Compiler sessions 100 | # - .v: Verilog netlist for gate-level simulation and P&R 101 | # - .sdf: SDF backannotated file containing gate and net latency 102 | # - .sdc: SDC constraints for ASCII flow 103 | ################################################################################ 104 | change_names -rules verilog -hierarchy 105 | 106 | # Write out design 107 | write -format verilog -hierarchy -output results/divider.mapped.v 108 | write -format ddc -hierarchy -output results/divider.mapped.ddc 109 | write_sdf results/divider.mapped.sdf 110 | write_sdc -nosplit results/divider.mapped.sdc 111 | 112 | # Generate reports 113 | report_qor > reports/divider.mapped.qor.rpt 114 | report_timing -transition_time -nets -attribute -nosplit \ 115 | > reports/divider.mapped.timing.rpt 116 | report_area -nosplit > reports/divider.mapped.area.rpt 117 | report_power -nosplit > reports/divider.mapped.power.rpt 118 | 119 | ################################################################################ 120 | # Exit Design Compiler 121 | ################################################################################ 122 | exit 123 | -------------------------------------------------------------------------------- /divider/rtl/divider.v: -------------------------------------------------------------------------------- 1 | // ============================================================================= 2 | // Filename: divider.v 3 | // Author: ZHU, Jingyang 4 | // Email: jzhuak@connect.ust.hk 5 | // Affiliation: Hong Kong University of Science and Technology 6 | // ----------------------------------------------------------------------------- 7 | // 8 | // This file implements an N-bit divider using the iterative algorithm. 9 | // The divider accepts 2 unsigned operands: dividend and divisor and generates 10 | // 2 results: quotient and remainder. The relation of input operands with output 11 | // results can be expressed as follows: 12 | // 13 | // dividend = quotient * divisor + remainder 14 | // 15 | // where the remainder is smaller than the divisor. 16 | // ============================================================================= 17 | 18 | module divider #(parameter N = 32) ( 19 | input wire clk, // system clock 20 | input wire rst, // system reset (active high) 21 | 22 | input wire start, // flag for starting division 23 | input wire [N-1:0] dividend, // operand 1: dividend 24 | input wire [N-1:0] divisor, // operand 2: divisor 25 | 26 | output wire done, // flag for finishing division 27 | output reg [N-1:0] quotient, // result 1: quotient 28 | output reg [N-1:0] remainder // result 2: remainder 29 | ); 30 | 31 | // ---------------------------------------------------- 32 | // Part I: state encoding 33 | // There exists 4 different states in divider 34 | // - STATE_IDLE: initial state of divider is idle 35 | // - STATE_DIV_BY_ZERO: error state when divisor is 0 36 | // - STATE_DIV_ON: calculating state of divider 37 | // - STATE_DIV_DONE: finish state of divider 38 | // ---------------------------------------------------- 39 | localparam STATE_IDLE = 2'b00, 40 | STATE_DIV_BY_ZERO = 2'b01, 41 | STATE_DIV_ON = 2'b10, 42 | STATE_DIV_DONE = 2'b11; 43 | 44 | // ---------------------------------------------------- 45 | // Internal variables 46 | // ---------------------------------------------------- 47 | reg [1:0] state_reg, state_next; // state register of the divider 48 | reg [N-1:0] divisor_reg, divisor_next; // divisor register 49 | reg [2*N:0] remainder_reg, remainder_next; // remainder register 50 | reg [clog2(N):0] cnt_reg, cnt_next; // counter register during division 51 | wire [N:0] alu_result; // N+1 bits ALU 52 | 53 | // ---------------------------------------------------- 54 | // Part II: sequential logic (synchronous DFF) 55 | // Assign the value of DFFs including 56 | // - control state register 57 | // - divisor register 58 | // - remainder register 59 | // - counter register 60 | // ---------------------------------------------------- 61 | always @(posedge clk) begin 62 | if (rst) begin 63 | state_reg <= STATE_IDLE; 64 | divisor_reg <= 0; 65 | remainder_reg <= 0; 66 | cnt_reg <= 0; 67 | end else begin 68 | state_reg <= state_next; 69 | divisor_reg <= divisor_next; 70 | remainder_reg <= remainder_next; 71 | cnt_reg <= cnt_next; 72 | end 73 | end 74 | 75 | // ---------------------------------------------------- 76 | // Part III: ALU result 77 | // The ALU simply compares the relation between 78 | // remainder register and divisor register (subtract) 79 | // ---------------------------------------------------- 80 | // TODO: place your code here 81 | assign alu_result = 0; 82 | 83 | // ---------------------------------------------------- 84 | // Part III: next state logic (combinational logic) 85 | // ---------------------------------------------------- 86 | always @(*) begin 87 | // default value for the outputs 88 | state_next = state_reg; 89 | divisor_next = divisor_reg; 90 | remainder_next = remainder_reg; 91 | cnt_next = cnt_reg; 92 | case(state_reg) 93 | STATE_IDLE: begin 94 | if (start) begin 95 | if (divisor == 0) begin 96 | // next state transfers to STATE_DIV_BY_ZERO 97 | // TODO: place your code here 98 | 99 | end else begin 100 | // next state transfers to STATE_DIV_ON 101 | // store the divisor to the register 102 | // store the dividend to the register 103 | // reset the counter during STATE_DIV_ON 104 | // TODO: place your code here 105 | 106 | end 107 | end 108 | end 109 | 110 | STATE_DIV_BY_ZERO: begin 111 | // next state transfers to STATE_IDLE 112 | // TODO: place your code here 113 | 114 | end 115 | 116 | STATE_DIV_ON: begin 117 | // counter to track the division progress: increment each cycle 118 | // TODO: place your code here 119 | 120 | // next state transfers to STATE_DIV_DONE after N iterations 121 | // TODO: place your code here 122 | 123 | 124 | // remainder register next value 125 | // - alu_result < 0: shift 1'b0 into remainder register 126 | // - alu_result >= 0: update MSB of remainder register with alu_result 127 | // and shift 1'b1 into remainder register 128 | // TODO: place your code here 129 | 130 | end 131 | 132 | STATE_DIV_DONE: begin 133 | // next state transfers to STATE_IDLE 134 | // TODO: place your code here 135 | 136 | end 137 | endcase 138 | end 139 | 140 | // ---------------------------------------------------- 141 | // Part IV: output logic assignment (combinatinoal 142 | // logic) 143 | // ---------------------------------------------------- 144 | // assert done when divided by 0 or the division is done 145 | // TODO: place your code here 146 | assign done = 0; 147 | // assign the quotient and remainder from the internal remainder register 148 | always @(*) begin 149 | if (state_reg == STATE_DIV_BY_ZERO) begin 150 | // outputs quotient and remainder as 0s when divided by 0 151 | // register 152 | // TODO: place your code here 153 | 154 | end else if (state_reg == STATE_DIV_DONE) begin 155 | // outputs calculated quotient and remainder from the internal remainder 156 | // register 157 | // TODO: place your code here 158 | 159 | end else begin 160 | // outputs quotient and remainder as 0s as default 161 | quotient = 0; 162 | remainder = 0; 163 | end 164 | end 165 | 166 | // ---------------------------------------------------- 167 | // Useful function: clog2 168 | // Return the ceil of log2(x) 169 | // ---------------------------------------------------- 170 | function integer clog2(input integer x); 171 | integer i; 172 | begin 173 | clog2 = 0; 174 | for (i = x - 1; i > 0; i = i >> 1) begin 175 | clog2 = clog2 + 1; 176 | end 177 | end 178 | endfunction 179 | 180 | endmodule 181 | -------------------------------------------------------------------------------- /divider/layout/scripts/divider.ioc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Filename: divisor.ioc 3 | # Author: ZHU, Jingyang 4 | # Email: jzhuak@connect.ust.hk 5 | # Affiliation: Hong Kong University of Science and Technology 6 | # ------------------------------------------------------------------------------ 7 | # 8 | # This file defines the IO location constraint of the divider module. The input 9 | # pins are allocated at the left and right edge (on Metal 5). The output pins 10 | # are allocated at the top and bottom edge (on Metal 6). The space between each 11 | # pin is set as 1.5um. There is an offset of 1um to ensure the module pins do 12 | # not have any overlap with each other. Each pin dimension is set to be 0.14um x 13 | # 0.14um. 14 | # 15 | # Note: if we do not provide the IO location constraint for our divider module, 16 | # the Encounter will randomly place our pins. 17 | ################################################################################ 18 | 19 | (globals 20 | version = 3 21 | io_order = default 22 | space = 1.5 23 | ) 24 | (iopin 25 | (top 26 | (pin name="quotient[0]" layer=6 width=0.1400 depth=0.1400 offset=1.0) 27 | (pin name="quotient[1]" layer=6 width=0.1400 depth=0.1400 ) 28 | (pin name="quotient[2]" layer=6 width=0.1400 depth=0.1400 ) 29 | (pin name="quotient[3]" layer=6 width=0.1400 depth=0.1400 ) 30 | (pin name="quotient[4]" layer=6 width=0.1400 depth=0.1400 ) 31 | (pin name="quotient[5]" layer=6 width=0.1400 depth=0.1400 ) 32 | (pin name="quotient[6]" layer=6 width=0.1400 depth=0.1400 ) 33 | (pin name="quotient[7]" layer=6 width=0.1400 depth=0.1400 ) 34 | (pin name="quotient[8]" layer=6 width=0.1400 depth=0.1400 ) 35 | (pin name="quotient[9]" layer=6 width=0.1400 depth=0.1400 ) 36 | (pin name="quotient[10]" layer=6 width=0.1400 depth=0.1400 ) 37 | (pin name="quotient[11]" layer=6 width=0.1400 depth=0.1400 ) 38 | (pin name="quotient[12]" layer=6 width=0.1400 depth=0.1400 ) 39 | (pin name="quotient[13]" layer=6 width=0.1400 depth=0.1400 ) 40 | (pin name="quotient[14]" layer=6 width=0.1400 depth=0.1400 ) 41 | (pin name="quotient[15]" layer=6 width=0.1400 depth=0.1400 ) 42 | (pin name="done" layer=6 width=0.1400 depth=0.1400 ) 43 | (pin name="quotient[16]" layer=6 width=0.1400 depth=0.1400 ) 44 | (pin name="quotient[17]" layer=6 width=0.1400 depth=0.1400 ) 45 | (pin name="quotient[18]" layer=6 width=0.1400 depth=0.1400 ) 46 | (pin name="quotient[19]" layer=6 width=0.1400 depth=0.1400 ) 47 | (pin name="quotient[20]" layer=6 width=0.1400 depth=0.1400 ) 48 | (pin name="quotient[21]" layer=6 width=0.1400 depth=0.1400 ) 49 | (pin name="quotient[22]" layer=6 width=0.1400 depth=0.1400 ) 50 | (pin name="quotient[23]" layer=6 width=0.1400 depth=0.1400 ) 51 | (pin name="quotient[24]" layer=6 width=0.1400 depth=0.1400 ) 52 | (pin name="quotient[25]" layer=6 width=0.1400 depth=0.1400 ) 53 | (pin name="quotient[26]" layer=6 width=0.1400 depth=0.1400 ) 54 | (pin name="quotient[27]" layer=6 width=0.1400 depth=0.1400 ) 55 | (pin name="quotient[28]" layer=6 width=0.1400 depth=0.1400 ) 56 | (pin name="quotient[29]" layer=6 width=0.1400 depth=0.1400 ) 57 | (pin name="quotient[30]" layer=6 width=0.1400 depth=0.1400 ) 58 | (pin name="quotient[31]" layer=6 width=0.1400 depth=0.1400 ) 59 | ) 60 | (left 61 | (pin name="dividend[0]" layer=5 width=0.1400 depth=0.1400 offset=1.0) 62 | (pin name="dividend[1]" layer=5 width=0.1400 depth=0.1400 ) 63 | (pin name="dividend[2]" layer=5 width=0.1400 depth=0.1400 ) 64 | (pin name="dividend[3]" layer=5 width=0.1400 depth=0.1400 ) 65 | (pin name="dividend[4]" layer=5 width=0.1400 depth=0.1400 ) 66 | (pin name="dividend[5]" layer=5 width=0.1400 depth=0.1400 ) 67 | (pin name="dividend[6]" layer=5 width=0.1400 depth=0.1400 ) 68 | (pin name="dividend[7]" layer=5 width=0.1400 depth=0.1400 ) 69 | (pin name="dividend[8]" layer=5 width=0.1400 depth=0.1400 ) 70 | (pin name="dividend[9]" layer=5 width=0.1400 depth=0.1400 ) 71 | (pin name="dividend[10]" layer=5 width=0.1400 depth=0.1400 ) 72 | (pin name="dividend[11]" layer=5 width=0.1400 depth=0.1400 ) 73 | (pin name="dividend[12]" layer=5 width=0.1400 depth=0.1400 ) 74 | (pin name="dividend[13]" layer=5 width=0.1400 depth=0.1400 ) 75 | (pin name="dividend[14]" layer=5 width=0.1400 depth=0.1400 ) 76 | (pin name="dividend[15]" layer=5 width=0.1400 depth=0.1400 ) 77 | (pin name="clk" layer=5 width=0.1400 depth=0.1400 ) 78 | (pin name="rst" layer=5 width=0.1400 depth=0.1400 ) 79 | (pin name="dividend[16]" layer=5 width=0.1400 depth=0.1400 ) 80 | (pin name="dividend[17]" layer=5 width=0.1400 depth=0.1400 ) 81 | (pin name="dividend[18]" layer=5 width=0.1400 depth=0.1400 ) 82 | (pin name="dividend[19]" layer=5 width=0.1400 depth=0.1400 ) 83 | (pin name="dividend[20]" layer=5 width=0.1400 depth=0.1400 ) 84 | (pin name="dividend[21]" layer=5 width=0.1400 depth=0.1400 ) 85 | (pin name="dividend[22]" layer=5 width=0.1400 depth=0.1400 ) 86 | (pin name="dividend[23]" layer=5 width=0.1400 depth=0.1400 ) 87 | (pin name="dividend[24]" layer=5 width=0.1400 depth=0.1400 ) 88 | (pin name="dividend[25]" layer=5 width=0.1400 depth=0.1400 ) 89 | (pin name="dividend[26]" layer=5 width=0.1400 depth=0.1400 ) 90 | (pin name="dividend[27]" layer=5 width=0.1400 depth=0.1400 ) 91 | (pin name="dividend[28]" layer=5 width=0.1400 depth=0.1400 ) 92 | (pin name="dividend[29]" layer=5 width=0.1400 depth=0.1400 ) 93 | (pin name="dividend[30]" layer=5 width=0.1400 depth=0.1400 ) 94 | (pin name="dividend[31]" layer=5 width=0.1400 depth=0.1400 ) 95 | ) 96 | (bottom 97 | (pin name="remainder[31]" layer=6 width=0.1400 depth=0.1400 offset=1.0) 98 | (pin name="remainder[30]" layer=6 width=0.1400 depth=0.1400 ) 99 | (pin name="remainder[29]" layer=6 width=0.1400 depth=0.1400 ) 100 | (pin name="remainder[28]" layer=6 width=0.1400 depth=0.1400 ) 101 | (pin name="remainder[27]" layer=6 width=0.1400 depth=0.1400 ) 102 | (pin name="remainder[26]" layer=6 width=0.1400 depth=0.1400 ) 103 | (pin name="remainder[25]" layer=6 width=0.1400 depth=0.1400 ) 104 | (pin name="remainder[24]" layer=6 width=0.1400 depth=0.1400 ) 105 | (pin name="remainder[23]" layer=6 width=0.1400 depth=0.1400 ) 106 | (pin name="remainder[22]" layer=6 width=0.1400 depth=0.1400 ) 107 | (pin name="remainder[21]" layer=6 width=0.1400 depth=0.1400 ) 108 | (pin name="remainder[20]" layer=6 width=0.1400 depth=0.1400 ) 109 | (pin name="remainder[19]" layer=6 width=0.1400 depth=0.1400 ) 110 | (pin name="remainder[18]" layer=6 width=0.1400 depth=0.1400 ) 111 | (pin name="remainder[17]" layer=6 width=0.1400 depth=0.1400 ) 112 | (pin name="remainder[16]" layer=6 width=0.1400 depth=0.1400 ) 113 | (pin name="remainder[15]" layer=6 width=0.1400 depth=0.1400 ) 114 | (pin name="remainder[14]" layer=6 width=0.1400 depth=0.1400 ) 115 | (pin name="remainder[13]" layer=6 width=0.1400 depth=0.1400 ) 116 | (pin name="remainder[12]" layer=6 width=0.1400 depth=0.1400 ) 117 | (pin name="remainder[11]" layer=6 width=0.1400 depth=0.1400 ) 118 | (pin name="remainder[10]" layer=6 width=0.1400 depth=0.1400 ) 119 | (pin name="remainder[9]" layer=6 width=0.1400 depth=0.1400 ) 120 | (pin name="remainder[8]" layer=6 width=0.1400 depth=0.1400 ) 121 | (pin name="remainder[7]" layer=6 width=0.1400 depth=0.1400 ) 122 | (pin name="remainder[6]" layer=6 width=0.1400 depth=0.1400 ) 123 | (pin name="remainder[5]" layer=6 width=0.1400 depth=0.1400 ) 124 | (pin name="remainder[4]" layer=6 width=0.1400 depth=0.1400 ) 125 | (pin name="remainder[3]" layer=6 width=0.1400 depth=0.1400 ) 126 | (pin name="remainder[2]" layer=6 width=0.1400 depth=0.1400 ) 127 | (pin name="remainder[1]" layer=6 width=0.1400 depth=0.1400 ) 128 | (pin name="remainder[0]" layer=6 width=0.1400 depth=0.1400 ) 129 | ) 130 | (right 131 | (pin name="divisor[31]" layer=5 width=0.1400 depth=0.1400 offset=1.0) 132 | (pin name="divisor[30]" layer=5 width=0.1400 depth=0.1400 ) 133 | (pin name="divisor[29]" layer=5 width=0.1400 depth=0.1400 ) 134 | (pin name="divisor[28]" layer=5 width=0.1400 depth=0.1400 ) 135 | (pin name="divisor[27]" layer=5 width=0.1400 depth=0.1400 ) 136 | (pin name="divisor[26]" layer=5 width=0.1400 depth=0.1400 ) 137 | (pin name="divisor[25]" layer=5 width=0.1400 depth=0.1400 ) 138 | (pin name="divisor[24]" layer=5 width=0.1400 depth=0.1400 ) 139 | (pin name="divisor[23]" layer=5 width=0.1400 depth=0.1400 ) 140 | (pin name="divisor[22]" layer=5 width=0.1400 depth=0.1400 ) 141 | (pin name="divisor[21]" layer=5 width=0.1400 depth=0.1400 ) 142 | (pin name="divisor[20]" layer=5 width=0.1400 depth=0.1400 ) 143 | (pin name="divisor[19]" layer=5 width=0.1400 depth=0.1400 ) 144 | (pin name="divisor[18]" layer=5 width=0.1400 depth=0.1400 ) 145 | (pin name="divisor[17]" layer=5 width=0.1400 depth=0.1400 ) 146 | (pin name="divisor[16]" layer=5 width=0.1400 depth=0.1400 ) 147 | (pin name="start" layer=5 width=0.1400 depth=0.1400 ) 148 | (pin name="divisor[15]" layer=5 width=0.1400 depth=0.1400 ) 149 | (pin name="divisor[14]" layer=5 width=0.1400 depth=0.1400 ) 150 | (pin name="divisor[13]" layer=5 width=0.1400 depth=0.1400 ) 151 | (pin name="divisor[12]" layer=5 width=0.1400 depth=0.1400 ) 152 | (pin name="divisor[11]" layer=5 width=0.1400 depth=0.1400 ) 153 | (pin name="divisor[10]" layer=5 width=0.1400 depth=0.1400 ) 154 | (pin name="divisor[9]" layer=5 width=0.1400 depth=0.1400 ) 155 | (pin name="divisor[8]" layer=5 width=0.1400 depth=0.1400 ) 156 | (pin name="divisor[7]" layer=5 width=0.1400 depth=0.1400 ) 157 | (pin name="divisor[6]" layer=5 width=0.1400 depth=0.1400 ) 158 | (pin name="divisor[5]" layer=5 width=0.1400 depth=0.1400 ) 159 | (pin name="divisor[4]" layer=5 width=0.1400 depth=0.1400 ) 160 | (pin name="divisor[3]" layer=5 width=0.1400 depth=0.1400 ) 161 | (pin name="divisor[2]" layer=5 width=0.1400 depth=0.1400 ) 162 | (pin name="divisor[1]" layer=5 width=0.1400 depth=0.1400 ) 163 | (pin name="divisor[0]" layer=5 width=0.1400 depth=0.1400 ) 164 | ) 165 | ) 166 | -------------------------------------------------------------------------------- /divider/layout/scripts/top.tcl: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # Filename: top.tcl 3 | # Author: ZHU, Jingyang 4 | # Email: jzhuak@connect.ust.hk 5 | # Affiliation: Hong Kong University of Science and Technology 6 | # ------------------------------------------------------------------------------ 7 | # 8 | # This file autmates the essential flow for running the place & route of the 9 | # divider. The P&R flow is based on the EDI 13.1 official workshop and use the 10 | # PDK of Nangate FreePDK 45nm standard cell. 11 | ################################################################################ 12 | 13 | ################################################################################ 14 | # Step 0: design import 15 | ################################################################################ 16 | # Synthesized verilog netlist from Design Compiler 17 | set init_verilog "designs/divider.mapped.v" 18 | # MMC script: corner settings of PDK library 19 | set init_mmmc_file "scripts/mmc2.view" 20 | # LEF file import: abstract view of layout 21 | set init_lef_file "/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Back_End/lef/NangateOpenCellLibrary.tech.lef /mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Back_End/lef/NangateOpenCellLibrary.macro.lef" 22 | # Power and ground net name 23 | set init_pwr_net VDD 24 | set init_gnd_net VSS 25 | 26 | init_design 27 | 28 | # Here we use the Nangate FreePDK45nm, thereby the process node is set to be 45 29 | setDesignMode -process 45 30 | 31 | ################################################################################ 32 | # Step 1: floorplan 33 | # It will configure the core utilization ratio, module aspect ratio, 34 | # IO pin location. 35 | # Since we do not have the MACRO and our design is very simple, the floorplan is 36 | # automatically handled by the tools. No human interaction is involved, like 37 | # specifying the memory location and placing halo provided in the EDI workshop. 38 | ################################################################################ 39 | # The aspect ratio: 1 40 | # Core utilization ratio: 0.6 41 | # Distance to IO boundary: 6 um 42 | floorPlan -r 1 0.6 6 6 6 6 43 | 44 | # Load IO assignment file: divider.ioc 45 | # It specifies the relative location of module pins and on which metal layer you 46 | # are preferred to place your module pins 47 | loadIoFile "scripts/divider.ioc" -noAdjustDieSize 48 | # Save the checkpoint for floorplan 49 | saveDesign db/divider_floorplan.enc 50 | 51 | ################################################################################ 52 | # Step 2: power plan 53 | # It mainly defines the power ring and power stripe 54 | # Depending on the different technology node, here FreePDK 45nm has 10 metal 55 | # layers. We are using the top metal (M9 & M10 for power rail). 56 | ################################################################################ 57 | # Define the global nets for power and ground 58 | globalNetConnect VDD -type pgpin -pin VDD -all 59 | globalNetConnect VSS -type pgpin -pin VSS -all 60 | globalNetConnect VDD -type tiehi 61 | globalNetConnect VSS -type tielo 62 | 63 | # Add power ring: use top metals (M9 & M10) for power ring and set the ring 64 | # width to be 1.5 and spacing to be 0.9 65 | addRing -center 1 -type core_rings -width 1.5 -spacing 0.9 -nets {VDD VSS} \ 66 | -layer {bottom metal9 top metal9 right metal10 left metal10} 67 | 68 | # Add power stripe: use vertical top metal for power stripe (M10). The width is 69 | # set to be 1.25 and spacing to be 0.9. There is only 1 set of power stripe 70 | # starting from the left offset 20.0 (roughly middle of the divider module) 71 | addStripe -number_of_sets 1 -width 1.25 -spacing 0.9 -xleft_offset 20 \ 72 | -nets {VDD VSS} -layer metal10 73 | 74 | # Special routing: connect the power and ground net to the standard cell rows 75 | # with layer range: M1 - M10 76 | sroute -connect {corePin} -nets {VDD VSS} -layerChangeRange {metal1 metal10} \ 77 | -blockPinTarget {nearestTarget} -allowJogging 1 -crossoverViaLayerRange \ 78 | {metal1 metal10} -allowLayerChange 1 -targetViaLayerRange {metal1 metal10} 79 | 80 | # Save the checkpoint for power plan 81 | saveDesign db/divider_powerplan.enc 82 | 83 | ################################################################################ 84 | # Step 3. placement 85 | # Run the placement to place the standard cell into the row. Disable any scan 86 | # chain since we do not consider scan chain for DFT. 87 | # Optimize the design at the phase of preCTS. 88 | ################################################################################ 89 | # Setup the placement mode: turn off the reorder scan connection 90 | setPlaceMode -reset 91 | setPlaceMode -reorderScan 0 92 | # Do the placement 93 | placeDesign 94 | 95 | # Set RC extraction mode: Pre-Route 96 | setExtractRCMode -engine preRoute 97 | 98 | # Optimize the design after placement 99 | optDesign -preCTS -outDir "reports/preCTSTimingReports" 100 | 101 | # Save the checkpoint for placement 102 | saveDesign db/divider_place.enc 103 | 104 | ################################################################################ 105 | # Step 4. Clock tree synthesize (CTS) 106 | # Generate the clock tree specification. Optimize the design at the CTS phase. 107 | ################################################################################ 108 | # Create clock tree specfication file: "Clock.ctstch" 109 | # The clock tree buffer includes 3 buffers: CLKBUF_X1, CLKBUF_X2, CLKBUF_X3 110 | # The clock tree buffer is PDK-dependent 111 | createClockTreeSpec -bufferList {CLKBUF_X1 CLKBUF_X2 CLKBUF_X3} -file \ 112 | Clock.ctstch 113 | 114 | # Set CTS engine: ck 115 | setCTSMode -engine ck 116 | 117 | # Perform CTS 118 | clockDesign -specFile Clock.ctstch -outDir clock_report -fixedInstBeforeCTS \ 119 | -updateIoLatency 120 | 121 | # Run post-CTS optimization 122 | setAnalysisMode -analysisType onChipVariation 123 | setAnalysisMode -cppr both 124 | optDesign -postCTS -outDir "reports/postCTSTimingReports" 125 | optDesign -postCTS -hold -outDir "reports/postCTSTimingReports" 126 | 127 | # Save the checkpoint for CTS 128 | saveDesign db/divider_cts.enc 129 | 130 | ################################################################################ 131 | # Step 6. Nano Routing 132 | # Run nano routing for the design. 133 | ################################################################################ 134 | # Run nano routing 135 | setNanoRouteMode -quiet -timingEngine {} 136 | setNanoRouteMode -quiet -routeWithTimingDriven 1 137 | setNanoRouteMode -quiet -routeWithSiDriven 1 138 | setNanoRouteMode -quiet -routeWithSiPostRouteFix 0 139 | setNanoRouteMode -quiet -routeTopRoutingLayer default 140 | setNanoRouteMode -quiet -routeBottomRoutingLayer default 141 | setNanoRouteMode -quiet -drouteEndIteration default 142 | setNanoRouteMode -quiet -routeWithTimingDriven true 143 | setNanoRouteMode -quiet -routeWithSiDriven true 144 | routeDesign -globalDetail 145 | 146 | # Run post-route timing and SI optimization 147 | setExtractRCMode -engine postRoute 148 | setExtractRCMode -effortLevel medium 149 | setDelayCalMode -engine default -SIAware true 150 | optDesign -postRoute -outDir "reports/postRouteTimingReports" 151 | optDesign -postRoute -hold -outDir "reports/postRouteTimingReports" 152 | 153 | # Run timing analysis for signoff 154 | # Enable either section bellowed 155 | # ------------------------------------------------------------------------------ 156 | # Without QRC license or QRC 157 | # ------------------------------------------------------------------------------ 158 | #setDelayCalMode -SIAware false 159 | #setDelayCalMode -engine signalStorm 160 | #setExtractRCMode -effortLevel medium 161 | #timeDesign -postRoute -si -outDir "reports/signoffTimingReports" 162 | #timeDesign -postRoute -si -hold -outDir "reports/signoffTimingReports" 163 | # ------------------------------------------------------------------------------ 164 | # With QRC license and QRC installed 165 | # Make sure the Cadence EXT (i.e. QRC) is installed 166 | # On UST server: source /usr/eelocal/cadence/ext142/.cshrc 167 | # ------------------------------------------------------------------------------ 168 | setDelayCalMode -SIAware false 169 | setDelayCalMode -engine signalStorm 170 | timeDesign -signoff -si -outDir "reports/signoffTimingReports" 171 | timeDesign -signoff -si -hold -outDir "reports/signoffTimingReports" 172 | 173 | # Add filler: FILLCELL_X32, X16, X8, X4, X2, X1 174 | addFiller -cell {FILLCELL_X32 FILLCELL_X16 FILLCELL_X8 FILLCELL_X4 FILLCELL_X2 \ 175 | FILLCELL_X1} 176 | 177 | # Save the checkpoint for post route 178 | saveDesign db/divider_postroute.enc 179 | 180 | ################################################################################ 181 | # Step 7. Exports designs into different formats, including 182 | # - spef file 183 | # - sdf file 184 | # - netlist file 185 | # - gds file 186 | ################################################################################ 187 | # ------------------------------------------------------------------------------ 188 | # Step 7a. Exports useful reports 189 | # ------------------------------------------------------------------------------ 190 | # Reports of Geometry and Connectivity (DRC) 191 | verifyGeometry -report reports/divider.geometry.rpt 192 | verifyConnectivity -type all -report reports/divider.connectivity.rpt 193 | 194 | # Summary reports: html to be browsed, including total area breakdown 195 | summaryReport -outdir reports/summaryReport 196 | 197 | # Area report: only report total standard cells area (excluding fillers) 198 | report_area -out_file reports/divider.routed.area.rpt 199 | 200 | # Power report 201 | report_power -outfile reports/divider.routed.power.rpt 202 | 203 | # ------------------------------------------------------------------------------ 204 | # Step 7b. Exports the design 205 | # ------------------------------------------------------------------------------ 206 | # SPEF file: parastic data of wires 207 | rcOut -spef results/divider.spef -rc_corner rc_worst 208 | 209 | # SDF file: delay files for gates and wires 210 | write_sdf results/divider.sdf 211 | 212 | # *.v: verilog netlist file 213 | saveNetlist results/divider.routed.v 214 | 215 | # *.gds: GDS file 216 | streamOut results/divider.gds -mapFile streamOut.map \ 217 | -merge {/mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/Back_End/gds/NangateOpenCellLibrary.gds} \ 218 | -stripes 1 -units 2000 -mode ALL 219 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # vlsi_project 2 | 3 | This is a template for the digital VLSI design project. It contains a complete 4 | design flow for an N-bit digital divider. The project includes 2 folders: 5 | - `divder`: the main folder of the design project 6 | - `document`: the useful PDF documents to understand the project 7 | 8 | ## Prerequisite: Linux development environment 9 | It is very important for users to get familiar with the Linux development 10 | environment, because people always work on Linux instead of Windows in the 11 | digital circuit domain. At least, you should be able to know some basic 12 | operations in Linux, such as: 13 | - `ls`: list all the files in the current folder 14 | - `cd`: change the working directory to a new location 15 | - `cp`: copy the specified file to a new location 16 | - `mv`: move the specified file to a new location 17 | - `mkdir`: create a new directory in the specified location 18 | - `rm`: remove a specified file or a specified directory 19 | - `chmod`: change the access permission to the specified files 20 | - `less` or `more`: view the content of a specified file 21 | - `find`: find the specified files or directories under a specified location 22 | - `grep`: find the specified pattern in the contents of files 23 | - `tar`: compress or un-compress of files into or from an archive 24 | - `history`: check the command line history you have used before 25 | 26 | There is a more detailed explanation called `linux_command.pdf` under 27 | the `document` directory. You can find more detailed information there if you 28 | are not familiar with the Linux environment. 29 | 30 | ## Design project: N-bit divider 31 | The main part of the design project (N-bit divider) is included in the `divider` 32 | folder. The `divider` folder contains different directories serving for 33 | different design stages of digital design flow: 34 | - `rtl`: the folder containing all Verilog/VHDL/SystemVerilog source codes 35 | - `behav_sim`: conduct the behavior simulation of the digital design 36 | - `syn`: run the synthesis flow in this directory 37 | - `syn_sim`: conduct the gate-level simulation of the post-synthesis results 38 | - `layout`: run the place and route (P&R) in this directory 39 | - `layout_sim`: conduct the gate-level simulation of the post-layout results 40 | 41 | ## Step 0: Tool chain setup 42 | In the sampled project, we will use the following tools for our VLSI design: 43 | - Synopsys VCS: RTL behavior simulation, post-synthesis simulation, and 44 | post-layout simulation. 45 | - Synopsys Design Compiler: RTL synthesis. 46 | - Cadence Encounter Digital Implementation: place and route. 47 | 48 | In order to launch the software properly, we should activate the running 49 | environment for each software on our server. The software can be enabled on UST 50 | server as follows: 51 | - Synopsys VCS: 52 | > source /usr/eelocal/synopsys/vcs_mx-vi2014.03-2/.cshrc 53 | - Synopsys Design Compiler: 54 | > source /usr/eelocal/synopsys/syn-vi2013.12-sp5-5/.cshrc 55 | - Cadence Encounter Digital Implementation: 56 | > source /usr/eelocal/cadence/edi142/.cshrc 57 | 58 | You can also append all these settings to your local `.cshrc` file so that you do 59 | not need to type it each time when you log in your system. Concretely, type the 60 | following shell commands in the terminal: 61 | 62 | ```sh 63 | echo "source /usr/eelocal/synopsys/vcs_mx-vi2014.03-2/.cshrc" >> ~/.cshrc 64 | echo "source /usr/eelocal/synopsys/syn-vi2013.12-sp5-5/.cshrc" >> ~/.cshrc 65 | echo "source /usr/eelocal/cadence/edi142/.cshrc" >> ~/.cshrc 66 | 67 | ``` 68 | 69 | ## Step 1: RTL design 70 | In `rtl` directory, we have provided a skeleton of the RTL design of an N-bit 71 | divider. Since the divider is a small module for a digital design project, there 72 | is only one file (`divider.v`) under this directory. In a real design, there may 73 | exist tens to hundreds of Verilog files in it. 74 | 75 | The provided `divider.v` is not complete. You have to read the structure of the 76 | source code and complete the `TODO` section in the `divider.v`. A supplementary 77 | document `divider.pdf` can be found under the `document` folder, which gives a 78 | great explanation of how a divider works in hardware. Basically, the division is 79 | conducted in a trail-and-error scheme, where the divisor is subtracted from the 80 | most significant bit (MSB) to the least significant bit (LSB) of the dividend 81 | iteratively. The quotient will be shifted in 1 or 0 depends on whether the 82 | subtraction result is positive or negative. The divisor operation is different 83 | from the simple add or multiplication operation, where it takes multiple clock 84 | cycles to give the final results of the division. For instance, it requires 33 85 | clock cycles for a 32-bit divider to generate the final quotient and remainder. 86 | Additional `done` signal will be asserted (i.e. raised to logic 1) to notify the 87 | outside world when the division is complete. 88 | 89 | ## Step 2: Behavior simulation 90 | After the RTL design is finished, we should run the behavior simulation to not 91 | only check there is no syntax error with our design, but also the functionality 92 | and timing of the design is correct. We will run the behavior simulation in the 93 | `behav_sim` directory. We provide the testbench code for our design, i.e. 94 | `divider_tb.v`. It is highly recommended to check the content of the testbench 95 | to see how the input stimulus are applied to the inputs of the divider. 96 | Moreover, there exists two simple shell scripts under `behav_sim` directory: 97 | 98 | - `run`: compile the source code and testbench of the divider using Synopsys VCS 99 | - `clean`: clean the intermediated files generated by Synopsys VCS 100 | 101 | It is suggested to read the content of these 2 scripts and to understand how to 102 | include the Verilog source codes to the VCS command. 103 | 104 | In order to launch the VCS compilation and simulation, you only have to type the 105 | following 2 commands in your terminal: 106 | 107 | > ./run 108 | 109 | > ./simv -gui 110 | 111 | The DVE GUI will be launched, and you are able to run the simulation and view 112 | the waveform. The usage of DVE GUI is very simple, you can simply drag the 113 | wires you want to inspect and add them into the waveform window. It is very 114 | similar to the Windows software. In addition, the testbench will print the 115 | division results to your terminal (a.k.a console). If the RTL design is correct 116 | in Step 1, you should be able to see the following division results in the 117 | terminal: 118 | 119 | ```sh 120 | 10 / 7: quotient = 1, remainder = 3 121 | 100 / 100: quotient = 1, remainder = 0 122 | 100 / 7: quotient = 14, remainder = 2 123 | 100 / 0: quotient = 0, remainder = 0 124 | 70 / 150: quotient = 0, remainder = 70 125 | ``` 126 | 127 | ## Step 3: Synthesize the design using Synopsys Design Compiler 128 | After the divider passes the behavior simulation, we can go to the next digital 129 | design stage: synthesis. We will run the synthesis in the `syn` directory. 130 | Initially, there exists 4 files under the `syn` directory: 131 | 132 | - `run`: the simple shell script launching the Synsopsys Design Compiler to run 133 | the synthesis 134 | - `clean`: the simple shell script removing the generated results by the 135 | Synopsys Design Compiler 136 | - `run.tcl`: the main TCL script to run the whole synthesis flow 137 | - `divider.constraints.tcl`: the TCL script containing the design constraints, 138 | including time constraint and environment constraint 139 | 140 | The provided `run.tcl` script uses an Open Source standard cell library, called 141 | Nangate FreePDK 45nm. It can be freely accessed 142 | [here](http://www.nangate.com/?page_id=2325) after the registration. 143 | You are recommended to use a different standard cell library if you are right 144 | now working on some projects using the commercial library such as TSMC 65nm 145 | or UMC 45nm. 146 | 147 | Before you run the synthesis for the divider, you must modify the TCL script 148 | `run.tcl`, which defines the library path to the Nangate FreePDK 45nm. More 149 | specifically, the standard cell library is stored on the following path in my 150 | system: 151 | 152 | ```sh 153 | /mnt/hgfs/PDK/NangateOpenCellLibrary_PDKv1_3_v2010_12/ 154 | ``` 155 | 156 | As a result, the `search_path` includes that directory. You have to modify the 157 | `search_path` accordingly based on your system settings. Of note, the Design 158 | Compiler requires the binary format of the standard cell library (\*.db) instead 159 | of readable ASCII format (\*.lib). For Nangate FreePDK, only the ASCII format is 160 | provided. Thereby, you need compile it into the binary format. Luckily, Design 161 | Compiler provides a companied tool to do this task, called `Library Compiler`. 162 | You can find the procedure to do the compilation from \*.lib to \*.db 163 | [here](https://www.utdallas.edu/~akshay.sridharan/index_files/Page6049.htm). 164 | 165 | In order to run the synthesis flow of the design project, you only need to type 166 | the following command in the terminal: 167 | 168 | > ./run 169 | 170 | If the settings are correct, you will observe 2 directories have been generated 171 | under the current directory: 172 | 173 | - `results`: the synthesized results, including gate-level netlist, Design 174 | Compiler binary file (\*.ddc), constraint file (\*.sdc), and delay file 175 | (\*.sdf) 176 | - `reports`: the reports of the synthesized results, including area, power and 177 | timing reports of the design 178 | 179 | It is suggested to closely read the generated reports and synthesized 180 | gate-level netlist. 181 | 182 | ### Step 4. Post-synthesis simulation 183 | The gate-level simulation of post-synthesis should be conducted under `post_syn` 184 | directory. In this step, you should first copy the synthesized results from Step 185 | 3. More specifically, the netlist (\*.mapped.v) and the delay file (\*.sdf) are 186 | needed to be copied from `syn` directory to the current directory. A sampled 187 | synthesized netlist and delay file are already included in this folder in case 188 | you fail to write the HDL design of the divider or do the synthesis. You should 189 | replace the sampled files with your synthesized results here. In addition, a 190 | modified testbench `divider_tb.v` is also included in this directory. The 191 | testbench contains the additional SDF back-annotation part as follows: 192 | 193 | ```verilog 194 | initial begin 195 | $sdf_annotate("your_sdf_filename.sdf", your_instantiate_module); 196 | end 197 | ``` 198 | 199 | Similar to the behavior simulation in Step 2, 2 handy shell scripts are provided 200 | to compile the simulation of synthesized netlist and clean the simulation. The 201 | `run` script for post-synthesis simulation should include the verilog behavior 202 | model of standard cell. Therefore, we need pass the behavior model to the VCS 203 | compilation. You should modify the file path to the verilog behavior model in 204 | `run` script. If your setting is correct, you can run the compilation and 205 | simulation as in Step 2: 206 | 207 | > ./run 208 | 209 | > ./simv -gui 210 | 211 | In the waveform of post-synthesis simulation, you should observe the latency as 212 | well as glitches. But the calculated results of each division should be the same 213 | as the behavior simulation. The results can be conveniently observed from the 214 | console of DVE. 215 | 216 | ### Step 5. Place and route (P&R) 217 | P&R takes the synthesized netlist from Step 3, and generates the final layouts 218 | for your design. In this step, we follow the flow of official EDI tutorial 219 | called `EDI13.1workshoplab1.pdf` in `document` directory. In the workshop, a 220 | LEON processor is placed and routed. The design flow is similar to the steps 221 | provided by the official workshop. The main differences of P&R with the official 222 | workshop are listed as follows: 223 | 224 | - Standard cell library: EDI official workshop uses Cadence FreePDK 45nm. In the 225 | sampled project, we are using Nangate FreePDK 45nm. You can also pick any 226 | commercial standard cell library. 227 | - Design complexity: the LEON processor in EDI offiical workshop is more 228 | complex than the simple divider module. For example, there exists 4 memory 229 | MACROs in LEON processor. Therefore, in the floorplan section in official 230 | workshop, 4 MACROs will be placed in the chip. However, the divider does not 231 | contain the memory MACRO. These floorplan steps can be skipped. But it is highly 232 | recommended to go through the floorplan section of the official workshop to 233 | understand the role of floorplan for the complex VLSI chip design. 234 | 235 | The first step is to import the synthesised netlist into `layout` directory. This is done 236 | in the script `mmc.view` located at directory `scripts`. A sampled 237 | `mmc.view` is included in `scripts` 238 | directory for your reference. As before, the file path of Nangate FreePDK should 239 | be varied on your system. You should modify the content of `mmc.view` to cater 240 | for your system settings. It is recommended to understand how we define the 241 | fast corner for hold time analysis and the slow corner for setup time analysis 242 | in `mmc.view`. Generally speaking, the fast corner includes the fast corner 243 | timing library (\*.lib), fast corner RC library (\*.capTbl), and different 244 | scaling factors for RC extraction. In addition, the abstract view of standard 245 | cell layout (\*.lef) needs to be specified during the design import. You can 246 | refer to `divider.globals` in the `scripts` folder to understand which lef files 247 | are imported in the design. 248 | 249 | During the power plan step, the width of power ring and the number of stripes 250 | can be decreased since the divider is much simpler than the LEON processor (less 251 | power hungry). 252 | 253 | Of note, the Nangate FreePDK does not provide QRC technology file. It only 254 | provides the capacitance table file. Therefore, in the final step of post-route 255 | timing and SI optimization, we are not able to set the RC extraction effort 256 | level to medium. As a compromise, we set the extraction level to *low* here. 257 | Keep in mind that in a commercial standard cell library, the foundry will 258 | always provide you with the QRC technology file. 259 | 260 | On UST server, we provide the compiled QRC technology file from NCSU FreePDK 261 | 45nm. It is possible for you to include the QRC file when you import the design. 262 | A new version of `mmc2.view` is provided for your reference to include the 263 | technology file as well as SI library file (\*.cdb). As before the data path of 264 | library needs to be modified accordingly based on your system. 265 | 266 | After the post-route timing and SI optimization are conducted, 2 additional 267 | files are required for the later post-layout simulation: 268 | 269 | - divider.sdf: SDF annotation file for the delay backannotation. 270 | - divider.v: verilog file of the P&R netlist. 271 | 272 | These two files can be generated as follows: 273 | 274 | - divider.sdf: the method to generate the SDF file has been described in 275 | `Extracting RC Data` section of the provided EDI workshop. However, SDF file 276 | is generated after detail routing here. Therefore, we will *deselect* the `Ideal 277 | Clock` because the clock tree has been synthesized. 278 | - divider.v: the netlist can be generated by typing the following command in EDI 279 | console: 280 | > saveNetlist divider.v 281 | 282 | ### Step 5b. Script-based P&R (update) 283 | In order to simplify the P&R flow of simple design, which does not have many 284 | hierarchies and memory MACROs. I update a sampled script named `top.tcl` under 285 | directory `divider/layout/top.tcl`. It should be noted that in order to make the 286 | script work, you should modify the library path accordingly in `top.tcl` and 287 | `mmc2.view`. Particulaly, you should modify directory of the synthesised netlist, 288 | or move your netlist to exsiting folder mentioned in the script. 289 | Similarly, to run the script-based P&R, two handy shell scripts, 290 | `run` and `clean` are provided. More specifically, to run the P&R of 291 | the divider, you can type the following command in the terminal: 292 | 293 | > ./run 294 | 295 | Three important directories will be generated: 296 | 297 | - `db`: checkpoints for the divider during different stages for doing P&R, 298 | including floorplan, power plan, place, CTS, and post-route. You can restore 299 | the corresponding checkpoint from that. 300 | - `reports`: various timing reports (setup and hold) for different phases 301 | (pre-CTS, post-CTS, post-route), the geometry and connectivity reports for the 302 | design (DRC) and area, power reports for the routed design 303 | - `results`: final netlist (\*.v), GDS file (\*.gds), and delay file (\*.sdf) 304 | 305 | To clean the P&R results and all intermediate files that have been generated by 306 | Encounter, you can type the following command in the terminal: 307 | 308 | > ./clean 309 | 310 | The P&R usually requires human interaction to do manual floorplan and powerplan. 311 | However, the divider is simple enough so that we let EDA tool to do the 312 | floorplan by itself. You should go through the scripts of `top.tcl` and compare 313 | the script-based flow with the GUI-based flow in provided EDI workshop. There 314 | exists a very nice one-to-one correspondence with these two flows. 315 | 316 | The final layout of the `divider` module is shown as bellowed: 317 | ![divider layout](./divider_layout.png) 318 | 319 | ### Step 6. Post-layout simulation 320 | This step is similar to Step 4 except the netlist (divider.v) and delay file 321 | (divider.sdf) are from P&R instead of synthesis results. You can follow the 322 | procedure in Step 4 to launch the post-layout simulation. It is expected to 323 | observe the waveform with latency and glitches but the functionality should be 324 | same as before. 325 | -------------------------------------------------------------------------------- /divider/layout/designs/divider.mapped.sdc: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | 3 | # Created by write_sdc on Sun Mar 4 18:24:23 2018 4 | 5 | ################################################################### 6 | set sdc_version 2.0 7 | 8 | set_units -time ns -resistance MOhm -capacitance fF -voltage V -current mA 9 | set_load -pin_load 1 [get_ports done] 10 | set_load -pin_load 1 [get_ports {quotient[31]}] 11 | set_load -pin_load 1 [get_ports {quotient[30]}] 12 | set_load -pin_load 1 [get_ports {quotient[29]}] 13 | set_load -pin_load 1 [get_ports {quotient[28]}] 14 | set_load -pin_load 1 [get_ports {quotient[27]}] 15 | set_load -pin_load 1 [get_ports {quotient[26]}] 16 | set_load -pin_load 1 [get_ports {quotient[25]}] 17 | set_load -pin_load 1 [get_ports {quotient[24]}] 18 | set_load -pin_load 1 [get_ports {quotient[23]}] 19 | set_load -pin_load 1 [get_ports {quotient[22]}] 20 | set_load -pin_load 1 [get_ports {quotient[21]}] 21 | set_load -pin_load 1 [get_ports {quotient[20]}] 22 | set_load -pin_load 1 [get_ports {quotient[19]}] 23 | set_load -pin_load 1 [get_ports {quotient[18]}] 24 | set_load -pin_load 1 [get_ports {quotient[17]}] 25 | set_load -pin_load 1 [get_ports {quotient[16]}] 26 | set_load -pin_load 1 [get_ports {quotient[15]}] 27 | set_load -pin_load 1 [get_ports {quotient[14]}] 28 | set_load -pin_load 1 [get_ports {quotient[13]}] 29 | set_load -pin_load 1 [get_ports {quotient[12]}] 30 | set_load -pin_load 1 [get_ports {quotient[11]}] 31 | set_load -pin_load 1 [get_ports {quotient[10]}] 32 | set_load -pin_load 1 [get_ports {quotient[9]}] 33 | set_load -pin_load 1 [get_ports {quotient[8]}] 34 | set_load -pin_load 1 [get_ports {quotient[7]}] 35 | set_load -pin_load 1 [get_ports {quotient[6]}] 36 | set_load -pin_load 1 [get_ports {quotient[5]}] 37 | set_load -pin_load 1 [get_ports {quotient[4]}] 38 | set_load -pin_load 1 [get_ports {quotient[3]}] 39 | set_load -pin_load 1 [get_ports {quotient[2]}] 40 | set_load -pin_load 1 [get_ports {quotient[1]}] 41 | set_load -pin_load 1 [get_ports {quotient[0]}] 42 | set_load -pin_load 1 [get_ports {remainder[31]}] 43 | set_load -pin_load 1 [get_ports {remainder[30]}] 44 | set_load -pin_load 1 [get_ports {remainder[29]}] 45 | set_load -pin_load 1 [get_ports {remainder[28]}] 46 | set_load -pin_load 1 [get_ports {remainder[27]}] 47 | set_load -pin_load 1 [get_ports {remainder[26]}] 48 | set_load -pin_load 1 [get_ports {remainder[25]}] 49 | set_load -pin_load 1 [get_ports {remainder[24]}] 50 | set_load -pin_load 1 [get_ports {remainder[23]}] 51 | set_load -pin_load 1 [get_ports {remainder[22]}] 52 | set_load -pin_load 1 [get_ports {remainder[21]}] 53 | set_load -pin_load 1 [get_ports {remainder[20]}] 54 | set_load -pin_load 1 [get_ports {remainder[19]}] 55 | set_load -pin_load 1 [get_ports {remainder[18]}] 56 | set_load -pin_load 1 [get_ports {remainder[17]}] 57 | set_load -pin_load 1 [get_ports {remainder[16]}] 58 | set_load -pin_load 1 [get_ports {remainder[15]}] 59 | set_load -pin_load 1 [get_ports {remainder[14]}] 60 | set_load -pin_load 1 [get_ports {remainder[13]}] 61 | set_load -pin_load 1 [get_ports {remainder[12]}] 62 | set_load -pin_load 1 [get_ports {remainder[11]}] 63 | set_load -pin_load 1 [get_ports {remainder[10]}] 64 | set_load -pin_load 1 [get_ports {remainder[9]}] 65 | set_load -pin_load 1 [get_ports {remainder[8]}] 66 | set_load -pin_load 1 [get_ports {remainder[7]}] 67 | set_load -pin_load 1 [get_ports {remainder[6]}] 68 | set_load -pin_load 1 [get_ports {remainder[5]}] 69 | set_load -pin_load 1 [get_ports {remainder[4]}] 70 | set_load -pin_load 1 [get_ports {remainder[3]}] 71 | set_load -pin_load 1 [get_ports {remainder[2]}] 72 | set_load -pin_load 1 [get_ports {remainder[1]}] 73 | set_load -pin_load 1 [get_ports {remainder[0]}] 74 | create_clock [get_ports clk] -period 5 -waveform {0 2.5} 75 | group_path -name FEEDTHROUGH -from [list [get_ports rst] [get_ports start] [get_ports {dividend[31]}] [get_ports {dividend[30]}] [get_ports {dividend[29]}] [get_ports {dividend[28]}] [get_ports {dividend[27]}] [get_ports {dividend[26]}] [get_ports {dividend[25]}] [get_ports {dividend[24]}] [get_ports {dividend[23]}] [get_ports {dividend[22]}] [get_ports {dividend[21]}] [get_ports {dividend[20]}] [get_ports {dividend[19]}] [get_ports {dividend[18]}] [get_ports {dividend[17]}] [get_ports {dividend[16]}] [get_ports {dividend[15]}] [get_ports {dividend[14]}] [get_ports {dividend[13]}] [get_ports {dividend[12]}] [get_ports {dividend[11]}] [get_ports {dividend[10]}] [get_ports {dividend[9]}] [get_ports {dividend[8]}] [get_ports {dividend[7]}] [get_ports {dividend[6]}] [get_ports {dividend[5]}] [get_ports {dividend[4]}] [get_ports {dividend[3]}] [get_ports {dividend[2]}] [get_ports {dividend[1]}] [get_ports {dividend[0]}] [get_ports {divisor[31]}] [get_ports {divisor[30]}] [get_ports {divisor[29]}] [get_ports {divisor[28]}] [get_ports {divisor[27]}] [get_ports {divisor[26]}] [get_ports {divisor[25]}] [get_ports {divisor[24]}] [get_ports {divisor[23]}] [get_ports {divisor[22]}] [get_ports {divisor[21]}] [get_ports {divisor[20]}] [get_ports {divisor[19]}] [get_ports {divisor[18]}] [get_ports {divisor[17]}] [get_ports {divisor[16]}] [get_ports {divisor[15]}] [get_ports {divisor[14]}] [get_ports {divisor[13]}] [get_ports {divisor[12]}] [get_ports {divisor[11]}] [get_ports {divisor[10]}] [get_ports {divisor[9]}] [get_ports {divisor[8]}] [get_ports {divisor[7]}] [get_ports {divisor[6]}] [get_ports {divisor[5]}] [get_ports {divisor[4]}] [get_ports {divisor[3]}] [get_ports {divisor[2]}] [get_ports {divisor[1]}] [get_ports {divisor[0]}]] -to [list [get_ports done] [get_ports {quotient[31]}] [get_ports {quotient[30]}] [get_ports {quotient[29]}] [get_ports {quotient[28]}] [get_ports {quotient[27]}] [get_ports {quotient[26]}] [get_ports {quotient[25]}] [get_ports {quotient[24]}] [get_ports {quotient[23]}] [get_ports {quotient[22]}] [get_ports {quotient[21]}] [get_ports {quotient[20]}] [get_ports {quotient[19]}] [get_ports {quotient[18]}] [get_ports {quotient[17]}] [get_ports {quotient[16]}] [get_ports {quotient[15]}] [get_ports {quotient[14]}] [get_ports {quotient[13]}] [get_ports {quotient[12]}] [get_ports {quotient[11]}] [get_ports {quotient[10]}] [get_ports {quotient[9]}] [get_ports {quotient[8]}] [get_ports {quotient[7]}] [get_ports {quotient[6]}] [get_ports {quotient[5]}] [get_ports {quotient[4]}] [get_ports {quotient[3]}] [get_ports {quotient[2]}] [get_ports {quotient[1]}] [get_ports {quotient[0]}] [get_ports {remainder[31]}] [get_ports {remainder[30]}] [get_ports {remainder[29]}] [get_ports {remainder[28]}] [get_ports {remainder[27]}] [get_ports {remainder[26]}] [get_ports {remainder[25]}] [get_ports {remainder[24]}] [get_ports {remainder[23]}] [get_ports {remainder[22]}] [get_ports {remainder[21]}] [get_ports {remainder[20]}] [get_ports {remainder[19]}] [get_ports {remainder[18]}] [get_ports {remainder[17]}] [get_ports {remainder[16]}] [get_ports {remainder[15]}] [get_ports {remainder[14]}] [get_ports {remainder[13]}] [get_ports {remainder[12]}] [get_ports {remainder[11]}] [get_ports {remainder[10]}] [get_ports {remainder[9]}] [get_ports {remainder[8]}] [get_ports {remainder[7]}] [get_ports {remainder[6]}] [get_ports {remainder[5]}] [get_ports {remainder[4]}] [get_ports {remainder[3]}] [get_ports {remainder[2]}] [get_ports {remainder[1]}] [get_ports {remainder[0]}]] 76 | group_path -name REGIN -from [list [get_ports rst] [get_ports start] [get_ports {dividend[31]}] [get_ports {dividend[30]}] [get_ports {dividend[29]}] [get_ports {dividend[28]}] [get_ports {dividend[27]}] [get_ports {dividend[26]}] [get_ports {dividend[25]}] [get_ports {dividend[24]}] [get_ports {dividend[23]}] [get_ports {dividend[22]}] [get_ports {dividend[21]}] [get_ports {dividend[20]}] [get_ports {dividend[19]}] [get_ports {dividend[18]}] [get_ports {dividend[17]}] [get_ports {dividend[16]}] [get_ports {dividend[15]}] [get_ports {dividend[14]}] [get_ports {dividend[13]}] [get_ports {dividend[12]}] [get_ports {dividend[11]}] [get_ports {dividend[10]}] [get_ports {dividend[9]}] [get_ports {dividend[8]}] [get_ports {dividend[7]}] [get_ports {dividend[6]}] [get_ports {dividend[5]}] [get_ports {dividend[4]}] [get_ports {dividend[3]}] [get_ports {dividend[2]}] [get_ports {dividend[1]}] [get_ports {dividend[0]}] [get_ports {divisor[31]}] [get_ports {divisor[30]}] [get_ports {divisor[29]}] [get_ports {divisor[28]}] [get_ports {divisor[27]}] [get_ports {divisor[26]}] [get_ports {divisor[25]}] [get_ports {divisor[24]}] [get_ports {divisor[23]}] [get_ports {divisor[22]}] [get_ports {divisor[21]}] [get_ports {divisor[20]}] [get_ports {divisor[19]}] [get_ports {divisor[18]}] [get_ports {divisor[17]}] [get_ports {divisor[16]}] [get_ports {divisor[15]}] [get_ports {divisor[14]}] [get_ports {divisor[13]}] [get_ports {divisor[12]}] [get_ports {divisor[11]}] [get_ports {divisor[10]}] [get_ports {divisor[9]}] [get_ports {divisor[8]}] [get_ports {divisor[7]}] [get_ports {divisor[6]}] [get_ports {divisor[5]}] [get_ports {divisor[4]}] [get_ports {divisor[3]}] [get_ports {divisor[2]}] [get_ports {divisor[1]}] [get_ports {divisor[0]}]] 77 | group_path -name REGOUT -to [list [get_ports done] [get_ports {quotient[31]}] [get_ports {quotient[30]}] [get_ports {quotient[29]}] [get_ports {quotient[28]}] [get_ports {quotient[27]}] [get_ports {quotient[26]}] [get_ports {quotient[25]}] [get_ports {quotient[24]}] [get_ports {quotient[23]}] [get_ports {quotient[22]}] [get_ports {quotient[21]}] [get_ports {quotient[20]}] [get_ports {quotient[19]}] [get_ports {quotient[18]}] [get_ports {quotient[17]}] [get_ports {quotient[16]}] [get_ports {quotient[15]}] [get_ports {quotient[14]}] [get_ports {quotient[13]}] [get_ports {quotient[12]}] [get_ports {quotient[11]}] [get_ports {quotient[10]}] [get_ports {quotient[9]}] [get_ports {quotient[8]}] [get_ports {quotient[7]}] [get_ports {quotient[6]}] [get_ports {quotient[5]}] [get_ports {quotient[4]}] [get_ports {quotient[3]}] [get_ports {quotient[2]}] [get_ports {quotient[1]}] [get_ports {quotient[0]}] [get_ports {remainder[31]}] [get_ports {remainder[30]}] [get_ports {remainder[29]}] [get_ports {remainder[28]}] [get_ports {remainder[27]}] [get_ports {remainder[26]}] [get_ports {remainder[25]}] [get_ports {remainder[24]}] [get_ports {remainder[23]}] [get_ports {remainder[22]}] [get_ports {remainder[21]}] [get_ports {remainder[20]}] [get_ports {remainder[19]}] [get_ports {remainder[18]}] [get_ports {remainder[17]}] [get_ports {remainder[16]}] [get_ports {remainder[15]}] [get_ports {remainder[14]}] [get_ports {remainder[13]}] [get_ports {remainder[12]}] [get_ports {remainder[11]}] [get_ports {remainder[10]}] [get_ports {remainder[9]}] [get_ports {remainder[8]}] [get_ports {remainder[7]}] [get_ports {remainder[6]}] [get_ports {remainder[5]}] [get_ports {remainder[4]}] [get_ports {remainder[3]}] [get_ports {remainder[2]}] [get_ports {remainder[1]}] [get_ports {remainder[0]}]] 78 | set_input_delay -clock clk -max 1 [get_ports rst] 79 | set_input_delay -clock clk -max 1 [get_ports start] 80 | set_input_delay -clock clk -max 1 [get_ports {dividend[31]}] 81 | set_input_delay -clock clk -max 1 [get_ports {dividend[30]}] 82 | set_input_delay -clock clk -max 1 [get_ports {dividend[29]}] 83 | set_input_delay -clock clk -max 1 [get_ports {dividend[28]}] 84 | set_input_delay -clock clk -max 1 [get_ports {dividend[27]}] 85 | set_input_delay -clock clk -max 1 [get_ports {dividend[26]}] 86 | set_input_delay -clock clk -max 1 [get_ports {dividend[25]}] 87 | set_input_delay -clock clk -max 1 [get_ports {dividend[24]}] 88 | set_input_delay -clock clk -max 1 [get_ports {dividend[23]}] 89 | set_input_delay -clock clk -max 1 [get_ports {dividend[22]}] 90 | set_input_delay -clock clk -max 1 [get_ports {dividend[21]}] 91 | set_input_delay -clock clk -max 1 [get_ports {dividend[20]}] 92 | set_input_delay -clock clk -max 1 [get_ports {dividend[19]}] 93 | set_input_delay -clock clk -max 1 [get_ports {dividend[18]}] 94 | set_input_delay -clock clk -max 1 [get_ports {dividend[17]}] 95 | set_input_delay -clock clk -max 1 [get_ports {dividend[16]}] 96 | set_input_delay -clock clk -max 1 [get_ports {dividend[15]}] 97 | set_input_delay -clock clk -max 1 [get_ports {dividend[14]}] 98 | set_input_delay -clock clk -max 1 [get_ports {dividend[13]}] 99 | set_input_delay -clock clk -max 1 [get_ports {dividend[12]}] 100 | set_input_delay -clock clk -max 1 [get_ports {dividend[11]}] 101 | set_input_delay -clock clk -max 1 [get_ports {dividend[10]}] 102 | set_input_delay -clock clk -max 1 [get_ports {dividend[9]}] 103 | set_input_delay -clock clk -max 1 [get_ports {dividend[8]}] 104 | set_input_delay -clock clk -max 1 [get_ports {dividend[7]}] 105 | set_input_delay -clock clk -max 1 [get_ports {dividend[6]}] 106 | set_input_delay -clock clk -max 1 [get_ports {dividend[5]}] 107 | set_input_delay -clock clk -max 1 [get_ports {dividend[4]}] 108 | set_input_delay -clock clk -max 1 [get_ports {dividend[3]}] 109 | set_input_delay -clock clk -max 1 [get_ports {dividend[2]}] 110 | set_input_delay -clock clk -max 1 [get_ports {dividend[1]}] 111 | set_input_delay -clock clk -max 1 [get_ports {dividend[0]}] 112 | set_input_delay -clock clk -max 1 [get_ports {divisor[31]}] 113 | set_input_delay -clock clk -max 1 [get_ports {divisor[30]}] 114 | set_input_delay -clock clk -max 1 [get_ports {divisor[29]}] 115 | set_input_delay -clock clk -max 1 [get_ports {divisor[28]}] 116 | set_input_delay -clock clk -max 1 [get_ports {divisor[27]}] 117 | set_input_delay -clock clk -max 1 [get_ports {divisor[26]}] 118 | set_input_delay -clock clk -max 1 [get_ports {divisor[25]}] 119 | set_input_delay -clock clk -max 1 [get_ports {divisor[24]}] 120 | set_input_delay -clock clk -max 1 [get_ports {divisor[23]}] 121 | set_input_delay -clock clk -max 1 [get_ports {divisor[22]}] 122 | set_input_delay -clock clk -max 1 [get_ports {divisor[21]}] 123 | set_input_delay -clock clk -max 1 [get_ports {divisor[20]}] 124 | set_input_delay -clock clk -max 1 [get_ports {divisor[19]}] 125 | set_input_delay -clock clk -max 1 [get_ports {divisor[18]}] 126 | set_input_delay -clock clk -max 1 [get_ports {divisor[17]}] 127 | set_input_delay -clock clk -max 1 [get_ports {divisor[16]}] 128 | set_input_delay -clock clk -max 1 [get_ports {divisor[15]}] 129 | set_input_delay -clock clk -max 1 [get_ports {divisor[14]}] 130 | set_input_delay -clock clk -max 1 [get_ports {divisor[13]}] 131 | set_input_delay -clock clk -max 1 [get_ports {divisor[12]}] 132 | set_input_delay -clock clk -max 1 [get_ports {divisor[11]}] 133 | set_input_delay -clock clk -max 1 [get_ports {divisor[10]}] 134 | set_input_delay -clock clk -max 1 [get_ports {divisor[9]}] 135 | set_input_delay -clock clk -max 1 [get_ports {divisor[8]}] 136 | set_input_delay -clock clk -max 1 [get_ports {divisor[7]}] 137 | set_input_delay -clock clk -max 1 [get_ports {divisor[6]}] 138 | set_input_delay -clock clk -max 1 [get_ports {divisor[5]}] 139 | set_input_delay -clock clk -max 1 [get_ports {divisor[4]}] 140 | set_input_delay -clock clk -max 1 [get_ports {divisor[3]}] 141 | set_input_delay -clock clk -max 1 [get_ports {divisor[2]}] 142 | set_input_delay -clock clk -max 1 [get_ports {divisor[1]}] 143 | set_input_delay -clock clk -max 1 [get_ports {divisor[0]}] 144 | set_output_delay -clock clk -max 1 [get_ports done] 145 | set_output_delay -clock clk -max 1 [get_ports {quotient[31]}] 146 | set_output_delay -clock clk -max 1 [get_ports {quotient[30]}] 147 | set_output_delay -clock clk -max 1 [get_ports {quotient[29]}] 148 | set_output_delay -clock clk -max 1 [get_ports {quotient[28]}] 149 | set_output_delay -clock clk -max 1 [get_ports {quotient[27]}] 150 | set_output_delay -clock clk -max 1 [get_ports {quotient[26]}] 151 | set_output_delay -clock clk -max 1 [get_ports {quotient[25]}] 152 | set_output_delay -clock clk -max 1 [get_ports {quotient[24]}] 153 | set_output_delay -clock clk -max 1 [get_ports {quotient[23]}] 154 | set_output_delay -clock clk -max 1 [get_ports {quotient[22]}] 155 | set_output_delay -clock clk -max 1 [get_ports {quotient[21]}] 156 | set_output_delay -clock clk -max 1 [get_ports {quotient[20]}] 157 | set_output_delay -clock clk -max 1 [get_ports {quotient[19]}] 158 | set_output_delay -clock clk -max 1 [get_ports {quotient[18]}] 159 | set_output_delay -clock clk -max 1 [get_ports {quotient[17]}] 160 | set_output_delay -clock clk -max 1 [get_ports {quotient[16]}] 161 | set_output_delay -clock clk -max 1 [get_ports {quotient[15]}] 162 | set_output_delay -clock clk -max 1 [get_ports {quotient[14]}] 163 | set_output_delay -clock clk -max 1 [get_ports {quotient[13]}] 164 | set_output_delay -clock clk -max 1 [get_ports {quotient[12]}] 165 | set_output_delay -clock clk -max 1 [get_ports {quotient[11]}] 166 | set_output_delay -clock clk -max 1 [get_ports {quotient[10]}] 167 | set_output_delay -clock clk -max 1 [get_ports {quotient[9]}] 168 | set_output_delay -clock clk -max 1 [get_ports {quotient[8]}] 169 | set_output_delay -clock clk -max 1 [get_ports {quotient[7]}] 170 | set_output_delay -clock clk -max 1 [get_ports {quotient[6]}] 171 | set_output_delay -clock clk -max 1 [get_ports {quotient[5]}] 172 | set_output_delay -clock clk -max 1 [get_ports {quotient[4]}] 173 | set_output_delay -clock clk -max 1 [get_ports {quotient[3]}] 174 | set_output_delay -clock clk -max 1 [get_ports {quotient[2]}] 175 | set_output_delay -clock clk -max 1 [get_ports {quotient[1]}] 176 | set_output_delay -clock clk -max 1 [get_ports {quotient[0]}] 177 | set_output_delay -clock clk -max 1 [get_ports {remainder[31]}] 178 | set_output_delay -clock clk -max 1 [get_ports {remainder[30]}] 179 | set_output_delay -clock clk -max 1 [get_ports {remainder[29]}] 180 | set_output_delay -clock clk -max 1 [get_ports {remainder[28]}] 181 | set_output_delay -clock clk -max 1 [get_ports {remainder[27]}] 182 | set_output_delay -clock clk -max 1 [get_ports {remainder[26]}] 183 | set_output_delay -clock clk -max 1 [get_ports {remainder[25]}] 184 | set_output_delay -clock clk -max 1 [get_ports {remainder[24]}] 185 | set_output_delay -clock clk -max 1 [get_ports {remainder[23]}] 186 | set_output_delay -clock clk -max 1 [get_ports {remainder[22]}] 187 | set_output_delay -clock clk -max 1 [get_ports {remainder[21]}] 188 | set_output_delay -clock clk -max 1 [get_ports {remainder[20]}] 189 | set_output_delay -clock clk -max 1 [get_ports {remainder[19]}] 190 | set_output_delay -clock clk -max 1 [get_ports {remainder[18]}] 191 | set_output_delay -clock clk -max 1 [get_ports {remainder[17]}] 192 | set_output_delay -clock clk -max 1 [get_ports {remainder[16]}] 193 | set_output_delay -clock clk -max 1 [get_ports {remainder[15]}] 194 | set_output_delay -clock clk -max 1 [get_ports {remainder[14]}] 195 | set_output_delay -clock clk -max 1 [get_ports {remainder[13]}] 196 | set_output_delay -clock clk -max 1 [get_ports {remainder[12]}] 197 | set_output_delay -clock clk -max 1 [get_ports {remainder[11]}] 198 | set_output_delay -clock clk -max 1 [get_ports {remainder[10]}] 199 | set_output_delay -clock clk -max 1 [get_ports {remainder[9]}] 200 | set_output_delay -clock clk -max 1 [get_ports {remainder[8]}] 201 | set_output_delay -clock clk -max 1 [get_ports {remainder[7]}] 202 | set_output_delay -clock clk -max 1 [get_ports {remainder[6]}] 203 | set_output_delay -clock clk -max 1 [get_ports {remainder[5]}] 204 | set_output_delay -clock clk -max 1 [get_ports {remainder[4]}] 205 | set_output_delay -clock clk -max 1 [get_ports {remainder[3]}] 206 | set_output_delay -clock clk -max 1 [get_ports {remainder[2]}] 207 | set_output_delay -clock clk -max 1 [get_ports {remainder[1]}] 208 | set_output_delay -clock clk -max 1 [get_ports {remainder[0]}] 209 | set_input_transition -max 0.1 [get_ports rst] 210 | set_input_transition -min 0.1 [get_ports rst] 211 | set_input_transition -max 0.1 [get_ports start] 212 | set_input_transition -min 0.1 [get_ports start] 213 | set_input_transition -max 0.1 [get_ports {dividend[31]}] 214 | set_input_transition -min 0.1 [get_ports {dividend[31]}] 215 | set_input_transition -max 0.1 [get_ports {dividend[30]}] 216 | set_input_transition -min 0.1 [get_ports {dividend[30]}] 217 | set_input_transition -max 0.1 [get_ports {dividend[29]}] 218 | set_input_transition -min 0.1 [get_ports {dividend[29]}] 219 | set_input_transition -max 0.1 [get_ports {dividend[28]}] 220 | set_input_transition -min 0.1 [get_ports {dividend[28]}] 221 | set_input_transition -max 0.1 [get_ports {dividend[27]}] 222 | set_input_transition -min 0.1 [get_ports {dividend[27]}] 223 | set_input_transition -max 0.1 [get_ports {dividend[26]}] 224 | set_input_transition -min 0.1 [get_ports {dividend[26]}] 225 | set_input_transition -max 0.1 [get_ports {dividend[25]}] 226 | set_input_transition -min 0.1 [get_ports {dividend[25]}] 227 | set_input_transition -max 0.1 [get_ports {dividend[24]}] 228 | set_input_transition -min 0.1 [get_ports {dividend[24]}] 229 | set_input_transition -max 0.1 [get_ports {dividend[23]}] 230 | set_input_transition -min 0.1 [get_ports {dividend[23]}] 231 | set_input_transition -max 0.1 [get_ports {dividend[22]}] 232 | set_input_transition -min 0.1 [get_ports {dividend[22]}] 233 | set_input_transition -max 0.1 [get_ports {dividend[21]}] 234 | set_input_transition -min 0.1 [get_ports {dividend[21]}] 235 | set_input_transition -max 0.1 [get_ports {dividend[20]}] 236 | set_input_transition -min 0.1 [get_ports {dividend[20]}] 237 | set_input_transition -max 0.1 [get_ports {dividend[19]}] 238 | set_input_transition -min 0.1 [get_ports {dividend[19]}] 239 | set_input_transition -max 0.1 [get_ports {dividend[18]}] 240 | set_input_transition -min 0.1 [get_ports {dividend[18]}] 241 | set_input_transition -max 0.1 [get_ports {dividend[17]}] 242 | set_input_transition -min 0.1 [get_ports {dividend[17]}] 243 | set_input_transition -max 0.1 [get_ports {dividend[16]}] 244 | set_input_transition -min 0.1 [get_ports {dividend[16]}] 245 | set_input_transition -max 0.1 [get_ports {dividend[15]}] 246 | set_input_transition -min 0.1 [get_ports {dividend[15]}] 247 | set_input_transition -max 0.1 [get_ports {dividend[14]}] 248 | set_input_transition -min 0.1 [get_ports {dividend[14]}] 249 | set_input_transition -max 0.1 [get_ports {dividend[13]}] 250 | set_input_transition -min 0.1 [get_ports {dividend[13]}] 251 | set_input_transition -max 0.1 [get_ports {dividend[12]}] 252 | set_input_transition -min 0.1 [get_ports {dividend[12]}] 253 | set_input_transition -max 0.1 [get_ports {dividend[11]}] 254 | set_input_transition -min 0.1 [get_ports {dividend[11]}] 255 | set_input_transition -max 0.1 [get_ports {dividend[10]}] 256 | set_input_transition -min 0.1 [get_ports {dividend[10]}] 257 | set_input_transition -max 0.1 [get_ports {dividend[9]}] 258 | set_input_transition -min 0.1 [get_ports {dividend[9]}] 259 | set_input_transition -max 0.1 [get_ports {dividend[8]}] 260 | set_input_transition -min 0.1 [get_ports {dividend[8]}] 261 | set_input_transition -max 0.1 [get_ports {dividend[7]}] 262 | set_input_transition -min 0.1 [get_ports {dividend[7]}] 263 | set_input_transition -max 0.1 [get_ports {dividend[6]}] 264 | set_input_transition -min 0.1 [get_ports {dividend[6]}] 265 | set_input_transition -max 0.1 [get_ports {dividend[5]}] 266 | set_input_transition -min 0.1 [get_ports {dividend[5]}] 267 | set_input_transition -max 0.1 [get_ports {dividend[4]}] 268 | set_input_transition -min 0.1 [get_ports {dividend[4]}] 269 | set_input_transition -max 0.1 [get_ports {dividend[3]}] 270 | set_input_transition -min 0.1 [get_ports {dividend[3]}] 271 | set_input_transition -max 0.1 [get_ports {dividend[2]}] 272 | set_input_transition -min 0.1 [get_ports {dividend[2]}] 273 | set_input_transition -max 0.1 [get_ports {dividend[1]}] 274 | set_input_transition -min 0.1 [get_ports {dividend[1]}] 275 | set_input_transition -max 0.1 [get_ports {dividend[0]}] 276 | set_input_transition -min 0.1 [get_ports {dividend[0]}] 277 | set_input_transition -max 0.1 [get_ports {divisor[31]}] 278 | set_input_transition -min 0.1 [get_ports {divisor[31]}] 279 | set_input_transition -max 0.1 [get_ports {divisor[30]}] 280 | set_input_transition -min 0.1 [get_ports {divisor[30]}] 281 | set_input_transition -max 0.1 [get_ports {divisor[29]}] 282 | set_input_transition -min 0.1 [get_ports {divisor[29]}] 283 | set_input_transition -max 0.1 [get_ports {divisor[28]}] 284 | set_input_transition -min 0.1 [get_ports {divisor[28]}] 285 | set_input_transition -max 0.1 [get_ports {divisor[27]}] 286 | set_input_transition -min 0.1 [get_ports {divisor[27]}] 287 | set_input_transition -max 0.1 [get_ports {divisor[26]}] 288 | set_input_transition -min 0.1 [get_ports {divisor[26]}] 289 | set_input_transition -max 0.1 [get_ports {divisor[25]}] 290 | set_input_transition -min 0.1 [get_ports {divisor[25]}] 291 | set_input_transition -max 0.1 [get_ports {divisor[24]}] 292 | set_input_transition -min 0.1 [get_ports {divisor[24]}] 293 | set_input_transition -max 0.1 [get_ports {divisor[23]}] 294 | set_input_transition -min 0.1 [get_ports {divisor[23]}] 295 | set_input_transition -max 0.1 [get_ports {divisor[22]}] 296 | set_input_transition -min 0.1 [get_ports {divisor[22]}] 297 | set_input_transition -max 0.1 [get_ports {divisor[21]}] 298 | set_input_transition -min 0.1 [get_ports {divisor[21]}] 299 | set_input_transition -max 0.1 [get_ports {divisor[20]}] 300 | set_input_transition -min 0.1 [get_ports {divisor[20]}] 301 | set_input_transition -max 0.1 [get_ports {divisor[19]}] 302 | set_input_transition -min 0.1 [get_ports {divisor[19]}] 303 | set_input_transition -max 0.1 [get_ports {divisor[18]}] 304 | set_input_transition -min 0.1 [get_ports {divisor[18]}] 305 | set_input_transition -max 0.1 [get_ports {divisor[17]}] 306 | set_input_transition -min 0.1 [get_ports {divisor[17]}] 307 | set_input_transition -max 0.1 [get_ports {divisor[16]}] 308 | set_input_transition -min 0.1 [get_ports {divisor[16]}] 309 | set_input_transition -max 0.1 [get_ports {divisor[15]}] 310 | set_input_transition -min 0.1 [get_ports {divisor[15]}] 311 | set_input_transition -max 0.1 [get_ports {divisor[14]}] 312 | set_input_transition -min 0.1 [get_ports {divisor[14]}] 313 | set_input_transition -max 0.1 [get_ports {divisor[13]}] 314 | set_input_transition -min 0.1 [get_ports {divisor[13]}] 315 | set_input_transition -max 0.1 [get_ports {divisor[12]}] 316 | set_input_transition -min 0.1 [get_ports {divisor[12]}] 317 | set_input_transition -max 0.1 [get_ports {divisor[11]}] 318 | set_input_transition -min 0.1 [get_ports {divisor[11]}] 319 | set_input_transition -max 0.1 [get_ports {divisor[10]}] 320 | set_input_transition -min 0.1 [get_ports {divisor[10]}] 321 | set_input_transition -max 0.1 [get_ports {divisor[9]}] 322 | set_input_transition -min 0.1 [get_ports {divisor[9]}] 323 | set_input_transition -max 0.1 [get_ports {divisor[8]}] 324 | set_input_transition -min 0.1 [get_ports {divisor[8]}] 325 | set_input_transition -max 0.1 [get_ports {divisor[7]}] 326 | set_input_transition -min 0.1 [get_ports {divisor[7]}] 327 | set_input_transition -max 0.1 [get_ports {divisor[6]}] 328 | set_input_transition -min 0.1 [get_ports {divisor[6]}] 329 | set_input_transition -max 0.1 [get_ports {divisor[5]}] 330 | set_input_transition -min 0.1 [get_ports {divisor[5]}] 331 | set_input_transition -max 0.1 [get_ports {divisor[4]}] 332 | set_input_transition -min 0.1 [get_ports {divisor[4]}] 333 | set_input_transition -max 0.1 [get_ports {divisor[3]}] 334 | set_input_transition -min 0.1 [get_ports {divisor[3]}] 335 | set_input_transition -max 0.1 [get_ports {divisor[2]}] 336 | set_input_transition -min 0.1 [get_ports {divisor[2]}] 337 | set_input_transition -max 0.1 [get_ports {divisor[1]}] 338 | set_input_transition -min 0.1 [get_ports {divisor[1]}] 339 | set_input_transition -max 0.1 [get_ports {divisor[0]}] 340 | set_input_transition -min 0.1 [get_ports {divisor[0]}] 341 | -------------------------------------------------------------------------------- /divider/syn_sim/divider.mapped.v: -------------------------------------------------------------------------------- 1 | 2 | module divider_DW01_sub_1 ( A, B, CI, DIFF, CO ); 3 | input [32:0] A; 4 | input [32:0] B; 5 | output [32:0] DIFF; 6 | input CI; 7 | output CO; 8 | wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, 9 | n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, 10 | n31, n32, n33, n34, n35, n37, n39, n40, n41, n42, n43, n45, n47, n48, 11 | n49, n50, n51, n53, n55, n56, n57, n58, n59, n61, n63, n64, n65, n66, 12 | n67, n69, n71, n72, n73, n74, n75, n76, n77, n78, n79, n81, n83, n84, 13 | n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, 14 | n101, n102, n103, n104, n106, n107, n108, n109, n110, n111, n112, 15 | n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, 16 | n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, 17 | n135, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, 18 | n147, n148, n149, n150, n151, n152, n153, n154, n156, n158, n160, 19 | n162, n164, n166, n168, n169, n170, n171, n172, n173, n174, n175, 20 | n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, 21 | n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, 22 | n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, 23 | n209, n210, n319, n320, n321, n322, n323, n324, n325, n326, n327, 24 | n328, n329; 25 | 26 | FA_X1 U2 ( .A(n179), .B(A[31]), .CI(n27), .CO(n26), .S(DIFF[31]) ); 27 | FA_X1 U4 ( .A(n181), .B(A[29]), .CI(n29), .CO(n28), .S(DIFF[29]) ); 28 | FA_X1 U5 ( .A(n182), .B(A[28]), .CI(n30), .CO(n29), .S(DIFF[28]) ); 29 | FA_X1 U6 ( .A(n183), .B(A[27]), .CI(n31), .CO(n30), .S(DIFF[27]) ); 30 | FA_X1 U7 ( .A(n184), .B(A[26]), .CI(n32), .CO(n31), .S(DIFF[26]) ); 31 | NOR2_X1 U241 ( .A1(n197), .A2(A[13]), .ZN(n89) ); 32 | NOR2_X1 U242 ( .A1(n208), .A2(A[2]), .ZN(n147) ); 33 | NOR2_X1 U243 ( .A1(n205), .A2(A[5]), .ZN(n133) ); 34 | NOR2_X1 U244 ( .A1(n203), .A2(A[7]), .ZN(n125) ); 35 | NOR2_X1 U245 ( .A1(n204), .A2(A[6]), .ZN(n128) ); 36 | NOR2_X1 U246 ( .A1(n210), .A2(A[0]), .ZN(n153) ); 37 | AOI21_X1 U247 ( .B1(n48), .B2(n322), .A(n45), .ZN(n43) ); 38 | AOI21_X1 U248 ( .B1(n56), .B2(n323), .A(n53), .ZN(n51) ); 39 | AOI21_X1 U249 ( .B1(n100), .B2(n113), .A(n101), .ZN(n99) ); 40 | NOR2_X2 U253 ( .A1(n199), .A2(A[11]), .ZN(n102) ); 41 | NAND2_X1 U256 ( .A1(n198), .A2(A[12]), .ZN(n95) ); 42 | NAND2_X1 U257 ( .A1(n208), .A2(A[2]), .ZN(n148) ); 43 | INV_X1 U259 ( .A(n97), .ZN(n96) ); 44 | NAND2_X1 U260 ( .A1(n112), .A2(n100), .ZN(n98) ); 45 | INV_X1 U261 ( .A(n120), .ZN(n119) ); 46 | AOI21_X1 U262 ( .B1(n140), .B2(n131), .A(n132), .ZN(n130) ); 47 | OAI21_X1 U263 ( .B1(n119), .B2(n110), .A(n111), .ZN(n109) ); 48 | INV_X1 U264 ( .A(n112), .ZN(n110) ); 49 | OAI21_X1 U265 ( .B1(n119), .B2(n98), .A(n99), .ZN(n97) ); 50 | INV_X1 U266 ( .A(n141), .ZN(n140) ); 51 | INV_X1 U270 ( .A(n150), .ZN(n149) ); 52 | OAI21_X1 U271 ( .B1(n67), .B2(n65), .A(n66), .ZN(n64) ); 53 | OAI21_X1 U272 ( .B1(n59), .B2(n57), .A(n58), .ZN(n56) ); 54 | OAI21_X1 U273 ( .B1(n75), .B2(n73), .A(n74), .ZN(n72) ); 55 | OAI21_X1 U274 ( .B1(n51), .B2(n49), .A(n50), .ZN(n48) ); 56 | OAI21_X1 U275 ( .B1(n114), .B2(n118), .A(n115), .ZN(n113) ); 57 | OAI21_X1 U276 ( .B1(n102), .B2(n108), .A(n103), .ZN(n101) ); 58 | OAI21_X1 U277 ( .B1(n133), .B2(n139), .A(n134), .ZN(n132) ); 59 | OAI21_X1 U278 ( .B1(n43), .B2(n41), .A(n42), .ZN(n40) ); 60 | INV_X1 U279 ( .A(n39), .ZN(n37) ); 61 | INV_X1 U280 ( .A(n55), .ZN(n53) ); 62 | INV_X1 U281 ( .A(n47), .ZN(n45) ); 63 | NOR2_X1 U282 ( .A1(n138), .A2(n133), .ZN(n131) ); 64 | OAI21_X1 U283 ( .B1(n151), .B2(n153), .A(n152), .ZN(n150) ); 65 | NOR2_X1 U284 ( .A1(n107), .A2(n102), .ZN(n100) ); 66 | OAI21_X1 U285 ( .B1(n89), .B2(n95), .A(n90), .ZN(n88) ); 67 | OAI21_X1 U286 ( .B1(n141), .B2(n121), .A(n122), .ZN(n120) ); 68 | NAND2_X1 U287 ( .A1(n131), .A2(n123), .ZN(n121) ); 69 | AOI21_X1 U288 ( .B1(n123), .B2(n132), .A(n124), .ZN(n122) ); 70 | NOR2_X1 U289 ( .A1(n128), .A2(n125), .ZN(n123) ); 71 | AOI21_X1 U290 ( .B1(n88), .B2(n319), .A(n81), .ZN(n79) ); 72 | INV_X1 U291 ( .A(n83), .ZN(n81) ); 73 | NOR2_X1 U292 ( .A1(n98), .A2(n78), .ZN(n76) ); 74 | OAI21_X1 U293 ( .B1(n99), .B2(n78), .A(n79), .ZN(n77) ); 75 | NAND2_X1 U294 ( .A1(n87), .A2(n319), .ZN(n78) ); 76 | AOI21_X1 U295 ( .B1(n72), .B2(n321), .A(n69), .ZN(n67) ); 77 | INV_X1 U296 ( .A(n71), .ZN(n69) ); 78 | INV_X1 U297 ( .A(n63), .ZN(n61) ); 79 | NOR2_X1 U298 ( .A1(n94), .A2(n89), .ZN(n87) ); 80 | NOR2_X1 U299 ( .A1(n117), .A2(n114), .ZN(n112) ); 81 | AOI21_X1 U300 ( .B1(n142), .B2(n150), .A(n143), .ZN(n141) ); 82 | NOR2_X1 U301 ( .A1(n147), .A2(n144), .ZN(n142) ); 83 | OAI21_X1 U302 ( .B1(n144), .B2(n148), .A(n145), .ZN(n143) ); 84 | OAI21_X1 U303 ( .B1(n125), .B2(n129), .A(n126), .ZN(n124) ); 85 | AOI21_X1 U304 ( .B1(n97), .B2(n92), .A(n93), .ZN(n91) ); 86 | INV_X1 U305 ( .A(n95), .ZN(n93) ); 87 | AOI21_X1 U306 ( .B1(n109), .B2(n169), .A(n106), .ZN(n104) ); 88 | INV_X1 U307 ( .A(n108), .ZN(n106) ); 89 | AOI21_X1 U308 ( .B1(n140), .B2(n175), .A(n137), .ZN(n135) ); 90 | INV_X1 U309 ( .A(n139), .ZN(n137) ); 91 | INV_X1 U310 ( .A(n94), .ZN(n92) ); 92 | INV_X1 U311 ( .A(n107), .ZN(n169) ); 93 | INV_X1 U312 ( .A(n138), .ZN(n175) ); 94 | OAI21_X1 U313 ( .B1(n119), .B2(n117), .A(n118), .ZN(n116) ); 95 | OAI21_X1 U314 ( .B1(n130), .B2(n128), .A(n129), .ZN(n127) ); 96 | OAI21_X1 U315 ( .B1(n149), .B2(n147), .A(n148), .ZN(n146) ); 97 | INV_X1 U316 ( .A(n117), .ZN(n171) ); 98 | INV_X1 U317 ( .A(n128), .ZN(n173) ); 99 | INV_X1 U318 ( .A(n147), .ZN(n177) ); 100 | INV_X1 U319 ( .A(n89), .ZN(n166) ); 101 | INV_X1 U320 ( .A(n125), .ZN(n172) ); 102 | INV_X1 U321 ( .A(n133), .ZN(n174) ); 103 | INV_X1 U322 ( .A(n144), .ZN(n176) ); 104 | INV_X1 U323 ( .A(n114), .ZN(n170) ); 105 | INV_X1 U324 ( .A(n151), .ZN(n178) ); 106 | INV_X1 U325 ( .A(n41), .ZN(n156) ); 107 | INV_X1 U326 ( .A(n49), .ZN(n158) ); 108 | INV_X1 U327 ( .A(n57), .ZN(n160) ); 109 | INV_X1 U328 ( .A(n65), .ZN(n162) ); 110 | INV_X1 U329 ( .A(n73), .ZN(n164) ); 111 | INV_X1 U330 ( .A(n33), .ZN(n154) ); 112 | INV_X1 U331 ( .A(n102), .ZN(n168) ); 113 | NOR2_X1 U332 ( .A1(n202), .A2(A[8]), .ZN(n117) ); 114 | NOR2_X2 U333 ( .A1(n207), .A2(A[3]), .ZN(n144) ); 115 | XOR2_X1 U334 ( .A(n135), .B(n21), .Z(DIFF[5]) ); 116 | NAND2_X1 U335 ( .A1(n174), .A2(n134), .ZN(n21) ); 117 | XNOR2_X1 U336 ( .A(n140), .B(n22), .ZN(DIFF[4]) ); 118 | NAND2_X1 U337 ( .A1(n175), .A2(n139), .ZN(n22) ); 119 | XNOR2_X1 U338 ( .A(n146), .B(n23), .ZN(DIFF[3]) ); 120 | NAND2_X1 U339 ( .A1(n176), .A2(n145), .ZN(n23) ); 121 | XOR2_X1 U340 ( .A(n149), .B(n24), .Z(DIFF[2]) ); 122 | NAND2_X1 U341 ( .A1(n177), .A2(n148), .ZN(n24) ); 123 | XOR2_X1 U342 ( .A(n25), .B(n153), .Z(DIFF[1]) ); 124 | NAND2_X1 U343 ( .A1(n178), .A2(n152), .ZN(n25) ); 125 | NOR2_X2 U344 ( .A1(n201), .A2(A[9]), .ZN(n114) ); 126 | OR2_X1 U345 ( .A1(n196), .A2(A[14]), .ZN(n319) ); 127 | NOR2_X1 U346 ( .A1(n200), .A2(A[10]), .ZN(n107) ); 128 | NOR2_X1 U347 ( .A1(n198), .A2(A[12]), .ZN(n94) ); 129 | NOR2_X1 U348 ( .A1(n206), .A2(A[4]), .ZN(n138) ); 130 | NOR2_X1 U349 ( .A1(n209), .A2(A[1]), .ZN(n151) ); 131 | INV_X1 U350 ( .A(B[29]), .ZN(n181) ); 132 | NAND2_X1 U351 ( .A1(n154), .A2(n34), .ZN(n1) ); 133 | NAND2_X1 U352 ( .A1(n324), .A2(n39), .ZN(n2) ); 134 | XOR2_X1 U353 ( .A(n43), .B(n3), .Z(DIFF[23]) ); 135 | NAND2_X1 U354 ( .A1(n156), .A2(n42), .ZN(n3) ); 136 | NAND2_X1 U355 ( .A1(n322), .A2(n47), .ZN(n4) ); 137 | XOR2_X1 U356 ( .A(n51), .B(n5), .Z(DIFF[21]) ); 138 | NAND2_X1 U357 ( .A1(n158), .A2(n50), .ZN(n5) ); 139 | XNOR2_X1 U358 ( .A(n56), .B(n6), .ZN(DIFF[20]) ); 140 | NAND2_X1 U359 ( .A1(n323), .A2(n55), .ZN(n6) ); 141 | NAND2_X1 U360 ( .A1(n160), .A2(n58), .ZN(n7) ); 142 | XNOR2_X1 U361 ( .A(n64), .B(n8), .ZN(DIFF[18]) ); 143 | NAND2_X1 U362 ( .A1(n320), .A2(n63), .ZN(n8) ); 144 | NAND2_X1 U363 ( .A1(n162), .A2(n66), .ZN(n9) ); 145 | NAND2_X1 U364 ( .A1(n321), .A2(n71), .ZN(n10) ); 146 | NAND2_X1 U365 ( .A1(n164), .A2(n74), .ZN(n11) ); 147 | XNOR2_X1 U366 ( .A(n84), .B(n12), .ZN(DIFF[14]) ); 148 | NAND2_X1 U367 ( .A1(n319), .A2(n83), .ZN(n12) ); 149 | XOR2_X1 U368 ( .A(n91), .B(n13), .Z(DIFF[13]) ); 150 | NAND2_X1 U369 ( .A1(n166), .A2(n90), .ZN(n13) ); 151 | XOR2_X1 U370 ( .A(n96), .B(n14), .Z(DIFF[12]) ); 152 | NAND2_X1 U371 ( .A1(n92), .A2(n95), .ZN(n14) ); 153 | XOR2_X1 U372 ( .A(n104), .B(n15), .Z(DIFF[11]) ); 154 | NAND2_X1 U373 ( .A1(n168), .A2(n103), .ZN(n15) ); 155 | XNOR2_X1 U374 ( .A(n109), .B(n16), .ZN(DIFF[10]) ); 156 | NAND2_X1 U375 ( .A1(n169), .A2(n108), .ZN(n16) ); 157 | XNOR2_X1 U376 ( .A(n116), .B(n17), .ZN(DIFF[9]) ); 158 | NAND2_X1 U377 ( .A1(n170), .A2(n115), .ZN(n17) ); 159 | XOR2_X1 U378 ( .A(n119), .B(n18), .Z(DIFF[8]) ); 160 | NAND2_X1 U379 ( .A1(n171), .A2(n118), .ZN(n18) ); 161 | XNOR2_X1 U380 ( .A(n127), .B(n19), .ZN(DIFF[7]) ); 162 | NAND2_X1 U381 ( .A1(n172), .A2(n126), .ZN(n19) ); 163 | XOR2_X1 U382 ( .A(n130), .B(n20), .Z(DIFF[6]) ); 164 | NAND2_X1 U383 ( .A1(n173), .A2(n129), .ZN(n20) ); 165 | XNOR2_X1 U384 ( .A(n210), .B(A[0]), .ZN(DIFF[0]) ); 166 | INV_X1 U385 ( .A(B[13]), .ZN(n197) ); 167 | INV_X1 U386 ( .A(B[12]), .ZN(n198) ); 168 | INV_X1 U387 ( .A(B[6]), .ZN(n204) ); 169 | INV_X1 U388 ( .A(B[10]), .ZN(n200) ); 170 | INV_X1 U389 ( .A(B[2]), .ZN(n208) ); 171 | INV_X1 U390 ( .A(B[8]), .ZN(n202) ); 172 | INV_X1 U391 ( .A(B[5]), .ZN(n205) ); 173 | INV_X1 U392 ( .A(B[7]), .ZN(n203) ); 174 | INV_X1 U393 ( .A(B[1]), .ZN(n209) ); 175 | INV_X1 U394 ( .A(B[9]), .ZN(n201) ); 176 | INV_X1 U395 ( .A(B[3]), .ZN(n207) ); 177 | INV_X1 U396 ( .A(B[4]), .ZN(n206) ); 178 | INV_X1 U397 ( .A(B[18]), .ZN(n192) ); 179 | INV_X1 U398 ( .A(B[17]), .ZN(n193) ); 180 | INV_X1 U399 ( .A(B[16]), .ZN(n194) ); 181 | INV_X1 U400 ( .A(B[15]), .ZN(n195) ); 182 | INV_X1 U401 ( .A(B[14]), .ZN(n196) ); 183 | NOR2_X1 U402 ( .A1(n193), .A2(A[17]), .ZN(n65) ); 184 | NOR2_X1 U403 ( .A1(n195), .A2(A[15]), .ZN(n73) ); 185 | NAND2_X1 U404 ( .A1(n204), .A2(A[6]), .ZN(n129) ); 186 | INV_X1 U405 ( .A(B[0]), .ZN(n210) ); 187 | NAND2_X1 U406 ( .A1(n206), .A2(A[4]), .ZN(n139) ); 188 | NAND2_X1 U407 ( .A1(n202), .A2(A[8]), .ZN(n118) ); 189 | INV_X1 U408 ( .A(B[26]), .ZN(n184) ); 190 | INV_X1 U409 ( .A(B[27]), .ZN(n183) ); 191 | INV_X1 U410 ( .A(B[28]), .ZN(n182) ); 192 | NAND2_X1 U411 ( .A1(n200), .A2(A[10]), .ZN(n108) ); 193 | INV_X1 U412 ( .A(B[31]), .ZN(n179) ); 194 | NAND2_X1 U413 ( .A1(n207), .A2(A[3]), .ZN(n145) ); 195 | NAND2_X1 U414 ( .A1(n197), .A2(A[13]), .ZN(n90) ); 196 | NAND2_X1 U415 ( .A1(n203), .A2(A[7]), .ZN(n126) ); 197 | NAND2_X1 U416 ( .A1(n205), .A2(A[5]), .ZN(n134) ); 198 | NAND2_X1 U417 ( .A1(n209), .A2(A[1]), .ZN(n152) ); 199 | OR2_X1 U418 ( .A1(n192), .A2(A[18]), .ZN(n320) ); 200 | OR2_X1 U419 ( .A1(n194), .A2(A[16]), .ZN(n321) ); 201 | NAND2_X1 U420 ( .A1(n192), .A2(A[18]), .ZN(n63) ); 202 | NAND2_X1 U421 ( .A1(n194), .A2(A[16]), .ZN(n71) ); 203 | NAND2_X1 U422 ( .A1(n196), .A2(A[14]), .ZN(n83) ); 204 | NAND2_X1 U423 ( .A1(n201), .A2(A[9]), .ZN(n115) ); 205 | NAND2_X1 U424 ( .A1(n193), .A2(A[17]), .ZN(n66) ); 206 | NAND2_X1 U425 ( .A1(n195), .A2(A[15]), .ZN(n74) ); 207 | INV_X1 U426 ( .A(B[25]), .ZN(n185) ); 208 | INV_X1 U427 ( .A(B[24]), .ZN(n186) ); 209 | INV_X1 U428 ( .A(B[23]), .ZN(n187) ); 210 | INV_X1 U429 ( .A(B[22]), .ZN(n188) ); 211 | INV_X1 U430 ( .A(B[21]), .ZN(n189) ); 212 | INV_X1 U431 ( .A(B[20]), .ZN(n190) ); 213 | INV_X1 U432 ( .A(B[19]), .ZN(n191) ); 214 | OR2_X1 U433 ( .A1(n188), .A2(A[22]), .ZN(n322) ); 215 | OR2_X1 U434 ( .A1(n190), .A2(A[20]), .ZN(n323) ); 216 | NOR2_X1 U435 ( .A1(n187), .A2(A[23]), .ZN(n41) ); 217 | NOR2_X1 U436 ( .A1(n189), .A2(A[21]), .ZN(n49) ); 218 | NOR2_X1 U437 ( .A1(n191), .A2(A[19]), .ZN(n57) ); 219 | NOR2_X1 U438 ( .A1(n185), .A2(A[25]), .ZN(n33) ); 220 | OR2_X1 U439 ( .A1(n186), .A2(A[24]), .ZN(n324) ); 221 | NAND2_X1 U440 ( .A1(n186), .A2(A[24]), .ZN(n39) ); 222 | NAND2_X1 U441 ( .A1(n188), .A2(A[22]), .ZN(n47) ); 223 | NAND2_X1 U442 ( .A1(n190), .A2(A[20]), .ZN(n55) ); 224 | NAND2_X1 U443 ( .A1(n187), .A2(A[23]), .ZN(n42) ); 225 | NAND2_X1 U444 ( .A1(n189), .A2(A[21]), .ZN(n50) ); 226 | NAND2_X1 U445 ( .A1(n191), .A2(A[19]), .ZN(n58) ); 227 | NAND2_X1 U446 ( .A1(n185), .A2(A[25]), .ZN(n34) ); 228 | XOR2_X1 U447 ( .A(n180), .B(A[30]), .Z(n325) ); 229 | XOR2_X1 U448 ( .A(n28), .B(n325), .Z(DIFF[30]) ); 230 | NAND2_X1 U449 ( .A1(n28), .A2(n180), .ZN(n326) ); 231 | NAND2_X1 U450 ( .A1(n28), .A2(A[30]), .ZN(n327) ); 232 | NAND2_X1 U451 ( .A1(n180), .A2(A[30]), .ZN(n328) ); 233 | NAND3_X1 U452 ( .A1(n326), .A2(n328), .A3(n327), .ZN(n27) ); 234 | INV_X1 U453 ( .A(B[30]), .ZN(n180) ); 235 | XNOR2_X1 U454 ( .A(n40), .B(n2), .ZN(DIFF[24]) ); 236 | XNOR2_X1 U455 ( .A(n72), .B(n10), .ZN(DIFF[16]) ); 237 | XOR2_X1 U456 ( .A(n59), .B(n7), .Z(DIFF[19]) ); 238 | XOR2_X1 U457 ( .A(n67), .B(n9), .Z(DIFF[17]) ); 239 | XOR2_X1 U458 ( .A(n75), .B(n11), .Z(DIFF[15]) ); 240 | INV_X1 U459 ( .A(n113), .ZN(n111) ); 241 | NAND2_X1 U460 ( .A1(n199), .A2(A[11]), .ZN(n103) ); 242 | INV_X1 U461 ( .A(n26), .ZN(DIFF[32]) ); 243 | XNOR2_X1 U462 ( .A(n48), .B(n4), .ZN(DIFF[22]) ); 244 | XOR2_X1 U463 ( .A(n35), .B(n1), .Z(DIFF[25]) ); 245 | OAI21_X1 U464 ( .B1(n35), .B2(n33), .A(n34), .ZN(n32) ); 246 | INV_X1 U465 ( .A(B[11]), .ZN(n199) ); 247 | AOI21_X2 U251 ( .B1(n40), .B2(n324), .A(n37), .ZN(n35) ); 248 | AOI21_X2 U252 ( .B1(n64), .B2(n320), .A(n61), .ZN(n59) ); 249 | AOI21_X2 U250 ( .B1(n120), .B2(n76), .A(n77), .ZN(n75) ); 250 | INV_X1 U254 ( .A(n329), .ZN(n84) ); 251 | AOI21_X1 U255 ( .B1(n97), .B2(n87), .A(n88), .ZN(n329) ); 252 | endmodule 253 | 254 | 255 | module divider ( clk, rst, start, dividend, divisor, done, quotient, remainder 256 | ); 257 | input [31:0] dividend; 258 | input [31:0] divisor; 259 | output [31:0] quotient; 260 | output [31:0] remainder; 261 | input clk, rst, start; 262 | output done; 263 | wire state_reg_1_, N230, N231, N232, N233, N234, n3, n4, n6, n7, n8, n9, 264 | n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, 265 | n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n37, n38, 266 | n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, 267 | n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, 268 | n67, n68, n75, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, 269 | n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, 270 | n105, n106, n107, n108, n109, n110, n111, n112, n147, n178, n180, 271 | n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, 272 | n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, 273 | n204, n205, n206, n207, n208, n209, n210, n218, n220, n221, n222, 274 | n223, n224, n225, n226, n227, n228, n229, n236, n237, n238, n239, 275 | n240, n241, n242, n243, n244, n245, n247, n248, n249, n250, n251, 276 | n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, 277 | n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, 278 | n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, 279 | n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, 280 | n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, 281 | n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, 282 | n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, 283 | n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, 284 | n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, 285 | n351, n352, n353, n358, n361, n362, n363, n364, n365, n374, n378, 286 | n381, n382, n384, n385, n386, n387, n388, n389, n390, n392, n393, 287 | n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, 288 | n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, 289 | n416, n417, n418, n419, n420, n421, n422, n423, n424, n426, n427, 290 | n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, 291 | n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, 292 | n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, 293 | n461, n462, n463, n464, n465, n466, n467, n468, n469, n470; 294 | wire [31:0] divisor_reg; 295 | wire [63:0] remainder_reg; 296 | wire [5:0] cnt_reg; 297 | wire [32:0] alu_result; 298 | wire [5:2] add_117_carry; 299 | 300 | DFF_X1 cnt_reg_reg_1_ ( .D(n431), .CK(clk), .Q(cnt_reg[1]) ); 301 | DFF_X1 cnt_reg_reg_2_ ( .D(n432), .CK(clk), .Q(cnt_reg[2]) ); 302 | DFF_X1 cnt_reg_reg_3_ ( .D(n433), .CK(clk), .Q(cnt_reg[3]) ); 303 | DFF_X1 cnt_reg_reg_4_ ( .D(n434), .CK(clk), .Q(cnt_reg[4]) ); 304 | DFF_X1 cnt_reg_reg_5_ ( .D(n435), .CK(clk), .Q(cnt_reg[5]) ); 305 | DFF_X1 remainder_reg_reg_1_ ( .D(n309), .CK(clk), .QN(n67) ); 306 | DFF_X1 remainder_reg_reg_2_ ( .D(n308), .CK(clk), .QN(n66) ); 307 | DFF_X1 remainder_reg_reg_3_ ( .D(n307), .CK(clk), .QN(n65) ); 308 | DFF_X1 remainder_reg_reg_4_ ( .D(n306), .CK(clk), .QN(n64) ); 309 | DFF_X1 remainder_reg_reg_5_ ( .D(n305), .CK(clk), .QN(n63) ); 310 | DFF_X1 remainder_reg_reg_6_ ( .D(n304), .CK(clk), .QN(n62) ); 311 | DFF_X1 remainder_reg_reg_7_ ( .D(n303), .CK(clk), .QN(n61) ); 312 | DFF_X1 remainder_reg_reg_8_ ( .D(n302), .CK(clk), .QN(n60) ); 313 | DFF_X1 remainder_reg_reg_9_ ( .D(n301), .CK(clk), .QN(n59) ); 314 | DFF_X1 remainder_reg_reg_10_ ( .D(n300), .CK(clk), .QN(n58) ); 315 | DFF_X1 remainder_reg_reg_11_ ( .D(n299), .CK(clk), .QN(n57) ); 316 | DFF_X1 remainder_reg_reg_12_ ( .D(n298), .CK(clk), .QN(n56) ); 317 | DFF_X1 remainder_reg_reg_13_ ( .D(n297), .CK(clk), .QN(n55) ); 318 | DFF_X1 remainder_reg_reg_14_ ( .D(n296), .CK(clk), .QN(n54) ); 319 | DFF_X1 remainder_reg_reg_15_ ( .D(n295), .CK(clk), .QN(n53) ); 320 | DFF_X1 remainder_reg_reg_16_ ( .D(n294), .CK(clk), .QN(n52) ); 321 | DFF_X1 remainder_reg_reg_17_ ( .D(n293), .CK(clk), .QN(n51) ); 322 | DFF_X1 remainder_reg_reg_18_ ( .D(n292), .CK(clk), .QN(n50) ); 323 | DFF_X1 remainder_reg_reg_19_ ( .D(n291), .CK(clk), .QN(n49) ); 324 | DFF_X1 remainder_reg_reg_20_ ( .D(n290), .CK(clk), .QN(n48) ); 325 | DFF_X1 remainder_reg_reg_21_ ( .D(n289), .CK(clk), .QN(n47) ); 326 | DFF_X1 remainder_reg_reg_22_ ( .D(n288), .CK(clk), .QN(n46) ); 327 | DFF_X1 remainder_reg_reg_23_ ( .D(n287), .CK(clk), .QN(n45) ); 328 | DFF_X1 remainder_reg_reg_24_ ( .D(n286), .CK(clk), .QN(n44) ); 329 | DFF_X1 remainder_reg_reg_25_ ( .D(n285), .CK(clk), .QN(n43) ); 330 | DFF_X1 remainder_reg_reg_26_ ( .D(n284), .CK(clk), .QN(n42) ); 331 | DFF_X1 remainder_reg_reg_27_ ( .D(n283), .CK(clk), .QN(n41) ); 332 | DFF_X1 remainder_reg_reg_28_ ( .D(n282), .CK(clk), .QN(n40) ); 333 | DFF_X1 remainder_reg_reg_29_ ( .D(n281), .CK(clk), .QN(n39) ); 334 | DFF_X1 remainder_reg_reg_30_ ( .D(n280), .CK(clk), .QN(n38) ); 335 | DFF_X1 remainder_reg_reg_31_ ( .D(n279), .CK(clk), .Q(remainder_reg[31]), 336 | .QN(n37) ); 337 | DFF_X1 remainder_reg_reg_32_ ( .D(n436), .CK(clk), .Q(remainder_reg[32]) ); 338 | DFF_X1 remainder_reg_reg_39_ ( .D(n272), .CK(clk), .Q(remainder_reg[39]), 339 | .QN(n29) ); 340 | DFF_X1 remainder_reg_reg_40_ ( .D(n271), .CK(clk), .Q(remainder_reg[40]), 341 | .QN(n28) ); 342 | DFF_X1 remainder_reg_reg_64_ ( .D(n247), .CK(clk), .QN(n3) ); 343 | NAND3_X1 U299 ( .A1(n387), .A2(n385), .A3(start), .ZN(n220) ); 344 | NAND3_X1 U300 ( .A1(n346), .A2(n349), .A3(start), .ZN(n226) ); 345 | NAND4_X1 U301 ( .A1(n345), .A2(n75), .A3(cnt_reg[5]), .A4(n229), .ZN(n228) 346 | ); 347 | NAND4_X1 U303 ( .A1(n445), .A2(n444), .A3(n443), .A4(n442), .ZN(n241) ); 348 | NAND4_X1 U304 ( .A1(n441), .A2(n440), .A3(n467), .A4(n439), .ZN(n240) ); 349 | NAND4_X1 U305 ( .A1(n438), .A2(n466), .A3(n465), .A4(n464), .ZN(n239) ); 350 | NAND4_X1 U306 ( .A1(n463), .A2(n462), .A3(n461), .A4(n460), .ZN(n238) ); 351 | NAND4_X1 U307 ( .A1(n469), .A2(n459), .A3(n458), .A4(n457), .ZN(n245) ); 352 | NAND4_X1 U308 ( .A1(n456), .A2(n455), .A3(n454), .A4(n453), .ZN(n244) ); 353 | NAND4_X1 U309 ( .A1(n452), .A2(n451), .A3(n450), .A4(n468), .ZN(n243) ); 354 | NAND4_X1 U310 ( .A1(n449), .A2(n448), .A3(n447), .A4(n446), .ZN(n242) ); 355 | HA_X1 add_117_U1_1_1 ( .A(cnt_reg[1]), .B(cnt_reg[0]), .CO(add_117_carry[2]), 356 | .S(N230) ); 357 | HA_X1 add_117_U1_1_2 ( .A(cnt_reg[2]), .B(add_117_carry[2]), .CO( 358 | add_117_carry[3]), .S(N231) ); 359 | HA_X1 add_117_U1_1_3 ( .A(cnt_reg[3]), .B(add_117_carry[3]), .CO( 360 | add_117_carry[4]), .S(N232) ); 361 | HA_X1 add_117_U1_1_4 ( .A(cnt_reg[4]), .B(add_117_carry[4]), .CO( 362 | add_117_carry[5]), .S(N233) ); 363 | divider_DW01_sub_1 sub_80 ( .A({1'b0, remainder_reg[63:32]}), .B({1'b0, 364 | divisor_reg}), .CI(1'b0), .DIFF(alu_result) ); 365 | DFF_X1 state_reg_reg_0_ ( .D(n344), .CK(clk), .Q(done), .QN(n387) ); 366 | DFF_X1 state_reg_reg_1_ ( .D(n343), .CK(clk), .Q(state_reg_1_), .QN(n385) ); 367 | DFF_X1 divisor_reg_reg_7_ ( .D(n334), .CK(clk), .Q(divisor_reg[7]), .QN(n105) ); 368 | DFF_X1 divisor_reg_reg_6_ ( .D(n335), .CK(clk), .Q(divisor_reg[6]), .QN(n106) ); 369 | DFF_X1 divisor_reg_reg_5_ ( .D(n336), .CK(clk), .Q(divisor_reg[5]), .QN(n107) ); 370 | DFF_X1 divisor_reg_reg_4_ ( .D(n337), .CK(clk), .Q(divisor_reg[4]), .QN(n108) ); 371 | DFF_X1 divisor_reg_reg_3_ ( .D(n338), .CK(clk), .Q(divisor_reg[3]), .QN(n109) ); 372 | DFF_X1 divisor_reg_reg_2_ ( .D(n339), .CK(clk), .Q(divisor_reg[2]), .QN(n110) ); 373 | DFF_X1 divisor_reg_reg_1_ ( .D(n340), .CK(clk), .Q(divisor_reg[1]), .QN(n111) ); 374 | DFF_X1 divisor_reg_reg_0_ ( .D(n341), .CK(clk), .Q(divisor_reg[0]), .QN(n112) ); 375 | DFF_X1 divisor_reg_reg_31_ ( .D(n310), .CK(clk), .Q(divisor_reg[31]), .QN( 376 | n81) ); 377 | DFF_X1 divisor_reg_reg_30_ ( .D(n311), .CK(clk), .Q(divisor_reg[30]), .QN( 378 | n82) ); 379 | DFF_X1 divisor_reg_reg_29_ ( .D(n312), .CK(clk), .Q(divisor_reg[29]), .QN( 380 | n83) ); 381 | DFF_X1 divisor_reg_reg_28_ ( .D(n313), .CK(clk), .Q(divisor_reg[28]), .QN( 382 | n84) ); 383 | DFF_X1 divisor_reg_reg_27_ ( .D(n314), .CK(clk), .Q(divisor_reg[27]), .QN( 384 | n85) ); 385 | DFF_X1 divisor_reg_reg_26_ ( .D(n315), .CK(clk), .Q(divisor_reg[26]), .QN( 386 | n86) ); 387 | DFF_X1 divisor_reg_reg_25_ ( .D(n316), .CK(clk), .Q(divisor_reg[25]), .QN( 388 | n87) ); 389 | DFF_X1 divisor_reg_reg_24_ ( .D(n317), .CK(clk), .Q(divisor_reg[24]), .QN( 390 | n88) ); 391 | DFF_X1 divisor_reg_reg_23_ ( .D(n318), .CK(clk), .Q(divisor_reg[23]), .QN( 392 | n89) ); 393 | DFF_X1 divisor_reg_reg_22_ ( .D(n319), .CK(clk), .Q(divisor_reg[22]), .QN( 394 | n90) ); 395 | DFF_X1 divisor_reg_reg_21_ ( .D(n320), .CK(clk), .Q(divisor_reg[21]), .QN( 396 | n91) ); 397 | DFF_X1 divisor_reg_reg_20_ ( .D(n321), .CK(clk), .Q(divisor_reg[20]), .QN( 398 | n92) ); 399 | DFF_X1 divisor_reg_reg_19_ ( .D(n322), .CK(clk), .Q(divisor_reg[19]), .QN( 400 | n93) ); 401 | DFF_X1 divisor_reg_reg_18_ ( .D(n323), .CK(clk), .Q(divisor_reg[18]), .QN( 402 | n94) ); 403 | DFF_X1 divisor_reg_reg_17_ ( .D(n324), .CK(clk), .Q(divisor_reg[17]), .QN( 404 | n95) ); 405 | DFF_X1 divisor_reg_reg_16_ ( .D(n325), .CK(clk), .Q(divisor_reg[16]), .QN( 406 | n96) ); 407 | DFF_X1 divisor_reg_reg_15_ ( .D(n326), .CK(clk), .Q(divisor_reg[15]), .QN( 408 | n97) ); 409 | DFF_X1 divisor_reg_reg_14_ ( .D(n327), .CK(clk), .Q(divisor_reg[14]), .QN( 410 | n98) ); 411 | DFF_X1 divisor_reg_reg_13_ ( .D(n328), .CK(clk), .Q(divisor_reg[13]), .QN( 412 | n99) ); 413 | DFF_X1 divisor_reg_reg_12_ ( .D(n329), .CK(clk), .Q(divisor_reg[12]), .QN( 414 | n100) ); 415 | DFF_X1 divisor_reg_reg_11_ ( .D(n330), .CK(clk), .Q(divisor_reg[11]), .QN( 416 | n101) ); 417 | DFF_X1 divisor_reg_reg_10_ ( .D(n331), .CK(clk), .Q(divisor_reg[10]), .QN( 418 | n102) ); 419 | DFF_X1 divisor_reg_reg_9_ ( .D(n332), .CK(clk), .Q(divisor_reg[9]), .QN(n103) ); 420 | DFF_X1 divisor_reg_reg_8_ ( .D(n333), .CK(clk), .Q(divisor_reg[8]), .QN(n104) ); 421 | DFF_X1 remainder_reg_reg_38_ ( .D(n273), .CK(clk), .Q(remainder_reg[38]), 422 | .QN(n30) ); 423 | DFF_X1 remainder_reg_reg_37_ ( .D(n274), .CK(clk), .Q(remainder_reg[37]), 424 | .QN(n31) ); 425 | DFF_X1 remainder_reg_reg_36_ ( .D(n275), .CK(clk), .Q(remainder_reg[36]), 426 | .QN(n32) ); 427 | DFF_X1 remainder_reg_reg_35_ ( .D(n276), .CK(clk), .Q(remainder_reg[35]), 428 | .QN(n33) ); 429 | DFF_X1 remainder_reg_reg_34_ ( .D(n277), .CK(clk), .Q(remainder_reg[34]), 430 | .QN(n34) ); 431 | DFF_X1 remainder_reg_reg_0_ ( .D(n429), .CK(clk), .Q(remainder_reg[0]), .QN( 432 | n68) ); 433 | DFF_X1 cnt_reg_reg_0_ ( .D(n342), .CK(clk), .Q(cnt_reg[0]), .QN(n75) ); 434 | DFF_X1 remainder_reg_reg_63_ ( .D(n248), .CK(clk), .Q(remainder_reg[63]), 435 | .QN(n4) ); 436 | DFF_X1 remainder_reg_reg_62_ ( .D(n249), .CK(clk), .Q(remainder_reg[62]), 437 | .QN(n6) ); 438 | DFF_X1 remainder_reg_reg_61_ ( .D(n250), .CK(clk), .Q(remainder_reg[61]), 439 | .QN(n7) ); 440 | DFF_X1 remainder_reg_reg_60_ ( .D(n251), .CK(clk), .Q(remainder_reg[60]), 441 | .QN(n8) ); 442 | DFF_X1 remainder_reg_reg_59_ ( .D(n252), .CK(clk), .Q(remainder_reg[59]), 443 | .QN(n9) ); 444 | DFF_X1 remainder_reg_reg_48_ ( .D(n263), .CK(clk), .Q(remainder_reg[48]), 445 | .QN(n20) ); 446 | DFF_X1 remainder_reg_reg_33_ ( .D(n278), .CK(clk), .Q(remainder_reg[33]), 447 | .QN(n35) ); 448 | DFF_X1 remainder_reg_reg_58_ ( .D(n253), .CK(clk), .Q(remainder_reg[58]), 449 | .QN(n10) ); 450 | DFF_X1 remainder_reg_reg_57_ ( .D(n254), .CK(clk), .Q(remainder_reg[57]), 451 | .QN(n11) ); 452 | DFF_X1 remainder_reg_reg_56_ ( .D(n255), .CK(clk), .Q(remainder_reg[56]), 453 | .QN(n12) ); 454 | DFF_X1 remainder_reg_reg_55_ ( .D(n256), .CK(clk), .Q(remainder_reg[55]), 455 | .QN(n13) ); 456 | DFF_X1 remainder_reg_reg_54_ ( .D(n257), .CK(clk), .Q(remainder_reg[54]), 457 | .QN(n14) ); 458 | DFF_X1 remainder_reg_reg_53_ ( .D(n258), .CK(clk), .Q(remainder_reg[53]), 459 | .QN(n15) ); 460 | DFF_X1 remainder_reg_reg_52_ ( .D(n259), .CK(clk), .Q(remainder_reg[52]), 461 | .QN(n16) ); 462 | DFF_X1 remainder_reg_reg_51_ ( .D(n260), .CK(clk), .Q(remainder_reg[51]), 463 | .QN(n17) ); 464 | DFF_X1 remainder_reg_reg_50_ ( .D(n261), .CK(clk), .Q(remainder_reg[50]), 465 | .QN(n18) ); 466 | DFF_X1 remainder_reg_reg_49_ ( .D(n262), .CK(clk), .Q(remainder_reg[49]), 467 | .QN(n19) ); 468 | DFF_X1 remainder_reg_reg_47_ ( .D(n264), .CK(clk), .Q(remainder_reg[47]), 469 | .QN(n21) ); 470 | DFF_X1 remainder_reg_reg_46_ ( .D(n265), .CK(clk), .Q(remainder_reg[46]), 471 | .QN(n22) ); 472 | DFF_X1 remainder_reg_reg_45_ ( .D(n266), .CK(clk), .Q(remainder_reg[45]), 473 | .QN(n23) ); 474 | DFF_X1 remainder_reg_reg_44_ ( .D(n267), .CK(clk), .Q(remainder_reg[44]), 475 | .QN(n24) ); 476 | DFF_X1 remainder_reg_reg_43_ ( .D(n268), .CK(clk), .Q(remainder_reg[43]), 477 | .QN(n25) ); 478 | DFF_X1 remainder_reg_reg_42_ ( .D(n269), .CK(clk), .Q(remainder_reg[42]), 479 | .QN(n26) ); 480 | DFF_X1 remainder_reg_reg_41_ ( .D(n270), .CK(clk), .Q(remainder_reg[41]), 481 | .QN(n27) ); 482 | AND2_X1 U312 ( .A1(n428), .A2(n384), .ZN(n346) ); 483 | AND2_X1 U315 ( .A1(n387), .A2(n385), .ZN(n349) ); 484 | AND2_X1 U318 ( .A1(remainder_reg[0]), .A2(n178), .ZN(n350) ); 485 | AND2_X1 U319 ( .A1(dividend[0]), .A2(n347), .ZN(n351) ); 486 | CLKBUF_X1 U321 ( .A(n430), .Z(n374) ); 487 | CLKBUF_X1 U326 ( .A(n352), .Z(n365) ); 488 | CLKBUF_X1 U327 ( .A(n352), .Z(n364) ); 489 | CLKBUF_X1 U328 ( .A(n353), .Z(n362) ); 490 | CLKBUF_X1 U329 ( .A(n353), .Z(n361) ); 491 | CLKBUF_X1 U330 ( .A(n353), .Z(n363) ); 492 | INV_X1 U334 ( .A(n345), .ZN(n378) ); 493 | AND2_X1 U335 ( .A1(alu_result[32]), .A2(n345), .ZN(n353) ); 494 | CLKBUF_X1 U342 ( .A(n424), .Z(n358) ); 495 | NOR4_X1 U346 ( .A1(n242), .A2(n243), .A3(n244), .A4(n245), .ZN(n236) ); 496 | NOR4_X1 U347 ( .A1(n238), .A2(n239), .A3(n240), .A4(n241), .ZN(n237) ); 497 | CLKBUF_X1 U348 ( .A(n147), .Z(n381) ); 498 | CLKBUF_X1 U351 ( .A(n147), .Z(n382) ); 499 | NAND2_X1 U353 ( .A1(dividend[31]), .A2(n347), .ZN(n180) ); 500 | OAI221_X1 U354 ( .B1(n39), .B2(n378), .C1(n374), .C2(n38), .A(n182), .ZN( 501 | n280) ); 502 | NAND2_X1 U355 ( .A1(dividend[30]), .A2(n347), .ZN(n182) ); 503 | OAI221_X1 U356 ( .B1(n40), .B2(n470), .C1(n374), .C2(n39), .A(n183), .ZN( 504 | n281) ); 505 | NAND2_X1 U357 ( .A1(dividend[29]), .A2(n347), .ZN(n183) ); 506 | OAI221_X1 U358 ( .B1(n41), .B2(n470), .C1(n374), .C2(n40), .A(n184), .ZN( 507 | n282) ); 508 | NAND2_X1 U359 ( .A1(dividend[28]), .A2(n347), .ZN(n184) ); 509 | OAI221_X1 U360 ( .B1(n42), .B2(n470), .C1(n374), .C2(n41), .A(n185), .ZN( 510 | n283) ); 511 | NAND2_X1 U361 ( .A1(dividend[27]), .A2(n347), .ZN(n185) ); 512 | OAI221_X1 U362 ( .B1(n43), .B2(n470), .C1(n374), .C2(n42), .A(n186), .ZN( 513 | n284) ); 514 | NAND2_X1 U363 ( .A1(dividend[26]), .A2(n347), .ZN(n186) ); 515 | OAI221_X1 U364 ( .B1(n44), .B2(n470), .C1(n430), .C2(n43), .A(n187), .ZN( 516 | n285) ); 517 | NAND2_X1 U365 ( .A1(dividend[25]), .A2(n347), .ZN(n187) ); 518 | OAI221_X1 U366 ( .B1(n45), .B2(n470), .C1(n374), .C2(n44), .A(n188), .ZN( 519 | n286) ); 520 | NAND2_X1 U367 ( .A1(dividend[24]), .A2(n347), .ZN(n188) ); 521 | OAI221_X1 U368 ( .B1(n46), .B2(n470), .C1(n430), .C2(n45), .A(n189), .ZN( 522 | n287) ); 523 | NAND2_X1 U369 ( .A1(dividend[23]), .A2(n347), .ZN(n189) ); 524 | OAI221_X1 U370 ( .B1(n47), .B2(n470), .C1(n430), .C2(n46), .A(n190), .ZN( 525 | n288) ); 526 | NAND2_X1 U371 ( .A1(dividend[22]), .A2(n347), .ZN(n190) ); 527 | OAI221_X1 U372 ( .B1(n48), .B2(n470), .C1(n430), .C2(n47), .A(n191), .ZN( 528 | n289) ); 529 | NAND2_X1 U373 ( .A1(dividend[21]), .A2(n347), .ZN(n191) ); 530 | OAI221_X1 U374 ( .B1(n49), .B2(n470), .C1(n430), .C2(n48), .A(n192), .ZN( 531 | n290) ); 532 | NAND2_X1 U375 ( .A1(dividend[20]), .A2(n347), .ZN(n192) ); 533 | OAI221_X1 U376 ( .B1(n50), .B2(n470), .C1(n430), .C2(n49), .A(n193), .ZN( 534 | n291) ); 535 | NAND2_X1 U377 ( .A1(dividend[19]), .A2(n347), .ZN(n193) ); 536 | OAI221_X1 U378 ( .B1(n51), .B2(n470), .C1(n430), .C2(n50), .A(n194), .ZN( 537 | n292) ); 538 | NAND2_X1 U379 ( .A1(dividend[18]), .A2(n347), .ZN(n194) ); 539 | OAI221_X1 U380 ( .B1(n52), .B2(n378), .C1(n430), .C2(n51), .A(n195), .ZN( 540 | n293) ); 541 | NAND2_X1 U381 ( .A1(dividend[17]), .A2(n347), .ZN(n195) ); 542 | OAI221_X1 U382 ( .B1(n53), .B2(n378), .C1(n430), .C2(n52), .A(n196), .ZN( 543 | n294) ); 544 | NAND2_X1 U383 ( .A1(dividend[16]), .A2(n347), .ZN(n196) ); 545 | OAI221_X1 U384 ( .B1(n54), .B2(n378), .C1(n430), .C2(n53), .A(n197), .ZN( 546 | n295) ); 547 | NAND2_X1 U385 ( .A1(dividend[15]), .A2(n347), .ZN(n197) ); 548 | OAI221_X1 U386 ( .B1(n55), .B2(n378), .C1(n430), .C2(n54), .A(n198), .ZN( 549 | n296) ); 550 | NAND2_X1 U387 ( .A1(dividend[14]), .A2(n347), .ZN(n198) ); 551 | OAI221_X1 U388 ( .B1(n56), .B2(n378), .C1(n430), .C2(n55), .A(n199), .ZN( 552 | n297) ); 553 | NAND2_X1 U389 ( .A1(dividend[13]), .A2(n347), .ZN(n199) ); 554 | OAI221_X1 U390 ( .B1(n57), .B2(n378), .C1(n430), .C2(n56), .A(n200), .ZN( 555 | n298) ); 556 | NAND2_X1 U391 ( .A1(dividend[12]), .A2(n347), .ZN(n200) ); 557 | OAI221_X1 U392 ( .B1(n58), .B2(n378), .C1(n430), .C2(n57), .A(n201), .ZN( 558 | n299) ); 559 | NAND2_X1 U393 ( .A1(dividend[11]), .A2(n347), .ZN(n201) ); 560 | OAI221_X1 U394 ( .B1(n59), .B2(n378), .C1(n430), .C2(n58), .A(n202), .ZN( 561 | n300) ); 562 | NAND2_X1 U395 ( .A1(dividend[10]), .A2(n347), .ZN(n202) ); 563 | OAI221_X1 U396 ( .B1(n60), .B2(n378), .C1(n430), .C2(n59), .A(n203), .ZN( 564 | n301) ); 565 | NAND2_X1 U397 ( .A1(dividend[9]), .A2(n347), .ZN(n203) ); 566 | OAI221_X1 U398 ( .B1(n61), .B2(n378), .C1(n430), .C2(n60), .A(n204), .ZN( 567 | n302) ); 568 | NAND2_X1 U399 ( .A1(dividend[8]), .A2(n347), .ZN(n204) ); 569 | OAI221_X1 U400 ( .B1(n62), .B2(n378), .C1(n430), .C2(n61), .A(n205), .ZN( 570 | n303) ); 571 | NAND2_X1 U401 ( .A1(dividend[7]), .A2(n347), .ZN(n205) ); 572 | OAI221_X1 U402 ( .B1(n63), .B2(n378), .C1(n430), .C2(n62), .A(n206), .ZN( 573 | n304) ); 574 | NAND2_X1 U403 ( .A1(dividend[6]), .A2(n347), .ZN(n206) ); 575 | OAI221_X1 U404 ( .B1(n64), .B2(n378), .C1(n430), .C2(n63), .A(n207), .ZN( 576 | n305) ); 577 | NAND2_X1 U405 ( .A1(dividend[5]), .A2(n347), .ZN(n207) ); 578 | OAI221_X1 U406 ( .B1(n65), .B2(n378), .C1(n430), .C2(n64), .A(n208), .ZN( 579 | n306) ); 580 | NAND2_X1 U407 ( .A1(dividend[4]), .A2(n347), .ZN(n208) ); 581 | OAI221_X1 U408 ( .B1(n66), .B2(n470), .C1(n430), .C2(n65), .A(n209), .ZN( 582 | n307) ); 583 | NAND2_X1 U409 ( .A1(dividend[3]), .A2(n347), .ZN(n209) ); 584 | OAI221_X1 U410 ( .B1(n67), .B2(n470), .C1(n430), .C2(n66), .A(n210), .ZN( 585 | n308) ); 586 | NAND2_X1 U411 ( .A1(dividend[2]), .A2(n347), .ZN(n210) ); 587 | INV_X1 U412 ( .A(n221), .ZN(n435) ); 588 | AOI22_X1 U413 ( .A1(n178), .A2(cnt_reg[5]), .B1(n345), .B2(N234), .ZN(n221) 589 | ); 590 | INV_X1 U414 ( .A(n222), .ZN(n434) ); 591 | AOI22_X1 U415 ( .A1(n178), .A2(cnt_reg[4]), .B1(n345), .B2(N233), .ZN(n222) 592 | ); 593 | INV_X1 U416 ( .A(n223), .ZN(n433) ); 594 | AOI22_X1 U417 ( .A1(n178), .A2(cnt_reg[3]), .B1(n345), .B2(N232), .ZN(n223) 595 | ); 596 | INV_X1 U418 ( .A(n224), .ZN(n432) ); 597 | AOI22_X1 U419 ( .A1(n178), .A2(cnt_reg[2]), .B1(n345), .B2(N231), .ZN(n224) 598 | ); 599 | INV_X1 U420 ( .A(n225), .ZN(n431) ); 600 | AOI22_X1 U421 ( .A1(n178), .A2(cnt_reg[1]), .B1(n345), .B2(N230), .ZN(n225) 601 | ); 602 | OAI22_X1 U422 ( .A1(n430), .A2(n75), .B1(n378), .B2(cnt_reg[0]), .ZN(n342) 603 | ); 604 | OAI21_X1 U423 ( .B1(n437), .B2(n227), .A(n228), .ZN(n344) ); 605 | INV_X1 U424 ( .A(start), .ZN(n437) ); 606 | NOR4_X1 U425 ( .A1(cnt_reg[4]), .A2(cnt_reg[3]), .A3(cnt_reg[2]), .A4( 607 | cnt_reg[1]), .ZN(n229) ); 608 | NAND2_X1 U426 ( .A1(n226), .A2(n470), .ZN(n343) ); 609 | NOR2_X1 U428 ( .A1(n147), .A2(n66), .ZN(quotient[2]) ); 610 | NOR2_X1 U429 ( .A1(n147), .A2(n65), .ZN(quotient[3]) ); 611 | NOR2_X1 U430 ( .A1(n147), .A2(n64), .ZN(quotient[4]) ); 612 | NOR2_X1 U431 ( .A1(n147), .A2(n63), .ZN(quotient[5]) ); 613 | NOR2_X1 U432 ( .A1(n147), .A2(n62), .ZN(quotient[6]) ); 614 | NOR2_X1 U433 ( .A1(n147), .A2(n61), .ZN(quotient[7]) ); 615 | NOR2_X1 U434 ( .A1(n147), .A2(n60), .ZN(quotient[8]) ); 616 | NOR2_X1 U435 ( .A1(n147), .A2(n59), .ZN(quotient[9]) ); 617 | NOR2_X1 U436 ( .A1(n381), .A2(n58), .ZN(quotient[10]) ); 618 | NOR2_X1 U437 ( .A1(n381), .A2(n57), .ZN(quotient[11]) ); 619 | NOR2_X1 U438 ( .A1(n381), .A2(n56), .ZN(quotient[12]) ); 620 | NOR2_X1 U439 ( .A1(n381), .A2(n55), .ZN(quotient[13]) ); 621 | NOR2_X1 U440 ( .A1(n381), .A2(n54), .ZN(quotient[14]) ); 622 | NOR2_X1 U441 ( .A1(n381), .A2(n53), .ZN(quotient[15]) ); 623 | NOR2_X1 U442 ( .A1(n147), .A2(n52), .ZN(quotient[16]) ); 624 | NOR2_X1 U443 ( .A1(n381), .A2(n51), .ZN(quotient[17]) ); 625 | NOR2_X1 U444 ( .A1(n147), .A2(n50), .ZN(quotient[18]) ); 626 | NOR2_X1 U445 ( .A1(n147), .A2(n49), .ZN(quotient[19]) ); 627 | NOR2_X1 U446 ( .A1(n147), .A2(n48), .ZN(quotient[20]) ); 628 | NOR2_X1 U447 ( .A1(n147), .A2(n47), .ZN(quotient[21]) ); 629 | NOR2_X1 U448 ( .A1(n147), .A2(n46), .ZN(quotient[22]) ); 630 | NOR2_X1 U449 ( .A1(n147), .A2(n45), .ZN(quotient[23]) ); 631 | NOR2_X1 U450 ( .A1(n147), .A2(n44), .ZN(quotient[24]) ); 632 | NOR2_X1 U451 ( .A1(n147), .A2(n43), .ZN(quotient[25]) ); 633 | NOR2_X1 U452 ( .A1(n147), .A2(n42), .ZN(quotient[26]) ); 634 | NOR2_X1 U453 ( .A1(n147), .A2(n41), .ZN(quotient[27]) ); 635 | NOR2_X1 U454 ( .A1(n147), .A2(n40), .ZN(quotient[28]) ); 636 | NOR2_X1 U455 ( .A1(n147), .A2(n39), .ZN(quotient[29]) ); 637 | NOR2_X1 U456 ( .A1(n147), .A2(n38), .ZN(quotient[30]) ); 638 | NOR2_X1 U457 ( .A1(n147), .A2(n67), .ZN(quotient[1]) ); 639 | NAND2_X1 U459 ( .A1(n428), .A2(n220), .ZN(n218) ); 640 | INV_X1 U461 ( .A(divisor[20]), .ZN(n449) ); 641 | INV_X1 U462 ( .A(divisor[21]), .ZN(n448) ); 642 | INV_X1 U463 ( .A(divisor[22]), .ZN(n447) ); 643 | INV_X1 U464 ( .A(divisor[23]), .ZN(n446) ); 644 | INV_X1 U465 ( .A(divisor[17]), .ZN(n452) ); 645 | INV_X1 U466 ( .A(divisor[18]), .ZN(n451) ); 646 | INV_X1 U467 ( .A(divisor[19]), .ZN(n450) ); 647 | INV_X1 U468 ( .A(divisor[1]), .ZN(n468) ); 648 | INV_X1 U469 ( .A(divisor[13]), .ZN(n456) ); 649 | INV_X1 U470 ( .A(divisor[14]), .ZN(n455) ); 650 | INV_X1 U471 ( .A(divisor[15]), .ZN(n454) ); 651 | INV_X1 U472 ( .A(divisor[16]), .ZN(n453) ); 652 | INV_X1 U473 ( .A(divisor[0]), .ZN(n469) ); 653 | INV_X1 U474 ( .A(divisor[10]), .ZN(n459) ); 654 | INV_X1 U475 ( .A(divisor[11]), .ZN(n458) ); 655 | INV_X1 U476 ( .A(divisor[12]), .ZN(n457) ); 656 | INV_X1 U477 ( .A(divisor[6]), .ZN(n463) ); 657 | INV_X1 U478 ( .A(divisor[7]), .ZN(n462) ); 658 | INV_X1 U479 ( .A(divisor[8]), .ZN(n461) ); 659 | INV_X1 U480 ( .A(divisor[9]), .ZN(n460) ); 660 | INV_X1 U481 ( .A(divisor[31]), .ZN(n438) ); 661 | INV_X1 U482 ( .A(divisor[3]), .ZN(n466) ); 662 | INV_X1 U483 ( .A(divisor[4]), .ZN(n465) ); 663 | INV_X1 U484 ( .A(divisor[5]), .ZN(n464) ); 664 | INV_X1 U485 ( .A(divisor[28]), .ZN(n441) ); 665 | INV_X1 U486 ( .A(divisor[29]), .ZN(n440) ); 666 | INV_X1 U487 ( .A(divisor[2]), .ZN(n467) ); 667 | INV_X1 U488 ( .A(divisor[30]), .ZN(n439) ); 668 | INV_X1 U489 ( .A(divisor[24]), .ZN(n445) ); 669 | INV_X1 U490 ( .A(divisor[25]), .ZN(n444) ); 670 | INV_X1 U491 ( .A(divisor[26]), .ZN(n443) ); 671 | INV_X1 U492 ( .A(divisor[27]), .ZN(n442) ); 672 | INV_X1 U493 ( .A(rst), .ZN(n428) ); 673 | NAND2_X1 U497 ( .A1(n349), .A2(n386), .ZN(n227) ); 674 | AOI21_X1 U498 ( .B1(state_reg_1_), .B2(n387), .A(start), .ZN(n388) ); 675 | OAI21_X1 U499 ( .B1(n388), .B2(done), .A(n428), .ZN(n389) ); 676 | OAI221_X1 U502 ( .B1(n37), .B2(n374), .C1(n38), .C2(n378), .A(n180), .ZN( 677 | n279) ); 678 | AOI22_X1 U503 ( .A1(remainder_reg[31]), .A2(n345), .B1(remainder_reg[32]), 679 | .B2(n178), .ZN(n390) ); 680 | INV_X1 U504 ( .A(n390), .ZN(n436) ); 681 | AOI22_X1 U506 ( .A1(alu_result[0]), .A2(n364), .B1(remainder_reg[32]), .B2( 682 | n361), .ZN(n392) ); 683 | OAI21_X1 U507 ( .B1(n35), .B2(n374), .A(n392), .ZN(n278) ); 684 | AOI22_X1 U508 ( .A1(alu_result[1]), .A2(n352), .B1(remainder_reg[33]), .B2( 685 | n361), .ZN(n393) ); 686 | OAI21_X1 U509 ( .B1(n34), .B2(n430), .A(n393), .ZN(n277) ); 687 | AOI22_X1 U510 ( .A1(alu_result[2]), .A2(n352), .B1(remainder_reg[34]), .B2( 688 | n361), .ZN(n394) ); 689 | OAI21_X1 U511 ( .B1(n33), .B2(n430), .A(n394), .ZN(n276) ); 690 | AOI22_X1 U512 ( .A1(alu_result[3]), .A2(n352), .B1(remainder_reg[35]), .B2( 691 | n361), .ZN(n395) ); 692 | OAI21_X1 U513 ( .B1(n32), .B2(n430), .A(n395), .ZN(n275) ); 693 | AOI22_X1 U514 ( .A1(alu_result[4]), .A2(n352), .B1(remainder_reg[36]), .B2( 694 | n361), .ZN(n396) ); 695 | OAI21_X1 U515 ( .B1(n31), .B2(n430), .A(n396), .ZN(n274) ); 696 | AOI22_X1 U516 ( .A1(alu_result[5]), .A2(n352), .B1(remainder_reg[37]), .B2( 697 | n361), .ZN(n397) ); 698 | OAI21_X1 U517 ( .B1(n30), .B2(n430), .A(n397), .ZN(n273) ); 699 | AOI22_X1 U518 ( .A1(alu_result[6]), .A2(n352), .B1(remainder_reg[38]), .B2( 700 | n361), .ZN(n398) ); 701 | OAI21_X1 U519 ( .B1(n29), .B2(n430), .A(n398), .ZN(n272) ); 702 | AOI22_X1 U520 ( .A1(alu_result[7]), .A2(n352), .B1(remainder_reg[39]), .B2( 703 | n361), .ZN(n399) ); 704 | OAI21_X1 U521 ( .B1(n28), .B2(n430), .A(n399), .ZN(n271) ); 705 | AOI22_X1 U522 ( .A1(alu_result[8]), .A2(n352), .B1(remainder_reg[40]), .B2( 706 | n361), .ZN(n400) ); 707 | OAI21_X1 U523 ( .B1(n27), .B2(n430), .A(n400), .ZN(n270) ); 708 | AOI22_X1 U524 ( .A1(alu_result[9]), .A2(n365), .B1(remainder_reg[41]), .B2( 709 | n361), .ZN(n401) ); 710 | OAI21_X1 U525 ( .B1(n26), .B2(n430), .A(n401), .ZN(n269) ); 711 | AOI22_X1 U526 ( .A1(alu_result[10]), .A2(n365), .B1(remainder_reg[42]), .B2( 712 | n361), .ZN(n402) ); 713 | OAI21_X1 U527 ( .B1(n25), .B2(n430), .A(n402), .ZN(n268) ); 714 | AOI22_X1 U528 ( .A1(alu_result[11]), .A2(n365), .B1(remainder_reg[43]), .B2( 715 | n361), .ZN(n403) ); 716 | OAI21_X1 U529 ( .B1(n24), .B2(n430), .A(n403), .ZN(n267) ); 717 | AOI22_X1 U530 ( .A1(alu_result[12]), .A2(n365), .B1(remainder_reg[44]), .B2( 718 | n362), .ZN(n404) ); 719 | OAI21_X1 U531 ( .B1(n23), .B2(n430), .A(n404), .ZN(n266) ); 720 | AOI22_X1 U532 ( .A1(alu_result[13]), .A2(n365), .B1(remainder_reg[45]), .B2( 721 | n362), .ZN(n405) ); 722 | OAI21_X1 U533 ( .B1(n22), .B2(n430), .A(n405), .ZN(n265) ); 723 | AOI22_X1 U534 ( .A1(alu_result[14]), .A2(n365), .B1(remainder_reg[46]), .B2( 724 | n362), .ZN(n406) ); 725 | OAI21_X1 U535 ( .B1(n21), .B2(n430), .A(n406), .ZN(n264) ); 726 | AOI22_X1 U536 ( .A1(alu_result[15]), .A2(n365), .B1(remainder_reg[47]), .B2( 727 | n362), .ZN(n407) ); 728 | OAI21_X1 U537 ( .B1(n20), .B2(n374), .A(n407), .ZN(n263) ); 729 | AOI22_X1 U538 ( .A1(alu_result[16]), .A2(n365), .B1(remainder_reg[48]), .B2( 730 | n362), .ZN(n408) ); 731 | OAI21_X1 U539 ( .B1(n19), .B2(n430), .A(n408), .ZN(n262) ); 732 | AOI22_X1 U540 ( .A1(alu_result[17]), .A2(n365), .B1(remainder_reg[49]), .B2( 733 | n362), .ZN(n409) ); 734 | OAI21_X1 U541 ( .B1(n18), .B2(n430), .A(n409), .ZN(n261) ); 735 | AOI22_X1 U542 ( .A1(alu_result[18]), .A2(n365), .B1(remainder_reg[50]), .B2( 736 | n362), .ZN(n410) ); 737 | OAI21_X1 U543 ( .B1(n17), .B2(n430), .A(n410), .ZN(n260) ); 738 | AOI22_X1 U544 ( .A1(alu_result[19]), .A2(n365), .B1(remainder_reg[51]), .B2( 739 | n362), .ZN(n411) ); 740 | OAI21_X1 U545 ( .B1(n16), .B2(n430), .A(n411), .ZN(n259) ); 741 | AOI22_X1 U546 ( .A1(alu_result[20]), .A2(n364), .B1(remainder_reg[52]), .B2( 742 | n362), .ZN(n412) ); 743 | OAI21_X1 U547 ( .B1(n15), .B2(n430), .A(n412), .ZN(n258) ); 744 | AOI22_X1 U548 ( .A1(alu_result[21]), .A2(n364), .B1(remainder_reg[53]), .B2( 745 | n362), .ZN(n413) ); 746 | OAI21_X1 U549 ( .B1(n14), .B2(n430), .A(n413), .ZN(n257) ); 747 | AOI22_X1 U550 ( .A1(alu_result[22]), .A2(n364), .B1(remainder_reg[54]), .B2( 748 | n362), .ZN(n414) ); 749 | OAI21_X1 U551 ( .B1(n13), .B2(n430), .A(n414), .ZN(n256) ); 750 | AOI22_X1 U552 ( .A1(alu_result[23]), .A2(n364), .B1(remainder_reg[55]), .B2( 751 | n362), .ZN(n415) ); 752 | OAI21_X1 U553 ( .B1(n12), .B2(n430), .A(n415), .ZN(n255) ); 753 | AOI22_X1 U554 ( .A1(alu_result[24]), .A2(n364), .B1(remainder_reg[56]), .B2( 754 | n363), .ZN(n416) ); 755 | OAI21_X1 U555 ( .B1(n11), .B2(n430), .A(n416), .ZN(n254) ); 756 | AOI22_X1 U556 ( .A1(alu_result[25]), .A2(n364), .B1(remainder_reg[57]), .B2( 757 | n363), .ZN(n417) ); 758 | OAI21_X1 U557 ( .B1(n10), .B2(n430), .A(n417), .ZN(n253) ); 759 | AOI22_X1 U558 ( .A1(alu_result[26]), .A2(n364), .B1(remainder_reg[58]), .B2( 760 | n363), .ZN(n418) ); 761 | OAI21_X1 U559 ( .B1(n9), .B2(n374), .A(n418), .ZN(n252) ); 762 | AOI22_X1 U560 ( .A1(alu_result[27]), .A2(n364), .B1(remainder_reg[59]), .B2( 763 | n363), .ZN(n419) ); 764 | OAI21_X1 U561 ( .B1(n8), .B2(n374), .A(n419), .ZN(n251) ); 765 | AOI22_X1 U562 ( .A1(alu_result[28]), .A2(n364), .B1(remainder_reg[60]), .B2( 766 | n363), .ZN(n420) ); 767 | OAI21_X1 U563 ( .B1(n7), .B2(n374), .A(n420), .ZN(n250) ); 768 | AOI22_X1 U564 ( .A1(alu_result[29]), .A2(n364), .B1(remainder_reg[61]), .B2( 769 | n363), .ZN(n421) ); 770 | OAI21_X1 U565 ( .B1(n6), .B2(n374), .A(n421), .ZN(n249) ); 771 | AOI22_X1 U566 ( .A1(alu_result[30]), .A2(n364), .B1(remainder_reg[62]), .B2( 772 | n363), .ZN(n422) ); 773 | OAI21_X1 U567 ( .B1(n4), .B2(n374), .A(n422), .ZN(n248) ); 774 | OAI22_X1 U569 ( .A1(n438), .A2(n358), .B1(n81), .B2(n348), .ZN(n310) ); 775 | OAI22_X1 U570 ( .A1(n439), .A2(n358), .B1(n82), .B2(n348), .ZN(n311) ); 776 | OAI22_X1 U571 ( .A1(n440), .A2(n358), .B1(n83), .B2(n348), .ZN(n312) ); 777 | OAI22_X1 U572 ( .A1(n441), .A2(n358), .B1(n84), .B2(n348), .ZN(n313) ); 778 | OAI22_X1 U573 ( .A1(n442), .A2(n358), .B1(n85), .B2(n348), .ZN(n314) ); 779 | OAI22_X1 U574 ( .A1(n443), .A2(n358), .B1(n86), .B2(n348), .ZN(n315) ); 780 | OAI22_X1 U575 ( .A1(n444), .A2(n358), .B1(n87), .B2(n348), .ZN(n316) ); 781 | OAI22_X1 U576 ( .A1(n445), .A2(n358), .B1(n88), .B2(n348), .ZN(n317) ); 782 | OAI22_X1 U577 ( .A1(n446), .A2(n358), .B1(n89), .B2(n348), .ZN(n318) ); 783 | OAI22_X1 U578 ( .A1(n447), .A2(n358), .B1(n90), .B2(n348), .ZN(n319) ); 784 | OAI22_X1 U579 ( .A1(n448), .A2(n358), .B1(n91), .B2(n348), .ZN(n320) ); 785 | OAI22_X1 U580 ( .A1(n449), .A2(n358), .B1(n92), .B2(n348), .ZN(n321) ); 786 | OAI22_X1 U581 ( .A1(n450), .A2(n424), .B1(n93), .B2(n348), .ZN(n322) ); 787 | OAI22_X1 U582 ( .A1(n451), .A2(n424), .B1(n94), .B2(n348), .ZN(n323) ); 788 | OAI22_X1 U583 ( .A1(n452), .A2(n424), .B1(n95), .B2(n348), .ZN(n324) ); 789 | OAI22_X1 U584 ( .A1(n453), .A2(n424), .B1(n96), .B2(n348), .ZN(n325) ); 790 | OAI22_X1 U585 ( .A1(n454), .A2(n424), .B1(n97), .B2(n348), .ZN(n326) ); 791 | OAI22_X1 U586 ( .A1(n455), .A2(n424), .B1(n98), .B2(n348), .ZN(n327) ); 792 | OAI22_X1 U587 ( .A1(n456), .A2(n424), .B1(n99), .B2(n348), .ZN(n328) ); 793 | OAI22_X1 U588 ( .A1(n457), .A2(n424), .B1(n100), .B2(n348), .ZN(n329) ); 794 | OAI22_X1 U589 ( .A1(n458), .A2(n424), .B1(n101), .B2(n348), .ZN(n330) ); 795 | OAI22_X1 U590 ( .A1(n459), .A2(n424), .B1(n102), .B2(n348), .ZN(n331) ); 796 | OAI22_X1 U591 ( .A1(n460), .A2(n424), .B1(n103), .B2(n348), .ZN(n332) ); 797 | OAI22_X1 U592 ( .A1(n461), .A2(n424), .B1(n104), .B2(n348), .ZN(n333) ); 798 | OAI22_X1 U593 ( .A1(n462), .A2(n424), .B1(n105), .B2(n348), .ZN(n334) ); 799 | OAI22_X1 U594 ( .A1(n463), .A2(n424), .B1(n106), .B2(n348), .ZN(n335) ); 800 | OAI22_X1 U595 ( .A1(n464), .A2(n424), .B1(n107), .B2(n348), .ZN(n336) ); 801 | OAI22_X1 U596 ( .A1(n465), .A2(n424), .B1(n108), .B2(n348), .ZN(n337) ); 802 | OAI22_X1 U597 ( .A1(n466), .A2(n424), .B1(n109), .B2(n348), .ZN(n338) ); 803 | OAI22_X1 U598 ( .A1(n467), .A2(n424), .B1(n110), .B2(n348), .ZN(n339) ); 804 | OAI22_X1 U599 ( .A1(n468), .A2(n424), .B1(n111), .B2(n348), .ZN(n340) ); 805 | OAI22_X1 U600 ( .A1(n469), .A2(n424), .B1(n112), .B2(n348), .ZN(n341) ); 806 | NAND2_X1 U602 ( .A1(dividend[1]), .A2(n347), .ZN(n426) ); 807 | OAI221_X1 U603 ( .B1(n67), .B2(n374), .C1(n68), .C2(n470), .A(n426), .ZN( 808 | n309) ); 809 | NOR2_X1 U604 ( .A1(n381), .A2(n35), .ZN(remainder[0]) ); 810 | NOR2_X1 U605 ( .A1(n381), .A2(n34), .ZN(remainder[1]) ); 811 | NOR2_X1 U606 ( .A1(n147), .A2(n33), .ZN(remainder[2]) ); 812 | NOR2_X1 U607 ( .A1(n147), .A2(n32), .ZN(remainder[3]) ); 813 | NOR2_X1 U608 ( .A1(n147), .A2(n31), .ZN(remainder[4]) ); 814 | NOR2_X1 U609 ( .A1(n147), .A2(n30), .ZN(remainder[5]) ); 815 | NOR2_X1 U610 ( .A1(n147), .A2(n29), .ZN(remainder[6]) ); 816 | NOR2_X1 U611 ( .A1(n382), .A2(n28), .ZN(remainder[7]) ); 817 | NOR2_X1 U612 ( .A1(n382), .A2(n27), .ZN(remainder[8]) ); 818 | NOR2_X1 U613 ( .A1(n382), .A2(n26), .ZN(remainder[9]) ); 819 | NOR2_X1 U614 ( .A1(n382), .A2(n25), .ZN(remainder[10]) ); 820 | NOR2_X1 U615 ( .A1(n382), .A2(n24), .ZN(remainder[11]) ); 821 | NOR2_X1 U616 ( .A1(n382), .A2(n23), .ZN(remainder[12]) ); 822 | NOR2_X1 U617 ( .A1(n382), .A2(n22), .ZN(remainder[13]) ); 823 | NOR2_X1 U618 ( .A1(n382), .A2(n21), .ZN(remainder[14]) ); 824 | NOR2_X1 U619 ( .A1(n382), .A2(n20), .ZN(remainder[15]) ); 825 | NOR2_X1 U620 ( .A1(n382), .A2(n19), .ZN(remainder[16]) ); 826 | NOR2_X1 U621 ( .A1(n382), .A2(n18), .ZN(remainder[17]) ); 827 | NOR2_X1 U622 ( .A1(n382), .A2(n17), .ZN(remainder[18]) ); 828 | NOR2_X1 U623 ( .A1(n382), .A2(n16), .ZN(remainder[19]) ); 829 | NOR2_X1 U624 ( .A1(n382), .A2(n15), .ZN(remainder[20]) ); 830 | NOR2_X1 U625 ( .A1(n382), .A2(n14), .ZN(remainder[21]) ); 831 | NOR2_X1 U626 ( .A1(n382), .A2(n13), .ZN(remainder[22]) ); 832 | NOR2_X1 U627 ( .A1(n382), .A2(n12), .ZN(remainder[23]) ); 833 | NOR2_X1 U628 ( .A1(n382), .A2(n11), .ZN(remainder[24]) ); 834 | NOR2_X1 U629 ( .A1(n382), .A2(n10), .ZN(remainder[25]) ); 835 | NOR2_X1 U630 ( .A1(n381), .A2(n9), .ZN(remainder[26]) ); 836 | NOR2_X1 U631 ( .A1(n381), .A2(n8), .ZN(remainder[27]) ); 837 | NOR2_X1 U632 ( .A1(n381), .A2(n7), .ZN(remainder[28]) ); 838 | NOR2_X1 U633 ( .A1(n381), .A2(n6), .ZN(remainder[29]) ); 839 | NOR2_X1 U634 ( .A1(n381), .A2(n4), .ZN(remainder[30]) ); 840 | AOI22_X1 U635 ( .A1(alu_result[31]), .A2(n365), .B1(remainder_reg[63]), .B2( 841 | n363), .ZN(n427) ); 842 | OAI21_X1 U636 ( .B1(n3), .B2(n374), .A(n427), .ZN(n247) ); 843 | NOR2_X1 U637 ( .A1(n3), .A2(n147), .ZN(remainder[31]) ); 844 | NOR2_X1 U638 ( .A1(n381), .A2(n68), .ZN(quotient[0]) ); 845 | XOR2_X1 U639 ( .A(add_117_carry[5]), .B(cnt_reg[5]), .Z(N234) ); 846 | INV_X2 U311 ( .A(n178), .ZN(n430) ); 847 | NAND2_X1 U313 ( .A1(n389), .A2(n227), .ZN(n178) ); 848 | AND2_X2 U314 ( .A1(n423), .A2(n218), .ZN(n348) ); 849 | NAND2_X1 U316 ( .A1(n218), .A2(n346), .ZN(n424) ); 850 | NAND2_X2 U317 ( .A1(done), .A2(state_reg_1_), .ZN(n147) ); 851 | AND3_X2 U320 ( .A1(n346), .A2(n389), .A3(n349), .ZN(n347) ); 852 | INV_X1 U322 ( .A(n386), .ZN(n423) ); 853 | NOR2_X1 U323 ( .A1(rst), .A2(n384), .ZN(n386) ); 854 | OR3_X1 U324 ( .A1(n352), .A2(n350), .A3(n351), .ZN(n429) ); 855 | NOR2_X1 U325 ( .A1(n37), .A2(n147), .ZN(quotient[31]) ); 856 | INV_X1 U331 ( .A(n470), .ZN(n345) ); 857 | NAND3_X1 U332 ( .A1(n428), .A2(state_reg_1_), .A3(n387), .ZN(n470) ); 858 | NOR2_X1 U333 ( .A1(alu_result[32]), .A2(n470), .ZN(n352) ); 859 | NAND2_X1 U336 ( .A1(n237), .A2(n236), .ZN(n384) ); 860 | endmodule 861 | 862 | -------------------------------------------------------------------------------- /divider/layout/designs/divider.mapped.v: -------------------------------------------------------------------------------- 1 | 2 | module divider_DW01_sub_1 ( A, B, CI, DIFF, CO ); 3 | input [32:0] A; 4 | input [32:0] B; 5 | output [32:0] DIFF; 6 | input CI; 7 | output CO; 8 | wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, 9 | n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, 10 | n31, n32, n33, n34, n35, n37, n39, n40, n41, n42, n43, n45, n47, n48, 11 | n49, n50, n51, n53, n55, n56, n57, n58, n59, n61, n63, n64, n65, n66, 12 | n67, n69, n71, n72, n73, n74, n75, n76, n77, n78, n79, n81, n83, n84, 13 | n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, 14 | n101, n102, n103, n104, n106, n107, n108, n109, n110, n111, n112, 15 | n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, 16 | n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134, 17 | n135, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, 18 | n147, n148, n149, n150, n151, n152, n153, n154, n156, n158, n160, 19 | n162, n164, n166, n168, n169, n170, n171, n172, n173, n174, n175, 20 | n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, 21 | n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, 22 | n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, 23 | n209, n210, n319, n320, n321, n322, n323, n324, n325, n326, n327, 24 | n328, n329; 25 | 26 | FA_X1 U2 ( .A(n179), .B(A[31]), .CI(n27), .CO(n26), .S(DIFF[31]) ); 27 | FA_X1 U4 ( .A(n181), .B(A[29]), .CI(n29), .CO(n28), .S(DIFF[29]) ); 28 | FA_X1 U5 ( .A(n182), .B(A[28]), .CI(n30), .CO(n29), .S(DIFF[28]) ); 29 | FA_X1 U6 ( .A(n183), .B(A[27]), .CI(n31), .CO(n30), .S(DIFF[27]) ); 30 | FA_X1 U7 ( .A(n184), .B(A[26]), .CI(n32), .CO(n31), .S(DIFF[26]) ); 31 | NOR2_X1 U241 ( .A1(n197), .A2(A[13]), .ZN(n89) ); 32 | NOR2_X1 U242 ( .A1(n208), .A2(A[2]), .ZN(n147) ); 33 | NOR2_X1 U243 ( .A1(n205), .A2(A[5]), .ZN(n133) ); 34 | NOR2_X1 U244 ( .A1(n203), .A2(A[7]), .ZN(n125) ); 35 | NOR2_X1 U245 ( .A1(n204), .A2(A[6]), .ZN(n128) ); 36 | NOR2_X1 U246 ( .A1(n210), .A2(A[0]), .ZN(n153) ); 37 | AOI21_X1 U247 ( .B1(n48), .B2(n322), .A(n45), .ZN(n43) ); 38 | AOI21_X1 U248 ( .B1(n56), .B2(n323), .A(n53), .ZN(n51) ); 39 | AOI21_X1 U249 ( .B1(n100), .B2(n113), .A(n101), .ZN(n99) ); 40 | NOR2_X2 U253 ( .A1(n199), .A2(A[11]), .ZN(n102) ); 41 | NAND2_X1 U256 ( .A1(n198), .A2(A[12]), .ZN(n95) ); 42 | NAND2_X1 U257 ( .A1(n208), .A2(A[2]), .ZN(n148) ); 43 | INV_X1 U259 ( .A(n97), .ZN(n96) ); 44 | NAND2_X1 U260 ( .A1(n112), .A2(n100), .ZN(n98) ); 45 | INV_X1 U261 ( .A(n120), .ZN(n119) ); 46 | AOI21_X1 U262 ( .B1(n140), .B2(n131), .A(n132), .ZN(n130) ); 47 | OAI21_X1 U263 ( .B1(n119), .B2(n110), .A(n111), .ZN(n109) ); 48 | INV_X1 U264 ( .A(n112), .ZN(n110) ); 49 | OAI21_X1 U265 ( .B1(n119), .B2(n98), .A(n99), .ZN(n97) ); 50 | INV_X1 U266 ( .A(n141), .ZN(n140) ); 51 | INV_X1 U270 ( .A(n150), .ZN(n149) ); 52 | OAI21_X1 U271 ( .B1(n67), .B2(n65), .A(n66), .ZN(n64) ); 53 | OAI21_X1 U272 ( .B1(n59), .B2(n57), .A(n58), .ZN(n56) ); 54 | OAI21_X1 U273 ( .B1(n75), .B2(n73), .A(n74), .ZN(n72) ); 55 | OAI21_X1 U274 ( .B1(n51), .B2(n49), .A(n50), .ZN(n48) ); 56 | OAI21_X1 U275 ( .B1(n114), .B2(n118), .A(n115), .ZN(n113) ); 57 | OAI21_X1 U276 ( .B1(n102), .B2(n108), .A(n103), .ZN(n101) ); 58 | OAI21_X1 U277 ( .B1(n133), .B2(n139), .A(n134), .ZN(n132) ); 59 | OAI21_X1 U278 ( .B1(n43), .B2(n41), .A(n42), .ZN(n40) ); 60 | INV_X1 U279 ( .A(n39), .ZN(n37) ); 61 | INV_X1 U280 ( .A(n55), .ZN(n53) ); 62 | INV_X1 U281 ( .A(n47), .ZN(n45) ); 63 | NOR2_X1 U282 ( .A1(n138), .A2(n133), .ZN(n131) ); 64 | OAI21_X1 U283 ( .B1(n151), .B2(n153), .A(n152), .ZN(n150) ); 65 | NOR2_X1 U284 ( .A1(n107), .A2(n102), .ZN(n100) ); 66 | OAI21_X1 U285 ( .B1(n89), .B2(n95), .A(n90), .ZN(n88) ); 67 | OAI21_X1 U286 ( .B1(n141), .B2(n121), .A(n122), .ZN(n120) ); 68 | NAND2_X1 U287 ( .A1(n131), .A2(n123), .ZN(n121) ); 69 | AOI21_X1 U288 ( .B1(n123), .B2(n132), .A(n124), .ZN(n122) ); 70 | NOR2_X1 U289 ( .A1(n128), .A2(n125), .ZN(n123) ); 71 | AOI21_X1 U290 ( .B1(n88), .B2(n319), .A(n81), .ZN(n79) ); 72 | INV_X1 U291 ( .A(n83), .ZN(n81) ); 73 | NOR2_X1 U292 ( .A1(n98), .A2(n78), .ZN(n76) ); 74 | OAI21_X1 U293 ( .B1(n99), .B2(n78), .A(n79), .ZN(n77) ); 75 | NAND2_X1 U294 ( .A1(n87), .A2(n319), .ZN(n78) ); 76 | AOI21_X1 U295 ( .B1(n72), .B2(n321), .A(n69), .ZN(n67) ); 77 | INV_X1 U296 ( .A(n71), .ZN(n69) ); 78 | INV_X1 U297 ( .A(n63), .ZN(n61) ); 79 | NOR2_X1 U298 ( .A1(n94), .A2(n89), .ZN(n87) ); 80 | NOR2_X1 U299 ( .A1(n117), .A2(n114), .ZN(n112) ); 81 | AOI21_X1 U300 ( .B1(n142), .B2(n150), .A(n143), .ZN(n141) ); 82 | NOR2_X1 U301 ( .A1(n147), .A2(n144), .ZN(n142) ); 83 | OAI21_X1 U302 ( .B1(n144), .B2(n148), .A(n145), .ZN(n143) ); 84 | OAI21_X1 U303 ( .B1(n125), .B2(n129), .A(n126), .ZN(n124) ); 85 | AOI21_X1 U304 ( .B1(n97), .B2(n92), .A(n93), .ZN(n91) ); 86 | INV_X1 U305 ( .A(n95), .ZN(n93) ); 87 | AOI21_X1 U306 ( .B1(n109), .B2(n169), .A(n106), .ZN(n104) ); 88 | INV_X1 U307 ( .A(n108), .ZN(n106) ); 89 | AOI21_X1 U308 ( .B1(n140), .B2(n175), .A(n137), .ZN(n135) ); 90 | INV_X1 U309 ( .A(n139), .ZN(n137) ); 91 | INV_X1 U310 ( .A(n94), .ZN(n92) ); 92 | INV_X1 U311 ( .A(n107), .ZN(n169) ); 93 | INV_X1 U312 ( .A(n138), .ZN(n175) ); 94 | OAI21_X1 U313 ( .B1(n119), .B2(n117), .A(n118), .ZN(n116) ); 95 | OAI21_X1 U314 ( .B1(n130), .B2(n128), .A(n129), .ZN(n127) ); 96 | OAI21_X1 U315 ( .B1(n149), .B2(n147), .A(n148), .ZN(n146) ); 97 | INV_X1 U316 ( .A(n117), .ZN(n171) ); 98 | INV_X1 U317 ( .A(n128), .ZN(n173) ); 99 | INV_X1 U318 ( .A(n147), .ZN(n177) ); 100 | INV_X1 U319 ( .A(n89), .ZN(n166) ); 101 | INV_X1 U320 ( .A(n125), .ZN(n172) ); 102 | INV_X1 U321 ( .A(n133), .ZN(n174) ); 103 | INV_X1 U322 ( .A(n144), .ZN(n176) ); 104 | INV_X1 U323 ( .A(n114), .ZN(n170) ); 105 | INV_X1 U324 ( .A(n151), .ZN(n178) ); 106 | INV_X1 U325 ( .A(n41), .ZN(n156) ); 107 | INV_X1 U326 ( .A(n49), .ZN(n158) ); 108 | INV_X1 U327 ( .A(n57), .ZN(n160) ); 109 | INV_X1 U328 ( .A(n65), .ZN(n162) ); 110 | INV_X1 U329 ( .A(n73), .ZN(n164) ); 111 | INV_X1 U330 ( .A(n33), .ZN(n154) ); 112 | INV_X1 U331 ( .A(n102), .ZN(n168) ); 113 | NOR2_X1 U332 ( .A1(n202), .A2(A[8]), .ZN(n117) ); 114 | NOR2_X2 U333 ( .A1(n207), .A2(A[3]), .ZN(n144) ); 115 | XOR2_X1 U334 ( .A(n135), .B(n21), .Z(DIFF[5]) ); 116 | NAND2_X1 U335 ( .A1(n174), .A2(n134), .ZN(n21) ); 117 | XNOR2_X1 U336 ( .A(n140), .B(n22), .ZN(DIFF[4]) ); 118 | NAND2_X1 U337 ( .A1(n175), .A2(n139), .ZN(n22) ); 119 | XNOR2_X1 U338 ( .A(n146), .B(n23), .ZN(DIFF[3]) ); 120 | NAND2_X1 U339 ( .A1(n176), .A2(n145), .ZN(n23) ); 121 | XOR2_X1 U340 ( .A(n149), .B(n24), .Z(DIFF[2]) ); 122 | NAND2_X1 U341 ( .A1(n177), .A2(n148), .ZN(n24) ); 123 | XOR2_X1 U342 ( .A(n25), .B(n153), .Z(DIFF[1]) ); 124 | NAND2_X1 U343 ( .A1(n178), .A2(n152), .ZN(n25) ); 125 | NOR2_X2 U344 ( .A1(n201), .A2(A[9]), .ZN(n114) ); 126 | OR2_X1 U345 ( .A1(n196), .A2(A[14]), .ZN(n319) ); 127 | NOR2_X1 U346 ( .A1(n200), .A2(A[10]), .ZN(n107) ); 128 | NOR2_X1 U347 ( .A1(n198), .A2(A[12]), .ZN(n94) ); 129 | NOR2_X1 U348 ( .A1(n206), .A2(A[4]), .ZN(n138) ); 130 | NOR2_X1 U349 ( .A1(n209), .A2(A[1]), .ZN(n151) ); 131 | INV_X1 U350 ( .A(B[29]), .ZN(n181) ); 132 | NAND2_X1 U351 ( .A1(n154), .A2(n34), .ZN(n1) ); 133 | NAND2_X1 U352 ( .A1(n324), .A2(n39), .ZN(n2) ); 134 | XOR2_X1 U353 ( .A(n43), .B(n3), .Z(DIFF[23]) ); 135 | NAND2_X1 U354 ( .A1(n156), .A2(n42), .ZN(n3) ); 136 | NAND2_X1 U355 ( .A1(n322), .A2(n47), .ZN(n4) ); 137 | XOR2_X1 U356 ( .A(n51), .B(n5), .Z(DIFF[21]) ); 138 | NAND2_X1 U357 ( .A1(n158), .A2(n50), .ZN(n5) ); 139 | XNOR2_X1 U358 ( .A(n56), .B(n6), .ZN(DIFF[20]) ); 140 | NAND2_X1 U359 ( .A1(n323), .A2(n55), .ZN(n6) ); 141 | NAND2_X1 U360 ( .A1(n160), .A2(n58), .ZN(n7) ); 142 | XNOR2_X1 U361 ( .A(n64), .B(n8), .ZN(DIFF[18]) ); 143 | NAND2_X1 U362 ( .A1(n320), .A2(n63), .ZN(n8) ); 144 | NAND2_X1 U363 ( .A1(n162), .A2(n66), .ZN(n9) ); 145 | NAND2_X1 U364 ( .A1(n321), .A2(n71), .ZN(n10) ); 146 | NAND2_X1 U365 ( .A1(n164), .A2(n74), .ZN(n11) ); 147 | XNOR2_X1 U366 ( .A(n84), .B(n12), .ZN(DIFF[14]) ); 148 | NAND2_X1 U367 ( .A1(n319), .A2(n83), .ZN(n12) ); 149 | XOR2_X1 U368 ( .A(n91), .B(n13), .Z(DIFF[13]) ); 150 | NAND2_X1 U369 ( .A1(n166), .A2(n90), .ZN(n13) ); 151 | XOR2_X1 U370 ( .A(n96), .B(n14), .Z(DIFF[12]) ); 152 | NAND2_X1 U371 ( .A1(n92), .A2(n95), .ZN(n14) ); 153 | XOR2_X1 U372 ( .A(n104), .B(n15), .Z(DIFF[11]) ); 154 | NAND2_X1 U373 ( .A1(n168), .A2(n103), .ZN(n15) ); 155 | XNOR2_X1 U374 ( .A(n109), .B(n16), .ZN(DIFF[10]) ); 156 | NAND2_X1 U375 ( .A1(n169), .A2(n108), .ZN(n16) ); 157 | XNOR2_X1 U376 ( .A(n116), .B(n17), .ZN(DIFF[9]) ); 158 | NAND2_X1 U377 ( .A1(n170), .A2(n115), .ZN(n17) ); 159 | XOR2_X1 U378 ( .A(n119), .B(n18), .Z(DIFF[8]) ); 160 | NAND2_X1 U379 ( .A1(n171), .A2(n118), .ZN(n18) ); 161 | XNOR2_X1 U380 ( .A(n127), .B(n19), .ZN(DIFF[7]) ); 162 | NAND2_X1 U381 ( .A1(n172), .A2(n126), .ZN(n19) ); 163 | XOR2_X1 U382 ( .A(n130), .B(n20), .Z(DIFF[6]) ); 164 | NAND2_X1 U383 ( .A1(n173), .A2(n129), .ZN(n20) ); 165 | XNOR2_X1 U384 ( .A(n210), .B(A[0]), .ZN(DIFF[0]) ); 166 | INV_X1 U385 ( .A(B[13]), .ZN(n197) ); 167 | INV_X1 U386 ( .A(B[12]), .ZN(n198) ); 168 | INV_X1 U387 ( .A(B[6]), .ZN(n204) ); 169 | INV_X1 U388 ( .A(B[10]), .ZN(n200) ); 170 | INV_X1 U389 ( .A(B[2]), .ZN(n208) ); 171 | INV_X1 U390 ( .A(B[8]), .ZN(n202) ); 172 | INV_X1 U391 ( .A(B[5]), .ZN(n205) ); 173 | INV_X1 U392 ( .A(B[7]), .ZN(n203) ); 174 | INV_X1 U393 ( .A(B[1]), .ZN(n209) ); 175 | INV_X1 U394 ( .A(B[9]), .ZN(n201) ); 176 | INV_X1 U395 ( .A(B[3]), .ZN(n207) ); 177 | INV_X1 U396 ( .A(B[4]), .ZN(n206) ); 178 | INV_X1 U397 ( .A(B[18]), .ZN(n192) ); 179 | INV_X1 U398 ( .A(B[17]), .ZN(n193) ); 180 | INV_X1 U399 ( .A(B[16]), .ZN(n194) ); 181 | INV_X1 U400 ( .A(B[15]), .ZN(n195) ); 182 | INV_X1 U401 ( .A(B[14]), .ZN(n196) ); 183 | NOR2_X1 U402 ( .A1(n193), .A2(A[17]), .ZN(n65) ); 184 | NOR2_X1 U403 ( .A1(n195), .A2(A[15]), .ZN(n73) ); 185 | NAND2_X1 U404 ( .A1(n204), .A2(A[6]), .ZN(n129) ); 186 | INV_X1 U405 ( .A(B[0]), .ZN(n210) ); 187 | NAND2_X1 U406 ( .A1(n206), .A2(A[4]), .ZN(n139) ); 188 | NAND2_X1 U407 ( .A1(n202), .A2(A[8]), .ZN(n118) ); 189 | INV_X1 U408 ( .A(B[26]), .ZN(n184) ); 190 | INV_X1 U409 ( .A(B[27]), .ZN(n183) ); 191 | INV_X1 U410 ( .A(B[28]), .ZN(n182) ); 192 | NAND2_X1 U411 ( .A1(n200), .A2(A[10]), .ZN(n108) ); 193 | INV_X1 U412 ( .A(B[31]), .ZN(n179) ); 194 | NAND2_X1 U413 ( .A1(n207), .A2(A[3]), .ZN(n145) ); 195 | NAND2_X1 U414 ( .A1(n197), .A2(A[13]), .ZN(n90) ); 196 | NAND2_X1 U415 ( .A1(n203), .A2(A[7]), .ZN(n126) ); 197 | NAND2_X1 U416 ( .A1(n205), .A2(A[5]), .ZN(n134) ); 198 | NAND2_X1 U417 ( .A1(n209), .A2(A[1]), .ZN(n152) ); 199 | OR2_X1 U418 ( .A1(n192), .A2(A[18]), .ZN(n320) ); 200 | OR2_X1 U419 ( .A1(n194), .A2(A[16]), .ZN(n321) ); 201 | NAND2_X1 U420 ( .A1(n192), .A2(A[18]), .ZN(n63) ); 202 | NAND2_X1 U421 ( .A1(n194), .A2(A[16]), .ZN(n71) ); 203 | NAND2_X1 U422 ( .A1(n196), .A2(A[14]), .ZN(n83) ); 204 | NAND2_X1 U423 ( .A1(n201), .A2(A[9]), .ZN(n115) ); 205 | NAND2_X1 U424 ( .A1(n193), .A2(A[17]), .ZN(n66) ); 206 | NAND2_X1 U425 ( .A1(n195), .A2(A[15]), .ZN(n74) ); 207 | INV_X1 U426 ( .A(B[25]), .ZN(n185) ); 208 | INV_X1 U427 ( .A(B[24]), .ZN(n186) ); 209 | INV_X1 U428 ( .A(B[23]), .ZN(n187) ); 210 | INV_X1 U429 ( .A(B[22]), .ZN(n188) ); 211 | INV_X1 U430 ( .A(B[21]), .ZN(n189) ); 212 | INV_X1 U431 ( .A(B[20]), .ZN(n190) ); 213 | INV_X1 U432 ( .A(B[19]), .ZN(n191) ); 214 | OR2_X1 U433 ( .A1(n188), .A2(A[22]), .ZN(n322) ); 215 | OR2_X1 U434 ( .A1(n190), .A2(A[20]), .ZN(n323) ); 216 | NOR2_X1 U435 ( .A1(n187), .A2(A[23]), .ZN(n41) ); 217 | NOR2_X1 U436 ( .A1(n189), .A2(A[21]), .ZN(n49) ); 218 | NOR2_X1 U437 ( .A1(n191), .A2(A[19]), .ZN(n57) ); 219 | NOR2_X1 U438 ( .A1(n185), .A2(A[25]), .ZN(n33) ); 220 | OR2_X1 U439 ( .A1(n186), .A2(A[24]), .ZN(n324) ); 221 | NAND2_X1 U440 ( .A1(n186), .A2(A[24]), .ZN(n39) ); 222 | NAND2_X1 U441 ( .A1(n188), .A2(A[22]), .ZN(n47) ); 223 | NAND2_X1 U442 ( .A1(n190), .A2(A[20]), .ZN(n55) ); 224 | NAND2_X1 U443 ( .A1(n187), .A2(A[23]), .ZN(n42) ); 225 | NAND2_X1 U444 ( .A1(n189), .A2(A[21]), .ZN(n50) ); 226 | NAND2_X1 U445 ( .A1(n191), .A2(A[19]), .ZN(n58) ); 227 | NAND2_X1 U446 ( .A1(n185), .A2(A[25]), .ZN(n34) ); 228 | XOR2_X1 U447 ( .A(n180), .B(A[30]), .Z(n325) ); 229 | XOR2_X1 U448 ( .A(n28), .B(n325), .Z(DIFF[30]) ); 230 | NAND2_X1 U449 ( .A1(n28), .A2(n180), .ZN(n326) ); 231 | NAND2_X1 U450 ( .A1(n28), .A2(A[30]), .ZN(n327) ); 232 | NAND2_X1 U451 ( .A1(n180), .A2(A[30]), .ZN(n328) ); 233 | NAND3_X1 U452 ( .A1(n326), .A2(n328), .A3(n327), .ZN(n27) ); 234 | INV_X1 U453 ( .A(B[30]), .ZN(n180) ); 235 | XNOR2_X1 U454 ( .A(n40), .B(n2), .ZN(DIFF[24]) ); 236 | XNOR2_X1 U455 ( .A(n72), .B(n10), .ZN(DIFF[16]) ); 237 | XOR2_X1 U456 ( .A(n59), .B(n7), .Z(DIFF[19]) ); 238 | XOR2_X1 U457 ( .A(n67), .B(n9), .Z(DIFF[17]) ); 239 | XOR2_X1 U458 ( .A(n75), .B(n11), .Z(DIFF[15]) ); 240 | INV_X1 U459 ( .A(n113), .ZN(n111) ); 241 | NAND2_X1 U460 ( .A1(n199), .A2(A[11]), .ZN(n103) ); 242 | INV_X1 U461 ( .A(n26), .ZN(DIFF[32]) ); 243 | XNOR2_X1 U462 ( .A(n48), .B(n4), .ZN(DIFF[22]) ); 244 | XOR2_X1 U463 ( .A(n35), .B(n1), .Z(DIFF[25]) ); 245 | OAI21_X1 U464 ( .B1(n35), .B2(n33), .A(n34), .ZN(n32) ); 246 | INV_X1 U465 ( .A(B[11]), .ZN(n199) ); 247 | AOI21_X2 U251 ( .B1(n40), .B2(n324), .A(n37), .ZN(n35) ); 248 | AOI21_X2 U252 ( .B1(n64), .B2(n320), .A(n61), .ZN(n59) ); 249 | AOI21_X2 U250 ( .B1(n120), .B2(n76), .A(n77), .ZN(n75) ); 250 | INV_X1 U254 ( .A(n329), .ZN(n84) ); 251 | AOI21_X1 U255 ( .B1(n97), .B2(n87), .A(n88), .ZN(n329) ); 252 | endmodule 253 | 254 | 255 | module divider ( clk, rst, start, dividend, divisor, done, quotient, remainder 256 | ); 257 | input [31:0] dividend; 258 | input [31:0] divisor; 259 | output [31:0] quotient; 260 | output [31:0] remainder; 261 | input clk, rst, start; 262 | output done; 263 | wire state_reg_1_, N230, N231, N232, N233, N234, n3, n4, n6, n7, n8, n9, 264 | n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, 265 | n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n37, n38, 266 | n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, 267 | n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, 268 | n67, n68, n75, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, 269 | n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, 270 | n105, n106, n107, n108, n109, n110, n111, n112, n147, n178, n180, 271 | n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, 272 | n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203, 273 | n204, n205, n206, n207, n208, n209, n210, n218, n220, n221, n222, 274 | n223, n224, n225, n226, n227, n228, n229, n236, n237, n238, n239, 275 | n240, n241, n242, n243, n244, n245, n247, n248, n249, n250, n251, 276 | n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, 277 | n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, 278 | n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, 279 | n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, 280 | n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, 281 | n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, 282 | n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, 283 | n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, 284 | n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, 285 | n351, n352, n353, n358, n361, n362, n363, n364, n365, n374, n378, 286 | n381, n382, n384, n385, n386, n387, n388, n389, n390, n392, n393, 287 | n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, 288 | n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, 289 | n416, n417, n418, n419, n420, n421, n422, n423, n424, n426, n427, 290 | n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, 291 | n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, 292 | n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, 293 | n461, n462, n463, n464, n465, n466, n467, n468, n469, n470; 294 | wire [31:0] divisor_reg; 295 | wire [63:0] remainder_reg; 296 | wire [5:0] cnt_reg; 297 | wire [32:0] alu_result; 298 | wire [5:2] add_117_carry; 299 | 300 | DFF_X1 cnt_reg_reg_1_ ( .D(n431), .CK(clk), .Q(cnt_reg[1]) ); 301 | DFF_X1 cnt_reg_reg_2_ ( .D(n432), .CK(clk), .Q(cnt_reg[2]) ); 302 | DFF_X1 cnt_reg_reg_3_ ( .D(n433), .CK(clk), .Q(cnt_reg[3]) ); 303 | DFF_X1 cnt_reg_reg_4_ ( .D(n434), .CK(clk), .Q(cnt_reg[4]) ); 304 | DFF_X1 cnt_reg_reg_5_ ( .D(n435), .CK(clk), .Q(cnt_reg[5]) ); 305 | DFF_X1 remainder_reg_reg_1_ ( .D(n309), .CK(clk), .QN(n67) ); 306 | DFF_X1 remainder_reg_reg_2_ ( .D(n308), .CK(clk), .QN(n66) ); 307 | DFF_X1 remainder_reg_reg_3_ ( .D(n307), .CK(clk), .QN(n65) ); 308 | DFF_X1 remainder_reg_reg_4_ ( .D(n306), .CK(clk), .QN(n64) ); 309 | DFF_X1 remainder_reg_reg_5_ ( .D(n305), .CK(clk), .QN(n63) ); 310 | DFF_X1 remainder_reg_reg_6_ ( .D(n304), .CK(clk), .QN(n62) ); 311 | DFF_X1 remainder_reg_reg_7_ ( .D(n303), .CK(clk), .QN(n61) ); 312 | DFF_X1 remainder_reg_reg_8_ ( .D(n302), .CK(clk), .QN(n60) ); 313 | DFF_X1 remainder_reg_reg_9_ ( .D(n301), .CK(clk), .QN(n59) ); 314 | DFF_X1 remainder_reg_reg_10_ ( .D(n300), .CK(clk), .QN(n58) ); 315 | DFF_X1 remainder_reg_reg_11_ ( .D(n299), .CK(clk), .QN(n57) ); 316 | DFF_X1 remainder_reg_reg_12_ ( .D(n298), .CK(clk), .QN(n56) ); 317 | DFF_X1 remainder_reg_reg_13_ ( .D(n297), .CK(clk), .QN(n55) ); 318 | DFF_X1 remainder_reg_reg_14_ ( .D(n296), .CK(clk), .QN(n54) ); 319 | DFF_X1 remainder_reg_reg_15_ ( .D(n295), .CK(clk), .QN(n53) ); 320 | DFF_X1 remainder_reg_reg_16_ ( .D(n294), .CK(clk), .QN(n52) ); 321 | DFF_X1 remainder_reg_reg_17_ ( .D(n293), .CK(clk), .QN(n51) ); 322 | DFF_X1 remainder_reg_reg_18_ ( .D(n292), .CK(clk), .QN(n50) ); 323 | DFF_X1 remainder_reg_reg_19_ ( .D(n291), .CK(clk), .QN(n49) ); 324 | DFF_X1 remainder_reg_reg_20_ ( .D(n290), .CK(clk), .QN(n48) ); 325 | DFF_X1 remainder_reg_reg_21_ ( .D(n289), .CK(clk), .QN(n47) ); 326 | DFF_X1 remainder_reg_reg_22_ ( .D(n288), .CK(clk), .QN(n46) ); 327 | DFF_X1 remainder_reg_reg_23_ ( .D(n287), .CK(clk), .QN(n45) ); 328 | DFF_X1 remainder_reg_reg_24_ ( .D(n286), .CK(clk), .QN(n44) ); 329 | DFF_X1 remainder_reg_reg_25_ ( .D(n285), .CK(clk), .QN(n43) ); 330 | DFF_X1 remainder_reg_reg_26_ ( .D(n284), .CK(clk), .QN(n42) ); 331 | DFF_X1 remainder_reg_reg_27_ ( .D(n283), .CK(clk), .QN(n41) ); 332 | DFF_X1 remainder_reg_reg_28_ ( .D(n282), .CK(clk), .QN(n40) ); 333 | DFF_X1 remainder_reg_reg_29_ ( .D(n281), .CK(clk), .QN(n39) ); 334 | DFF_X1 remainder_reg_reg_30_ ( .D(n280), .CK(clk), .QN(n38) ); 335 | DFF_X1 remainder_reg_reg_31_ ( .D(n279), .CK(clk), .Q(remainder_reg[31]), 336 | .QN(n37) ); 337 | DFF_X1 remainder_reg_reg_32_ ( .D(n436), .CK(clk), .Q(remainder_reg[32]) ); 338 | DFF_X1 remainder_reg_reg_39_ ( .D(n272), .CK(clk), .Q(remainder_reg[39]), 339 | .QN(n29) ); 340 | DFF_X1 remainder_reg_reg_40_ ( .D(n271), .CK(clk), .Q(remainder_reg[40]), 341 | .QN(n28) ); 342 | DFF_X1 remainder_reg_reg_64_ ( .D(n247), .CK(clk), .QN(n3) ); 343 | NAND3_X1 U299 ( .A1(n387), .A2(n385), .A3(start), .ZN(n220) ); 344 | NAND3_X1 U300 ( .A1(n346), .A2(n349), .A3(start), .ZN(n226) ); 345 | NAND4_X1 U301 ( .A1(n345), .A2(n75), .A3(cnt_reg[5]), .A4(n229), .ZN(n228) 346 | ); 347 | NAND4_X1 U303 ( .A1(n445), .A2(n444), .A3(n443), .A4(n442), .ZN(n241) ); 348 | NAND4_X1 U304 ( .A1(n441), .A2(n440), .A3(n467), .A4(n439), .ZN(n240) ); 349 | NAND4_X1 U305 ( .A1(n438), .A2(n466), .A3(n465), .A4(n464), .ZN(n239) ); 350 | NAND4_X1 U306 ( .A1(n463), .A2(n462), .A3(n461), .A4(n460), .ZN(n238) ); 351 | NAND4_X1 U307 ( .A1(n469), .A2(n459), .A3(n458), .A4(n457), .ZN(n245) ); 352 | NAND4_X1 U308 ( .A1(n456), .A2(n455), .A3(n454), .A4(n453), .ZN(n244) ); 353 | NAND4_X1 U309 ( .A1(n452), .A2(n451), .A3(n450), .A4(n468), .ZN(n243) ); 354 | NAND4_X1 U310 ( .A1(n449), .A2(n448), .A3(n447), .A4(n446), .ZN(n242) ); 355 | HA_X1 add_117_U1_1_1 ( .A(cnt_reg[1]), .B(cnt_reg[0]), .CO(add_117_carry[2]), 356 | .S(N230) ); 357 | HA_X1 add_117_U1_1_2 ( .A(cnt_reg[2]), .B(add_117_carry[2]), .CO( 358 | add_117_carry[3]), .S(N231) ); 359 | HA_X1 add_117_U1_1_3 ( .A(cnt_reg[3]), .B(add_117_carry[3]), .CO( 360 | add_117_carry[4]), .S(N232) ); 361 | HA_X1 add_117_U1_1_4 ( .A(cnt_reg[4]), .B(add_117_carry[4]), .CO( 362 | add_117_carry[5]), .S(N233) ); 363 | divider_DW01_sub_1 sub_80 ( .A({1'b0, remainder_reg[63:32]}), .B({1'b0, 364 | divisor_reg}), .CI(1'b0), .DIFF(alu_result) ); 365 | DFF_X1 state_reg_reg_0_ ( .D(n344), .CK(clk), .Q(done), .QN(n387) ); 366 | DFF_X1 state_reg_reg_1_ ( .D(n343), .CK(clk), .Q(state_reg_1_), .QN(n385) ); 367 | DFF_X1 divisor_reg_reg_7_ ( .D(n334), .CK(clk), .Q(divisor_reg[7]), .QN(n105) ); 368 | DFF_X1 divisor_reg_reg_6_ ( .D(n335), .CK(clk), .Q(divisor_reg[6]), .QN(n106) ); 369 | DFF_X1 divisor_reg_reg_5_ ( .D(n336), .CK(clk), .Q(divisor_reg[5]), .QN(n107) ); 370 | DFF_X1 divisor_reg_reg_4_ ( .D(n337), .CK(clk), .Q(divisor_reg[4]), .QN(n108) ); 371 | DFF_X1 divisor_reg_reg_3_ ( .D(n338), .CK(clk), .Q(divisor_reg[3]), .QN(n109) ); 372 | DFF_X1 divisor_reg_reg_2_ ( .D(n339), .CK(clk), .Q(divisor_reg[2]), .QN(n110) ); 373 | DFF_X1 divisor_reg_reg_1_ ( .D(n340), .CK(clk), .Q(divisor_reg[1]), .QN(n111) ); 374 | DFF_X1 divisor_reg_reg_0_ ( .D(n341), .CK(clk), .Q(divisor_reg[0]), .QN(n112) ); 375 | DFF_X1 divisor_reg_reg_31_ ( .D(n310), .CK(clk), .Q(divisor_reg[31]), .QN( 376 | n81) ); 377 | DFF_X1 divisor_reg_reg_30_ ( .D(n311), .CK(clk), .Q(divisor_reg[30]), .QN( 378 | n82) ); 379 | DFF_X1 divisor_reg_reg_29_ ( .D(n312), .CK(clk), .Q(divisor_reg[29]), .QN( 380 | n83) ); 381 | DFF_X1 divisor_reg_reg_28_ ( .D(n313), .CK(clk), .Q(divisor_reg[28]), .QN( 382 | n84) ); 383 | DFF_X1 divisor_reg_reg_27_ ( .D(n314), .CK(clk), .Q(divisor_reg[27]), .QN( 384 | n85) ); 385 | DFF_X1 divisor_reg_reg_26_ ( .D(n315), .CK(clk), .Q(divisor_reg[26]), .QN( 386 | n86) ); 387 | DFF_X1 divisor_reg_reg_25_ ( .D(n316), .CK(clk), .Q(divisor_reg[25]), .QN( 388 | n87) ); 389 | DFF_X1 divisor_reg_reg_24_ ( .D(n317), .CK(clk), .Q(divisor_reg[24]), .QN( 390 | n88) ); 391 | DFF_X1 divisor_reg_reg_23_ ( .D(n318), .CK(clk), .Q(divisor_reg[23]), .QN( 392 | n89) ); 393 | DFF_X1 divisor_reg_reg_22_ ( .D(n319), .CK(clk), .Q(divisor_reg[22]), .QN( 394 | n90) ); 395 | DFF_X1 divisor_reg_reg_21_ ( .D(n320), .CK(clk), .Q(divisor_reg[21]), .QN( 396 | n91) ); 397 | DFF_X1 divisor_reg_reg_20_ ( .D(n321), .CK(clk), .Q(divisor_reg[20]), .QN( 398 | n92) ); 399 | DFF_X1 divisor_reg_reg_19_ ( .D(n322), .CK(clk), .Q(divisor_reg[19]), .QN( 400 | n93) ); 401 | DFF_X1 divisor_reg_reg_18_ ( .D(n323), .CK(clk), .Q(divisor_reg[18]), .QN( 402 | n94) ); 403 | DFF_X1 divisor_reg_reg_17_ ( .D(n324), .CK(clk), .Q(divisor_reg[17]), .QN( 404 | n95) ); 405 | DFF_X1 divisor_reg_reg_16_ ( .D(n325), .CK(clk), .Q(divisor_reg[16]), .QN( 406 | n96) ); 407 | DFF_X1 divisor_reg_reg_15_ ( .D(n326), .CK(clk), .Q(divisor_reg[15]), .QN( 408 | n97) ); 409 | DFF_X1 divisor_reg_reg_14_ ( .D(n327), .CK(clk), .Q(divisor_reg[14]), .QN( 410 | n98) ); 411 | DFF_X1 divisor_reg_reg_13_ ( .D(n328), .CK(clk), .Q(divisor_reg[13]), .QN( 412 | n99) ); 413 | DFF_X1 divisor_reg_reg_12_ ( .D(n329), .CK(clk), .Q(divisor_reg[12]), .QN( 414 | n100) ); 415 | DFF_X1 divisor_reg_reg_11_ ( .D(n330), .CK(clk), .Q(divisor_reg[11]), .QN( 416 | n101) ); 417 | DFF_X1 divisor_reg_reg_10_ ( .D(n331), .CK(clk), .Q(divisor_reg[10]), .QN( 418 | n102) ); 419 | DFF_X1 divisor_reg_reg_9_ ( .D(n332), .CK(clk), .Q(divisor_reg[9]), .QN(n103) ); 420 | DFF_X1 divisor_reg_reg_8_ ( .D(n333), .CK(clk), .Q(divisor_reg[8]), .QN(n104) ); 421 | DFF_X1 remainder_reg_reg_38_ ( .D(n273), .CK(clk), .Q(remainder_reg[38]), 422 | .QN(n30) ); 423 | DFF_X1 remainder_reg_reg_37_ ( .D(n274), .CK(clk), .Q(remainder_reg[37]), 424 | .QN(n31) ); 425 | DFF_X1 remainder_reg_reg_36_ ( .D(n275), .CK(clk), .Q(remainder_reg[36]), 426 | .QN(n32) ); 427 | DFF_X1 remainder_reg_reg_35_ ( .D(n276), .CK(clk), .Q(remainder_reg[35]), 428 | .QN(n33) ); 429 | DFF_X1 remainder_reg_reg_34_ ( .D(n277), .CK(clk), .Q(remainder_reg[34]), 430 | .QN(n34) ); 431 | DFF_X1 remainder_reg_reg_0_ ( .D(n429), .CK(clk), .Q(remainder_reg[0]), .QN( 432 | n68) ); 433 | DFF_X1 cnt_reg_reg_0_ ( .D(n342), .CK(clk), .Q(cnt_reg[0]), .QN(n75) ); 434 | DFF_X1 remainder_reg_reg_63_ ( .D(n248), .CK(clk), .Q(remainder_reg[63]), 435 | .QN(n4) ); 436 | DFF_X1 remainder_reg_reg_62_ ( .D(n249), .CK(clk), .Q(remainder_reg[62]), 437 | .QN(n6) ); 438 | DFF_X1 remainder_reg_reg_61_ ( .D(n250), .CK(clk), .Q(remainder_reg[61]), 439 | .QN(n7) ); 440 | DFF_X1 remainder_reg_reg_60_ ( .D(n251), .CK(clk), .Q(remainder_reg[60]), 441 | .QN(n8) ); 442 | DFF_X1 remainder_reg_reg_59_ ( .D(n252), .CK(clk), .Q(remainder_reg[59]), 443 | .QN(n9) ); 444 | DFF_X1 remainder_reg_reg_48_ ( .D(n263), .CK(clk), .Q(remainder_reg[48]), 445 | .QN(n20) ); 446 | DFF_X1 remainder_reg_reg_33_ ( .D(n278), .CK(clk), .Q(remainder_reg[33]), 447 | .QN(n35) ); 448 | DFF_X1 remainder_reg_reg_58_ ( .D(n253), .CK(clk), .Q(remainder_reg[58]), 449 | .QN(n10) ); 450 | DFF_X1 remainder_reg_reg_57_ ( .D(n254), .CK(clk), .Q(remainder_reg[57]), 451 | .QN(n11) ); 452 | DFF_X1 remainder_reg_reg_56_ ( .D(n255), .CK(clk), .Q(remainder_reg[56]), 453 | .QN(n12) ); 454 | DFF_X1 remainder_reg_reg_55_ ( .D(n256), .CK(clk), .Q(remainder_reg[55]), 455 | .QN(n13) ); 456 | DFF_X1 remainder_reg_reg_54_ ( .D(n257), .CK(clk), .Q(remainder_reg[54]), 457 | .QN(n14) ); 458 | DFF_X1 remainder_reg_reg_53_ ( .D(n258), .CK(clk), .Q(remainder_reg[53]), 459 | .QN(n15) ); 460 | DFF_X1 remainder_reg_reg_52_ ( .D(n259), .CK(clk), .Q(remainder_reg[52]), 461 | .QN(n16) ); 462 | DFF_X1 remainder_reg_reg_51_ ( .D(n260), .CK(clk), .Q(remainder_reg[51]), 463 | .QN(n17) ); 464 | DFF_X1 remainder_reg_reg_50_ ( .D(n261), .CK(clk), .Q(remainder_reg[50]), 465 | .QN(n18) ); 466 | DFF_X1 remainder_reg_reg_49_ ( .D(n262), .CK(clk), .Q(remainder_reg[49]), 467 | .QN(n19) ); 468 | DFF_X1 remainder_reg_reg_47_ ( .D(n264), .CK(clk), .Q(remainder_reg[47]), 469 | .QN(n21) ); 470 | DFF_X1 remainder_reg_reg_46_ ( .D(n265), .CK(clk), .Q(remainder_reg[46]), 471 | .QN(n22) ); 472 | DFF_X1 remainder_reg_reg_45_ ( .D(n266), .CK(clk), .Q(remainder_reg[45]), 473 | .QN(n23) ); 474 | DFF_X1 remainder_reg_reg_44_ ( .D(n267), .CK(clk), .Q(remainder_reg[44]), 475 | .QN(n24) ); 476 | DFF_X1 remainder_reg_reg_43_ ( .D(n268), .CK(clk), .Q(remainder_reg[43]), 477 | .QN(n25) ); 478 | DFF_X1 remainder_reg_reg_42_ ( .D(n269), .CK(clk), .Q(remainder_reg[42]), 479 | .QN(n26) ); 480 | DFF_X1 remainder_reg_reg_41_ ( .D(n270), .CK(clk), .Q(remainder_reg[41]), 481 | .QN(n27) ); 482 | AND2_X1 U312 ( .A1(n428), .A2(n384), .ZN(n346) ); 483 | AND2_X1 U315 ( .A1(n387), .A2(n385), .ZN(n349) ); 484 | AND2_X1 U318 ( .A1(remainder_reg[0]), .A2(n178), .ZN(n350) ); 485 | AND2_X1 U319 ( .A1(dividend[0]), .A2(n347), .ZN(n351) ); 486 | CLKBUF_X1 U321 ( .A(n430), .Z(n374) ); 487 | CLKBUF_X1 U326 ( .A(n352), .Z(n365) ); 488 | CLKBUF_X1 U327 ( .A(n352), .Z(n364) ); 489 | CLKBUF_X1 U328 ( .A(n353), .Z(n362) ); 490 | CLKBUF_X1 U329 ( .A(n353), .Z(n361) ); 491 | CLKBUF_X1 U330 ( .A(n353), .Z(n363) ); 492 | INV_X1 U334 ( .A(n345), .ZN(n378) ); 493 | AND2_X1 U335 ( .A1(alu_result[32]), .A2(n345), .ZN(n353) ); 494 | CLKBUF_X1 U342 ( .A(n424), .Z(n358) ); 495 | NOR4_X1 U346 ( .A1(n242), .A2(n243), .A3(n244), .A4(n245), .ZN(n236) ); 496 | NOR4_X1 U347 ( .A1(n238), .A2(n239), .A3(n240), .A4(n241), .ZN(n237) ); 497 | CLKBUF_X1 U348 ( .A(n147), .Z(n381) ); 498 | CLKBUF_X1 U351 ( .A(n147), .Z(n382) ); 499 | NAND2_X1 U353 ( .A1(dividend[31]), .A2(n347), .ZN(n180) ); 500 | OAI221_X1 U354 ( .B1(n39), .B2(n378), .C1(n374), .C2(n38), .A(n182), .ZN( 501 | n280) ); 502 | NAND2_X1 U355 ( .A1(dividend[30]), .A2(n347), .ZN(n182) ); 503 | OAI221_X1 U356 ( .B1(n40), .B2(n470), .C1(n374), .C2(n39), .A(n183), .ZN( 504 | n281) ); 505 | NAND2_X1 U357 ( .A1(dividend[29]), .A2(n347), .ZN(n183) ); 506 | OAI221_X1 U358 ( .B1(n41), .B2(n470), .C1(n374), .C2(n40), .A(n184), .ZN( 507 | n282) ); 508 | NAND2_X1 U359 ( .A1(dividend[28]), .A2(n347), .ZN(n184) ); 509 | OAI221_X1 U360 ( .B1(n42), .B2(n470), .C1(n374), .C2(n41), .A(n185), .ZN( 510 | n283) ); 511 | NAND2_X1 U361 ( .A1(dividend[27]), .A2(n347), .ZN(n185) ); 512 | OAI221_X1 U362 ( .B1(n43), .B2(n470), .C1(n374), .C2(n42), .A(n186), .ZN( 513 | n284) ); 514 | NAND2_X1 U363 ( .A1(dividend[26]), .A2(n347), .ZN(n186) ); 515 | OAI221_X1 U364 ( .B1(n44), .B2(n470), .C1(n430), .C2(n43), .A(n187), .ZN( 516 | n285) ); 517 | NAND2_X1 U365 ( .A1(dividend[25]), .A2(n347), .ZN(n187) ); 518 | OAI221_X1 U366 ( .B1(n45), .B2(n470), .C1(n374), .C2(n44), .A(n188), .ZN( 519 | n286) ); 520 | NAND2_X1 U367 ( .A1(dividend[24]), .A2(n347), .ZN(n188) ); 521 | OAI221_X1 U368 ( .B1(n46), .B2(n470), .C1(n430), .C2(n45), .A(n189), .ZN( 522 | n287) ); 523 | NAND2_X1 U369 ( .A1(dividend[23]), .A2(n347), .ZN(n189) ); 524 | OAI221_X1 U370 ( .B1(n47), .B2(n470), .C1(n430), .C2(n46), .A(n190), .ZN( 525 | n288) ); 526 | NAND2_X1 U371 ( .A1(dividend[22]), .A2(n347), .ZN(n190) ); 527 | OAI221_X1 U372 ( .B1(n48), .B2(n470), .C1(n430), .C2(n47), .A(n191), .ZN( 528 | n289) ); 529 | NAND2_X1 U373 ( .A1(dividend[21]), .A2(n347), .ZN(n191) ); 530 | OAI221_X1 U374 ( .B1(n49), .B2(n470), .C1(n430), .C2(n48), .A(n192), .ZN( 531 | n290) ); 532 | NAND2_X1 U375 ( .A1(dividend[20]), .A2(n347), .ZN(n192) ); 533 | OAI221_X1 U376 ( .B1(n50), .B2(n470), .C1(n430), .C2(n49), .A(n193), .ZN( 534 | n291) ); 535 | NAND2_X1 U377 ( .A1(dividend[19]), .A2(n347), .ZN(n193) ); 536 | OAI221_X1 U378 ( .B1(n51), .B2(n470), .C1(n430), .C2(n50), .A(n194), .ZN( 537 | n292) ); 538 | NAND2_X1 U379 ( .A1(dividend[18]), .A2(n347), .ZN(n194) ); 539 | OAI221_X1 U380 ( .B1(n52), .B2(n378), .C1(n430), .C2(n51), .A(n195), .ZN( 540 | n293) ); 541 | NAND2_X1 U381 ( .A1(dividend[17]), .A2(n347), .ZN(n195) ); 542 | OAI221_X1 U382 ( .B1(n53), .B2(n378), .C1(n430), .C2(n52), .A(n196), .ZN( 543 | n294) ); 544 | NAND2_X1 U383 ( .A1(dividend[16]), .A2(n347), .ZN(n196) ); 545 | OAI221_X1 U384 ( .B1(n54), .B2(n378), .C1(n430), .C2(n53), .A(n197), .ZN( 546 | n295) ); 547 | NAND2_X1 U385 ( .A1(dividend[15]), .A2(n347), .ZN(n197) ); 548 | OAI221_X1 U386 ( .B1(n55), .B2(n378), .C1(n430), .C2(n54), .A(n198), .ZN( 549 | n296) ); 550 | NAND2_X1 U387 ( .A1(dividend[14]), .A2(n347), .ZN(n198) ); 551 | OAI221_X1 U388 ( .B1(n56), .B2(n378), .C1(n430), .C2(n55), .A(n199), .ZN( 552 | n297) ); 553 | NAND2_X1 U389 ( .A1(dividend[13]), .A2(n347), .ZN(n199) ); 554 | OAI221_X1 U390 ( .B1(n57), .B2(n378), .C1(n430), .C2(n56), .A(n200), .ZN( 555 | n298) ); 556 | NAND2_X1 U391 ( .A1(dividend[12]), .A2(n347), .ZN(n200) ); 557 | OAI221_X1 U392 ( .B1(n58), .B2(n378), .C1(n430), .C2(n57), .A(n201), .ZN( 558 | n299) ); 559 | NAND2_X1 U393 ( .A1(dividend[11]), .A2(n347), .ZN(n201) ); 560 | OAI221_X1 U394 ( .B1(n59), .B2(n378), .C1(n430), .C2(n58), .A(n202), .ZN( 561 | n300) ); 562 | NAND2_X1 U395 ( .A1(dividend[10]), .A2(n347), .ZN(n202) ); 563 | OAI221_X1 U396 ( .B1(n60), .B2(n378), .C1(n430), .C2(n59), .A(n203), .ZN( 564 | n301) ); 565 | NAND2_X1 U397 ( .A1(dividend[9]), .A2(n347), .ZN(n203) ); 566 | OAI221_X1 U398 ( .B1(n61), .B2(n378), .C1(n430), .C2(n60), .A(n204), .ZN( 567 | n302) ); 568 | NAND2_X1 U399 ( .A1(dividend[8]), .A2(n347), .ZN(n204) ); 569 | OAI221_X1 U400 ( .B1(n62), .B2(n378), .C1(n430), .C2(n61), .A(n205), .ZN( 570 | n303) ); 571 | NAND2_X1 U401 ( .A1(dividend[7]), .A2(n347), .ZN(n205) ); 572 | OAI221_X1 U402 ( .B1(n63), .B2(n378), .C1(n430), .C2(n62), .A(n206), .ZN( 573 | n304) ); 574 | NAND2_X1 U403 ( .A1(dividend[6]), .A2(n347), .ZN(n206) ); 575 | OAI221_X1 U404 ( .B1(n64), .B2(n378), .C1(n430), .C2(n63), .A(n207), .ZN( 576 | n305) ); 577 | NAND2_X1 U405 ( .A1(dividend[5]), .A2(n347), .ZN(n207) ); 578 | OAI221_X1 U406 ( .B1(n65), .B2(n378), .C1(n430), .C2(n64), .A(n208), .ZN( 579 | n306) ); 580 | NAND2_X1 U407 ( .A1(dividend[4]), .A2(n347), .ZN(n208) ); 581 | OAI221_X1 U408 ( .B1(n66), .B2(n470), .C1(n430), .C2(n65), .A(n209), .ZN( 582 | n307) ); 583 | NAND2_X1 U409 ( .A1(dividend[3]), .A2(n347), .ZN(n209) ); 584 | OAI221_X1 U410 ( .B1(n67), .B2(n470), .C1(n430), .C2(n66), .A(n210), .ZN( 585 | n308) ); 586 | NAND2_X1 U411 ( .A1(dividend[2]), .A2(n347), .ZN(n210) ); 587 | INV_X1 U412 ( .A(n221), .ZN(n435) ); 588 | AOI22_X1 U413 ( .A1(n178), .A2(cnt_reg[5]), .B1(n345), .B2(N234), .ZN(n221) 589 | ); 590 | INV_X1 U414 ( .A(n222), .ZN(n434) ); 591 | AOI22_X1 U415 ( .A1(n178), .A2(cnt_reg[4]), .B1(n345), .B2(N233), .ZN(n222) 592 | ); 593 | INV_X1 U416 ( .A(n223), .ZN(n433) ); 594 | AOI22_X1 U417 ( .A1(n178), .A2(cnt_reg[3]), .B1(n345), .B2(N232), .ZN(n223) 595 | ); 596 | INV_X1 U418 ( .A(n224), .ZN(n432) ); 597 | AOI22_X1 U419 ( .A1(n178), .A2(cnt_reg[2]), .B1(n345), .B2(N231), .ZN(n224) 598 | ); 599 | INV_X1 U420 ( .A(n225), .ZN(n431) ); 600 | AOI22_X1 U421 ( .A1(n178), .A2(cnt_reg[1]), .B1(n345), .B2(N230), .ZN(n225) 601 | ); 602 | OAI22_X1 U422 ( .A1(n430), .A2(n75), .B1(n378), .B2(cnt_reg[0]), .ZN(n342) 603 | ); 604 | OAI21_X1 U423 ( .B1(n437), .B2(n227), .A(n228), .ZN(n344) ); 605 | INV_X1 U424 ( .A(start), .ZN(n437) ); 606 | NOR4_X1 U425 ( .A1(cnt_reg[4]), .A2(cnt_reg[3]), .A3(cnt_reg[2]), .A4( 607 | cnt_reg[1]), .ZN(n229) ); 608 | NAND2_X1 U426 ( .A1(n226), .A2(n470), .ZN(n343) ); 609 | NOR2_X1 U428 ( .A1(n147), .A2(n66), .ZN(quotient[2]) ); 610 | NOR2_X1 U429 ( .A1(n147), .A2(n65), .ZN(quotient[3]) ); 611 | NOR2_X1 U430 ( .A1(n147), .A2(n64), .ZN(quotient[4]) ); 612 | NOR2_X1 U431 ( .A1(n147), .A2(n63), .ZN(quotient[5]) ); 613 | NOR2_X1 U432 ( .A1(n147), .A2(n62), .ZN(quotient[6]) ); 614 | NOR2_X1 U433 ( .A1(n147), .A2(n61), .ZN(quotient[7]) ); 615 | NOR2_X1 U434 ( .A1(n147), .A2(n60), .ZN(quotient[8]) ); 616 | NOR2_X1 U435 ( .A1(n147), .A2(n59), .ZN(quotient[9]) ); 617 | NOR2_X1 U436 ( .A1(n381), .A2(n58), .ZN(quotient[10]) ); 618 | NOR2_X1 U437 ( .A1(n381), .A2(n57), .ZN(quotient[11]) ); 619 | NOR2_X1 U438 ( .A1(n381), .A2(n56), .ZN(quotient[12]) ); 620 | NOR2_X1 U439 ( .A1(n381), .A2(n55), .ZN(quotient[13]) ); 621 | NOR2_X1 U440 ( .A1(n381), .A2(n54), .ZN(quotient[14]) ); 622 | NOR2_X1 U441 ( .A1(n381), .A2(n53), .ZN(quotient[15]) ); 623 | NOR2_X1 U442 ( .A1(n147), .A2(n52), .ZN(quotient[16]) ); 624 | NOR2_X1 U443 ( .A1(n381), .A2(n51), .ZN(quotient[17]) ); 625 | NOR2_X1 U444 ( .A1(n147), .A2(n50), .ZN(quotient[18]) ); 626 | NOR2_X1 U445 ( .A1(n147), .A2(n49), .ZN(quotient[19]) ); 627 | NOR2_X1 U446 ( .A1(n147), .A2(n48), .ZN(quotient[20]) ); 628 | NOR2_X1 U447 ( .A1(n147), .A2(n47), .ZN(quotient[21]) ); 629 | NOR2_X1 U448 ( .A1(n147), .A2(n46), .ZN(quotient[22]) ); 630 | NOR2_X1 U449 ( .A1(n147), .A2(n45), .ZN(quotient[23]) ); 631 | NOR2_X1 U450 ( .A1(n147), .A2(n44), .ZN(quotient[24]) ); 632 | NOR2_X1 U451 ( .A1(n147), .A2(n43), .ZN(quotient[25]) ); 633 | NOR2_X1 U452 ( .A1(n147), .A2(n42), .ZN(quotient[26]) ); 634 | NOR2_X1 U453 ( .A1(n147), .A2(n41), .ZN(quotient[27]) ); 635 | NOR2_X1 U454 ( .A1(n147), .A2(n40), .ZN(quotient[28]) ); 636 | NOR2_X1 U455 ( .A1(n147), .A2(n39), .ZN(quotient[29]) ); 637 | NOR2_X1 U456 ( .A1(n147), .A2(n38), .ZN(quotient[30]) ); 638 | NOR2_X1 U457 ( .A1(n147), .A2(n67), .ZN(quotient[1]) ); 639 | NAND2_X1 U459 ( .A1(n428), .A2(n220), .ZN(n218) ); 640 | INV_X1 U461 ( .A(divisor[20]), .ZN(n449) ); 641 | INV_X1 U462 ( .A(divisor[21]), .ZN(n448) ); 642 | INV_X1 U463 ( .A(divisor[22]), .ZN(n447) ); 643 | INV_X1 U464 ( .A(divisor[23]), .ZN(n446) ); 644 | INV_X1 U465 ( .A(divisor[17]), .ZN(n452) ); 645 | INV_X1 U466 ( .A(divisor[18]), .ZN(n451) ); 646 | INV_X1 U467 ( .A(divisor[19]), .ZN(n450) ); 647 | INV_X1 U468 ( .A(divisor[1]), .ZN(n468) ); 648 | INV_X1 U469 ( .A(divisor[13]), .ZN(n456) ); 649 | INV_X1 U470 ( .A(divisor[14]), .ZN(n455) ); 650 | INV_X1 U471 ( .A(divisor[15]), .ZN(n454) ); 651 | INV_X1 U472 ( .A(divisor[16]), .ZN(n453) ); 652 | INV_X1 U473 ( .A(divisor[0]), .ZN(n469) ); 653 | INV_X1 U474 ( .A(divisor[10]), .ZN(n459) ); 654 | INV_X1 U475 ( .A(divisor[11]), .ZN(n458) ); 655 | INV_X1 U476 ( .A(divisor[12]), .ZN(n457) ); 656 | INV_X1 U477 ( .A(divisor[6]), .ZN(n463) ); 657 | INV_X1 U478 ( .A(divisor[7]), .ZN(n462) ); 658 | INV_X1 U479 ( .A(divisor[8]), .ZN(n461) ); 659 | INV_X1 U480 ( .A(divisor[9]), .ZN(n460) ); 660 | INV_X1 U481 ( .A(divisor[31]), .ZN(n438) ); 661 | INV_X1 U482 ( .A(divisor[3]), .ZN(n466) ); 662 | INV_X1 U483 ( .A(divisor[4]), .ZN(n465) ); 663 | INV_X1 U484 ( .A(divisor[5]), .ZN(n464) ); 664 | INV_X1 U485 ( .A(divisor[28]), .ZN(n441) ); 665 | INV_X1 U486 ( .A(divisor[29]), .ZN(n440) ); 666 | INV_X1 U487 ( .A(divisor[2]), .ZN(n467) ); 667 | INV_X1 U488 ( .A(divisor[30]), .ZN(n439) ); 668 | INV_X1 U489 ( .A(divisor[24]), .ZN(n445) ); 669 | INV_X1 U490 ( .A(divisor[25]), .ZN(n444) ); 670 | INV_X1 U491 ( .A(divisor[26]), .ZN(n443) ); 671 | INV_X1 U492 ( .A(divisor[27]), .ZN(n442) ); 672 | INV_X1 U493 ( .A(rst), .ZN(n428) ); 673 | NAND2_X1 U497 ( .A1(n349), .A2(n386), .ZN(n227) ); 674 | AOI21_X1 U498 ( .B1(state_reg_1_), .B2(n387), .A(start), .ZN(n388) ); 675 | OAI21_X1 U499 ( .B1(n388), .B2(done), .A(n428), .ZN(n389) ); 676 | OAI221_X1 U502 ( .B1(n37), .B2(n374), .C1(n38), .C2(n378), .A(n180), .ZN( 677 | n279) ); 678 | AOI22_X1 U503 ( .A1(remainder_reg[31]), .A2(n345), .B1(remainder_reg[32]), 679 | .B2(n178), .ZN(n390) ); 680 | INV_X1 U504 ( .A(n390), .ZN(n436) ); 681 | AOI22_X1 U506 ( .A1(alu_result[0]), .A2(n364), .B1(remainder_reg[32]), .B2( 682 | n361), .ZN(n392) ); 683 | OAI21_X1 U507 ( .B1(n35), .B2(n374), .A(n392), .ZN(n278) ); 684 | AOI22_X1 U508 ( .A1(alu_result[1]), .A2(n352), .B1(remainder_reg[33]), .B2( 685 | n361), .ZN(n393) ); 686 | OAI21_X1 U509 ( .B1(n34), .B2(n430), .A(n393), .ZN(n277) ); 687 | AOI22_X1 U510 ( .A1(alu_result[2]), .A2(n352), .B1(remainder_reg[34]), .B2( 688 | n361), .ZN(n394) ); 689 | OAI21_X1 U511 ( .B1(n33), .B2(n430), .A(n394), .ZN(n276) ); 690 | AOI22_X1 U512 ( .A1(alu_result[3]), .A2(n352), .B1(remainder_reg[35]), .B2( 691 | n361), .ZN(n395) ); 692 | OAI21_X1 U513 ( .B1(n32), .B2(n430), .A(n395), .ZN(n275) ); 693 | AOI22_X1 U514 ( .A1(alu_result[4]), .A2(n352), .B1(remainder_reg[36]), .B2( 694 | n361), .ZN(n396) ); 695 | OAI21_X1 U515 ( .B1(n31), .B2(n430), .A(n396), .ZN(n274) ); 696 | AOI22_X1 U516 ( .A1(alu_result[5]), .A2(n352), .B1(remainder_reg[37]), .B2( 697 | n361), .ZN(n397) ); 698 | OAI21_X1 U517 ( .B1(n30), .B2(n430), .A(n397), .ZN(n273) ); 699 | AOI22_X1 U518 ( .A1(alu_result[6]), .A2(n352), .B1(remainder_reg[38]), .B2( 700 | n361), .ZN(n398) ); 701 | OAI21_X1 U519 ( .B1(n29), .B2(n430), .A(n398), .ZN(n272) ); 702 | AOI22_X1 U520 ( .A1(alu_result[7]), .A2(n352), .B1(remainder_reg[39]), .B2( 703 | n361), .ZN(n399) ); 704 | OAI21_X1 U521 ( .B1(n28), .B2(n430), .A(n399), .ZN(n271) ); 705 | AOI22_X1 U522 ( .A1(alu_result[8]), .A2(n352), .B1(remainder_reg[40]), .B2( 706 | n361), .ZN(n400) ); 707 | OAI21_X1 U523 ( .B1(n27), .B2(n430), .A(n400), .ZN(n270) ); 708 | AOI22_X1 U524 ( .A1(alu_result[9]), .A2(n365), .B1(remainder_reg[41]), .B2( 709 | n361), .ZN(n401) ); 710 | OAI21_X1 U525 ( .B1(n26), .B2(n430), .A(n401), .ZN(n269) ); 711 | AOI22_X1 U526 ( .A1(alu_result[10]), .A2(n365), .B1(remainder_reg[42]), .B2( 712 | n361), .ZN(n402) ); 713 | OAI21_X1 U527 ( .B1(n25), .B2(n430), .A(n402), .ZN(n268) ); 714 | AOI22_X1 U528 ( .A1(alu_result[11]), .A2(n365), .B1(remainder_reg[43]), .B2( 715 | n361), .ZN(n403) ); 716 | OAI21_X1 U529 ( .B1(n24), .B2(n430), .A(n403), .ZN(n267) ); 717 | AOI22_X1 U530 ( .A1(alu_result[12]), .A2(n365), .B1(remainder_reg[44]), .B2( 718 | n362), .ZN(n404) ); 719 | OAI21_X1 U531 ( .B1(n23), .B2(n430), .A(n404), .ZN(n266) ); 720 | AOI22_X1 U532 ( .A1(alu_result[13]), .A2(n365), .B1(remainder_reg[45]), .B2( 721 | n362), .ZN(n405) ); 722 | OAI21_X1 U533 ( .B1(n22), .B2(n430), .A(n405), .ZN(n265) ); 723 | AOI22_X1 U534 ( .A1(alu_result[14]), .A2(n365), .B1(remainder_reg[46]), .B2( 724 | n362), .ZN(n406) ); 725 | OAI21_X1 U535 ( .B1(n21), .B2(n430), .A(n406), .ZN(n264) ); 726 | AOI22_X1 U536 ( .A1(alu_result[15]), .A2(n365), .B1(remainder_reg[47]), .B2( 727 | n362), .ZN(n407) ); 728 | OAI21_X1 U537 ( .B1(n20), .B2(n374), .A(n407), .ZN(n263) ); 729 | AOI22_X1 U538 ( .A1(alu_result[16]), .A2(n365), .B1(remainder_reg[48]), .B2( 730 | n362), .ZN(n408) ); 731 | OAI21_X1 U539 ( .B1(n19), .B2(n430), .A(n408), .ZN(n262) ); 732 | AOI22_X1 U540 ( .A1(alu_result[17]), .A2(n365), .B1(remainder_reg[49]), .B2( 733 | n362), .ZN(n409) ); 734 | OAI21_X1 U541 ( .B1(n18), .B2(n430), .A(n409), .ZN(n261) ); 735 | AOI22_X1 U542 ( .A1(alu_result[18]), .A2(n365), .B1(remainder_reg[50]), .B2( 736 | n362), .ZN(n410) ); 737 | OAI21_X1 U543 ( .B1(n17), .B2(n430), .A(n410), .ZN(n260) ); 738 | AOI22_X1 U544 ( .A1(alu_result[19]), .A2(n365), .B1(remainder_reg[51]), .B2( 739 | n362), .ZN(n411) ); 740 | OAI21_X1 U545 ( .B1(n16), .B2(n430), .A(n411), .ZN(n259) ); 741 | AOI22_X1 U546 ( .A1(alu_result[20]), .A2(n364), .B1(remainder_reg[52]), .B2( 742 | n362), .ZN(n412) ); 743 | OAI21_X1 U547 ( .B1(n15), .B2(n430), .A(n412), .ZN(n258) ); 744 | AOI22_X1 U548 ( .A1(alu_result[21]), .A2(n364), .B1(remainder_reg[53]), .B2( 745 | n362), .ZN(n413) ); 746 | OAI21_X1 U549 ( .B1(n14), .B2(n430), .A(n413), .ZN(n257) ); 747 | AOI22_X1 U550 ( .A1(alu_result[22]), .A2(n364), .B1(remainder_reg[54]), .B2( 748 | n362), .ZN(n414) ); 749 | OAI21_X1 U551 ( .B1(n13), .B2(n430), .A(n414), .ZN(n256) ); 750 | AOI22_X1 U552 ( .A1(alu_result[23]), .A2(n364), .B1(remainder_reg[55]), .B2( 751 | n362), .ZN(n415) ); 752 | OAI21_X1 U553 ( .B1(n12), .B2(n430), .A(n415), .ZN(n255) ); 753 | AOI22_X1 U554 ( .A1(alu_result[24]), .A2(n364), .B1(remainder_reg[56]), .B2( 754 | n363), .ZN(n416) ); 755 | OAI21_X1 U555 ( .B1(n11), .B2(n430), .A(n416), .ZN(n254) ); 756 | AOI22_X1 U556 ( .A1(alu_result[25]), .A2(n364), .B1(remainder_reg[57]), .B2( 757 | n363), .ZN(n417) ); 758 | OAI21_X1 U557 ( .B1(n10), .B2(n430), .A(n417), .ZN(n253) ); 759 | AOI22_X1 U558 ( .A1(alu_result[26]), .A2(n364), .B1(remainder_reg[58]), .B2( 760 | n363), .ZN(n418) ); 761 | OAI21_X1 U559 ( .B1(n9), .B2(n374), .A(n418), .ZN(n252) ); 762 | AOI22_X1 U560 ( .A1(alu_result[27]), .A2(n364), .B1(remainder_reg[59]), .B2( 763 | n363), .ZN(n419) ); 764 | OAI21_X1 U561 ( .B1(n8), .B2(n374), .A(n419), .ZN(n251) ); 765 | AOI22_X1 U562 ( .A1(alu_result[28]), .A2(n364), .B1(remainder_reg[60]), .B2( 766 | n363), .ZN(n420) ); 767 | OAI21_X1 U563 ( .B1(n7), .B2(n374), .A(n420), .ZN(n250) ); 768 | AOI22_X1 U564 ( .A1(alu_result[29]), .A2(n364), .B1(remainder_reg[61]), .B2( 769 | n363), .ZN(n421) ); 770 | OAI21_X1 U565 ( .B1(n6), .B2(n374), .A(n421), .ZN(n249) ); 771 | AOI22_X1 U566 ( .A1(alu_result[30]), .A2(n364), .B1(remainder_reg[62]), .B2( 772 | n363), .ZN(n422) ); 773 | OAI21_X1 U567 ( .B1(n4), .B2(n374), .A(n422), .ZN(n248) ); 774 | OAI22_X1 U569 ( .A1(n438), .A2(n358), .B1(n81), .B2(n348), .ZN(n310) ); 775 | OAI22_X1 U570 ( .A1(n439), .A2(n358), .B1(n82), .B2(n348), .ZN(n311) ); 776 | OAI22_X1 U571 ( .A1(n440), .A2(n358), .B1(n83), .B2(n348), .ZN(n312) ); 777 | OAI22_X1 U572 ( .A1(n441), .A2(n358), .B1(n84), .B2(n348), .ZN(n313) ); 778 | OAI22_X1 U573 ( .A1(n442), .A2(n358), .B1(n85), .B2(n348), .ZN(n314) ); 779 | OAI22_X1 U574 ( .A1(n443), .A2(n358), .B1(n86), .B2(n348), .ZN(n315) ); 780 | OAI22_X1 U575 ( .A1(n444), .A2(n358), .B1(n87), .B2(n348), .ZN(n316) ); 781 | OAI22_X1 U576 ( .A1(n445), .A2(n358), .B1(n88), .B2(n348), .ZN(n317) ); 782 | OAI22_X1 U577 ( .A1(n446), .A2(n358), .B1(n89), .B2(n348), .ZN(n318) ); 783 | OAI22_X1 U578 ( .A1(n447), .A2(n358), .B1(n90), .B2(n348), .ZN(n319) ); 784 | OAI22_X1 U579 ( .A1(n448), .A2(n358), .B1(n91), .B2(n348), .ZN(n320) ); 785 | OAI22_X1 U580 ( .A1(n449), .A2(n358), .B1(n92), .B2(n348), .ZN(n321) ); 786 | OAI22_X1 U581 ( .A1(n450), .A2(n424), .B1(n93), .B2(n348), .ZN(n322) ); 787 | OAI22_X1 U582 ( .A1(n451), .A2(n424), .B1(n94), .B2(n348), .ZN(n323) ); 788 | OAI22_X1 U583 ( .A1(n452), .A2(n424), .B1(n95), .B2(n348), .ZN(n324) ); 789 | OAI22_X1 U584 ( .A1(n453), .A2(n424), .B1(n96), .B2(n348), .ZN(n325) ); 790 | OAI22_X1 U585 ( .A1(n454), .A2(n424), .B1(n97), .B2(n348), .ZN(n326) ); 791 | OAI22_X1 U586 ( .A1(n455), .A2(n424), .B1(n98), .B2(n348), .ZN(n327) ); 792 | OAI22_X1 U587 ( .A1(n456), .A2(n424), .B1(n99), .B2(n348), .ZN(n328) ); 793 | OAI22_X1 U588 ( .A1(n457), .A2(n424), .B1(n100), .B2(n348), .ZN(n329) ); 794 | OAI22_X1 U589 ( .A1(n458), .A2(n424), .B1(n101), .B2(n348), .ZN(n330) ); 795 | OAI22_X1 U590 ( .A1(n459), .A2(n424), .B1(n102), .B2(n348), .ZN(n331) ); 796 | OAI22_X1 U591 ( .A1(n460), .A2(n424), .B1(n103), .B2(n348), .ZN(n332) ); 797 | OAI22_X1 U592 ( .A1(n461), .A2(n424), .B1(n104), .B2(n348), .ZN(n333) ); 798 | OAI22_X1 U593 ( .A1(n462), .A2(n424), .B1(n105), .B2(n348), .ZN(n334) ); 799 | OAI22_X1 U594 ( .A1(n463), .A2(n424), .B1(n106), .B2(n348), .ZN(n335) ); 800 | OAI22_X1 U595 ( .A1(n464), .A2(n424), .B1(n107), .B2(n348), .ZN(n336) ); 801 | OAI22_X1 U596 ( .A1(n465), .A2(n424), .B1(n108), .B2(n348), .ZN(n337) ); 802 | OAI22_X1 U597 ( .A1(n466), .A2(n424), .B1(n109), .B2(n348), .ZN(n338) ); 803 | OAI22_X1 U598 ( .A1(n467), .A2(n424), .B1(n110), .B2(n348), .ZN(n339) ); 804 | OAI22_X1 U599 ( .A1(n468), .A2(n424), .B1(n111), .B2(n348), .ZN(n340) ); 805 | OAI22_X1 U600 ( .A1(n469), .A2(n424), .B1(n112), .B2(n348), .ZN(n341) ); 806 | NAND2_X1 U602 ( .A1(dividend[1]), .A2(n347), .ZN(n426) ); 807 | OAI221_X1 U603 ( .B1(n67), .B2(n374), .C1(n68), .C2(n470), .A(n426), .ZN( 808 | n309) ); 809 | NOR2_X1 U604 ( .A1(n381), .A2(n35), .ZN(remainder[0]) ); 810 | NOR2_X1 U605 ( .A1(n381), .A2(n34), .ZN(remainder[1]) ); 811 | NOR2_X1 U606 ( .A1(n147), .A2(n33), .ZN(remainder[2]) ); 812 | NOR2_X1 U607 ( .A1(n147), .A2(n32), .ZN(remainder[3]) ); 813 | NOR2_X1 U608 ( .A1(n147), .A2(n31), .ZN(remainder[4]) ); 814 | NOR2_X1 U609 ( .A1(n147), .A2(n30), .ZN(remainder[5]) ); 815 | NOR2_X1 U610 ( .A1(n147), .A2(n29), .ZN(remainder[6]) ); 816 | NOR2_X1 U611 ( .A1(n382), .A2(n28), .ZN(remainder[7]) ); 817 | NOR2_X1 U612 ( .A1(n382), .A2(n27), .ZN(remainder[8]) ); 818 | NOR2_X1 U613 ( .A1(n382), .A2(n26), .ZN(remainder[9]) ); 819 | NOR2_X1 U614 ( .A1(n382), .A2(n25), .ZN(remainder[10]) ); 820 | NOR2_X1 U615 ( .A1(n382), .A2(n24), .ZN(remainder[11]) ); 821 | NOR2_X1 U616 ( .A1(n382), .A2(n23), .ZN(remainder[12]) ); 822 | NOR2_X1 U617 ( .A1(n382), .A2(n22), .ZN(remainder[13]) ); 823 | NOR2_X1 U618 ( .A1(n382), .A2(n21), .ZN(remainder[14]) ); 824 | NOR2_X1 U619 ( .A1(n382), .A2(n20), .ZN(remainder[15]) ); 825 | NOR2_X1 U620 ( .A1(n382), .A2(n19), .ZN(remainder[16]) ); 826 | NOR2_X1 U621 ( .A1(n382), .A2(n18), .ZN(remainder[17]) ); 827 | NOR2_X1 U622 ( .A1(n382), .A2(n17), .ZN(remainder[18]) ); 828 | NOR2_X1 U623 ( .A1(n382), .A2(n16), .ZN(remainder[19]) ); 829 | NOR2_X1 U624 ( .A1(n382), .A2(n15), .ZN(remainder[20]) ); 830 | NOR2_X1 U625 ( .A1(n382), .A2(n14), .ZN(remainder[21]) ); 831 | NOR2_X1 U626 ( .A1(n382), .A2(n13), .ZN(remainder[22]) ); 832 | NOR2_X1 U627 ( .A1(n382), .A2(n12), .ZN(remainder[23]) ); 833 | NOR2_X1 U628 ( .A1(n382), .A2(n11), .ZN(remainder[24]) ); 834 | NOR2_X1 U629 ( .A1(n382), .A2(n10), .ZN(remainder[25]) ); 835 | NOR2_X1 U630 ( .A1(n381), .A2(n9), .ZN(remainder[26]) ); 836 | NOR2_X1 U631 ( .A1(n381), .A2(n8), .ZN(remainder[27]) ); 837 | NOR2_X1 U632 ( .A1(n381), .A2(n7), .ZN(remainder[28]) ); 838 | NOR2_X1 U633 ( .A1(n381), .A2(n6), .ZN(remainder[29]) ); 839 | NOR2_X1 U634 ( .A1(n381), .A2(n4), .ZN(remainder[30]) ); 840 | AOI22_X1 U635 ( .A1(alu_result[31]), .A2(n365), .B1(remainder_reg[63]), .B2( 841 | n363), .ZN(n427) ); 842 | OAI21_X1 U636 ( .B1(n3), .B2(n374), .A(n427), .ZN(n247) ); 843 | NOR2_X1 U637 ( .A1(n3), .A2(n147), .ZN(remainder[31]) ); 844 | NOR2_X1 U638 ( .A1(n381), .A2(n68), .ZN(quotient[0]) ); 845 | XOR2_X1 U639 ( .A(add_117_carry[5]), .B(cnt_reg[5]), .Z(N234) ); 846 | INV_X2 U311 ( .A(n178), .ZN(n430) ); 847 | NAND2_X1 U313 ( .A1(n389), .A2(n227), .ZN(n178) ); 848 | AND2_X2 U314 ( .A1(n423), .A2(n218), .ZN(n348) ); 849 | NAND2_X1 U316 ( .A1(n218), .A2(n346), .ZN(n424) ); 850 | NAND2_X2 U317 ( .A1(done), .A2(state_reg_1_), .ZN(n147) ); 851 | AND3_X2 U320 ( .A1(n346), .A2(n389), .A3(n349), .ZN(n347) ); 852 | INV_X1 U322 ( .A(n386), .ZN(n423) ); 853 | NOR2_X1 U323 ( .A1(rst), .A2(n384), .ZN(n386) ); 854 | OR3_X1 U324 ( .A1(n352), .A2(n350), .A3(n351), .ZN(n429) ); 855 | NOR2_X1 U325 ( .A1(n37), .A2(n147), .ZN(quotient[31]) ); 856 | INV_X1 U331 ( .A(n470), .ZN(n345) ); 857 | NAND3_X1 U332 ( .A1(n428), .A2(state_reg_1_), .A3(n387), .ZN(n470) ); 858 | NOR2_X1 U333 ( .A1(alu_result[32]), .A2(n470), .ZN(n352) ); 859 | NAND2_X1 U336 ( .A1(n237), .A2(n236), .ZN(n384) ); 860 | endmodule 861 | 862 | --------------------------------------------------------------------------------