├── .idea ├── .gitignore ├── deobf.iml ├── inspectionProfiles │ └── profiles_settings.xml ├── misc.xml ├── modules.xml └── vcs.xml ├── LICENSE ├── README.md ├── VMEngine.py ├── Vm ├── BinjaAst.py ├── CONSTS.py ├── VMGlobalData.py ├── VmExploration.py ├── VmState.py ├── __init__.py ├── __pycache__ │ ├── BinjaAst.cpython-311.pyc │ ├── CONSTS.cpython-310.pyc │ ├── CONSTS.cpython-311.pyc │ ├── VMGlobalData.cpython-310.pyc │ ├── VMGlobalData.cpython-311.pyc │ ├── VmExploration.cpython-310.pyc │ ├── VmExploration.cpython-311.pyc │ ├── VmState.cpython-310.pyc │ ├── VmState.cpython-311.pyc │ ├── __init__.cpython-310.pyc │ └── __init__.cpython-311.pyc └── doctest-output │ ├── 100_8320FACB.gv │ ├── 100_8320FACB.gv.pdf │ ├── 101_13A50A15.gv │ ├── 101_13A50A15.gv.pdf │ ├── 102_13A50415.gv │ ├── 102_13A50415.gv.pdf │ ├── 103_4010015.gv │ ├── 103_4010015.gv.pdf │ ├── 104_13BE0617.gv │ ├── 104_13BE0617.gv.pdf │ ├── 105_13B60417.gv │ ├── 105_13B60417.gv.pdf │ ├── 106_13A10817.gv │ ├── 106_13A10817.gv.pdf │ ├── 107_3BE0828.gv │ ├── 107_3BE0828.gv.pdf │ ├── 108_8200C1CB.gv │ ├── 108_8200C1CB.gv.pdf │ ├── 109_8320FACB.gv │ ├── 109_8320FACB.gv.pdf │ ├── 10_1FB10217.gv │ ├── 10_1FB10217.gv.pdf │ ├── 110_3C021CB.gv │ ├── 110_3C021CB.gv.pdf │ ├── 111_FA50E15.gv │ ├── 111_FA50E15.gv.pdf │ ├── 112_6C10015.gv │ ├── 112_6C10015.gv.pdf │ ├── 113_13B70017.gv │ ├── 113_13B70017.gv.pdf │ ├── 114_FA10E17.gv │ ├── 114_FA10E17.gv.pdf │ ├── 115_13B30217.gv │ ├── 115_13B30217.gv.pdf │ ├── 116_8200C1CB.gv │ ├── 116_8200C1CB.gv.pdf │ ├── 117_8320FACB.gv │ ├── 117_8320FACB.gv.pdf │ ├── 118_3C021CB.gv │ ├── 118_3C021CB.gv.pdf │ ├── 119_10811.gv │ ├── 119_10811.gv.pdf │ ├── 11_1FB00017.gv │ ├── 11_1FB00017.gv.pdf │ ├── 120_FB50A17.gv │ ├── 120_FB50A17.gv.pdf │ ├── 121_3B30A28.gv │ ├── 121_3B30A28.gv.pdf │ ├── 122_FB30817.gv │ ├── 122_FB30817.gv.pdf │ ├── 123_FA10C30.gv │ ├── 123_FA10C30.gv.pdf │ ├── 124_3A40C28.gv │ ├── 124_3A40C28.gv.pdf │ ├── 125_8200C1CB.gv │ ├── 125_8200C1CB.gv.pdf │ ├── 126_8320FACB.gv │ ├── 126_8320FACB.gv.pdf │ ├── 127_FA50815.gv │ ├── 127_FA50815.gv.pdf │ ├── 128_2610995.gv │ ├── 128_2610995.gv.pdf │ ├── 129_3B30428.gv │ ├── 129_3B30428.gv.pdf │ ├── 12_E081CB.gv │ ├── 12_E081CB.gv.pdf │ ├── 130_20411.gv │ ├── 130_20411.gv.pdf │ ├── 131_BA30215.gv │ ├── 131_BA30215.gv.pdf │ ├── 132_BB30A17.gv │ ├── 132_BB30A17.gv.pdf │ ├── 133_BA20C30.gv │ ├── 133_BA20C30.gv.pdf │ ├── 134_BB40E17.gv │ ├── 134_BB40E17.gv.pdf │ ├── 135_FB60017.gv │ ├── 135_FB60017.gv.pdf │ ├── 136_FB10217.gv │ ├── 136_FB10217.gv.pdf │ ├── 137_FA10417.gv │ ├── 137_FA10417.gv.pdf │ ├── 138_FA30617.gv │ ├── 138_FA30617.gv.pdf │ ├── 139_BA10228.gv │ ├── 139_BA10228.gv.pdf │ ├── 13_8B0428.gv │ ├── 13_8B0428.gv.pdf │ ├── 140_FC21F695.gv │ ├── 140_FC21F695.gv.pdf │ ├── 141_BA10217.gv │ ├── 141_BA10217.gv.pdf │ ├── 142_3A40E28.gv │ ├── 142_3A40E28.gv.pdf │ ├── 143_8200C1CB.gv │ ├── 143_8200C1CB.gv.pdf │ ├── 144_8320FACB.gv │ ├── 144_8320FACB.gv.pdf │ ├── 145_BA50A15.gv │ ├── 145_BA50A15.gv.pdf │ ├── 146_BA20228.gv │ ├── 146_BA20228.gv.pdf │ ├── 148_64B.gv │ ├── 148_64B.gv.pdf │ ├── 149_410995.gv │ ├── 149_410995.gv.pdf │ ├── 14_8C0028.gv │ ├── 14_8C0028.gv.pdf │ ├── 151_2410017.gv │ ├── 151_2410017.gv.pdf │ ├── 152_BB50817.gv │ ├── 152_BB50817.gv.pdf │ ├── 153_BA50815.gv │ ├── 153_BA50815.gv.pdf │ ├── 154_7B10028.gv │ ├── 154_7B10028.gv.pdf │ ├── 155_8200C1CB.gv │ ├── 155_8200C1CB.gv.pdf │ ├── 156_8320FACB.gv │ ├── 156_8320FACB.gv.pdf │ ├── 157_22021CB.gv │ ├── 157_22021CB.gv.pdf │ ├── 158_BB30617.gv │ ├── 158_BB30617.gv.pdf │ ├── 159_BA50615.gv │ ├── 159_BA50615.gv.pdf │ ├── 15_C20028.gv │ ├── 15_C20028.gv.pdf │ ├── 160_8200C1CB.gv │ ├── 160_8200C1CB.gv.pdf │ ├── 161_8320FACB.gv │ ├── 161_8320FACB.gv.pdf │ ├── 162_22021CB.gv │ ├── 162_22021CB.gv.pdf │ ├── 163_BA50415.gv │ ├── 163_BA50415.gv.pdf │ ├── 164_BB60417.gv │ ├── 164_BB60417.gv.pdf │ ├── 165_8200C1CB.gv │ ├── 165_8200C1CB.gv.pdf │ ├── 166_8320FACB.gv │ ├── 166_8320FACB.gv.pdf │ ├── 167_22021CB.gv │ ├── 167_22021CB.gv.pdf │ ├── 168_1FB00028.gv │ ├── 168_1FB00028.gv.pdf │ ├── 169_1FB10228.gv │ ├── 169_1FB10228.gv.pdf │ ├── 16_C30228.gv │ ├── 16_C30228.gv.pdf │ ├── 170_1FB20428.gv │ ├── 170_1FB20428.gv.pdf │ ├── 171_1FB30628.gv │ ├── 171_1FB30628.gv.pdf │ ├── 172_1FB40828.gv │ ├── 172_1FB40828.gv.pdf │ ├── 173_1FB50A28.gv │ ├── 173_1FB50A28.gv.pdf │ ├── 174_1FB60C28.gv │ ├── 174_1FB60C28.gv.pdf │ ├── 175_1FB70E28.gv │ ├── 175_1FB70E28.gv.pdf │ ├── 176_23BE0028.gv │ ├── 176_23BE0028.gv.pdf │ ├── 177_23BF0228.gv │ ├── 177_23BF0228.gv.pdf │ ├── 179_23BD0415.gv │ ├── 179_23BD0415.gv.pdf │ ├── 17_C50428.gv │ ├── 17_C50428.gv.pdf │ ├── 18_C70628.gv │ ├── 18_C70628.gv.pdf │ ├── 19_C80828.gv │ ├── 19_C80828.gv.pdf │ ├── 1_DFBDFC15.gv │ ├── 1_DFBDFC15.gv.pdf │ ├── 20_C90A28.gv │ ├── 20_C90A28.gv.pdf │ ├── 21_920628.gv │ ├── 21_920628.gv.pdf │ ├── 22_CA0C28.gv │ ├── 22_CA0C28.gv.pdf │ ├── 23_C60E28.gv │ ├── 23_C60E28.gv.pdf │ ├── 24_930228.gv │ ├── 24_930228.gv.pdf │ ├── 25_6610D95.gv │ ├── 25_6610D95.gv.pdf │ ├── 26_BA10217.gv │ ├── 26_BA10217.gv.pdf │ ├── 27_2440028.gv │ ├── 27_2440028.gv.pdf │ ├── 28_808109CB.gv │ ├── 28_808109CB.gv.pdf │ ├── 2_23BF0217.gv │ ├── 2_23BF0217.gv.pdf │ ├── 30_64B.gv │ ├── 30_64B.gv.pdf │ ├── 31_F001F8B4.gv │ ├── 31_F001F8B4.gv.pdf │ ├── 32_84215C07.gv │ ├── 32_84215C07.gv.pdf │ ├── 33_C1230B.gv │ ├── 33_C1230B.gv.pdf │ ├── 34_7A40017.gv │ ├── 34_7A40017.gv.pdf │ ├── 35_141230B.gv │ ├── 35_141230B.gv.pdf │ ├── 36_3A40E17.gv │ ├── 36_3A40E17.gv.pdf │ ├── 37_121230B.gv │ ├── 37_121230B.gv.pdf │ ├── 38_3A40C17.gv │ ├── 38_3A40C17.gv.pdf │ ├── 39_101230B.gv │ ├── 39_101230B.gv.pdf │ ├── 3_23BE0017.gv │ ├── 3_23BE0017.gv.pdf │ ├── 40_3A40817.gv │ ├── 40_3A40817.gv.pdf │ ├── 41_E1230B.gv │ ├── 41_E1230B.gv.pdf │ ├── 42_3A40617.gv │ ├── 42_3A40617.gv.pdf │ ├── 43_A1230B.gv │ ├── 43_A1230B.gv.pdf │ ├── 44_3A40017.gv │ ├── 44_3A40017.gv.pdf │ ├── 45_8061B30B.gv │ ├── 45_8061B30B.gv.pdf │ ├── 46_41F30B.gv │ ├── 46_41F30B.gv.pdf │ ├── 47_140815.gv │ ├── 47_140815.gv.pdf │ ├── 48_1BB40C17.gv │ ├── 48_1BB40C17.gv.pdf │ ├── 49_1BA50C15.gv │ ├── 49_1BA50C15.gv.pdf │ ├── 4_1FB70E17.gv │ ├── 4_1FB70E17.gv.pdf │ ├── 50_3C021CB.gv │ ├── 50_3C021CB.gv.pdf │ ├── 51_8200C1CB.gv │ ├── 51_8200C1CB.gv.pdf │ ├── 52_3AB0A17.gv │ ├── 52_3AB0A17.gv.pdf │ ├── 53_8320FACB.gv │ ├── 53_8320FACB.gv.pdf │ ├── 54_3AC0217.gv │ ├── 54_3AC0217.gv.pdf │ ├── 55_1BB40A17.gv │ ├── 55_1BB40A17.gv.pdf │ ├── 56_1BB50E28.gv │ ├── 56_1BB50E28.gv.pdf │ ├── 57_1BB50817.gv │ ├── 57_1BB50817.gv.pdf │ ├── 58_1BA50815.gv │ ├── 58_1BA50815.gv.pdf │ ├── 59_8200C1CB.gv │ ├── 59_8200C1CB.gv.pdf │ ├── 5_1FB60C17.gv │ ├── 5_1FB60C17.gv.pdf │ ├── 60_8320FACB.gv │ ├── 60_8320FACB.gv.pdf │ ├── 61_2E021CB.gv │ ├── 61_2E021CB.gv.pdf │ ├── 62_1BA50415.gv │ ├── 62_1BA50415.gv.pdf │ ├── 63_160415.gv │ ├── 63_160415.gv.pdf │ ├── 64_1BB60417.gv │ ├── 64_1BB60417.gv.pdf │ ├── 65_8200C1CB.gv │ ├── 65_8200C1CB.gv.pdf │ ├── 66_8320FACB.gv │ ├── 66_8320FACB.gv.pdf │ ├── 67_3C021CB.gv │ ├── 67_3C021CB.gv.pdf │ ├── 68_1BA50015.gv │ ├── 68_1BA50015.gv.pdf │ ├── 69_1BB60017.gv │ ├── 69_1BB60017.gv.pdf │ ├── 6_1FB50A17.gv │ ├── 6_1FB50A17.gv.pdf │ ├── 70_1BB10628.gv │ ├── 70_1BB10628.gv.pdf │ ├── 71_3B10417.gv │ ├── 71_3B10417.gv.pdf │ ├── 72_8200C1CB.gv │ ├── 72_8200C1CB.gv.pdf │ ├── 73_8320FACB.gv │ ├── 73_8320FACB.gv.pdf │ ├── 74_3C021CB.gv │ ├── 74_3C021CB.gv.pdf │ ├── 75_17B50417.gv │ ├── 75_17B50417.gv.pdf │ ├── 76_17B40617.gv │ ├── 76_17B40617.gv.pdf │ ├── 77_17B10817.gv │ ├── 77_17B10817.gv.pdf │ ├── 78_17B60A17.gv │ ├── 78_17B60A17.gv.pdf │ ├── 79_17B60E17.gv │ ├── 79_17B60E17.gv.pdf │ ├── 7_1FB40817.gv │ ├── 7_1FB40817.gv.pdf │ ├── 80_1BB40228.gv │ ├── 80_1BB40228.gv.pdf │ ├── 81_17B40C17.gv │ ├── 81_17B40C17.gv.pdf │ ├── 82_3A40028.gv │ ├── 82_3A40028.gv.pdf │ ├── 83_8200C1CB.gv │ ├── 83_8200C1CB.gv.pdf │ ├── 84_8320FACB.gv │ ├── 84_8320FACB.gv.pdf │ ├── 85_17A50415.gv │ ├── 85_17A50415.gv.pdf │ ├── 86_6710015.gv │ ├── 86_6710015.gv.pdf │ ├── 87_17A50015.gv │ ├── 87_17A50015.gv.pdf │ ├── 88_17B10017.gv │ ├── 88_17B10017.gv.pdf │ ├── 89_8200C1CB.gv │ ├── 89_8200C1CB.gv.pdf │ ├── 8_1FB30617.gv │ ├── 8_1FB30617.gv.pdf │ ├── 90_8320FACB.gv │ ├── 90_8320FACB.gv.pdf │ ├── 91_3C021CB.gv │ ├── 91_3C021CB.gv.pdf │ ├── 92_7BE0215.gv │ ├── 92_7BE0215.gv.pdf │ ├── 93_17B60228.gv │ ├── 93_17B60228.gv.pdf │ ├── 94_13B30C17.gv │ ├── 94_13B30C17.gv.pdf │ ├── 95_3B70228.gv │ ├── 95_3B70228.gv.pdf │ ├── 96_13B70A17.gv │ ├── 96_13B70A17.gv.pdf │ ├── 97_13BE0E17.gv │ ├── 97_13BE0E17.gv.pdf │ ├── 98_3A40628.gv │ ├── 98_3A40628.gv.pdf │ ├── 99_8200C1CB.gv │ ├── 99_8200C1CB.gv.pdf │ ├── 9_1FB20417.gv │ ├── 9_1FB20417.gv.pdf │ ├── ADD sp, sp, #-0x210.gv │ ├── ADD sp, sp, #-0x210.gv.pdf │ ├── extra_info_match.gv │ └── extra_info_match.gv.pdf ├── __init__.py ├── __pycache__ ├── VMEngine.cpython-311.pyc ├── __init__.cpython-310.pyc ├── __init__.cpython-311.pyc ├── graphviz_tools.cpython-310.pyc ├── graphviz_tools.cpython-311.pyc ├── header_less.cpython-310.pyc ├── header_less.cpython-311.pyc ├── user_il.cpython-310.pyc ├── user_il.cpython-311.pyc ├── utils.cpython-310.pyc ├── utils.cpython-311.pyc ├── vm_tools.cpython-311.pyc ├── work_flow.cpython-310.pyc └── work_flow.cpython-311.pyc ├── angr_tools.py ├── arch_hook.py ├── data.json ├── data.py ├── de_br.py ├── dec_opcode.py ├── doctest-output ├── 100_8320FACB.gv ├── 100_8320FACB.gv.pdf ├── 101_13A50A15.gv ├── 101_13A50A15.gv.pdf ├── 102_13A50415.gv ├── 102_13A50415.gv.pdf ├── 103_4010015.gv ├── 103_4010015.gv.pdf ├── 104_13BE0617.gv ├── 104_13BE0617.gv.pdf ├── 105_13B60417.gv ├── 105_13B60417.gv.pdf ├── 106_13A10817.gv ├── 106_13A10817.gv.pdf ├── 107_3BE0828.gv ├── 107_3BE0828.gv.pdf ├── 108_8200C1CB.gv ├── 108_8200C1CB.gv.pdf ├── 109_8320FACB.gv ├── 109_8320FACB.gv.pdf ├── 10_1FB10217.gv ├── 10_1FB10217.gv.pdf ├── 110_3C021CB.gv ├── 110_3C021CB.gv.pdf ├── 111_FA50E15.gv ├── 111_FA50E15.gv.pdf ├── 112_6C10015.gv ├── 112_6C10015.gv.pdf ├── 113_13B70017.gv ├── 113_13B70017.gv.pdf ├── 114_FA10E17.gv ├── 114_FA10E17.gv.pdf ├── 115_13B30217.gv ├── 115_13B30217.gv.pdf ├── 116_8200C1CB.gv ├── 116_8200C1CB.gv.pdf ├── 117_8320FACB.gv ├── 117_8320FACB.gv.pdf ├── 118_3C021CB.gv ├── 118_3C021CB.gv.pdf ├── 119_10811.gv ├── 119_10811.gv.pdf ├── 11_1FB00017.gv ├── 11_1FB00017.gv.pdf ├── 120_FB50A17.gv ├── 120_FB50A17.gv.pdf ├── 121_3B30A28.gv ├── 121_3B30A28.gv.pdf ├── 122_FB30817.gv ├── 122_FB30817.gv.pdf ├── 123_FA10C30.gv ├── 123_FA10C30.gv.pdf ├── 124_3A40C28.gv ├── 124_3A40C28.gv.pdf ├── 125_8200C1CB.gv ├── 125_8200C1CB.gv.pdf ├── 126_8320FACB.gv ├── 126_8320FACB.gv.pdf ├── 127_FA50815.gv ├── 127_FA50815.gv.pdf ├── 128_2610995.gv ├── 128_2610995.gv.pdf ├── 129_3B30428.gv ├── 129_3B30428.gv.pdf ├── 12_E081CB.gv ├── 12_E081CB.gv.pdf ├── 130_20411.gv ├── 130_20411.gv.pdf ├── 131_BA30215.gv ├── 131_BA30215.gv.pdf ├── 132_BB30A17.gv ├── 132_BB30A17.gv.pdf ├── 133_BA20C30.gv ├── 133_BA20C30.gv.pdf ├── 134_BB40E17.gv ├── 134_BB40E17.gv.pdf ├── 135_FB60017.gv ├── 135_FB60017.gv.pdf ├── 136_FB10217.gv ├── 136_FB10217.gv.pdf ├── 137_FA10417.gv ├── 137_FA10417.gv.pdf ├── 138_FA30617.gv ├── 138_FA30617.gv.pdf ├── 139_BA10228.gv ├── 139_BA10228.gv.pdf ├── 13_8B0428.gv ├── 13_8B0428.gv.pdf ├── 140_FC21F695.gv ├── 140_FC21F695.gv.pdf ├── 141_BA10217.gv ├── 141_BA10217.gv.pdf ├── 142_3A40E28.gv ├── 142_3A40E28.gv.pdf ├── 143_8200C1CB.gv ├── 143_8200C1CB.gv.pdf ├── 144_8320FACB.gv ├── 144_8320FACB.gv.pdf ├── 145_BA50A15.gv ├── 145_BA50A15.gv.pdf ├── 146_BA20228.gv ├── 146_BA20228.gv.pdf ├── 148_64B.gv ├── 148_64B.gv.pdf ├── 149_410995.gv ├── 149_410995.gv.pdf ├── 14_8C0028.gv ├── 14_8C0028.gv.pdf ├── 151_2410017.gv ├── 151_2410017.gv.pdf ├── 152_BB50817.gv ├── 152_BB50817.gv.pdf ├── 153_BA50815.gv ├── 153_BA50815.gv.pdf ├── 154_7B10028.gv ├── 154_7B10028.gv.pdf ├── 155_8200C1CB.gv ├── 155_8200C1CB.gv.pdf ├── 156_8320FACB.gv ├── 156_8320FACB.gv.pdf ├── 157_22021CB.gv ├── 157_22021CB.gv.pdf ├── 158_BB30617.gv ├── 158_BB30617.gv.pdf ├── 159_BA50615.gv ├── 159_BA50615.gv.pdf ├── 15_C20028.gv ├── 15_C20028.gv.pdf ├── 160_8200C1CB.gv ├── 160_8200C1CB.gv.pdf ├── 161_8320FACB.gv ├── 161_8320FACB.gv.pdf ├── 162_22021CB.gv ├── 162_22021CB.gv.pdf ├── 163_BA50415.gv ├── 163_BA50415.gv.pdf ├── 164_BB60417.gv ├── 164_BB60417.gv.pdf ├── 165_8200C1CB.gv ├── 165_8200C1CB.gv.pdf ├── 166_8320FACB.gv ├── 166_8320FACB.gv.pdf ├── 167_22021CB.gv ├── 167_22021CB.gv.pdf ├── 168_1FB00028.gv ├── 168_1FB00028.gv.pdf ├── 169_1FB10228.gv ├── 169_1FB10228.gv.pdf ├── 16_C30228.gv ├── 16_C30228.gv.pdf ├── 170_1FB20428.gv ├── 170_1FB20428.gv.pdf ├── 171_1FB30628.gv ├── 171_1FB30628.gv.pdf ├── 172_1FB40828.gv ├── 172_1FB40828.gv.pdf ├── 173_1FB50A28.gv ├── 173_1FB50A28.gv.pdf ├── 174_1FB60C28.gv ├── 174_1FB60C28.gv.pdf ├── 175_1FB70E28.gv ├── 175_1FB70E28.gv.pdf ├── 176_23BE0028.gv ├── 176_23BE0028.gv.pdf ├── 177_23BF0228.gv ├── 177_23BF0228.gv.pdf ├── 179_23BD0415.gv ├── 179_23BD0415.gv.pdf ├── 17_C50428.gv ├── 17_C50428.gv.pdf ├── 18_C70628.gv ├── 18_C70628.gv.pdf ├── 19_C80828.gv ├── 19_C80828.gv.pdf ├── 1_DFBDFC15.gv ├── 1_DFBDFC15.gv.pdf ├── 20_C90A28.gv ├── 20_C90A28.gv.pdf ├── 21_920628.gv ├── 21_920628.gv.pdf ├── 22_CA0C28.gv ├── 22_CA0C28.gv.pdf ├── 23_C60E28.gv ├── 23_C60E28.gv.pdf ├── 24_930228.gv ├── 24_930228.gv.pdf ├── 25_6610D95.gv ├── 25_6610D95.gv.pdf ├── 26_BA10217.gv ├── 26_BA10217.gv.pdf ├── 27_2440028.gv ├── 27_2440028.gv.pdf ├── 2_23BF0217.gv ├── 2_23BF0217.gv.pdf ├── 30_64B.gv ├── 30_64B.gv.pdf ├── 31_F001F8B4.gv ├── 31_F001F8B4.gv.pdf ├── 32_2400017.gv ├── 32_2400017.gv.pdf ├── 32_84215C07.gv ├── 32_84215C07.gv.pdf ├── 33_1FB00028.gv ├── 33_1FB00028.gv.pdf ├── 33_C1230B.gv ├── 33_C1230B.gv.pdf ├── 34_1FB10228.gv ├── 34_1FB10228.gv.pdf ├── 34_7A40017.gv ├── 34_7A40017.gv.pdf ├── 35_141230B.gv ├── 35_141230B.gv.pdf ├── 35_1FB20428.gv ├── 35_1FB20428.gv.pdf ├── 36_1FB30628.gv ├── 36_1FB30628.gv.pdf ├── 36_3A40E17.gv ├── 36_3A40E17.gv.pdf ├── 37_121230B.gv ├── 37_121230B.gv.pdf ├── 37_1FB40828.gv ├── 37_1FB40828.gv.pdf ├── 38_1FB50A28.gv ├── 38_1FB50A28.gv.pdf ├── 38_3A40C17.gv ├── 38_3A40C17.gv.pdf ├── 39_101230B.gv ├── 39_101230B.gv.pdf ├── 39_1FB60C28.gv ├── 39_1FB60C28.gv.pdf ├── 3_23BE0017.gv ├── 3_23BE0017.gv.pdf ├── 40_1FB70E28.gv ├── 40_1FB70E28.gv.pdf ├── 40_3A40817.gv ├── 40_3A40817.gv.pdf ├── 41_23BE0028.gv ├── 41_23BE0028.gv.pdf ├── 41_E1230B.gv ├── 41_E1230B.gv.pdf ├── 42_23BF0228.gv ├── 42_23BF0228.gv.pdf ├── 42_3A40617.gv ├── 42_3A40617.gv.pdf ├── 43_A1230B.gv ├── 43_A1230B.gv.pdf ├── 44_23BD0415.gv ├── 44_23BD0415.gv.pdf ├── 44_3A40017.gv ├── 44_3A40017.gv.pdf ├── 45_8061B30B.gv ├── 45_8061B30B.gv.pdf ├── 46_41F30B.gv ├── 46_41F30B.gv.pdf ├── 47_140815.gv ├── 47_140815.gv.pdf ├── 48_1BB40C17.gv ├── 48_1BB40C17.gv.pdf ├── 49_1BA50C15.gv ├── 49_1BA50C15.gv.pdf ├── 4_1FB70E17.gv ├── 4_1FB70E17.gv.pdf ├── 50_3C021CB.gv ├── 50_3C021CB.gv.pdf ├── 51_8200C1CB.gv ├── 51_8200C1CB.gv.pdf ├── 52_3AB0A17.gv ├── 52_3AB0A17.gv.pdf ├── 53_8320FACB.gv ├── 53_8320FACB.gv.pdf ├── 54_3AC0217.gv ├── 54_3AC0217.gv.pdf ├── 55_1BB40A17.gv ├── 55_1BB40A17.gv.pdf ├── 56_1BB50E28.gv ├── 56_1BB50E28.gv.pdf ├── 57_1BB50817.gv ├── 57_1BB50817.gv.pdf ├── 58_1BA50815.gv ├── 58_1BA50815.gv.pdf ├── 59_8200C1CB.gv ├── 59_8200C1CB.gv.pdf ├── 5_1FB60C17.gv ├── 5_1FB60C17.gv.pdf ├── 60_8320FACB.gv ├── 60_8320FACB.gv.pdf ├── 61_2E021CB.gv ├── 61_2E021CB.gv.pdf ├── 62_1BA50415.gv ├── 62_1BA50415.gv.pdf ├── 63_160415.gv ├── 63_160415.gv.pdf ├── 64_1BB60417.gv ├── 64_1BB60417.gv.pdf ├── 65_8200C1CB.gv ├── 65_8200C1CB.gv.pdf ├── 66_8320FACB.gv ├── 66_8320FACB.gv.pdf ├── 67_3C021CB.gv ├── 67_3C021CB.gv.pdf ├── 68_1BA50015.gv ├── 68_1BA50015.gv.pdf ├── 69_1BB60017.gv ├── 69_1BB60017.gv.pdf ├── 6_1FB50A17.gv ├── 6_1FB50A17.gv.pdf ├── 70_1BB10628.gv ├── 70_1BB10628.gv.pdf ├── 71_3B10417.gv ├── 71_3B10417.gv.pdf ├── 72_8200C1CB.gv ├── 72_8200C1CB.gv.pdf ├── 73_8320FACB.gv ├── 73_8320FACB.gv.pdf ├── 74_3C021CB.gv ├── 74_3C021CB.gv.pdf ├── 75_17B50417.gv ├── 75_17B50417.gv.pdf ├── 76_17B40617.gv ├── 76_17B40617.gv.pdf ├── 77_17B10817.gv ├── 77_17B10817.gv.pdf ├── 78_17B60A17.gv ├── 78_17B60A17.gv.pdf ├── 79_17B60E17.gv ├── 79_17B60E17.gv.pdf ├── 7_1FB40817.gv ├── 7_1FB40817.gv.pdf ├── 80_1BB40228.gv ├── 80_1BB40228.gv.pdf ├── 81_17B40C17.gv ├── 81_17B40C17.gv.pdf ├── 82_3A40028.gv ├── 82_3A40028.gv.pdf ├── 83_8200C1CB.gv ├── 83_8200C1CB.gv.pdf ├── 84_8320FACB.gv ├── 84_8320FACB.gv.pdf ├── 85_17A50415.gv ├── 85_17A50415.gv.pdf ├── 86_6710015.gv ├── 86_6710015.gv.pdf ├── 87_17A50015.gv ├── 87_17A50015.gv.pdf ├── 88_17B10017.gv ├── 88_17B10017.gv.pdf ├── 89_8200C1CB.gv ├── 89_8200C1CB.gv.pdf ├── 8_1FB30617.gv ├── 8_1FB30617.gv.pdf ├── 90_8320FACB.gv ├── 90_8320FACB.gv.pdf ├── 91_3C021CB.gv ├── 91_3C021CB.gv.pdf ├── 92_7BE0215.gv ├── 92_7BE0215.gv.pdf ├── 93_17B60228.gv ├── 93_17B60228.gv.pdf ├── 94_13B30C17.gv ├── 94_13B30C17.gv.pdf ├── 95_3B70228.gv ├── 95_3B70228.gv.pdf ├── 96_13B70A17.gv ├── 96_13B70A17.gv.pdf ├── 97_13BE0E17.gv ├── 97_13BE0E17.gv.pdf ├── 98_3A40628.gv ├── 98_3A40628.gv.pdf ├── 99_8200C1CB.gv ├── 99_8200C1CB.gv.pdf ├── 9_1FB20417.gv └── 9_1FB20417.gv.pdf ├── dy_code.py ├── graphviz_tools.py ├── header_less.py ├── llil.S ├── plugin.json ├── symbolic_.py ├── symbolic_libEncryptor.py ├── symbolic_libEncryptor2.py ├── symbolic_libEncryptor2_back.py ├── symbolic_libEncryptor2_back2.py ├── test_exe.py ├── triton_test.py ├── ttEncrypt ├── DeviceRegister.py ├── decode_opcode.py ├── generate_aes_key_iv.asm ├── libEncryptor.so ├── libEncryptor.so.bndb ├── ttEncryptorUtil.py └── ttencryptor.asm ├── user_il.py ├── utils.py ├── vm_data.json ├── vm_tools.py └── work_flow.py /.idea/.gitignore: -------------------------------------------------------------------------------- 1 | # Default ignored files 2 | /shelf/ 3 | /workspace.xml 4 | # Editor-based HTTP Client requests 5 | /httpRequests/ 6 | # Datasource local storage ignored files 7 | /dataSources/ 8 | /dataSources.local.xml 9 | -------------------------------------------------------------------------------- /.idea/deobf.iml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /.idea/inspectionProfiles/profiles_settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | -------------------------------------------------------------------------------- /.idea/misc.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 6 | 7 | -------------------------------------------------------------------------------- /.idea/modules.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /.idea/vcs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | 这个项目上次 还原 ollvm 基础上改的 3 | 4 | 有问题提 issue 可以一起交流 vm 的还原 5 | 6 | 我保留了探索过程中写的代码,所以会稍微有点乱,只关注被调用的部分就好了 7 | ```angular2html 8 | 9 | │ angr_tools.py 10 | │ arch_hook.py 11 | │ data.json 12 | │ data.py 13 | │ dec_opcode.py 14 | │ de_br.py 15 | │ dy_code.py 16 | │ graphviz_tools.py 17 | │ header_less.py 18 | │ LICENSE 19 | │ llil.S 20 | │ plugin.json 21 | │ README.md 22 | │ symbolic_.py 23 | │ symbolic_libEncryptor.py 24 | │ symbolic_libEncryptor2.py 本次代码的主要入口 25 | │ symbolic_libEncryptor2_back.py 26 | │ symbolic_libEncryptor2_back2.py 27 | │ test_exe.py 28 | │ triton_test.py 29 | │ user_il.py 30 | │ utils.py 31 | │ VMEngine.py 32 | │ vm_data.json 33 | │ vm_tools.py 34 | │ work_flow.py 35 | │ __init__.py 36 | │ 37 | ├───doctest-output 38 | │ 100_8320FACB.gv 39 | │ 100_8320FACB.gv.pdf 40 | │ 101_13A50A15.gv 41 | │ 42 | ├───Vm 利用angr 捕获数据(比较核心) 43 | │ │ BinjaAst.py 44 | │ │ CONSTS.py 45 | │ │ VmExploration.py 46 | │ │ VMGlobalData.py 47 | │ │ VmState.py 48 | │ │ __init__.py 49 | 50 | 51 | ``` 52 | 53 | -------------------------------------------------------------------------------- /VMEngine.py: -------------------------------------------------------------------------------- 1 | import pyvex 2 | from angr.engines import UberEngine 3 | 4 | 5 | class VmEngine(UberEngine): 6 | 7 | def _handle_vex_expr_RdTmp(self, expr: pyvex.expr.RdTmp): 8 | return super()._handle_vex_expr_RdTmp(expr) 9 | -------------------------------------------------------------------------------- /Vm/CONSTS.py: -------------------------------------------------------------------------------- 1 | or_offset = 0x3920 2 | dispatcher_offset = 0x2cc8 3 | ip_increase_offset = 0x3a78 4 | external_call_offset = 0x3c28 5 | -------------------------------------------------------------------------------- /Vm/VMGlobalData.py: -------------------------------------------------------------------------------- 1 | # 全局唯一的 2 | import copy 3 | 4 | from angr.state_plugins import SimStateHistory 5 | 6 | from Vm import VmState 7 | 8 | 9 | class VMGlobalData(): 10 | def __init__(self, 11 | opcode2history=None, 12 | opcode_index2_ext_call=None, 13 | opcode_count=0, 14 | parent=None): 15 | 16 | self.opcode2history = {} if opcode2history is None else opcode2history 17 | self.opcode_index2_ext_call = {} if opcode_index2_ext_call is None else opcode_index2_ext_call 18 | self.opcode_count = opcode_count 19 | self.parent: VMGlobalData = None if parent is None else parent 20 | 21 | # self.history: "SimStateHistory" 22 | # print("VMGlobalData 初始化") 23 | 24 | @property 25 | def get_history(self): 26 | return self.opcode2history 27 | 28 | @property 29 | def history(self): 30 | # 如果有父类，优先获取父类的历史记录 31 | if self.parent: 32 | yield from self.parent.history # 递归获取父类的历史记录 33 | # 返回当前对象的历史记录 34 | yield from self.opcode2history.items() 35 | def set_history(self, vm_state: VmState, history: SimStateHistory): 36 | # self.opcode2history[f"{vm_state.opcode_count}_{vm_state.current_opcode:X}"] = history 37 | self.opcode2history[(vm_state.opcode_count,vm_state.current_opcode)] = history 38 | 39 | def add_opcode(self, opcode): 40 | self.opcode_count += 1 41 | 42 | # 记录外部调用的函数 43 | def record_ext_call(self,vm_state,ext_func_addr): 44 | self.opcode_index2_ext_call[(self.opcode_count, vm_state.current_opcode)] = ext_func_addr 45 | 46 | def add_branch(self, vm_state): 47 | self.branch.append((vm_state.opcode_count,vm_state.current_opcode)) 48 | # def __del__(self): 49 | # print(f'TestClas 对象被回收--- : {self.opcodes}') 50 | def __deepcopy__(self, memodict={}): 51 | # 检查对象是否已经在 memodict 中 52 | if id(self) in memodict: 53 | return memodict[id(self)] 54 | return VMGlobalData( 55 | opcode_count=self.opcode_count, 56 | parent=self, 57 | opcode_index2_ext_call=copy.deepcopy(self.opcode_index2_ext_call), 58 | ) 59 | -------------------------------------------------------------------------------- /Vm/VmExploration.py: -------------------------------------------------------------------------------- 1 | import copy 2 | import logging 3 | 4 | import angr 5 | import claripy 6 | from Vm.VmState import VmState 7 | from .CONSTS import * 8 | from pprint import pprint as pp 9 | 10 | l = logging.getLogger(name=__name__) 11 | class VmExploration(angr.ExplorationTechnique): 12 | def __init__(self,project_base_addr, stashes=('active', 'deferred', 'errored', 'cut')): 13 | super(VmExploration, self).__init__() 14 | self._stashes = stashes 15 | self.project_base_addr = project_base_addr 16 | self.trace_options = [ 17 | angr.options.TRACK_OP_ACTIONS, 18 | angr.options.TRACK_ACTION_HISTORY, 19 | # 记录 寄存器 操作 20 | angr.options.TRACK_REGISTER_ACTIONS, 21 | # 记录 中间变量的操作 22 | angr.options.TRACK_TMP_ACTIONS 23 | ] 24 | 25 | def setup(self, simgr): 26 | super().setup(simgr) 27 | # state.register_plugin("VmState", VmState()) 28 | simgr.stashes['active'][0].register_plugin('VmState', VmState()) 29 | 30 | def step(self, simgr, stash="active", **kwargs): 31 | 32 | super_ret = super().step(simgr, stash, **kwargs) 33 | return super_ret 34 | 35 | def mem_write(self,state: angr.SimState): 36 | 37 | _inspect: angr.state_plugins.inspect.SimInspector = state.inspect 38 | 39 | # step_state 调用 successors 40 | def step_state(self, simgr, state, **kwargs): 41 | solver = state.solver 42 | vm_state: VmState = state.VmState 43 | # print(f"step_state {state.addr:X}") 44 | match state.addr: 45 | case addr if addr == self.project_base_addr + or_offset: 46 | print(f"{hex(state.addr)} vreg {state.regs.w10} = {state.regs.x8} | {state.regs.x9}") 47 | case addr if addr == self.project_base_addr + dispatcher_offset: 48 | self._handle_dispatcher(state) 49 | case addr if addr == self.project_base_addr + ip_increase_offset: 50 | self._handle_ip_increase(state) 51 | case addr if addr == self.project_base_addr + external_call_offset: 52 | self._handle_external_func_call(state) 53 | case _: 54 | # super_ret = super().step_state(simgr, state, **kwargs) 55 | pass 56 | return super().step_state(simgr, state, **kwargs) 57 | 58 | def _handle_external_func_call(self,state): 59 | vm_state: VmState = state.VmState 60 | solver = state.solver 61 | x0 = solver.eval_one(state.regs.x0) 62 | x1 = solver.eval_one(state.regs.x1) 63 | vm_state.data.record_ext_call(vm_state,x0) 64 | l.error(f"调用外部函数[{hex(vm_state.current_opcode)}] x0 = 0x{x0:X}, x1 = 0x{x1:X}", ) 65 | def _handle_dispatcher(self,state : angr.SimState): 66 | solver = state.solver 67 | vm_state: VmState = state.VmState 68 | # 分发器开始 69 | # state.scratch.irsb.pp() 70 | # 读取 opcode 71 | x0 = state.regs.x0 72 | solver.eval_one(x0) 73 | opcode = state.memory.load(solver.eval_one(x0), 4).reversed 74 | opcode = solver.eval_one(opcode) 75 | 76 | # 调试代码 77 | # 如果代码没进入 ip++ 就直接重新分发了 78 | if vm_state.opcode_count !=0: 79 | # key = f"{vm_state.opcode_count}_{vm_state.current_opcode:X}" 80 | key = (vm_state.opcode_count,vm_state.current_opcode) 81 | if "exit" not in vm_state.enter_exit[key]: 82 | # 没进入 ip++ 就进入分发,只可能是 vm_exit 要么就应该报错 83 | exit_opcode = vm_state.exit_opcode 84 | if exit_opcode is None: 85 | # 还没找到 exit_opcode 就赋值 86 | # TODO 还没想好怎么处理 87 | vm_state.exit_opcode = opcode 88 | elif exit_opcode != vm_state.current_opcode: 89 | raise Exception("未知的opcode ,没有经过ip++就到了分发器") 90 | 91 | 92 | # 函数调用 返回无约束 防止陷入函数 (vm会调用别的vm) 93 | state.options.add(angr.options.CALLLESS) 94 | state.options.update(self.trace_options) 95 | 96 | 97 | vm_state.add_opcode(opcode) 98 | # 这里不清空的话会出现一些 上一次opcode的action 可能是angr自带的一些 option 才导致记录的action 99 | state.history.trim() 100 | 101 | 102 | # self.enter_exit[f"{self.opcode_count}_{self.current_opcode:X}"] =["enter"] 103 | # 必须放后面 104 | vm_state.enter_exit[(vm_state.opcode_count,vm_state.current_opcode)] =["enter"] 105 | 106 | def _handle_ip_increase(self,state): 107 | vm_state: VmState = state.VmState 108 | # ip++ 109 | # 这里就是 当前opcode 执行结束的位置 110 | # 需要赋值新的 vmState 来让 一个 vmState 对应一个opcode 111 | # vm_state.dataClass.add_state(vm_state) 112 | if vm_state.current_opcode == 0x8b0428: 113 | pass 114 | x19: claripy.ast.bv.BV = state.regs.x19 115 | flag_value = state.mem[x19.concrete_value - 0x20].uint64_t.concrete 116 | 117 | if flag_value != 0: 118 | external_func_addr = state.mem[x19.concrete_value - 0x18].uint64_t.concrete 119 | l.warning(f"[{vm_state.current_opcode:X}]未知标志位 {flag_value} , {external_func_addr:X}") 120 | 121 | # vm_state.enter_exit[f"{vm_state.opcode_count}_{vm_state.current_opcode:X}"].append("exit") 122 | vm_state.enter_exit[(vm_state.opcode_count,vm_state.current_opcode)].append("exit") 123 | vm_state.get_data.set_history(vm_state, state.history) 124 | # 清空 记录的 action 125 | state.history.trim() 126 | 127 | # 从 ip++ 到重新回到分发器的过程,可能会调用 外部函数 需要特殊处理 128 | # 目前来看 只需要知道调用了 外部函数就可以了 129 | new_options = state.options.difference(self.trace_options) 130 | state.options = new_options 131 | def successors(self, simgr, state, **kwargs): 132 | super_ret = super().successors(simgr, state, **kwargs) 133 | 134 | for exit_state in list(super_ret.all_successors): 135 | exit_jumpkind = exit_state.history.jumpkind if exit_state.history.jumpkind else "" 136 | solver = exit_state.solver 137 | 138 | if exit_jumpkind == "Ijk_Call": 139 | x0 = solver.eval_one(exit_state.regs.x0) 140 | x1 = solver.eval_one(exit_state.regs.x1) 141 | 142 | l.error(f"调用外部函数[{hex(exit_state.addr)}] x0 = 0x{x0:X}, x1 = 0x{x1:X}",) 143 | 144 | # 当前 state 执行完之后产生了 两个分支的话 需要赋值 赋值一个全新的 VMGlobalData 145 | successor_len = len(super_ret.successors) 146 | match successor_len: 147 | case 2: 148 | for succ_state in super_ret.successors: 149 | vm_state: VmState = succ_state.VmState 150 | vm_state.data = copy.deepcopy(succ_state.VmState.data) 151 | vm_state.add_branch_record() 152 | 153 | case 1: 154 | pass 155 | case _: 156 | raise Exception("未处理异常") 157 | return super_ret 158 | 159 | -------------------------------------------------------------------------------- /Vm/VmState.py: -------------------------------------------------------------------------------- 1 | import opcode 2 | 3 | from angr import SimStatePlugin, SimState 4 | 5 | from Vm.VMGlobalData import VMGlobalData 6 | import copy 7 | 8 | 9 | # 10 | # class VmState(SimStatePlugin): 11 | # 12 | # def __init__(self, clone=None, opcodes=None, data_class=None, branch_stream=None): 13 | # super().__init__() 14 | # 15 | # if clone is None: 16 | # self.opcode = opcode 17 | # self.dataClass = VMGlobalData() if data_class is None else data_class 18 | # self.branch_stream = [0] if branch_stream is None else branch_stream 19 | # self.opcodes = [] if opcodes is None else opcodes 20 | # else: 21 | # self.opcode = clone.opcode 22 | # self.dataClass = clone.dataClass 23 | # self.branch_stream = clone.branch_stream 24 | # self.opcodes = clone.opcodes 25 | # 26 | # @property 27 | # def data(self): 28 | # return self.dataClass 29 | # def set_opcode(self, op_code): 30 | # self.opcode = op_code 31 | # 32 | # def add_opcodes(self, _opcode): 33 | # self.opcodes.append(_opcode) 34 | # 35 | # def add_new_branch_stream(self): 36 | # # copy.deepcopy(dataClass) 37 | # self.branch_stream.append(self.branch_stream[-1] + 1) 38 | # 39 | # def set_vm_global_data(self, dataClass: VMGlobalData): 40 | # # copy.deepcopy(dataClass) 41 | # self.dataClass = VMGlobalData(dataClass.vmStates) 42 | # 43 | # # copy 比 init_state 先调用 44 | # @SimStatePlugin.memo 45 | # def copy(self, memo): # pylint: disable=unused-argument 46 | # return VmState(clone=self, opcodes=self.opcodes) 47 | # 48 | # def init_state(self): 49 | # super().init_state() 50 | 51 | # self.opcodes.append(opcode) 52 | # 符号执行的过程会一直 创建state 然后再销毁 所以不适合放大量数据 history 会一直复制数据 53 | # def __del__(self): 54 | # print(f'VmState 对象被回收--- : {self.opcodes}') 55 | 56 | 57 | class VmState(SimStatePlugin): 58 | 59 | def __init__(self, clone=None): 60 | SimStatePlugin.__init__(self) 61 | if clone is None: 62 | self.opcodes = [] 63 | self.current_opcode = None 64 | self.data = VMGlobalData() 65 | self.opcode_count = 0 66 | self.enter_exit = {} 67 | self.exit_opcode = None 68 | self.branch = [] 69 | else: 70 | 71 | self.current_opcode = clone.current_opcode 72 | self.opcode_count = clone.opcode_count 73 | self.enter_exit = copy.deepcopy(clone.enter_exit) 74 | self.branch = copy.deepcopy(clone.branch) 75 | # 这里不能用浅拷贝,不然会导致state共享这个变量 76 | # self.opcodes = clone.opcodes 77 | self.opcodes = copy.deepcopy(clone.opcodes) 78 | # 在 angr符号执行过程会一直复制 state,这里先 浅拷贝,共享 VMGlobalData,出现分支再深拷贝 79 | self.data : VMGlobalData = clone.data 80 | self.exit_opcode = clone.exit_opcode 81 | 82 | def add_opcode(self, _opcode): 83 | self.opcode_count+=1 84 | 85 | self.current_opcode = _opcode 86 | 87 | # self.enter_exit[f"{self.opcode_count}_{self.current_opcode:X}"] =["enter"] 88 | # self.opcodes.append(_opcode) 89 | self.data.add_opcode(_opcode) 90 | print("add_opcode",hex(_opcode),self.opcode_count) 91 | 92 | def add_branch_record(self): 93 | self.branch.append((self.opcode_count, self.current_opcode)) 94 | 95 | # copy 比 init_state 先调用 96 | @SimStatePlugin.memo 97 | def copy(self, memo): # pylint: disable=unused-argument 98 | return VmState(clone=self) 99 | 100 | # 为了后面写代码有提示 101 | @property 102 | def get_data(self) -> VMGlobalData: 103 | return self.data 104 | # SimState.register_default('vmState', VmState) 105 | -------------------------------------------------------------------------------- /Vm/__init__.py: -------------------------------------------------------------------------------- 1 | from .VmState import VmState 2 | from .VmExploration import VmExploration 3 | from .VMGlobalData import VMGlobalData 4 | 5 | -------------------------------------------------------------------------------- /Vm/__pycache__/BinjaAst.cpython-311.pyc: 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1 | // The Round Table 2 | digraph "100_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "100_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "100_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/100_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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Round Table 2 | digraph "109_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "109_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "109_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/109_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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The Round Table 2 | digraph "117_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "117_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "117_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/117_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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Round Table 2 | digraph "144_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "144_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "144_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/144_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "156_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/156_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/156_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/157_22021CB.gv.pdf: -------------------------------------------------------------------------------- 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x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "161_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/161_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/161_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/162_22021CB.gv.pdf: -------------------------------------------------------------------------------- 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Table 2 | digraph "53_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "53_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "53_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/53_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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- 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "60_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/60_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/60_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/61_2E021CB.gv.pdf: -------------------------------------------------------------------------------- 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x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "66_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/66_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/66_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/67_3C021CB.gv.pdf: -------------------------------------------------------------------------------- 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43 | llil -> x0#2 + 8 44 | " 45 | "73_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/73_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/73_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/74_3C021CB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/74_3C021CB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/75_17B50417.gv.pdf: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/83_8200C1CB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/84_8320FACB.gv: -------------------------------------------------------------------------------- 1 | // The Round Table 2 | digraph "84_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "84_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "84_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/84_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/84_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/85_17A50415.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/85_17A50415.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/86_6710015.gv.pdf: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/89_8200C1CB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/8_1FB30617.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/8_1FB30617.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/90_8320FACB.gv: -------------------------------------------------------------------------------- 1 | // The Round Table 2 | digraph "90_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "90_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "90_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /Vm/doctest-output/90_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/90_8320FACB.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/91_3C021CB.gv.pdf: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/9_1FB20417.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/ADD sp, sp, #-0x210.gv: -------------------------------------------------------------------------------- 1 | // The Round Table 2 | digraph "ADD sp, sp, #-0x210" { 3 | "6 4 | operation=LLIL_SUB 5 | llil=x19#1 - 0x138 6 | " -> "7 7 | stop_reg=x19 8 | " 9 | "6 10 | operation=LLIL_SUB 11 | llil=x19#1 - 0x138 12 | " -> "8 13 | value=312 14 | " 15 | "5 16 | llil=x21#1 = x19#1 - 0x138 17 | " -> "6 18 | operation=LLIL_SUB 19 | llil=x19#1 - 0x138 20 | " 21 | "4 22 | llil=x21#1 23 | " -> "5 24 | llil=x21#1 = x19#1 - 0x138 25 | " 26 | "3 27 | operation=LLIL_ADD 28 | llil=x21#1 + 8 29 | " -> "4 30 | llil=x21#1 31 | " 32 | "3 33 | operation=LLIL_ADD 34 | llil=x21#1 + 8 35 | " -> "9 36 | value=8 37 | " 38 | "2 39 | llil=x11#42 = x21#1 + 8 40 | " -> "3 41 | operation=LLIL_ADD 42 | llil=x21#1 + 8 43 | " 44 | "1 45 | llil=x11#42 46 | " -> "2 47 | llil=x11#42 = x21#1 + 8 48 | " 49 | "0 50 | operation=LLIL_ADD 51 | llil=x11#42 + (zx.q(x8#11.w8) << 3) 52 | " -> "1 53 | llil=x11#42 54 | " 55 | "11 56 | ext=LLIL_ZX 57 | llil=zx.q(x8#11.w8) 58 | " -> "12 59 | reg=w8 60 | " 61 | "10 62 | operation=LLIL_LSL 63 | llil=zx.q(x8#11.w8) << 3 64 | " -> "11 65 | ext=LLIL_ZX 66 | llil=zx.q(x8#11.w8) 67 | " 68 | "10 69 | operation=LLIL_LSL 70 | llil=zx.q(x8#11.w8) << 3 71 | " -> "13 72 | value=3 73 | " 74 | "0 75 | operation=LLIL_ADD 76 | llil=x11#42 + (zx.q(x8#11.w8) << 3) 77 | " -> "10 78 | operation=LLIL_LSL 79 | llil=zx.q(x8#11.w8) << 3 80 | " 81 | "ADD sp, sp, #-0x210" -> "0 82 | operation=LLIL_ADD 83 | llil=x11#42 + (zx.q(x8#11.w8) << 3) 84 | " 85 | "26 86 | operation=LLIL_SUB 87 | llil=x19#1 - 0x138 88 | " -> "27 89 | stop_reg=x19 90 | " 91 | "26 92 | operation=LLIL_SUB 93 | llil=x19#1 - 0x138 94 | " -> "28 95 | value=312 96 | " 97 | "25 98 | llil=x21#1 = x19#1 - 0x138 99 | " -> "26 100 | operation=LLIL_SUB 101 | llil=x19#1 - 0x138 102 | " 103 | "24 104 | llil=x21#1 105 | " -> "25 106 | llil=x21#1 = x19#1 - 0x138 107 | " 108 | "23 109 | operation=LLIL_ADD 110 | llil=x21#1 + 8 111 | " -> "24 112 | llil=x21#1 113 | " 114 | "23 115 | operation=LLIL_ADD 116 | llil=x21#1 + 8 117 | " -> "29 118 | value=8 119 | " 120 | "22 121 | llil=x11#42 = x21#1 + 8 122 | " -> "23 123 | operation=LLIL_ADD 124 | llil=x21#1 + 8 125 | " 126 | "21 127 | llil=x11#42 128 | " -> "22 129 | llil=x11#42 = x21#1 + 8 130 | " 131 | "20 132 | operation=LLIL_ADD 133 | llil=x11#42 + (zx.q(x9#6.w9) << 3) 134 | " -> "21 135 | llil=x11#42 136 | " 137 | "31 138 | ext=LLIL_ZX 139 | llil=zx.q(x9#6.w9) 140 | " -> "32 141 | reg=w9 142 | " 143 | "30 144 | operation=LLIL_LSL 145 | llil=zx.q(x9#6.w9) << 3 146 | " -> "31 147 | ext=LLIL_ZX 148 | llil=zx.q(x9#6.w9) 149 | " 150 | "30 151 | operation=LLIL_LSL 152 | llil=zx.q(x9#6.w9) << 3 153 | " -> "33 154 | value=3 155 | " 156 | "20 157 | operation=LLIL_ADD 158 | llil=x11#42 + (zx.q(x9#6.w9) << 3) 159 | " -> "30 160 | operation=LLIL_LSL 161 | llil=zx.q(x9#6.w9) << 3 162 | " 163 | "19 164 | operation=LLIL_LOAD_SSA 165 | llil=[x11#42 + (zx.q(x9#6.w9) << 3)].q @ mem#26 166 | " -> "20 167 | operation=LLIL_ADD 168 | llil=x11#42 + (zx.q(x9#6.w9) << 3) 169 | " 170 | "18 171 | llil=x9#61 = [x11#42 + (zx.q(x9#6.w9) << 3)].q @ mem#26 172 | " -> "19 173 | operation=LLIL_LOAD_SSA 174 | llil=[x11#42 + (zx.q(x9#6.w9) << 3)].q @ mem#26 175 | " 176 | "17 177 | llil=x9#61 178 | " -> "18 179 | llil=x9#61 = [x11#42 + (zx.q(x9#6.w9) << 3)].q @ mem#26 180 | " 181 | "16 182 | operation=LLIL_ADD 183 | llil=x9#61 + sx.q((x10#52.w10).w) 184 | " -> "17 185 | llil=x9#61 186 | " 187 | "34 188 | ext=LLIL_SX 189 | llil=sx.q((x10#52.w10).w) 190 | " -> "35 191 | reg=w10 192 | " 193 | "16 194 | operation=LLIL_ADD 195 | llil=x9#61 + sx.q((x10#52.w10).w) 196 | " -> "34 197 | ext=LLIL_SX 198 | llil=sx.q((x10#52.w10).w) 199 | " 200 | "15 201 | llil=x9#62 = x9#61 + sx.q((x10#52.w10).w) 202 | " -> "16 203 | operation=LLIL_ADD 204 | llil=x9#61 + sx.q((x10#52.w10).w) 205 | " 206 | "14 207 | llil=x9#62 208 | " -> "15 209 | llil=x9#62 = x9#61 + sx.q((x10#52.w10).w) 210 | " 211 | "ADD sp, sp, #-0x210" -> "14 212 | llil=x9#62 213 | " 214 | } 215 | -------------------------------------------------------------------------------- /Vm/doctest-output/ADD sp, sp, #-0x210.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/ADD sp, sp, #-0x210.gv.pdf -------------------------------------------------------------------------------- /Vm/doctest-output/extra_info_match.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/Vm/doctest-output/extra_info_match.gv.pdf -------------------------------------------------------------------------------- /__init__.py: -------------------------------------------------------------------------------- 1 | from binaryninja import * 2 | 3 | from .header_less import print_jump_target 4 | # from .header_less import Arm64RetHook 5 | from .work_flow import cus_workflow 6 | from .user_il import create_user_func 7 | 8 | 9 | pwf = Workflow().clone("PythonLogWarnWorkflow") 10 | pwf.show_topology() 11 | pwf.register_activity(Activity("PythonLogWarn", action=cus_workflow)) 12 | # pwf.insert("core.function.translateTailCalls", ["PythonLogWarn"]) 13 | pwf.insert("core.function.generateMediumLevelIL", ["PythonLogWarn"]) 14 | pwf.register() 15 | 16 | 17 | title = "启动自定义workflow" 18 | description = "启动自定义workflow" 19 | properties = f'{{"title" : "{title}", "description" : "{description}", "type" : "boolean", "default" : false}}' 20 | _settings = Settings() 21 | _settings.register_group("zhuzhu", "My Plugin") 22 | _settings.register_setting("zhuzhu.workFlow", properties) 23 | 24 | def plugin_main(bv: BinaryView,func): 25 | # print(bv.arch.regs) 26 | # print_jump_target(bv) 27 | 28 | create_user_func(bv) 29 | # if Settings().get_bool("zhuzhu.workFlow"): 30 | # _settings.set_bool("zhuzhu.workFlow", False) 31 | # else: 32 | # _settings.set_bool("zhuzhu.workFlow", True) 33 | # is_enbale_custom_workflow = Settings().get_bool("zhuzhu.workFlow") 34 | # log_info("zhuzhu.custom_workflow : {}".format(is_enbale_custom_workflow)) 35 | # 36 | # bv.get_functions_containing(0x9cc7c)[0].reanalyze() 37 | # PluginCommand.register("ROP\\Create ROP Function", "Make some space for your ROP", plugin_main) 38 | PluginCommand.register_for_function("切换workflow状态", "Make some space for your ROP", plugin_main) 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /__pycache__/VMEngine.cpython-311.pyc: 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/__pycache__/work_flow.cpython-310.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/__pycache__/work_flow.cpython-310.pyc -------------------------------------------------------------------------------- /__pycache__/work_flow.cpython-311.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/__pycache__/work_flow.cpython-311.pyc -------------------------------------------------------------------------------- /angr_tools.py: -------------------------------------------------------------------------------- 1 | 2 | 3 | def collect_action_info(found_state,start_address): 4 | addrs = [] 5 | index = 0 6 | addr2action = { 7 | 8 | } 9 | for action in found_state.history.actions: 10 | real_addr = action.ins_addr - start_address 11 | 12 | if index != 0 and addrs[index - 1] == real_addr: 13 | addr2action[real_addr].append(action) 14 | continue 15 | addrs.append(real_addr) 16 | addr2action[real_addr] = [] 17 | addr2action[real_addr].append(action) 18 | index += 1 19 | 20 | return addrs,addr2action -------------------------------------------------------------------------------- /arch_hook.py: -------------------------------------------------------------------------------- 1 | from binaryninja.architecture import Architecture, ArchitectureHook 2 | from capstone import * 3 | from binaryninja import * 4 | import binaryninja._binaryninjacore as core 5 | md = Cs(CS_ARCH_ARM64, CS_MODE_ARM) 6 | md.detail = True 7 | 8 | 9 | 10 | 11 | 12 | 13 | class Arm64RetHook(ArchitectureHook): 14 | 15 | def __init__(self, base_arch): 16 | super(Arm64RetHook, self).__init__(base_arch) 17 | 18 | # def get_instruction_info(self, data, addr): 19 | # info = super(Arm64RetHook, self).get_instruction_info(data, addr) 20 | # branches = info.branches 21 | # # So dataflow doesn't stop at a return 22 | # for b in branches: 23 | # if b.type == BranchType.FunctionReturn: 24 | # b.type = BranchType.UnresolvedBranch 25 | # info.branches = branches 26 | # return info 27 | 28 | def get_instruction_low_level_il(self, data, addr, il: LowLevelILFunction): 29 | insn = md.disasm(data, addr) 30 | il.handle 31 | if addr == 0x9cc58: 32 | core.BNLowLevelILAddExprWithLocation(il.handle,LowLevelILOperation.LLIL_SET_REG) 33 | # nzcv_reg = self.get_reg_index("nzcv") 34 | il 35 | # il.set_flag() 36 | il.append(il.set_reg(4, "nzcv",il.reg(4,"nzcv"))) 37 | # il.append(il.set_reg(16,"w1",il.const(16,2))) 38 | # return 4 39 | 40 | return super(Arm64RetHook, self).get_instruction_low_level_il(data, addr, il) 41 | -------------------------------------------------------------------------------- /data.json: -------------------------------------------------------------------------------- 1 | { 2 | "642172":{ 3 | "cmp_addr":642148, 4 | "true_addr":642176, 5 | "false_addr":642188 6 | }, 7 | "642184":{ 8 | "cmp_addr":642168, 9 | "true_addr":642224, 10 | "false_addr":642172 11 | }, 12 | "642196":{ 13 | "cmp_addr":642136, 14 | "true_addr":642200, 15 | "false_addr":642212 16 | }, 17 | "642208":{ 18 | "cmp_addr":642156, 19 | "true_addr":642248, 20 | "false_addr":642172 21 | }, 22 | "642220":{ 23 | "cmp_addr":642140, 24 | "true_addr":642296, 25 | "false_addr":642172 26 | }, 27 | "procedure_addr":[ 28 | 642176, 29 | 642148, 30 | 642180, 31 | 642212, 32 | 642152, 33 | 642216, 34 | 642188, 35 | 642156, 36 | 642140, 37 | 642192, 38 | 642164, 39 | 642168, 40 | 642136, 41 | 642204, 42 | 642200 43 | ], 44 | "reg2values":{ 45 | "642076":{ 46 | "w15":2736531929 47 | }, 48 | "642080":{ 49 | "w22":1482094495 50 | }, 51 | "642084":{ 52 | "w23":1104611000 53 | }, 54 | "642112":{ 55 | "x21":-206106152 56 | }, 57 | "642128":{ 58 | "w12":2736531929 59 | }, 60 | "642132":{ 61 | "w22":1482094495 62 | }, 63 | "642144":{ 64 | "w23":1104611000 65 | }, 66 | "642160":{ 67 | "w15":2736531929 68 | }, 69 | "642240":{ 70 | "w23":1104611000, 71 | "w22":1482094495 72 | }, 73 | "642284":{ 74 | "w15":2736531929 75 | } 76 | } 77 | } -------------------------------------------------------------------------------- /data.py: -------------------------------------------------------------------------------- 1 | global_war = 0 -------------------------------------------------------------------------------- /de_br.py: -------------------------------------------------------------------------------- 1 | aaa=0 -------------------------------------------------------------------------------- /dec_opcode.py: -------------------------------------------------------------------------------- 1 | import os 2 | 3 | # 4 | # for i in range(int(0x538/8)): 5 | # print(hex(int(i*8))) 6 | import struct 7 | 8 | pcode_start = 0xB090 9 | pcode_size = 0x2D8 10 | with open(r"D:\window\AndroidRe\ttEncrypt\libEncryptor.so", "rb") as f: 11 | content = f.read() 12 | bytes_code = content[pcode_start: pcode_start + pcode_size] 13 | def un(): 14 | 15 | insts_sets = {} 16 | for pc in range(0, pcode_size, 4): 17 | word = struct.unpack(" 0: 19 | opcode = word[0] 20 | op1 = opcode & 0x3F 21 | if insts_sets.get(op1, None) == None: 22 | insts_sets[op1] = 1 23 | else: 24 | insts_sets[op1] += 1 25 | sorted_dict = dict(sorted(insts_sets.items(), key=lambda item: item[1], reverse=True)) 26 | for inst, count in sorted_dict.items(): 27 | print(f'op1: {inst} [{hex(inst)}], count: {count}', hex(0xab24 + (inst << 2))) 28 | 29 | 30 | def pb(value): 31 | binary_representation = f"{value:032b}" 32 | header = "" 33 | for i in range(32): 34 | _str = f"{i:<3d}" 35 | header = f"{_str}{header}" 36 | header+="\r\n" 37 | for i in range(32): 38 | _str = f"{binary_representation[i]:<3s}" 39 | header+=_str 40 | print(header) 41 | # Rotate left: 0b1001 --> 0b0011 42 | rol = lambda val, r_bits, max_bits: \ 43 | (val << r_bits%max_bits) & (2**max_bits-1) | \ 44 | ((val & (2**max_bits-1)) >> (max_bits-(r_bits%max_bits))) 45 | # Rotate right: 0b1001 --> 0b1100 46 | ror = lambda val, r_bits, max_bits: \ 47 | ((val & (2**max_bits-1)) >> r_bits%max_bits) | \ 48 | (val << (max_bits-(r_bits%max_bits)) & (2**max_bits-1)) 49 | def get_imm16(opcode, sign=True): 50 | # opcode[15-12] | opcode[31->11] | opcode[30->10] | opcode[29->9] | opcode[28->8] | opcode[27->7] | opcode[26->6] | opcode[11-6->5-0] 51 | result = (opcode & 0xF000) | (opcode >> 20 & 0xFC0) | (opcode >> 6 & 0x3F) 52 | if result & 0x8000 and sign: 53 | return result | ~0xFFFF 54 | else: 55 | return result 56 | 57 | 58 | def get_openand1(opcode): 59 | # w8 60 | return opcode >> 16 & 0x1F 61 | 62 | 63 | def get_operand2(opcode): 64 | # w9 65 | return opcode >> 21 & 0x1F 66 | 67 | 68 | def get_operand3(opcode): 69 | # w10 70 | return ((opcode & 0xF000) >> 11) | \ 71 | opcode >> 31 72 | 73 | 74 | def get_operand4(opcode): 75 | # w11 76 | return opcode >> 26 & 0x1F 77 | 78 | def get_op1(opcode): 79 | return opcode & 0x3F 80 | def outer_decode(): 81 | for pc in range(0, pcode_size, 4): 82 | word = struct.unpack(" 0: 84 | 85 | opcode = word[0] 86 | print(hex(opcode),",") 87 | op1 = get_op1(opcode) 88 | Xt = get_openand1(opcode) # x8/w8 89 | Xn = get_operand2(opcode) # x9/w9 90 | Xm = get_operand3(opcode) # x10/w10 91 | X4 = get_operand4(opcode) # x11/w11 92 | 93 | # if opcode == 94 | match op1: 95 | case 11: 96 | jump_key = ror(((opcode & 0xfff) - 0xb),6,32) 97 | print(f'opcode[1]:{opcode & 0x3f} hex(bv.parse_expression("(([0xa6a0 + {hex((opcode & 0x3f) << 2)}].d)+0xa6a0) & 0xffffffff")) ') 98 | print(f'opcode[2]:{opcode & 0x3f} hex(bv.parse_expression("(([0xadb0 + {hex(jump_key << 2)}].d)+0xadb0) & 0xffffffff")) ') 99 | 100 | case 23: 101 | 102 | 103 | print(f'opcode[1]:{opcode & 0x3f} hex(bv.parse_expression("(([0xa6a0 + {hex((opcode & 0x3f) << 2)}].d)+0xa6a0) & 0xffffffff")) ') 104 | print(f'opcode[2]:{opcode & 0x3f} hex(bv.parse_expression("(([0xab24 + {hex(((opcode & 0x3f) - 0x14) << 2)}].d)+0xab24) & 0xffffffff")) ') 105 | print(f"opcode: str {op1}[{hex(op1)}] Xt:{Xt:>2d} Xn:{Xn:>2d} imm:{hex(get_imm16(opcode))} ") 106 | pass 107 | case 21: 108 | print(f'opcode[1]:{opcode & 0x3f} hex(bv.parse_expression("(([0xa6a0 + {hex((opcode & 0x3f) << 2)}].d)+0xa6a0) & 0xffffffff")) ') 109 | print(f"opcode: add {op1}[{hex(op1)}] Xt:{Xt:>2d} Xn:{Xn:>2d} imm:{hex(get_imm16(opcode))} ") 110 | pass 111 | aaa=0 112 | # 0x2e50 0x3380 113 | 114 | # print(f'opcode[2]:{w12 & 0x3f} hex(bv.parse_expression("(([0xab24 + {hex(((w12 & 0x3f)-0x14)<<2)}].d)+0xab24) & 0xffffffff")) ') 115 | 116 | 117 | 118 | outer_decode() 119 | # hex(0xffffffff & bv.parse_expression("[0xa6fc].d")+0xa6a0) 120 | # hex(0xffffffff & bv.parse_expression("[0xa6fc].d")+0xab24) -------------------------------------------------------------------------------- /doctest-output/100_8320FACB.gv: -------------------------------------------------------------------------------- 1 | // The Round Table 2 | digraph "100_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "100_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "100_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/100_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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digraph "109_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "109_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "109_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/109_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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digraph "117_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "117_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "117_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/117_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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| llil -> x0#2 + 8 44 | " 45 | "126_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/126_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/126_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/127_FA50815.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/127_FA50815.gv.pdf -------------------------------------------------------------------------------- /doctest-output/128_2610995.gv.pdf: -------------------------------------------------------------------------------- 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digraph "144_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "144_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "144_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/144_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "156_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/156_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/156_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/157_22021CB.gv.pdf: -------------------------------------------------------------------------------- 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21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "161_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/161_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/161_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/162_22021CB.gv.pdf: -------------------------------------------------------------------------------- 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| llil -> x0#2 + 8 44 | " 45 | "166_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/166_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/166_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/167_22021CB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/167_22021CB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/168_1FB00028.gv.pdf: -------------------------------------------------------------------------------- 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" 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "53_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/53_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/53_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/54_3AC0217.gv.pdf: -------------------------------------------------------------------------------- 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llil -> x0#2 + 8 44 | " 45 | "60_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/60_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/60_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/61_2E021CB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/61_2E021CB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/62_1BA50415.gv.pdf: -------------------------------------------------------------------------------- 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llil -> x0#2 + 8 44 | " 45 | "66_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/66_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/66_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/67_3C021CB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/67_3C021CB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/68_1BA50015.gv.pdf: -------------------------------------------------------------------------------- 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"73_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "73_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "73_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/73_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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"84_8320FACB" { 3 | "0 4 | 3550 5 | operation -> LLIL_ADD 6 | llil -> x19#1 - 0x10 7 | " -> "1 8 | stop_reg -> x19 9 | " 10 | "0 11 | 3550 12 | operation -> LLIL_ADD 13 | llil -> x19#1 - 0x10 14 | " -> "2 15 | value -> -16 16 | " 17 | "84_8320FACB" -> "0 18 | 3550 19 | operation -> LLIL_ADD 20 | llil -> x19#1 - 0x10 21 | " 22 | "4 23 | 441C 24 | operation -> LLIL_ADD 25 | llil -> x0#2 + 8 26 | " -> "5 27 | stop_reg -> x0 28 | " 29 | "4 30 | 441C 31 | operation -> LLIL_ADD 32 | llil -> x0#2 + 8 33 | " -> "6 34 | value -> 8 35 | " 36 | "3 37 | 3550 38 | reg -> x8 39 | llil -> x8#260 40 | " -> "4 41 | 441C 42 | operation -> LLIL_ADD 43 | llil -> x0#2 + 8 44 | " 45 | "84_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/84_8320FACB.gv.pdf: -------------------------------------------------------------------------------- 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llil -> x0#2 + 8 44 | " 45 | "90_8320FACB" -> "3 46 | 3550 47 | reg -> x8 48 | llil -> x8#260 49 | " 50 | } 51 | -------------------------------------------------------------------------------- /doctest-output/90_8320FACB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/90_8320FACB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/91_3C021CB.gv.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/doctest-output/91_3C021CB.gv.pdf -------------------------------------------------------------------------------- /doctest-output/92_7BE0215.gv.pdf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /graphviz_tools.py: -------------------------------------------------------------------------------- 1 | import graphviz 2 | 3 | 4 | def generate_dot_for_llil_var(root: str, tree: dict): 5 | dot = graphviz.Digraph(f'{root}', comment='The Round Table') 6 | index = 0 7 | 8 | def _fill_content(parent=None, _tree=None): 9 | nonlocal index 10 | if parent is None: 11 | if tree.get("left_child") is not None: 12 | left = _fill_content("root", tree["left_child"]) 13 | dot.edge(root, left) 14 | if tree.get("right_child") is not None: 15 | right = _fill_content("root", tree["right_child"]) 16 | dot.edge(root, right) 17 | if tree.get("child"): 18 | child = _fill_content("root", tree["child"]) 19 | dot.edge(root, child) 20 | else: 21 | llil = _tree["il"] 22 | current_node_text = f"{index}\n{hex(llil.address)}\n{llil.operation.name}\n{str(llil)}" 23 | index += 1 24 | if _tree.get("left_child") is not None: 25 | left = _fill_content(current_node_text, _tree["left_child"]) 26 | dot.edge(current_node_text, left) 27 | if _tree.get("right_child") is not None: 28 | right = _fill_content(current_node_text, _tree["right_child"]) 29 | dot.edge(current_node_text, right) 30 | 31 | if _tree.get("child"): 32 | child = _fill_content(current_node_text, _tree["child"]) 33 | dot.edge(current_node_text, child) 34 | 35 | return current_node_text 36 | 37 | _fill_content() 38 | 39 | dot.render(directory='doctest-output', view=True) 40 | 41 | 42 | if __name__ == '__main__': 43 | dot = graphviz.Digraph('hello') 44 | -------------------------------------------------------------------------------- /plugin.json: -------------------------------------------------------------------------------- 1 | { 2 | "pluginmetadataversion": 2, 3 | "name": "deobf", 4 | "type": [ 5 | "core", 6 | "ui", 7 | "architecture", 8 | "binaryview", 9 | "helper" 10 | ], 11 | "api": [ 12 | "python3" 13 | ], 14 | "description": "deobf", 15 | "longdescription": "deobf tx libtprt's obfuscation", 16 | "license": { 17 | "name": "GPL-3.0", 18 | "text": "Copyright (c) 2024 <0xEEEE>\n\nPermission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n" 19 | }, 20 | "platforms": [ 21 | "Darwin", 22 | "Linux", 23 | "Windows" 24 | ], 25 | "installinstructions": { 26 | "Darwin": "Install `unicorn` using pip : `pip install setuptools unicorn`", 27 | "Linux": "Install `unicorn` using pip : `pip install setuptools unicorn`", 28 | "Windows": "Install `unicorn` using pip : `pip install setuptools unicorn`" 29 | }, 30 | "dependencies": { 31 | }, 32 | "version": "1.0.0", 33 | "author": "0xEEEE", 34 | "minimumbinaryninjaversion": 5571 35 | } 36 | -------------------------------------------------------------------------------- /symbolic_.py: -------------------------------------------------------------------------------- 1 | from angr import SimulationManager 2 | import angr 3 | from queue import Queue 4 | from angr.procedures.procedure_dict import SIM_PROCEDURES 5 | from pyvex.lifting.util import JumpKind 6 | 7 | 8 | def loop_state(simgr : SimulationManager): 9 | 10 | # if simgr.successors(state).is_empty: 11 | # return 12 | new_state = simgr.step() 13 | while len(simgr.active) > 0: 14 | for active_index,active in enumerate(simgr.active): 15 | for index,suc in enumerate(new_state.successors(active)): 16 | print(hex(active.addr),f" - [{active_index}][{index}]-> " ,hex(suc.addr)) 17 | print("*"*10) 18 | new_state = simgr.step() 19 | # for index,active_state in enumerate(simgr.active): 20 | # print(hex(state.addr) ,f" - [{index}]-> " , hex(active_state.addr)) 21 | # loop_state(simgr,active_state) 22 | 23 | project = angr.Project('D:/TMP/libtprt.so', load_options={"auto_load_libs": False}) 24 | 25 | def get_dispatcher_state(function): 26 | state = project.factory.call_state(addr=function) 27 | # Ignore function calls 28 | # https://github.com/angr/angr/issues/723 29 | state.options.add(angr.options.CALLLESS) 30 | simgr = project.factory.simulation_manager(state) 31 | # Find the dispatcher 32 | # while True: 33 | # simgr.step() 34 | # assert len(simgr.active) == 1 35 | # state = simgr.active[0] 36 | # if state.addr == dispatcher: 37 | # return state.copy() 38 | # 直接使用上面的 strp无法停在分发器的开始位置,所以不能按照文章上的写 39 | simgr.explore(find=dispatcher_addr) 40 | if simgr.found: 41 | _init = simgr.found[0] 42 | return _init.copy() 43 | else: 44 | raise Exception("未找到分发器") 45 | 46 | def find_successors(state_value, dispatcher,debug = False): 47 | state = dispatcher_state.copy() 48 | setattr(state.regs,state_register_name,state.solver.BVV(state_value, 64)) 49 | simgr = project.factory.simulation_manager(state) 50 | # 必须先step一下 不然就直接结束了 51 | new_sm = simgr.step() 52 | back_state = new_sm.active[0] 53 | 54 | if debug and state_value == 0xf3498be1: 55 | print(hex(state.addr)," -> ",hex(back_state.addr)) 56 | while True: 57 | simgr.step() 58 | find_state = simgr.active[0] 59 | print(hex(simgr.active[0].addr)) 60 | pass 61 | new_sm.explore(find=dispatcher) 62 | if new_sm.found: 63 | # [可能1] 直接跳转到下一个块 64 | # [可能2] 这个block下面有两个后继可以选择 65 | # 所以 eval_upto 第二个参数是 2 66 | found_state = new_sm.found[0] 67 | solutions = found_state.solver.eval_upto(getattr(found_state.regs,state_register_name), 2) 68 | return found_state, solutions 69 | else: 70 | # 不跳转到分发器 可能是 ret 71 | def find_ret(_state: angr.SimState): 72 | return _state.history.jumpkind == JumpKind.Ret 73 | 74 | _ret_sm = project.factory.simulation_manager(back_state) 75 | _ret_sm.explore(find=find_ret) 76 | if _ret_sm.found: 77 | found_state = _ret_sm.found[0] 78 | return found_state, [] 79 | else: 80 | raise Exception("未处理异常,可能不是ret的情况") 81 | # while True: 82 | # print(f"eax: {simgr.active[0].regs.x12}") 83 | # print(f"Stepping: {simgr.active} ...") 84 | # simgr.step() 85 | # new_state = simgr.active[0] 86 | # if simgr.successors(new_state).is_empty: # 为空就是 ret 的 block 87 | # return state,[] 88 | # if new_state.addr == dispatcher: 89 | # solutions = new_state.solver.eval_upto(new_state.regs.x12, 2) 90 | # return state, solutions 91 | # state = new_state 92 | 93 | 94 | # state_value => real basic block state 95 | states = {} 96 | 97 | if __name__ == '__main__': 98 | 99 | start_address = project.loader.min_addr 100 | # state = project.factory.blank_state(addr=start_address + 0x0009cbe0, remove_options={angr.sim_options.LAZY_SOLVES}) 101 | # simgr = project.factory.simulation_manager(state) 102 | # simgr = project.factory.successors(state) 103 | # project.hook(start_address+0x9ccdc, angr.SIM_PROCEDURES["stubs"]["ReturnUnconstrained"](), replace=True) 104 | # simgr.explore(find=start_address+0x9cd14) 105 | # bin_cfg = project.analyses.CFGFast( 106 | # regions=[(start_address+0x9ccdc,start_address+0x9cd14)], 107 | # normalize=True, 108 | # resolve_indirect_jumps=True, 109 | # data_references=True, 110 | # ) 111 | # dispatcher_addr = start_address+0x9cc54 112 | # dispatcher_state = get_dispatcher_state(start_address + 0x0009cbe0) 113 | # 负责跳转的寄存器 114 | state_register_name = "x22" 115 | # 分发器的地址(必须是第一行) 116 | dispatcher_addr = start_address+0x9cf7c 117 | # 根据函数起始地址获取分发器的初始 state 118 | dispatcher_state = get_dispatcher_state(start_address + 0x9ceb8) 119 | 120 | print(f"Dispatcher state: {dispatcher_state}") 121 | initial_state = dispatcher_state.solver.eval_one(dispatcher_state.regs.get(state_register_name)) 122 | print(f"Initial {state_register_name}: {hex(initial_state)}") 123 | 124 | q = Queue() 125 | q.put(initial_state) 126 | while not q.empty(): 127 | state_value = q.get() 128 | # Skip visited states 129 | if state_value in states: 130 | continue 131 | 132 | bb_state, successors = find_successors(state_value,dispatcher_addr,False) 133 | 134 | states[state_value] = bb_state, successors 135 | for state_value in successors: 136 | q.put(state_value) 137 | 138 | for state_value,values in states.items(): 139 | _state: angr.SimState = values[0] 140 | successors = values[1] 141 | if len(successors) >0 : 142 | #条件跳转 143 | print(f"{hex(state_value)} ==>",hex(_state.history.addr -start_address),[hex(i) for i in successors]) 144 | else: 145 | print(f"{hex(state_value)} ==>",hex(_state.history.addr), " [ret] ") 146 | 147 | # target_func = bin_cfg.functions.get_by_addr(start_address + 0x0009cbe0) 148 | # loop_state(simgr) 149 | # simgr.step() 150 | # while len(simgr.active) > 0: 151 | # for active_state in simgr.active: 152 | # print(hex(active_state.addr)) 153 | # simgr.step() 154 | 155 | 156 | 157 | # bv = load(r"D:\TMP\libtprt.so.bndb") 158 | # project = angr.Project('D:/TMP/libtprt.so', load_options={"auto_load_libs": False}) 159 | 160 | # Main(bv, project) 161 | -------------------------------------------------------------------------------- /symbolic_libEncryptor2.py: -------------------------------------------------------------------------------- 1 | import itertools 2 | import json 3 | from array import array 4 | from typing import Dict, List 5 | 6 | import angr 7 | import faulthandler 8 | import logging 9 | import copy 10 | import pyvex 11 | from angr.state_plugins import SimStateHistory 12 | 13 | from Vm import * 14 | from Vm.BinjaAst import VarAst, decode_vm_operand 15 | from Vm.CONSTS import * 16 | import binaryninja as binja 17 | from itertools import groupby 18 | 19 | from graphviz_tools import generate_dot_for_llil_var 20 | from utils import get_llil_var_def_tree 21 | from vm_tools import VmIL, VmConst 22 | 23 | # import colorlog 24 | # logging.getLogger('angr').setLevel('DEBUG') 25 | 26 | logger = logging.getLogger('angr') 27 | # logger.setLevel(logging.INFO) 28 | logger.setLevel(logging.ERROR) 29 | 30 | bv = binja.load(r"D:\window\AndroidRe\ttEncrypt\libEncryptor.so.bndb") 31 | func = bv.get_function_at(0x2c18) 32 | project = angr.Project(r'D:\window\AndroidRe\ttEncrypt\libEncryptor.so', load_options={"auto_load_libs": False}) 33 | 34 | start_address = project.loader.min_addr 35 | 36 | 37 | def collect_llil_action(_history: SimStateHistory): 38 | addr2llil = {} 39 | addr2action = {} 40 | # actions_len = len(_history.actions) 41 | last_ins_addr = 0 42 | last_llil = 0 43 | addrs = [] 44 | for index,action in enumerate(history.actions): 45 | ins_addr = action.ins_addr-start_address 46 | # 跟上一个action的地址不一样才收集 47 | if ins_addr != last_ins_addr: 48 | current_llil = func.get_llil_at(ins_addr) 49 | if current_llil == last_llil: 50 | # 上一个跟 现在的 llil是一样的话,就把上一个删掉 51 | del addr2llil[last_ins_addr] 52 | addr2llil[ins_addr] = current_llil 53 | addrs.append(ins_addr) 54 | if addr2action.get(ins_addr) is None: 55 | addr2action[ins_addr] = [action] 56 | else: 57 | addr2action[ins_addr].append(action) 58 | 59 | last_ins_addr = ins_addr 60 | 61 | addrs.reverse() 62 | 63 | # 这种写法会遇到写奇怪的东西 64 | # for index,action in enumerate(history.actions): 65 | # ins_addr = action.ins_addr - start_address 66 | # current_llil = func.get_llil_at(ins_addr) 67 | # if ins_addr != last_action_addr: 68 | # addr2action[current_llil.address] = [action] 69 | # last_action_addr = current_llil.address 70 | # 71 | # 72 | # addr2llil[current_llil.address] = current_llil 73 | # else: 74 | # addr2action[current_llil.address].append(action) 75 | 76 | # for addr,llil in addr2llil.items(): 77 | # print(hex(addr),llil) 78 | # for action in addr2action[addr]: 79 | # print("\t",action) 80 | return addrs,addr2llil,addr2action 81 | 82 | 83 | def from_action_get_value(addr2action,hlil : binja.HighLevelILInstruction): 84 | actions = addr2action[hlil.address] 85 | actions.reverse() 86 | reg_name = hlil.llil.dest.reg.name 87 | for action in actions: 88 | if isinstance(action, angr.state_plugins.SimActionData): 89 | if action.type == action.REG and action.WRITE and action.storage == reg_name: 90 | # reg/write 91 | bv = action.data.ast 92 | actions.reverse() 93 | return bv.concrete_value,bv.length 94 | raise Exception("没有在action里面找到寄存器的值") 95 | if __name__ == '__main__': 96 | faulthandler.enable() # start @ the beginning 97 | state = project.factory.blank_state(addr=start_address+0x2AC4) 98 | project.factory.block(0x402394).vex 99 | 100 | simgr = project.factory.simgr(state) 101 | simgr.use_technique(VmExploration(start_address)) 102 | # simgr.explore(find=start_address+0x3c18, extra_stop_points=[or_addr]) 103 | 104 | simgr.explore(find=start_address+0x4440, 105 | extra_stop_points= 106 | [start_address+i for i in 107 | [ 108 | or_offset, 109 | dispatcher_offset, 110 | external_call_offset, 111 | ip_increase_offset 112 | ] 113 | ], 114 | # [start_address+or_offset, 115 | # start_address+dispatcher_offset, 116 | # start_address+external_call_offset], 117 | # num_find=1, 118 | num_find=100, 119 | fail_fast=True 120 | ) 121 | # simgr.explore(find=start_address+0x2c20,num_find=1) 122 | if simgr.found: 123 | # for found_state in simgr.found[2]: 124 | found_state = simgr.found[2] 125 | # found_state = simgr.found[0] 126 | data: VMGlobalData = found_state.VmState.data 127 | 128 | vm_info = {} 129 | for index_opcode,history in data.history: 130 | history: SimStateHistory 131 | # 最后一个 指令来 132 | last_ins_addr = history.actions[-1].ins_addr - start_address 133 | primary_llil = func.get_llil_at(last_ins_addr) 134 | 135 | if primary_llil.operation == binja.LowLevelILOperation.LLIL_STORE: 136 | 137 | primary_hlil_ssa = primary_llil.hlil.ssa_form 138 | 139 | addrs,addr2llil,addr2action = collect_llil_action(history) 140 | str_index_opcode = f"{index_opcode[0]}_{index_opcode[1]:X}" 141 | vm_info[f"{str_index_opcode}"] = list(addrs) 142 | if index_opcode[0] == 28: 143 | print("branch0(先不处理)") 144 | continue 145 | var_ast = VarAst(func, addrs) 146 | var_ast.generate_dot_for_llil_var(str_index_opcode, var_ast.tree) 147 | var_ast.explore_vm_object() 148 | 149 | if len(var_ast.left_vm_operand) < 1: 150 | print("未知") 151 | continue 152 | if len(var_ast.right_vm_operand) < 1: 153 | print("未知") 154 | continue 155 | # print(f"{index_opcode[0]}_{index_opcode[1]:X}") 156 | if index_opcode[0] == 40: 157 | pass 158 | 159 | decode_vm_operand(var_ast,addr2action) 160 | else: 161 | # 不是store就是 if ==> 跳转指令 162 | addrs = [] 163 | for i in history.actions: 164 | addrs.append(i.ins_addr-start_address) 165 | for k,g in groupby(addrs): 166 | _llil = func.get_llil_at(k) 167 | # print(hex(_llil.address),_llil) 168 | # print(f"{primary_llil.operation} {primary_llil.address:X}: {primary_llil}") 169 | # print(history) 170 | 171 | if data.opcode_index2_ext_call.get(index_opcode) is not None: 172 | ext_call_addr = data.opcode_index2_ext_call.get(index_opcode) 173 | ext_call_addr -= start_address 174 | print(f"call {hex(ext_call_addr)}") 175 | pass 176 | with open("./vm_data.json","w") as f: 177 | f.write(json.dumps(vm_info)) 178 | 179 | 180 | -------------------------------------------------------------------------------- /symbolic_libEncryptor2_back.py: -------------------------------------------------------------------------------- 1 | from angr import SimulationManager 2 | import angr 3 | from queue import Queue 4 | from angr.procedures.procedure_dict import SIM_PROCEDURES 5 | from angr.sim_options import * 6 | from pyvex.lifting.util import JumpKind 7 | import pyvex 8 | import json 9 | from binaryninja import * 10 | import logging 11 | logging.getLogger('angr').setLevel('DEBUG') 12 | from graphviz_tools import generate_dot_for_llil_var 13 | 14 | project = angr.Project(r'D:\window\AndroidRe\ttEncrypt\libEncryptor.so', load_options={"auto_load_libs": False}) 15 | bv = load(r"D:\window\AndroidRe\ttEncrypt\libEncryptor.so.bndb") 16 | func = bv.get_function_at(0x2c18) 17 | 18 | 19 | def get_dispatcher_state(statr_addr): 20 | state = project.factory.blank_state(addr=statr_addr) 21 | state.options.add(SYMBOL_FILL_UNCONSTRAINED_MEMORY) 22 | state.options.add(SYMBOL_FILL_UNCONSTRAINED_REGISTERS) 23 | 24 | 25 | # SYMBOL_FILL_UNCONSTRAINED_ 26 | # {MEMORY, REGISTERS} 27 | # Ignore function calls 28 | # https://github.com/angr/angr/issues/723 29 | # state.options.add(angr.options.CALLLESS) 30 | simgr = project.factory.simulation_manager(state) 31 | # state.options.add(angr.options.TRACK_OP_ACTIONS) 32 | # state.options.add(angr.options.TRACK_ACTION_HISTORY) 33 | # state.options.add(angr.options.TRACK_REGISTER_ACTIONS) 34 | # 记录中间变量 35 | # state.options.add(angr.options.TRACK_TMP_ACTIONS) 36 | simgr.explore(find=dispatcher_addr) 37 | # simgr.explore(find=start_address+ 0x3c1c) 38 | if simgr.found: 39 | _init = simgr.found[0] 40 | return _init.copy() 41 | else: 42 | raise Exception("未找到分发器") 43 | 44 | 45 | def explore_vm(init_state): 46 | init_state.options.add(angr.options.TRACK_REGISTER_ACTIONS) 47 | 48 | ip_increase_addr = start_address + 0x00003a78 # ip++ 的位置 49 | simgr = project.factory.simulation_manager(init_state) 50 | 51 | def step_func(lsm: angr.SimulationManager): 52 | 53 | """ 54 | if len(lsm.active) != 1: 55 | raise Exception("未知") 56 | sim_state = lsm.active[0] 57 | if dispatcher_addr == sim_state.addr: 58 | opcode = sim_state.regs.w12.v 59 | index2opcode[index] = opcode 60 | # new_simgr = project.factory.simulation_manager(new_state) 61 | IndexOpcode2simgr[f"{index}_{opcode:X}"] = sim_state.history.actions 62 | sim_state.history.trim() 63 | index += 1 64 | if start_address+0x2cd4 == sim_state.addr: 65 | sim_state.history.trim() 66 | if ip_increase_addr == sim_state.addr: 67 | print(f"ip increase addr : {sim_state.addr}") 68 | """ 69 | return lsm 70 | 71 | simgr.explore(find=start_address + 0x3c18, step_func=step_func, 72 | extra_stop_points=[dispatcher_addr, 73 | ip_increase_addr]) 74 | 75 | if simgr.found: 76 | aaa = 0 77 | 78 | 79 | if __name__ == '__main__': 80 | start_address = project.loader.min_addr 81 | 82 | # 负责跳转的寄存器 83 | state_register_name = "w12" 84 | # 分发器的地址(必须是第一行) 85 | dispatcher_addr = start_address + 0x2cd0 86 | # 根据函数起始地址获取分发器的初始 state 87 | dispatcher_state = get_dispatcher_state(start_address + 0x2ac4) 88 | 89 | print(f"Dispatcher state: {dispatcher_state}") 90 | initial_state = dispatcher_state.solver.eval_one(dispatcher_state.regs.get(state_register_name)) 91 | print(f"Initial {state_register_name}: {hex(initial_state)}") 92 | 93 | collected_info = { 94 | 95 | } 96 | # explore_vm(init_state=dispatcher_state) 97 | 98 | # bv = load(r"D:\TMP\libtprt.so.bndb") 99 | # project = angr.Project('D:/TMP/libtprt.so', load_options={"auto_load_libs": False}) 100 | 101 | # Main(bv, project) 102 | -------------------------------------------------------------------------------- /symbolic_libEncryptor2_back2.py: -------------------------------------------------------------------------------- 1 | 2 | import angr 3 | import faulthandler 4 | import logging 5 | import copy 6 | import pyvex 7 | from Vm import * 8 | 9 | # import colorlog 10 | # logging.getLogger('angr').setLevel('DEBUG') 11 | 12 | # logger = logging.getLogger('angr') 13 | # logger.setLevel(logging.INFO) 14 | 15 | project = angr.Project(r'D:\window\AndroidRe\ttEncrypt\libEncryptor.so', load_options={"auto_load_libs": False}) 16 | 17 | start_address = project.loader.min_addr 18 | 19 | dispatcher_addr = start_address + 0x2cc8 20 | or_addr = start_address + 0x3920 21 | 22 | 23 | if __name__ == '__main__': 24 | faulthandler.enable() # start @ the beginning 25 | 26 | state = project.factory.blank_state(addr=start_address+0x2AC4) 27 | 28 | state.register_plugin("VmState",VmState()) 29 | 30 | 31 | simgr = project.factory.simgr(state) 32 | # simgr.use_technique(VmExploration(start_address)) 33 | # simgr.explore(find=start_address+0x3c18, extra_stop_points=[or_addr]) 34 | # simgr.explore(find=start_address+0x4440, 35 | # extra_stop_points=[or_addr,dispatcher_addr],num_find=1) 36 | simgr.explore(find=start_address+0x2c20,num_find=1) 37 | if simgr.found: 38 | 39 | found_state = simgr.found[0] 40 | found_state.options.add(angr.options.CALLLESS) 41 | 42 | def my_engine_process(state): 43 | if state.addr == dispatcher_addr: 44 | solver =state.solver 45 | x0 = state.regs.x0 46 | solver.eval_one(x0) 47 | opcode = state.memory.load(solver.eval_one(x0), 4).reversed 48 | opcode = solver.eval_one(opcode) 49 | state.VmState.add_opcode(opcode) 50 | 51 | 52 | found_state.inspect.make_breakpoint("engine_process",when=angr.BP_BEFORE,action=my_engine_process) 53 | new_simgr = project.factory.simgr(found_state) 54 | new_simgr.explore(find=start_address+0x4440, 55 | extra_stop_points=[or_addr,dispatcher_addr],num_find=100) 56 | if new_simgr.found: 57 | 58 | # for found in simgr.found: 59 | # for t_state in simgr.found[0].VmState.dataClass.vmStates: 60 | # t_state : VmState 61 | # print(hex(t_state.opcode)) 62 | print(new_simgr.found) 63 | 64 | -------------------------------------------------------------------------------- /test_exe.py: -------------------------------------------------------------------------------- 1 | from itertools import groupby 2 | 3 | import angr 4 | from VMEngine import VmEngine 5 | 6 | 7 | project = angr.Project(r'D:\window\code\c++\MesonX\buildDir\main.exe', 8 | engine=VmEngine, 9 | load_options={"auto_load_libs": False}) 10 | 11 | 12 | def get_dispatcher_state(): 13 | state = project.factory.blank_state(addr=start_addr + 0x1000) 14 | blokc_vex = project.factory.block(addr=start_addr + 0x1000).vex 15 | 16 | state.options.add(angr.options.TRACK_OP_ACTIONS) 17 | state.options.add(angr.options.TRACK_ACTION_HISTORY) 18 | state.options.add(angr.options.TRACK_REGISTER_ACTIONS) 19 | 20 | state.regs.rcx = state.solver.BVS("rcx", 64, uninitialized=True) 21 | state.regs.rdx = state.solver.BVS("rdx", 64, uninitialized=True) 22 | simgr = project.factory.simulation_manager(state) 23 | 24 | # bin_cfg = project.analyses.CFGFast( 25 | # regions=[(start_addr+0x1000,start_addr+0x103C)], 26 | # normalize=True, 27 | # resolve_indirect_jumps=True, 28 | # data_references=True, 29 | # ) 30 | 31 | # 这个函数是step成功之后调用的 32 | def step_func(lsm: angr.SimulationManager): 33 | 34 | return lsm 35 | 36 | # simgr.explore(find=start_addr + 0x3c18, step_func=step_func, num_find=10, 37 | # extra_stop_points=[start_addr + 0x100E, start_addr + 0x1038]) 38 | simgr.explore(find=start_addr+0x103C,step_func=step_func,num_find=10) 39 | 40 | if simgr.found: 41 | _init = simgr.found[0] 42 | return _init.copy() 43 | else: 44 | raise Exception("未找到分发器") 45 | 46 | 47 | if __name__ == '__main__': 48 | 49 | for k, g in groupby('AAAABBBCCDAABBB'): 50 | pass 51 | 52 | 53 | start_addr = project.loader.min_addr 54 | 55 | get_dispatcher_state() 56 | -------------------------------------------------------------------------------- /triton_test.py: -------------------------------------------------------------------------------- 1 | from __future__ import print_function 2 | from triton import * 3 | 4 | import sys 5 | 6 | # A dumb function to emulate. 7 | function = { 8 | 0x40056d: b"\x55", # push rbp 9 | 0x40056e: b"\x48\x89\xe5", # mov rbp,rsp 10 | 0x400571: b"\x48\x89\x7d\xe8", # mov QWORD PTR [rbp-0x18],rdi 11 | 0x400575: b"\xc7\x45\xfc\x00\x00\x00\x00", # mov DWORD PTR [rbp-0x4],0x0 12 | 0x40057c: b"\xeb\x3f", # jmp 4005bd 13 | 0x40057e: b"\x8b\x45\xfc", # mov eax,DWORD PTR [rbp-0x4] 14 | 0x400581: b"\x48\x63\xd0", # movsxd rdx,eax 15 | 0x400584: b"\x48\x8b\x45\xe8", # mov rax,QWORD PTR [rbp-0x18] 16 | 0x400588: b"\x48\x01\xd0", # add rax,rdx 17 | 0x40058b: b"\x0f\xb6\x00", # movzx eax,BYTE PTR [rax] 18 | 0x40058e: b"\x0f\xbe\xc0", # movsx eax,al 19 | 0x400591: b"\x83\xe8\x01", # sub eax,0x1 20 | 0x400594: b"\x83\xf0\x55", # xor eax,0x55 21 | 0x400597: b"\x89\xc1", # mov ecx,eax 22 | 0x400599: b"\x48\x8b\x15\xa0\x0a\x20\x00", # mov rdx,QWORD PTR [rip+0x200aa0] # 601040 23 | 0x4005a0: b"\x8b\x45\xfc", # mov eax,DWORD PTR [rbp-0x4] 24 | 0x4005a3: b"\x48\x98", # cdqe 25 | 0x4005a5: b"\x48\x01\xd0", # add rax,rdx 26 | 0x4005a8: b"\x0f\xb6\x00", # movzx eax,BYTE PTR [rax] 27 | 0x4005ab: b"\x0f\xbe\xc0", # movsx eax,al 28 | 0x4005ae: b"\x39\xc1", # cmp ecx,eax 29 | 0x4005b0: b"\x74\x07", # je 4005b9 30 | 0x4005b2: b"\xb8\x01\x00\x00\x00", # mov eax,0x1 31 | 0x4005b7: b"\xeb\x0f", # jmp 4005c8 32 | 0x4005b9: b"\x83\x45\xfc\x01", # add DWORD PTR [rbp-0x4],0x1 33 | 0x4005bd: b"\x83\x7d\xfc\x04", # cmp DWORD PTR [rbp-0x4],0x4 34 | 0x4005c1: b"\x7e\xbb", # jle 40057e 35 | 0x4005c3: b"\xb8\x00\x00\x00\x00", # mov eax,0x0 36 | 0x4005c8: b"\x5d", # pop rbp 37 | 0x4005c9: b"\xc3", # ret 38 | } 39 | 40 | 41 | 42 | if __name__ == '__main__': 43 | # Triton context 44 | ctx = TritonContext() 45 | 46 | # Set the architecture 47 | ctx.setArchitecture(ARCH.X86_64) 48 | 49 | # Symbolic optimization 50 | ctx.setMode(MODE.ALIGNED_MEMORY, True) 51 | 52 | # Define the Python syntax 53 | ctx.setAstRepresentationMode(AST_REPRESENTATION.PYTHON) 54 | 55 | # Define entry point 56 | pc = 0x40056d 57 | 58 | # Define our input context 59 | ctx.setConcreteMemoryValue(0x1000, ord('a')) 60 | ctx.setConcreteMemoryValue(0x1001, ord('b')) 61 | ctx.setConcreteMemoryValue(0x1002, ord('c')) 62 | ctx.setConcreteMemoryValue(0x1003, ord('d')) 63 | ctx.setConcreteMemoryValue(0x1004, ord('e')) 64 | 65 | # Define the serial pointer 66 | ctx.setConcreteMemoryValue(0x601040, 0x00) 67 | ctx.setConcreteMemoryValue(0x601041, 0x00) 68 | ctx.setConcreteMemoryValue(0x601042, 0x90) 69 | 70 | # Define the serial context 71 | ctx.setConcreteMemoryValue(0x900000, 0x31) 72 | ctx.setConcreteMemoryValue(0x900001, 0x3e) 73 | ctx.setConcreteMemoryValue(0x900002, 0x3d) 74 | ctx.setConcreteMemoryValue(0x900003, 0x26) 75 | ctx.setConcreteMemoryValue(0x900004, 0x31) 76 | 77 | # Point rdi on our buffer 78 | ctx.setConcreteRegisterValue(ctx.registers.rdi, 0x1000) 79 | 80 | # Setup stack 81 | ctx.setConcreteRegisterValue(ctx.registers.rsp, 0x7fffffff) 82 | ctx.setConcreteRegisterValue(ctx.registers.rbp, 0x7fffffff) 83 | 84 | # Let's emulate the function 85 | while pc in function: 86 | # Build an instruction 87 | inst = Instruction() 88 | 89 | # Setup opcode 90 | inst.setOpcode(function[pc]) 91 | 92 | # Setup Address 93 | inst.setAddress(pc) 94 | 95 | # Process the instruction 96 | ctx.processing(inst) 97 | 98 | # I know that at 0x40058b the user can control eax, so i'm tainting it. 99 | if inst.getAddress() == 0x40058b: 100 | ctx.taintRegister(ctx.registers.eax) 101 | 102 | # Print only instructions that are tainted. 103 | if inst.isTainted(): 104 | print('[tainted] %s' %(str(inst))) 105 | 106 | # Next instruction 107 | pc = ctx.getConcreteRegisterValue(ctx.registers.rip) 108 | 109 | sys.exit(0) 110 | -------------------------------------------------------------------------------- /ttEncrypt/DeviceRegister.py: -------------------------------------------------------------------------------- 1 | import secrets 2 | import uuid 3 | import time 4 | import json 5 | import hashlib 6 | import gzip 7 | import requests # pip install requests 8 | import ttEncryptorUtil 9 | 10 | 11 | # 注: 协议来自Tiktok 12 | 13 | 14 | def UUID(): 15 | return str(uuid.uuid4()) 16 | 17 | 18 | def md5(message): 19 | md5_hash = hashlib.md5() 20 | md5_hash.update(message) 21 | return md5_hash.hexdigest() 22 | 23 | 24 | def get_timestamp_in_millisecond(): 25 | return int(time.time() * 1000) 26 | 27 | 28 | def get_timestamp_in_second(): 29 | return int(time.time()) 30 | 31 | 32 | def generate_android_id(): 33 | return secrets.token_bytes(8).hex() 34 | 35 | 36 | def http_post(url, headers, payload): 37 | response = requests.request("POST", url, headers=headers, data=payload) 38 | return response.text 39 | 40 | 41 | def gzip_compress(buff): 42 | return gzip.compress(buff) 43 | 44 | 45 | def get_post_data(android_id, cdid, google_aid, clientudid): 46 | openudid = android_id 47 | postDataObj = { 48 | "magic_tag": "ss_app_log", 49 | "header": { 50 | "display_name": "TikTok", 51 | "update_version_code": 2023205030, 52 | "manifest_version_code": 2023205030, 53 | "app_version_minor": "", 54 | "aid": 1233, 55 | "channel": "googleplay", 56 | "package": "com.zhiliaoapp.musically", 57 | "app_version": "32.5.3", 58 | "version_code": 320503, 59 | "sdk_version": "3.9.17-bugfix.9", 60 | "sdk_target_version": 29, 61 | "git_hash": "3e93151", 62 | "os": "Android", 63 | "os_version": "11", 64 | "os_api": 30, 65 | "device_model": "Pixel 2", 66 | "device_brand": "google", 67 | "device_manufacturer": "Google", 68 | "cpu_abi": "arm64-v8a", 69 | "release_build": "e7cd5de_20231207", 70 | "density_dpi": 420, 71 | "display_density": "mdpi", 72 | "resolution": "1794x1080", 73 | "language": "en", 74 | "timezone": -5, 75 | "access": "wifi", 76 | "not_request_sender": 1, 77 | "rom": "6934943", 78 | "rom_version": "RP1A.201005.004.A1", 79 | "cdid": cdid, 80 | "sig_hash": "194326e82c84a639a52e5c023116f12a", # md5(packageInfo.signatures[0]) 81 | "gaid_limited": 0, 82 | "google_aid": google_aid, 83 | "openudid": openudid, 84 | "clientudid": clientudid, 85 | "tz_name": "America\\/New_York", 86 | "tz_offset": -18000, 87 | "req_id": UUID(), 88 | "device_platform": "android", 89 | "custom": { 90 | "is_kids_mode": 0, 91 | "filter_warn": 0, 92 | "web_ua": "Mozilla\\/5.0 (Linux; Android 11; Pixel 2 Build\\/RP1A.201005.004.A1; wv) AppleWebKit\\/537.36 (KHTML, like Gecko) Version\\/4.0 Chrome\\/116.0.0.0 Mobile Safari\\/537.36", 93 | "user_period": 0, 94 | "screen_height_dp": 683, 95 | "user_mode": -1, 96 | "apk_last_update_time": 1702363135217, 97 | "screen_width_dp": 411 98 | }, 99 | "apk_first_install_time": 1697783355395, 100 | "is_system_app": 0, 101 | "sdk_flavor": "global", 102 | "guest_mode": 0 103 | }, 104 | "_gen_time": get_timestamp_in_millisecond() 105 | } 106 | 107 | return gzip_compress(json.dumps(postDataObj).encode(encoding='utf-8')) 108 | 109 | 110 | def get_headers(md5Hash): 111 | headers = { 112 | 'log-encode-type': 'gzip', 113 | 'x-tt-request-tag': 't=0;n=1', 114 | 'sdk-version': '2', 115 | 'X-SS-REQ-TICKET': f'{get_timestamp_in_millisecond()}', 116 | 'passport-sdk-version': '19', 117 | 'x-tt-dm-status': 'login=0;ct=1;rt=4', 118 | 'x-vc-bdturing-sdk-version': '2.3.4.i18n', 119 | 'Content-Type': 'application/octet-stream;tt-data=a', 120 | 'X-SS-STUB': md5Hash, 121 | 'Host': 'log-va.tiktokv.com' 122 | } 123 | return headers 124 | 125 | 126 | def get_device_register_url(openudid, cdid): 127 | url = 'https://log-va.tiktokv.com/service/2/device_register/?' + \ 128 | "tt_data=a" + \ 129 | "ac=wifi" + \ 130 | "channel=googleplay" + \ 131 | "aid=1233" + \ 132 | "app_name=musical_ly" + \ 133 | "version_code=320503" + \ 134 | "version_name=32.5.3" + \ 135 | "device_platform=android" + \ 136 | "os=android" + \ 137 | "ab_version=32.5.3" + \ 138 | "ssmix=a" + \ 139 | "device_type=Pixel+2" + \ 140 | "device_brand=google" + \ 141 | "language=en" + \ 142 | "os_api=30" + \ 143 | "os_version=11" + \ 144 | f"openudid={openudid}" + \ 145 | "manifest_version_code=2023205030" + \ 146 | "resolution=1080*1794" + \ 147 | "dpi=420" + \ 148 | "update_version_code=2023205030" + \ 149 | f"_rticket={get_timestamp_in_millisecond()}" + \ 150 | "is_pad=0" + \ 151 | "current_region=TW" + \ 152 | "app_type=normal" + \ 153 | "timezone_name=America%2FNew_York" + \ 154 | "residence=TW" + \ 155 | "app_language=en" + \ 156 | "ac2=wifi5g" + \ 157 | "uoo=0" + \ 158 | "op_region=TW" + \ 159 | "timezone_offset=-18000" + \ 160 | "build_number=32.5.3" + \ 161 | "host_abi=arm64-v8a" + \ 162 | "locale=en" + \ 163 | f"ts={get_timestamp_in_second()}" + \ 164 | f"cdid={cdid}" 165 | return url 166 | 167 | 168 | def device_register(): 169 | android_id = generate_android_id() 170 | cdid = UUID() 171 | google_aid = UUID() 172 | clientudid = UUID() 173 | gzip_post_data = get_post_data(android_id, cdid, google_aid, clientudid) 174 | ttencrypt_post_data = ttEncryptorUtil.ttEncrypt(gzip_post_data) 175 | headers = get_headers(md5(ttencrypt_post_data)) 176 | url = get_device_register_url(android_id, cdid) 177 | response = http_post(url, headers, ttencrypt_post_data) 178 | print(f"设备注册结果:\n{response}") 179 | 180 | if __name__ == "__main__": 181 | device_register() -------------------------------------------------------------------------------- /ttEncrypt/libEncryptor.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/ttEncrypt/libEncryptor.so -------------------------------------------------------------------------------- /ttEncrypt/libEncryptor.so.bndb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zhuzhu-Top/de_vm/875ee2839767f8d69511c69f92368e1a247bd672/ttEncrypt/libEncryptor.so.bndb -------------------------------------------------------------------------------- /ttEncrypt/ttEncryptorUtil.py: -------------------------------------------------------------------------------- 1 | import secrets 2 | import hashlib 3 | from Crypto.Cipher import AES # pip install pycryptodome 4 | from Crypto.Util.Padding import pad, unpad 5 | 6 | 7 | def generate_rand_number(): 8 | return secrets.token_bytes(32) 9 | 10 | 11 | def decrypt_seeds(): 12 | key1 = [0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB] 13 | key1 += [0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB] 14 | key1 += [0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E] 15 | key1 += [0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25] 16 | 17 | key2 = [0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F] 18 | key2 += [0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF] 19 | key2 += [0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61] 20 | key2 += [0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D] 21 | 22 | results = bytearray() 23 | for i in range(len(key1)): 24 | results.append(key1[i] ^ key2[i]) 25 | return results 26 | 27 | 28 | def sha512(buff): 29 | sha512_hash = hashlib.sha512() 30 | sha512_hash.update(buff) 31 | return sha512_hash.digest() 32 | 33 | 34 | def get_aes_key_iv(rand_num): 35 | rand_num_hash = sha512(rand_num) 36 | seeds = decrypt_seeds() 37 | data = rand_num_hash + seeds 38 | key_iv_hash = sha512(data) 39 | 40 | print(f"rand_num: {rand_num.hex()}") 41 | print(f"rand_num_hash: {rand_num_hash.hex()}") 42 | print(f"seeds: {seeds.hex()}") 43 | print(f"rand_num_hash + seeds: {data.hex()}") 44 | print(f"key_iv_hash: {key_iv_hash.hex()}") 45 | print(f"aes key: {key_iv_hash[0:0x10].hex()}") 46 | print(f"aes iv: {key_iv_hash[0x10:0x20].hex()}") 47 | return key_iv_hash[0:0x10], key_iv_hash[0x10:0x20] 48 | 49 | 50 | def aes_128_cbc_encrypt(plaintext, key, iv): 51 | # 创建一个 AES 加密器对象 52 | cipher = AES.new(key, AES.MODE_CBC, iv) 53 | 54 | # 添加填充并加密数据 55 | padded_data = pad(plaintext, AES.block_size) 56 | ciphertext = cipher.encrypt(padded_data) 57 | return ciphertext 58 | 59 | 60 | def get_magic(): 61 | return b"\x74\x63\x05\x10\x00\x00" 62 | 63 | 64 | def ttEncrypt(buff): 65 | magic = get_magic() 66 | rand_number = generate_rand_number() 67 | aes_key, aes_iv = get_aes_key_iv(rand_number) 68 | buff_hash = sha512(buff) 69 | aes_plaintext = buff_hash + buff 70 | aes_ciphertext = aes_128_cbc_encrypt(aes_plaintext, aes_key, aes_iv) 71 | 72 | print(f"plaintext: {buff.hex()}") 73 | print(f"rand_number: {rand_number.hex()}") 74 | print(f"buff hash: {buff_hash.hex()}") 75 | print(f"aes_plaintext: {aes_plaintext.hex()}") 76 | print(f"ciphertext: {aes_ciphertext.hex()}") 77 | 78 | return magic + rand_number + aes_ciphertext 79 | 80 | 81 | def main(): 82 | buff = b'aabbccddeeffgg' 83 | result = ttEncrypt(buff) 84 | print(f"ttEncrypt: {result.hex()}") 85 | 86 | 87 | def test_aes(): 88 | buff = b"\x61\x02\xbe\x54\xa6\x2a\x73\xe7\x65\xba\x38\xc9\x87\x34\x09\xbd" +\ 89 | b"\xeb\xb6\xb0\xd3\x7e\xa0\x60\x40\x3d\x0c\x26\xfe\xa5\xeb\xb6\xba" +\ 90 | b"\x5a\x0c\x7f\x36\xec\xb7\x58\xc7\x7e\x19\x37\x50\x5f\xa8\x5b\x4e" +\ 91 | b"\x77\xce\x82\x7a\x70\x09\xd2\x2b\x2f\xaf\xc4\x68\x00\xd7\xa9\xff" +\ 92 | b"\x62\x69\x61\x6e\x66\x65\x6e\x67" 93 | aes_key = b"\xe8\xaf\x6e\x91\xde\x99\x7e\xf0\xfa\xfb\xcd\xbe\x97\x73\xb2\xc5" 94 | aes_iv = b"\x03\x7e\xed\x97\x4e\x1e\xc5\x19\xdc\xc2\xb4\x35\x5b\x26\xf0\x1b" 95 | ciphertext = aes_128_cbc_encrypt(buff, aes_key, aes_iv) 96 | print(f"ciphertext: {ciphertext.hex()}") 97 | 98 | 99 | if __name__ == "__main__": 100 | main() 101 | # test_aes() 102 | -------------------------------------------------------------------------------- /user_il.py: -------------------------------------------------------------------------------- 1 | from binaryninja import * 2 | 3 | 4 | def create_user_func(bv: BinaryView): 5 | max_addr = 0 6 | for segment in bv.segments: 7 | max_addr = max(max_addr, segment.end + 1) 8 | # Skip one and align to 0x1000 9 | max_addr += 0x1fff 10 | max_addr &= ~0xfff 11 | 12 | segment_start = max_addr 13 | segment_length = 0x1000 14 | file_start = bv.file.raw.end 15 | bv.file.raw.insert(file_start, b'\x00' * segment_length) 16 | bv.add_user_segment(segment_start, segment_length, 17 | file_start, segment_length, 18 | SegmentFlag.SegmentContainsCode | SegmentFlag.SegmentExecutable | SegmentFlag.SegmentReadable) 19 | bv.add_user_section("rop cave", segment_start, segment_length, SectionSemantics.ReadOnlyCodeSectionSemantics) 20 | 21 | 22 | bv.create_user_function(segment_start) 23 | bv.define_user_symbol(Symbol(SymbolType.FunctionSymbol, segment_start, "rop", "rop")) 24 | func = bv.get_function_at(segment_start) 25 | func.reanalyze() 26 | 27 | 28 | 29 | 30 | -------------------------------------------------------------------------------- /utils.py: -------------------------------------------------------------------------------- 1 | import capstone 2 | from binaryninja import * 3 | from capstone.arm64 import * 4 | from pprint import pprint 5 | def pp_print(str): 6 | pprint(str) 7 | 8 | def get_targte_reg_name(bv,cs,address): 9 | # address = 0x9cc7c 10 | inst_bytes = bv.read(address, bv.get_instruction_length(address)) 11 | for inst in cs.disasm(inst_bytes, address): 12 | inst: capstone.CsInsn = inst 13 | for operand in inst.operands: 14 | operand: capstone.arm64.Arm64Op = operand 15 | return inst.reg_name(operand.value.reg) 16 | 17 | 18 | def find_operation(llil :LowLevelILFunction,llil_operation: LowLevelILOperation) -> List[Optional[LowLevelILInstruction]]: 19 | def find_(llil_inst: LowLevelILInstruction): 20 | if llil_inst.operation == llil_operation: 21 | return llil_inst 22 | return list(llil.traverse(find_)) 23 | 24 | 25 | # 找到所有设置 flag的地方 并返回 operation(怎么比较的) raw_operands 比较的寄存器 26 | def find_all_flag_def_info(llil :LowLevelILFunction): 27 | fag_defs_il = find_operation(llil,LowLevelILOperation.LLIL_SET_FLAG) 28 | info = { 29 | 30 | } 31 | for flag in llil.flags: 32 | for index,il in enumerate(fag_defs_il): 33 | il : LowLevelILSetFlag 34 | if il.operands[0].name == flag.name: 35 | info[flag.name] = { 36 | "operation": il.operands[1].operation, 37 | "raw_operands": il.operands[1].raw_operands, 38 | "size": il.operands[1].size 39 | } 40 | fag_defs_il.pop(index) 41 | break 42 | return info 43 | 44 | # 只获取只有一个值的寄存器的值 45 | def get_reg_const_value_after(il,reg): 46 | reg_value = il.get_possible_reg_values_after(reg) 47 | # 只需要 只可能是一个值的 48 | # 多个值的是 InSetOfValues 未知的是 UndeterminedValue 49 | if not reg_value.type == RegisterValueType.ConstantValue: 50 | return None 51 | return reg_value 52 | 53 | # 判断是否是操作自己 sp = sp - 0x70 54 | # x20 = x20 + 0xc80 55 | def is_operate_self(il:LowLevelILInstruction): 56 | 57 | if not hasattr(il,"src") or not hasattr(il,"dest"): 58 | return False 59 | 60 | 61 | def get_llil_var_def_tree(func,llil): 62 | func_llil_ssa = func.llil.ssa_form 63 | if isinstance(llil, LowLevelILBinaryBase): 64 | left = llil.left 65 | right = llil.right 66 | _left = get_llil_var_def_tree(func,left) 67 | _right = get_llil_var_def_tree(func,right) 68 | return { 69 | "il": llil, 70 | "left_child": _left, 71 | "right_child": _right, 72 | "addr": llil.address, 73 | } 74 | elif isinstance(llil, LowLevelILConst): 75 | return { 76 | "il": llil, 77 | "value": llil.value.value, 78 | "addr": llil.address, 79 | } 80 | elif isinstance(llil, LowLevelILRegSsaPartial): 81 | operands = llil.operands 82 | register = operands[0] 83 | set_reg_ssa_il = func_llil_ssa.get_ssa_reg_definition(register) 84 | return get_llil_var_def_tree(func,set_reg_ssa_il) 85 | elif isinstance(llil, LowLevelILLowPart): 86 | return get_llil_var_def_tree(func,llil.src) 87 | elif isinstance(llil, LowLevelILZx) or isinstance(llil, LowLevelILSx): 88 | # 直接返回出去 89 | return get_llil_var_def_tree(func,llil.src) 90 | elif isinstance(llil, LowLevelILSetRegSsa): 91 | _ret = get_llil_var_def_tree(func,llil.src) 92 | return { 93 | "il": llil, 94 | "child": _ret, 95 | "addr": llil.address, 96 | } 97 | # ret[f"{llil.src.reg.name}#{llil.src.version}"] = _ret 98 | elif isinstance(llil, LowLevelILLoadSsa): 99 | _ret = get_llil_var_def_tree(func,llil.src) 100 | return { 101 | "il": llil, 102 | "child": _ret, 103 | "addr": llil.address, 104 | } 105 | elif isinstance(llil, LowLevelILRegSsa): 106 | set_reg_ssa_il = func_llil_ssa.get_ssa_reg_definition(llil.src) 107 | # _ret = get_llil_var_def_tree(set_reg_ssa_il) 108 | return get_llil_var_def_tree(func,set_reg_ssa_il) 109 | # ret[f"{llil.src.reg.name}#{llil.src.version}"] = _ret 110 | 111 | 112 | 113 | def to_signed(value, bits): 114 | if value & (1 << (bits - 1)): 115 | return value - (1 << bits) 116 | return value --------------------------------------------------------------------------------