├── .gitattributes ├── Final_Project ├── 00_TESTBED │ ├── ANS_CPU.v │ ├── ANS_MEM.v │ ├── DATA_MEM.v │ ├── DRAM │ │ ├── data_file.dat │ │ ├── inst_1_file.dat │ │ └── inst_2_file.dat │ ├── INST_MEM_1.v │ ├── INST_MEM_2.v │ ├── MEM_MAP_define.v │ ├── PATTERN.v │ ├── TESTBED.v │ └── ncprotect.log ├── 01_RTL │ ├── 01_run_test_cpu │ ├── 02_run_test_bridge │ ├── 03_run_test_mem │ ├── 04_combine_all_files │ ├── 09_clean_up │ ├── CPU.fsdb │ ├── CPU.sv │ ├── CPU.v │ ├── CPU2.fsdb │ ├── CPU_MEM.fsdb │ ├── DATA_BRIDGE.v │ ├── DATA_BRIDGE2.v │ ├── DATA_CONTROLLER.sv │ ├── DATA_CONTROLLER.v │ ├── DATA_MLRU_20210328.v │ ├── INCA_libs │ │ ├── irun.lnx86.13.10.nc │ │ │ ├── .nclib.lock │ │ │ ├── .ncrun.lock │ │ │ ├── .ncv.lock │ │ │ ├── .timestamp.ts │ │ │ ├── UVMHOME │ │ │ ├── bind.lst.lnx86 │ │ │ ├── cds.lib │ │ │ ├── cdsrun.lib │ │ │ ├── files.ts │ │ │ ├── hdl.var │ │ │ ├── hdlrun.var │ │ │ ├── irun.args │ │ │ ├── ncelab.args │ │ │ ├── ncelab.env │ │ │ ├── ncelab.hrd │ │ │ ├── ncsim.args │ │ │ ├── ncsim.env │ │ │ ├── ncsim_restart.args │ │ │ ├── ncsim_restart.env │ │ │ ├── ncvlog.args │ │ │ ├── ncvlog.env │ │ │ ├── ncvlog.files │ │ │ ├── ncvlog.hrd │ │ │ ├── svpp.args │ │ │ └── svpp.env │ │ ├── irun.nc │ │ │ ├── .nclib.lock │ │ │ ├── .ncrun.lock │ │ │ ├── .ncv.lock │ │ │ ├── .timestamp.ts │ │ │ ├── UVMHOME │ │ │ ├── bind.lst.lnx86 │ │ │ ├── cds.lib │ │ │ ├── cdsrun.lib │ │ │ ├── files.ts │ │ │ ├── hdl.var │ │ │ ├── hdlrun.var │ │ │ ├── irun.args │ │ │ ├── ncelab.args │ │ │ ├── ncelab.env │ │ │ ├── ncelab.hrd │ │ │ ├── ncsim.args │ │ │ ├── ncsim.env │ │ │ ├── ncsim_restart.args │ │ │ ├── ncsim_restart.env │ │ │ ├── ncvlog.args │ │ │ ├── ncvlog.env │ │ │ ├── ncvlog.files │ │ │ ├── ncvlog.hrd │ │ │ ├── svpp.args │ │ │ └── svpp.env │ │ └── worklib │ │ │ ├── .cdsvmod │ │ │ ├── .inca.db.021.lnx86 │ │ │ ├── cdsinfo.tag │ │ │ └── inca.lnx86.021.pak │ ├── INST_BRIDGE.v │ ├── INST_CONTROLLER.v │ ├── PATTERN.v │ ├── PATTERN_BRIDGE.v │ ├── SA.log │ ├── TESTBED.sv │ ├── TESTBED.v │ ├── TESTBED2.v │ ├── TESTBED_BRIDGE.sv │ ├── TESTBED_BRIDGE.v │ ├── TESTBED_MEM.v │ ├── file_list.f │ ├── irun.key │ ├── irun.log │ ├── nWaveLog │ │ ├── .3979ee05.conf │ │ ├── fsdb.log │ │ ├── nWave.cmd │ │ ├── nWave.cmd.bak │ │ ├── novas.rc │ │ ├── pes.bat │ │ └── turbo.log │ ├── novas.conf │ ├── novas_dump.log │ └── score_analysis.log ├── 02_SYN │ ├── 01_run_dc │ ├── 09_clean_up │ ├── CPU.v │ └── syn.tcl ├── 03_GATE │ ├── 01_run │ ├── 09_clean_up │ ├── CPU_SYN.v │ ├── PATTERN.v │ ├── TESTBED.v │ └── file_list.f ├── 04_MEM │ ├── SRAM128W16B.db │ ├── SRAM128W16B.v │ ├── SRAM256W16B.db │ └── SRAM256W16B.v ├── 05_APR │ ├── 00_combine │ ├── 01_run │ ├── 09_clean_up │ ├── CHIP.io │ ├── CHIP.sdc │ ├── CHIP_SHELL.v │ ├── PATTERN.v │ ├── RCGen.tch │ ├── REF_CHIP_SHELL.v │ ├── TESTBED.v │ ├── fast.cdb │ ├── fast.lib │ ├── file_list.f │ ├── slow.cdb │ ├── slow.lib │ ├── umc18.gds2 │ ├── umc18_1p6m.captbl │ ├── umc18_6lm.lef │ ├── umc18_6lm_antenna.lef │ ├── umc18io3v5v_6lm.gds2 │ ├── umc18io3v5v_6lm.lef │ ├── umc18io3v5v_fast.lib │ └── umc18io3v5v_slow.lib ├── 06_POST │ ├── 01_run │ ├── 09_clean_up │ ├── PATTERN.v │ ├── TESTBED.v │ └── file_list.f ├── Customized ISA Processor.pdf ├── Final_Project_2019_Fall_v4.pdf ├── Note.pdf ├── README.md ├── iclab134_final │ ├── 01_mem_gen.sh │ ├── 02_lib_gen_syntax_match.sh │ ├── 08_delete_mem │ ├── 08_delete_mem.sh │ ├── 09_clean │ ├── SRAM128W16B.db │ ├── SRAM128W16B.ps │ ├── SRAM128W16B.v │ ├── SRAM128W16B.vclef │ ├── SRAM128W16B_backup.v │ ├── SRAM128W16B_fast_syn.lib │ ├── SRAM128W16B_lc.tcl │ ├── SRAM128W16B_slow_syn.lib │ ├── SRAM128W16B_typical_syn.lib │ ├── SRAM256W16B.db │ ├── SRAM256W16B.ps │ ├── SRAM256W16B.v │ ├── SRAM256W16B.vclef │ ├── SRAM256W16B_backup.v │ ├── SRAM256W16B_fast_syn.lib │ ├── SRAM256W16B_lc.tcl │ ├── SRAM256W16B_slow_syn.lib │ ├── SRAM256W16B_typical_syn.lib │ ├── lc_shell.tcl │ └── lc_shell_command.log ├── output.txt └── top_level_block_diagram.png ├── Lab01 Combinational Circuit Design ├── CC_iclab134.v └── Lab01_Exercise.pdf ├── Lab02 Sequential Circuit ├── 4.5_iclab134.txt ├── Lab02_Exercise.pdf └── RIM_iclab134.v ├── Lab03 Testbench And Pattern ├── CC_iclab134.v ├── Lab03_Exercise.pdf ├── PATTERN_iclab134.v ├── action_iclab134.txt ├── ans_iclab134.txt ├── color_iclab134.txt ├── start_pos_iclab134.txt └── stripe_iclab134.txt ├── Lab04 Advanced Sequential Circuit Design ├── 4.3_iclab134.txt ├── DH_iclab134.v ├── Lab04_Exercise.pdf └── Lab04_Exercise_Note.pdf ├── Lab05 Introduction to macros and SRAM ├── 20.0_iclab134.txt ├── Lab05_Exercise_v3.pdf ├── MC_iclab134.v ├── RA1SH_iclab134.db └── RA1SH_iclab134.v ├── Lab06 Introduction to Synthesis Flow ├── 8.5_iclab134.txt ├── CONV2D_iclab134.v ├── CP_iclab134.v └── Lab06_Exercise.pdf ├── Lab07 Static Timing Analysis ├── CDC_iclab134.sdc ├── DESIGN_MODULE_iclab134 (1).v ├── Lab07_Exercise_v2.pdf └── Lab07_pattern.zip ├── Lab08 Low Power Design ├── IP_iclab134.v ├── IP_wocg_iclab134.v ├── Lab08_Exercise.pdf └── Lab08_PATTERN.tar ├── Lab09 System Verilog ├── Lab09_Exercise_note.pdf ├── Lab09_Exercise_v4.pdf ├── Usertype_PKG_iclab134.sv ├── bridge_iclab134.sv ├── iclab134_2.7.txt └── payment_iclab134.sv ├── Lab10 Coverage and Assertion ├── CHECKER_iclab134.sv ├── Lab10_Exercise.pdf └── PATTERN_iclab134.sv ├── Lab10_5 SystemVerilog - Formal Verification (Bonus) ├── Bonus_Formal_Verification_Exercise.pdf ├── bridge_iclab134.sv └── top_iclab134.sv ├── Lab11 Cell Based APR Design Flow ├── Lab11_Exercise.pdf ├── iclab134.tar └── iclab134 │ ├── 4.8_iclab134.txt │ ├── CHIP_iclab134.io │ ├── CHIP_iclab134.sdc │ ├── CHIP_iclab134.sdf │ ├── CHIP_iclab134.v │ ├── iclab134.inn │ └── iclab134.inn.dat.tar ├── Lec12 APRII ├── CHIP_APR2_iclab134.tar ├── CHIP_APR2_iclab134 │ ├── CHIP.inn │ ├── CHIP.inn.dat │ │ ├── AAE │ │ │ └── persistAaeAr.dat │ │ ├── CHIP.apa │ │ ├── CHIP.dbglobals │ │ ├── CHIP.fp.gz │ │ ├── CHIP.fp.spr.gz │ │ ├── CHIP.globals │ │ ├── CHIP.init │ │ ├── CHIP.metric.gz │ │ ├── CHIP.mode │ │ ├── CHIP.opconds │ │ ├── CHIP.place.gz │ │ ├── CHIP.ppcmd │ │ ├── CHIP.prop │ │ ├── CHIP.route.gz │ │ ├── CHIP.symtbl.gz │ │ ├── CHIP.v.bin │ │ ├── CHIP.v.bin_lib │ │ ├── CHIP_power_constraints.tcl │ │ ├── ccopt │ │ │ ├── clock_trees.tcl.gz │ │ │ ├── prop_store_1.tcl.gz │ │ │ ├── prop_store_2.tcl.gz │ │ │ └── skew_groups.tcl.gz │ │ ├── glitchData.tgz │ │ ├── gui.pref.tcl │ │ ├── inn.cmd.gz │ │ ├── libs │ │ │ ├── iofile │ │ │ │ └── CHIP.io │ │ │ ├── lef │ │ │ │ ├── umc18_6lm.lef │ │ │ │ ├── umc18_6lm_antenna.lef │ │ │ │ └── umc18io3v5v_6lm.lef │ │ │ ├── misc │ │ │ │ ├── qrc_lefdef.layermap │ │ │ │ └── rc_model.bin │ │ │ └── mmmc │ │ │ │ ├── RC_Corner │ │ │ │ └── RCGen.tch │ │ │ │ ├── fast.cdb │ │ │ │ ├── fast.lib │ │ │ │ ├── slow.cdb │ │ │ │ ├── slow.lib │ │ │ │ ├── umc18_1p6m.captbl │ │ │ │ ├── umc18io3v5v_fast.lib │ │ │ │ └── umc18io3v5v_slow.lib │ │ ├── mmmc │ │ │ ├── modes │ │ │ │ └── func_mode │ │ │ │ │ └── func_mode.sdc │ │ │ └── views │ │ │ │ ├── av_func_mode_max │ │ │ │ └── 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