├── project_benches ├── proj_1 │ ├── sim │ │ ├── .__afsF385 │ │ ├── wave.do │ │ └── Makefile │ ├── gradesheet_p1.xlsx │ └── rtl │ │ ├── filter.vhd │ │ ├── iicmb_int_pkg.vhd │ │ └── avalon_mm.vhd ├── proj_2 │ ├── sim │ │ ├── .__afsF385 │ │ ├── wave.do │ │ └── Makefile │ ├── gradesheet_p2.xlsx │ ├── rtl │ │ ├── filter.vhd │ │ ├── iicmb_int_pkg.vhd │ │ └── avalon_mm.vhd │ └── testbench │ │ └── top.sv ├── proj_3 │ ├── sim │ │ ├── .__afsF385 │ │ ├── work │ │ │ ├── _vmake │ │ │ ├── _lib.qdb │ │ │ ├── _lib1_0.qdb │ │ │ ├── _lib1_0.qpg │ │ │ ├── _lib1_0.qtl │ │ │ └── optimized_debug_top_tb │ │ │ │ ├── _lib.qdb │ │ │ │ ├── _lib1_0.qdb │ │ │ │ ├── _lib1_0.qpg │ │ │ │ ├── _lib1_0.qtl │ │ │ │ ├── _lib2_0.qdb │ │ │ │ ├── _lib2_0.qpg │ │ │ │ ├── _lib2_0.qtl │ │ │ │ ├── _lib3_0.qdb │ │ │ │ ├── _lib3_0.qpg │ │ │ │ ├── _lib3_0.qtl │ │ │ │ ├── _lib4_0.qdb │ │ │ │ ├── _lib4_0.qpg │ │ │ │ ├── _lib4_0.qtl │ │ │ │ ├── _lib5_0.qdb │ │ │ │ ├── _lib5_0.qpg │ │ │ │ ├── _lib5_0.qtl │ │ │ │ └── _data │ │ │ │ ├── exemptnyvgNw │ │ │ │ ├── exemptpKiLK2 │ │ │ │ └── exempt9gKImX │ │ ├── vsim_cli.do │ │ ├── i2cmb_test_plan.ucdb │ │ ├── i2cmb_test_plan.xls │ │ ├── i2cmb_generator_register_test.3074353043.ucdb │ │ ├── i2cmb_generator_fsm_functionality_test.1421797240.ucdb │ │ ├── i2cmb_generator_control_functionality_test.4148094673.ucdb │ │ ├── load_ucdbs_and_merge_with_test_plan.do │ │ ├── wave.do │ │ ├── transcript │ │ └── Makefile │ ├── gradesheet_p3.xlsx │ ├── transcript │ └── rtl │ │ ├── filter.vhd │ │ ├── iicmb_int_pkg.vhd │ │ └── avalon_mm.vhd ├── proj_4 │ ├── gradesheet_p4.xlsx │ ├── sim │ │ ├── i2cmb_test_plan.xls │ │ ├── vsim_cli.do │ │ ├── load_ucdbs_and_merge_with_test_plan.do │ │ ├── testlist.sh │ │ ├── wave.do │ │ └── Makefile │ ├── transcript │ └── rtl │ │ ├── filter.vhd │ │ ├── iicmb_int_pkg.vhd │ │ └── avalon_mm.vhd └── lab_1 │ ├── sim │ ├── wave.do │ └── Makefile │ ├── rtl │ ├── filter.vhd │ ├── iicmb_int_pkg.vhd │ └── avalon_mm.vhd │ └── testbench │ └── top.sv ├── verification_ip ├── environment_packages │ └── i2cmb_env_pkg │ │ ├── src │ │ ├── .__afs2774 │ │ ├── i2cmb_env_configuration.svh │ │ ├── i2cmb_test.svh │ │ ├── i2cmb_type.svh │ │ ├── i2cmb_environment.svh │ │ ├── i2cmb_coverage_i2c.svh │ │ ├── i2cmb_scoreboard.svh │ │ ├── i2cmb_checker.sv │ │ ├── i2cmb_generator_random_test.svh │ │ ├── i2cmb_coverage_wb.svh │ │ └── i2cmb_generator_control_functionality_test.svh │ │ ├── Makefile │ │ └── i2cmb_env_pkg.sv ├── .DS_Store ├── ncsu_pkg │ ├── src │ │ ├── ncsu_void.svh │ │ ├── ncsu_object_wrapper.svh │ │ ├── ncsu_configuration.svh │ │ ├── ncsu_config_db.svh │ │ ├── ncsu_pkg_version.svh │ │ ├── ncsu_object_registry.svh │ │ ├── ncsu_transaction.svh │ │ ├── ncsu_component_base.svh │ │ ├── ncsu_typedefs.svh │ │ ├── ncsu_object_factory.svh │ │ ├── ncsu_component.svh │ │ └── ncsu_object.svh │ ├── .DS_Store │ ├── Makefile │ ├── ncsu_macros.svh │ └── ncsu_pkg.sv └── interface_packages │ ├── .DS_Store │ ├── wb_pkg │ ├── .DS_Store │ ├── wb_macros.svh │ ├── Makefile │ ├── src │ │ ├── wb_configuration.svh │ │ ├── wb_monitor.svh │ │ ├── wb_transaction_rand.svh │ │ ├── wb_irq_transaction.svh │ │ ├── wb_agent.svh │ │ ├── wb_driver.svh │ │ ├── wb_transaction.svh │ │ ├── wb_type.svh │ │ └── wb_if.sv │ └── wb_pkg.sv │ ├── handler_pkg │ ├── handler_pkg.sv │ ├── Makefile │ └── src │ │ ├── .__afsFEDD │ │ ├── .__afs2DA7 │ │ ├── .__afs40DB │ │ ├── .__afs5B1D │ │ └── transaction_handler.svh │ └── i2c_pkg │ ├── i2c_macros.svh │ ├── Makefile │ ├── src │ ├── i2c_type.svh │ ├── i2c_configuration.svh │ ├── i2c_monitor.svh │ ├── i2c_transaction_rand.svh │ ├── i2c_driver.svh │ ├── i2c_agent.svh │ └── i2c_transaction.svh │ └── i2c_pkg.sv ├── docs ├── iicmb_mb.pdf └── i2cmb_test_plan.xls ├── pic ├── dut_arch.png └── ver_arch.png └── README.md /project_benches/proj_1/sim/.__afsF385: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project_benches/proj_2/sim/.__afsF385: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/.__afsF385: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/.__afs2774: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /docs/iicmb_mb.pdf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /project_benches/proj_4/sim/vsim_cli.do: -------------------------------------------------------------------------------- 1 | set NoQuitOnFinish 1; 2 | coverage exclude -scope /top/DUT/iicmb_m_inst0/mbit_inst0 3 | run -all; 4 | coverage save $1.$Sv_Seed.ucdb ; 5 | quit -f; 6 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zli87/Wishbone-to-I2C-bus-controller-IP-Verification/HEAD/verification_ip/interface_packages/wb_pkg/.DS_Store -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/handler_pkg.sv: -------------------------------------------------------------------------------- 1 | package my_pkg; 2 | import ncsu_pkg::*; 3 | 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virtual class ncsu_object_wrapper; 2 | pure virtual function string get_type_name(); 3 | pure virtual function ncsu_object create_object(string name); 4 | endclass 5 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/i2cmb_generator_register_test.3074353043.ucdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zli87/Wishbone-to-I2C-bus-controller-IP-Verification/HEAD/project_benches/proj_3/sim/i2cmb_generator_register_test.3074353043.ucdb -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/Makefile: -------------------------------------------------------------------------------- 1 | comp_handler_pkg: 2 | vlog +incdir+$(ECE745_PROJECT_HOME)/verification_ip/ncsu_pkg $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/handler_pkg/handler_pkg.sv 3 | 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-------------------------------------------------------------------------------- 1 | `define GET_WB_OP(x) wb_op_t'(x.get_op()[0]) 2 | `define GET_WB_ADDR(x) (iicmb_reg_ofst_t'(x.get_addr()[WB_ADDR_WIDTH-1:0])) 3 | `define GET_WB_DATA(x) (x.get_data_0()[WB_DATA_WIDTH-1:0]) 4 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/i2cmb_generator_fsm_functionality_test.1421797240.ucdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zli87/Wishbone-to-I2C-bus-controller-IP-Verification/HEAD/project_benches/proj_3/sim/i2cmb_generator_fsm_functionality_test.1421797240.ucdb -------------------------------------------------------------------------------- /project_benches/proj_3/sim/i2cmb_generator_control_functionality_test.4148094673.ucdb: -------------------------------------------------------------------------------- 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vcover merge -stats=none -strip 0 -totals i2cmb_test_plan.ucdb ./*.ucdb 4 | add testbrowser ./i2cmb_test_plan.ucdb 5 | #vsim -viewcov ./i2cmb_test_plan.ucdb 6 | -------------------------------------------------------------------------------- /project_benches/proj_4/sim/load_ucdbs_and_merge_with_test_plan.do: -------------------------------------------------------------------------------- 1 | add testbrowser ./*.ucdb 2 | xml2ucdb -format Excel ./i2cmb_test_plan.xml ./i2cmb_test_plan.ucdb 3 | vcover merge -stats=none -strip 0 -totals i2cmb_test_plan.ucdb ./*.ucdb 4 | add testbrowser ./i2cmb_test_plan.ucdb 5 | #vsim -viewcov ./i2cmb_test_plan.ucdb 6 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_configuration.svh: -------------------------------------------------------------------------------- 1 | class ncsu_configuration extends ncsu_object; 2 | 3 | function new(string name=""); 4 | super.new(name); 5 | endfunction 6 | 7 | virtual function string convert2string(); 8 | return $sformatf("name: %s ",name); 9 | endfunction 10 | 11 | endclass 12 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/Makefile: -------------------------------------------------------------------------------- 1 | comp_i2cmb_env_pkg: 2 | vlog +incdir+$(ECE745_PROJECT_HOME)/verification_ip/ncsu_pkg $(ECE745_PROJECT_HOME)/verification_ip/environment_packages/i2cmb_env_pkg/i2cmb_env_pkg.sv 3 | vlog $(ECE745_PROJECT_HOME)/verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_checker.sv 4 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/Makefile: -------------------------------------------------------------------------------- 1 | comp_wb_pkg: 2 | vlog +incdir+$(ECE745_PROJECT_HOME)/verification_ip/ncsu_pkg +incdir+$(ECE745_PROJECT_HOME)/verification_ip/interface_packages/my_pkg $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/wb_pkg/wb_pkg.sv 3 | vlog $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/wb_pkg/src/wb_if.sv 4 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/Makefile: -------------------------------------------------------------------------------- 1 | comp_i2c_pkg: 2 | vlog +incdir+$(ECE745_PROJECT_HOME)/verification_ip/ncsu_pkg +incdir+$(ECE745_PROJECT_HOME)/verification_ip/interface_packages/my_pkg $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/i2c_pkg/i2c_pkg.sv 3 | vlog $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/i2c_pkg/src/i2c_if.sv 4 | -------------------------------------------------------------------------------- /project_benches/proj_4/sim/testlist.sh: -------------------------------------------------------------------------------- 1 | make clean 2 | make compile 3 | make run_cli GEN_TYPE=i2cmb_generator_register_test 4 | make run_cli GEN_TYPE=i2cmb_generator_fsm_functionality_test 5 | make run_cli GEN_TYPE=i2cmb_generator_control_functionality_test 6 | make run_cli GEN_TYPE=i2cmb_generator_direct_test 7 | make run_cli GEN_TYPE=i2cmb_generator_random_test TEST_SEED=100 8 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_type.svh: -------------------------------------------------------------------------------- 1 | 2 | parameter int I2C_ADDR_WIDTH = 7; 3 | parameter int I2C_DATA_WIDTH = 8; 4 | parameter bit [6:0] I2C_SLAVE_ADDRESS = 7'h22; 5 | 6 | typedef enum bit { 7 | I2C_WRITE=0, 8 | I2C_READ=1 9 | } i2c_op_t; 10 | 11 | string map_op_name [ i2c_op_t ] = '{ 12 | I2C_READ : "READ", 13 | I2C_WRITE : "WRITE" 14 | }; 15 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_configuration.svh: -------------------------------------------------------------------------------- 1 | class wb_configuration extends ncsu_configuration; 2 | 3 | function new(string name=""); 4 | super.new(name); 5 | endfunction 6 | 7 | virtual function string convert2string(); 8 | return {super.convert2string}; 9 | endfunction 10 | 11 | function string get_name(); 12 | return name; 13 | endfunction 14 | 15 | endclass 16 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_configuration.svh: -------------------------------------------------------------------------------- 1 | class i2c_configuration extends ncsu_configuration; 2 | 3 | function new(string name=""); 4 | super.new(name); 5 | endfunction 6 | 7 | virtual function string convert2string(); 8 | return {super.convert2string}; 9 | endfunction 10 | 11 | function string get_name(); 12 | return name; 13 | endfunction 14 | 15 | endclass 16 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_env_configuration.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_env_configuration extends ncsu_configuration; 2 | 3 | function new(string name=""); 4 | super.new(name); 5 | endfunction 6 | 7 | virtual function string convert2string(); 8 | return {super.convert2string}; 9 | endfunction 10 | 11 | function string get_name(); 12 | return name; 13 | endfunction 14 | 15 | endclass 16 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_config_db.svh: -------------------------------------------------------------------------------- 1 | class ncsu_config_db #(type T) extends ncsu_void; 2 | static T db[string]; 3 | 4 | static function void set(input string name, input T value); 5 | db[name] = value; 6 | endfunction 7 | 8 | static function bit get(input string name, ref T value); 9 | if ( db.exists(name) ) begin 10 | value = db[name]; 11 | return 1; 12 | end else begin 13 | return 0; 14 | end 15 | endfunction 16 | 17 | endclass 18 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/i2c_pkg.sv: -------------------------------------------------------------------------------- 1 | package i2c_pkg; 2 | 3 | import ncsu_pkg::*; 4 | import my_pkg::*; 5 | `include "ncsu_macros.svh" 6 | `include "i2c_macros.svh" 7 | 8 | `include "src/i2c_type.svh" 9 | `include "src/i2c_transaction.svh" 10 | `include "src/i2c_transaction_rand.svh" 11 | `include "src/i2c_configuration.svh" 12 | `include "src/i2c_driver.svh" 13 | `include "src/i2c_monitor.svh" 14 | `include "src/i2c_agent.svh" 15 | 16 | endpackage 17 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/wb_pkg.sv: -------------------------------------------------------------------------------- 1 | package wb_pkg; 2 | import ncsu_pkg::*; 3 | import my_pkg::*; 4 | `include "ncsu_macros.svh" 5 | `include "wb_macros.svh" 6 | 7 | `include "src/wb_type.svh" 8 | `include "src/wb_transaction.svh" 9 | `include "src/wb_transaction_rand.svh" 10 | `include "src/wb_irq_transaction.svh" 11 | `include "src/wb_configuration.svh" 12 | `include "src/wb_driver.svh" 13 | `include "src/wb_monitor.svh" 14 | `include "src/wb_agent.svh" 15 | 16 | endpackage 17 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/ncsu_macros.svh: -------------------------------------------------------------------------------- 1 | `define ncsu_register_object(T) \ 2 | typedef ncsu_object_registry #(T,`"T`") type_id; 3 | 4 | // ***************************************** 5 | // Terminal Text Color Code 6 | // BRIGHT_RED" 91 7 | // BRIGHT_GREEN" 92 8 | // BRIGHT_YELLOW" 93 9 | // BRIGHT_CYAN" 96 10 | // ***************************************** 11 | 12 | `ifdef TERMINAL 13 | `define displayY(x) $display("\033[93m%s\033[0m",x); 14 | `else 15 | `define displayY(x) $display("%s",x); 16 | `endif 17 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/ncsu_pkg.sv: -------------------------------------------------------------------------------- 1 | package ncsu_pkg; 2 | 3 | `include "ncsu_macros.svh" 4 | 5 | `include "src/ncsu_pkg_version.svh" 6 | `include "src/ncsu_typedefs.svh" 7 | `include "src/ncsu_void.svh" 8 | `include "src/ncsu_object.svh" 9 | `include "src/ncsu_config_db.svh" 10 | `include "src/ncsu_configuration.svh" 11 | 12 | `include "src/ncsu_component_base.svh" 13 | `include "src/ncsu_component.svh" 14 | `include "src/ncsu_object_wrapper.svh" 15 | `include "src/ncsu_object_factory.svh" 16 | `include "src/ncsu_object_registry.svh" 17 | `include "src/ncsu_transaction.svh" 18 | endpackage 19 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_pkg_version.svh: -------------------------------------------------------------------------------- 1 | `define NCSU_MAJOR_VERSION 1 2 | `define NCSU_MINOR_VERSION 0 3 | `define NCSU_LETTER_VERSION "a" 4 | 5 | class ncsu_pkg_version; 6 | 7 | static bit b = print_version(); 8 | static function bit print_version(); 9 | 10 | $display("----------------------------------------------------------------"); 11 | $display("// NCSU Package "); 12 | $display("// Version %0d.%0d%s" , `NCSU_MAJOR_VERSION , `NCSU_MINOR_VERSION, `NCSU_LETTER_VERSION); 13 | $display("----------------------------------------------------------------"); 14 | $display("\n"); 15 | return 1; 16 | endfunction 17 | 18 | endclass 19 | 20 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_object_registry.svh: -------------------------------------------------------------------------------- 1 | class ncsu_object_registry #( type T=ncsu_object, string T_NAME="") extends ncsu_object_wrapper; 2 | 3 | typedef ncsu_object_registry #(T,T_NAME) this_type; 4 | 5 | virtual function string get_type_name(); 6 | return T_NAME; 7 | endfunction 8 | 9 | static this_type me = get(); 10 | 11 | static function this_type get(); 12 | if ( me == null ) begin 13 | ncsu_object_factory f_obj = ncsu_object_factory::get(); 14 | me = new(); 15 | f_obj.register_object(me); 16 | end 17 | return me; 18 | endfunction 19 | 20 | virtual function ncsu_object create_object(string name =""); 21 | T obj; 22 | obj = new(name); 23 | return obj; 24 | endfunction 25 | 26 | endclass 27 | -------------------------------------------------------------------------------- /project_benches/proj_3/transcript: -------------------------------------------------------------------------------- 1 | # // Questa Sim 2 | # // Version 2021.2_2 linux Jun 19 2021 3 | # // 4 | # // Copyright 1991-2021 Mentor Graphics Corporation 5 | # // All Rights Reserved. 6 | # // 7 | # // QuestaSim and its associated documentation contain trade 8 | # // secrets and commercial or financial information that are the property of 9 | # // Mentor Graphics Corporation and are privileged, confidential, 10 | # // and exempt from disclosure under the Freedom of Information Act, 11 | # // 5 U.S.C. Section 552. Furthermore, this information 12 | # // is prohibited from disclosure under the Trade Secrets Act, 13 | # // 18 U.S.C. Section 1905. 14 | # // 15 | # Project file /afs/unity.ncsu.edu/users/z/zli87/ece-745-Projects/ece745_projects/project_benches/proj1/sim/tt1.mpf was not found. 16 | # Unable to open project. 17 | -------------------------------------------------------------------------------- /project_benches/proj_4/transcript: -------------------------------------------------------------------------------- 1 | # // Questa Sim 2 | # // Version 2021.2_2 linux Jun 19 2021 3 | # // 4 | # // Copyright 1991-2021 Mentor Graphics Corporation 5 | # // All Rights Reserved. 6 | # // 7 | # // QuestaSim and its associated documentation contain trade 8 | # // secrets and commercial or financial information that are the property of 9 | # // Mentor Graphics Corporation and are privileged, confidential, 10 | # // and exempt from disclosure under the Freedom of Information Act, 11 | # // 5 U.S.C. Section 552. Furthermore, this information 12 | # // is prohibited from disclosure under the Trade Secrets Act, 13 | # // 18 U.S.C. Section 1905. 14 | # // 15 | # Project file /afs/unity.ncsu.edu/users/z/zli87/ece-745-Projects/ece745_projects/project_benches/proj1/sim/tt1.mpf was not found. 16 | # Unable to open project. 17 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_transaction.svh: -------------------------------------------------------------------------------- 1 | class ncsu_transaction extends ncsu_object; 2 | 3 | int transaction_id; 4 | static int transaction_count; 5 | time start_time, end_time; 6 | int transaction_view_h; 7 | 8 | function new(string name=""); 9 | super.new(name); 10 | this.name = name; 11 | transaction_id = transaction_count++; 12 | endfunction 13 | 14 | virtual function string convert2string(); 15 | return $sformatf("name: %s transaction_count: %0d ",name,transaction_id); 16 | endfunction 17 | 18 | virtual function void add_to_wave(int transaction_viewing_stream_h); 19 | if ( transaction_view_h == 0) 20 | transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"Transaction",start_time); 21 | $add_attribute( transaction_view_h, transaction_id, "transaction_id" ); 22 | endfunction 23 | 24 | endclass 25 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_component_base.svh: -------------------------------------------------------------------------------- 1 | class ncsu_component_base extends ncsu_object; 2 | 3 | ncsu_component_base parent; 4 | int transaction_viewing_stream; 5 | bit enable_transaction_viewing; 6 | 7 | function new(string name="", ncsu_component_base parent=null); 8 | super.new(name); 9 | this.parent = parent; 10 | endfunction 11 | 12 | virtual function string get_name(); 13 | return(name); 14 | endfunction 15 | 16 | virtual function string get_full_name(); 17 | if ( parent == null ) return (name); 18 | else return ({parent.get_full_name(),".",name}); 19 | endfunction 20 | 21 | virtual function void build(); 22 | if (enable_transaction_viewing) begin 23 | transaction_viewing_stream = $create_transaction_stream({"\\",get_full_name(),".txn_stream"}); 24 | end 25 | endfunction 26 | endclass 27 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_typedefs.svh: -------------------------------------------------------------------------------- 1 | // Enum: ncsu_verbosity 2 | // 3 | // Defines standard verbosity levels for reports. 4 | // 5 | // NCSU_NONE - Report is always printed. Verbosity level setting can not 6 | // disable it. 7 | // NCSU_LOW - Report is issued if configured verbosity is set to UVM_LOW 8 | // or above. 9 | // NCSU_MEDIUM - Report is issued if configured verbosity is set to UVM_MEDIUM 10 | // or above. 11 | // NCSU_HIGH - Report is issued if configured verbosity is set to UVM_HIGH 12 | // or above. 13 | // NCSU_FULL - Report is issued if configured verbosity is set to UVM_FULL 14 | // or above. 15 | 16 | typedef enum 17 | { 18 | NCSU_NONE = 0, 19 | NCSU_LOW = 100, 20 | NCSU_MEDIUM = 200, 21 | NCSU_HIGH = 300, 22 | NCSU_FULL = 400, 23 | NCSU_DEBUG = 500 24 | } ncsu_verbosity_e; 25 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/i2cmb_env_pkg.sv: -------------------------------------------------------------------------------- 1 | package i2cmb_env_pkg; 2 | import ncsu_pkg::*; 3 | import my_pkg::*; 4 | import wb_pkg::*; 5 | import i2c_pkg::*; 6 | `include "../../ncsu_pkg/ncsu_macros.svh" 7 | 8 | `include "src/i2cmb_type.svh" 9 | `include "src/i2cmb_generator.svh" 10 | `include "src/i2cmb_generator_register_test.svh" 11 | `include "src/i2cmb_generator_control_functionality_test.svh" 12 | `include "src/i2cmb_generator_fsm_functionality_test.svh" 13 | `include "src/i2cmb_generator_direct_test.svh" 14 | `include "src/i2cmb_generator_random_test.svh" 15 | `include "src/i2cmb_env_configuration.svh" 16 | `include "src/i2cmb_predictor.svh" 17 | `include "src/i2cmb_scoreboard.svh" 18 | `include "src/i2cmb_coverage_wb.svh" 19 | `include "src/i2cmb_coverage_i2c.svh" 20 | `include "src/i2cmb_environment.svh" 21 | `include "src/i2cmb_test.svh" 22 | 23 | endpackage 24 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_object_factory.svh: -------------------------------------------------------------------------------- 1 | class ncsu_object_factory extends ncsu_object; 2 | static ncsu_object_wrapper m_object_type_names[string]; 3 | static ncsu_object_factory m_object_factory_inst; 4 | 5 | static function ncsu_object_factory get(); 6 | if ( m_object_factory_inst == null) m_object_factory_inst = new(); 7 | return m_object_factory_inst; 8 | endfunction 9 | 10 | static function void register_object(ncsu_object_wrapper c); 11 | m_object_type_names[c.get_type_name()] = c; 12 | endfunction 13 | 14 | static function ncsu_object create(string obj_name); 15 | if ( m_object_type_names.exists(obj_name) ) begin 16 | return m_object_type_names[obj_name].create_object(obj_name); 17 | end else begin 18 | $display("FATAL: ncsu_object_factory::create() - %s class not registered with object factory", obj_name); 19 | $fatal; 20 | end 21 | endfunction 22 | 23 | endclass 24 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/src/.__afsFEDD: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------ 2 | 3 | //------------------------------------------------------------------ 4 | 5 | virtual class my_port_component_base#(T) extends ncsu_component#(.T(T)); 6 | 7 | function new (string name, ncsu_component#(.T(T)) parent); 8 | super.new(name,parent); 9 | endfunction 10 | 11 | // pure virtual function void get_connected_to(ref uvm_port_list list); 12 | 13 | pure virtual function bit is_port(); 14 | 15 | pure virtual function bit is_export(); 16 | 17 | pure virtual function bit is_imp(); 18 | 19 | pure virtual function void nb_put(input T trans); 20 | 21 | pure virtual task bl_get(output T trans); 22 | 23 | pure virtual function void nb_get(output T trans); 24 | 25 | pure virtual task bl_transport(input T input_trans, output T output_trans); 26 | 27 | pure virtual function void nb_transport(input T input_trans, output T output_trans); 28 | 29 | endclass 30 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/work/optimized_debug_top_tb/_data/exempt9gKImX: -------------------------------------------------------------------------------- 1 | 16UYONhzeNM1H42SUig6:121,82lYKkN8@dhJb<8:lmg[me38,845l:WUj8KN4WPTWM]7:dC223,85OaeHoFoWjA_1b_YI;enk29,85jz?^ehc5BJlXB2Z2C<3T213,87`A0I`noiLoNWW_Uo@D=m11,88VY1F[^in>Rg:=U?8ncmG14,8FCm`c4XNY3Hd^ma1IBCD1017,8FdKe9^A7XPPN`kn119,8b>c5hOm:MdSVhkYW=Rzh[118,8dUnIkml4`039I6@5JjmYD116,8f`B00HHA2_JEmb8Ja6>>C015,8gfD3?Pdhn6m=j1NmWJPSN12,8zEH[MW4HJLeMImza5WfOz06,8 -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_test.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_test extends ncsu_component #(.T(wb_transaction)); 2 | 3 | i2cmb_env_configuration cfg; 4 | i2cmb_environment env; 5 | i2cmb_generator gen; 6 | string gen_type; 7 | 8 | function new(string name="", ncsu_component_base parent=null); 9 | super.new(name, parent); 10 | 11 | if(!$value$plusargs("GEN_TYPE=%s", gen_type)) $fatal("FATAL: +GEN_TYPE plusarg not found on command line"); 12 | else ncsu_info("i2cmb_test::new()", $sformatf("found +GEN_TYPE=%s", gen_type),NCSU_NONE); 13 | 14 | cfg = new(gen_type); 15 | env = new("env", this); 16 | env.set_configuration(cfg); 17 | env.build(); 18 | // !TBD: in project3 & project4 19 | // dynamic construction of generator class 20 | 21 | $cast(gen, ncsu_object_factory::create(gen_type)); 22 | //gen = new("gen", this); 23 | gen.set_wb_agent(env.get_wb_agent()); 24 | gen.set_i2c_agent(env.get_i2c_agent()); 25 | endfunction 26 | 27 | virtual task run(); 28 | env.run(); 29 | gen.run(); 30 | endtask 31 | 32 | endclass 33 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/src/.__afs2DA7: -------------------------------------------------------------------------------- 1 | class my_blocking_put_port#(T) extends my_port_component_base#(.T(T)); 2 | 3 | typedef my_port_component_base#(.T(T)) my_port; 4 | typedef ncsu_component#(.T(T)) parent_type; 5 | 6 | function new (string name, parent_type parent); 7 | super.new(name,parent); 8 | endfunction 9 | 10 | // input: 11 | function void connect( input my_port PORT ); 12 | endfunction 13 | 14 | virtual function bit is_port(); 15 | return 1; 16 | endfunction 17 | 18 | virtual function bit is_export(); 19 | return 0; 20 | endfunction 21 | 22 | virtual function bit is_imp(); 23 | return 0; 24 | endfunction 25 | 26 | virtual function void nb_put(input T trans); 27 | endfunction 28 | 29 | virtual task bl_get(output T trans); 30 | endtask 31 | 32 | virtual function void nb_get(output T trans); 33 | endfunction 34 | 35 | virtual task bl_transport(input T input_trans, output T output_trans); 36 | endtask 37 | 38 | virtual function void nb_transport(input T input_trans, output T output_trans); 39 | endfunction 40 | 41 | endclass 42 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_monitor.svh: -------------------------------------------------------------------------------- 1 | class i2c_monitor extends ncsu_component#(.T(i2c_transaction)); 2 | 3 | i2c_configuration i2c_cfg0; 4 | virtual i2c_if#(.I2C_ADDR_WIDTH(I2C_ADDR_WIDTH), .I2C_DATA_WIDTH(I2C_DATA_WIDTH)) i2c_bus; 5 | T i2c_monitor_trans; 6 | T i2c_byte_trans; 7 | ncsu_component#(T) agent; 8 | 9 | function new(string name="", ncsu_component_base parent=null); 10 | super.new(name, parent); 11 | endfunction 12 | 13 | function void set_configuration(i2c_configuration cfg); 14 | i2c_cfg0 = cfg; 15 | endfunction 16 | 17 | function void set_agent(ncsu_component#(T) agent); 18 | this.agent = agent; 19 | endfunction 20 | 21 | virtual task run(); 22 | forever begin 23 | // $display("i2c monitor1"); 24 | $cast(i2c_monitor_trans, ncsu_object_factory::create("i2c_transaction")); 25 | i2c_bus.monitor(i2c_monitor_trans.i2c_addr, i2c_monitor_trans.i2c_op, i2c_monitor_trans.i2c_data); 26 | // $display("i2c monitor"); 27 | this.agent.nb_put(i2c_monitor_trans); 28 | end 29 | endtask 30 | 31 | endclass 32 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/src/.__afs40DB: -------------------------------------------------------------------------------- 1 | class my_blocking_put_export#(T) extends my_port_component_base#(.T(T)); 2 | 3 | typedef my_port_component_base#(.T(T)) my_port; 4 | typedef ncsu_component#(.T(T)) parent_type; 5 | 6 | my_port port; 7 | 8 | function new (string name, parent_type parent); 9 | super.new(name,parent); 10 | endfunction 11 | 12 | // input: my_blocking_put_imp 13 | function void connect( input my_port PORT ); 14 | this.port = PORT; 15 | endfunction 16 | 17 | virtual function bit is_port(); 18 | return 0; 19 | endfunction 20 | 21 | virtual function bit is_export(); 22 | return 1; 23 | endfunction 24 | 25 | virtual function bit is_imp(); 26 | return 0; 27 | endfunction 28 | 29 | virtual function void nb_put(input T trans); 30 | endfunction 31 | 32 | virtual task bl_get(output T trans); 33 | endtask 34 | 35 | virtual function void nb_get(output T trans); 36 | endfunction 37 | 38 | virtual task bl_transport(input T input_trans, output T output_trans); 39 | endtask 40 | 41 | virtual function void nb_transport(input T input_trans, output T output_trans); 42 | endfunction 43 | 44 | endclass 45 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_monitor.svh: -------------------------------------------------------------------------------- 1 | class wb_monitor extends ncsu_component#(.T(wb_transaction)); 2 | 3 | wb_configuration wb_cfg0; 4 | virtual wb_if#(.ADDR_WIDTH(WB_ADDR_WIDTH), .DATA_WIDTH(WB_DATA_WIDTH)) wb_bus; 5 | T monitor_trans; 6 | T wb_irq_trans; 7 | ncsu_component#(T) agent; 8 | 9 | function new(string name ="", ncsu_component_base parent=null); 10 | super.new(name, parent); 11 | endfunction 12 | 13 | function void set_configuration(wb_configuration cfg); 14 | wb_cfg0 = cfg; 15 | endfunction 16 | 17 | function void set_agent(ncsu_component#(T) agent); 18 | this.agent = agent; 19 | endfunction 20 | 21 | virtual task run(); 22 | wb_bus.wait_for_reset(); 23 | fork 24 | begin forever begin 25 | $cast(monitor_trans, ncsu_object_factory::create("wb_transaction")); 26 | wb_bus.master_monitor(monitor_trans.wb_addr, monitor_trans.wb_data, monitor_trans.wb_op); 27 | this.agent.nb_put(monitor_trans); 28 | end end 29 | begin forever begin 30 | wb_bus.wait_for_interrupt(); 31 | $cast( wb_irq_trans, ncsu_object_factory::create("wb_irq_transaction")); 32 | this.agent.nb_put(wb_irq_trans); 33 | end end 34 | join 35 | endtask 36 | 37 | endclass 38 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/src/.__afs5B1D: -------------------------------------------------------------------------------- 1 | class my_blocking_put_imp#(T) extends my_port_component_base#(.T(T)); 2 | 3 | typedef my_port_component_base#(.T(T)) my_port; 4 | typedef ncsu_component#(.T(T)) parent_type; 5 | 6 | my_port port; 7 | parent_type my_parent; 8 | 9 | function new (string name, parent_type parent); 10 | super.new(name,parent); 11 | my_parent = parent; 12 | endfunction 13 | 14 | function void connect( input my_port PORT ); 15 | this.port = PORT; 16 | endfunction 17 | 18 | virtual function bit is_port(); 19 | return 0; 20 | endfunction 21 | 22 | virtual function bit is_export(); 23 | return 0; 24 | endfunction 25 | 26 | virtual function bit is_imp(); 27 | return 1; 28 | endfunction 29 | 30 | virtual function void nb_put(input T trans); 31 | my_parent.np_put(trans); 32 | endfunction 33 | 34 | virtual task bl_get(output T trans); 35 | endtask 36 | 37 | virtual function void nb_get(output T trans); 38 | endfunction 39 | 40 | virtual task bl_transport(input T input_trans, output T output_trans); 41 | endtask 42 | 43 | virtual function void nb_transport(input T input_trans, output T output_trans); 44 | endfunction 45 | 46 | endclass 47 | -------------------------------------------------------------------------------- /project_benches/lab_1/sim/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider I2C_MB 4 | add wave -noupdate -divider {WB Signals} 5 | add wave -noupdate /top/DUT/clk_i 6 | add wave -noupdate /top/DUT/rst_i 7 | add wave -noupdate /top/DUT/cyc_i 8 | add wave -noupdate /top/DUT/stb_i 9 | add wave -noupdate /top/DUT/ack_o 10 | add wave -noupdate /top/DUT/adr_i 11 | add wave -noupdate /top/DUT/we_i 12 | add wave -noupdate /top/DUT/dat_i 13 | add wave -noupdate /top/DUT/dat_o 14 | add wave -noupdate /top/DUT/irq 15 | add wave -noupdate -divider {I2C Signals} 16 | add wave -noupdate /top/DUT/scl_i 17 | add wave -noupdate /top/DUT/sda_i 18 | add wave -noupdate /top/DUT/scl_o 19 | add wave -noupdate /top/DUT/sda_o 20 | TreeUpdate [SetDefaultTree] 21 | WaveRestoreCursors {{Cursor 1} {0 ns} 0} 22 | quietly wave cursor active 0 23 | configure wave -namecolwidth 263 24 | configure wave -valuecolwidth 100 25 | configure wave -justifyvalue left 26 | configure wave -signalnamewidth 0 27 | configure wave -snapdistance 10 28 | configure wave -datasetprefix 0 29 | configure wave -rowmargin 4 30 | configure wave -childrowmargin 2 31 | configure wave -gridoffset 0 32 | configure wave -gridperiod 1 33 | configure wave -griddelta 40 34 | configure wave -timeline 0 35 | configure wave -timelineunits ns 36 | update 37 | WaveRestoreZoom {0 ns} {888 ns} 38 | -------------------------------------------------------------------------------- /project_benches/proj_1/sim/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider I2C_MB 4 | add wave -noupdate -divider {WB Signals} 5 | add wave -noupdate /top/DUT/clk_i 6 | add wave -noupdate /top/DUT/rst_i 7 | add wave -noupdate /top/DUT/cyc_i 8 | add wave -noupdate /top/DUT/stb_i 9 | add wave -noupdate /top/DUT/ack_o 10 | add wave -noupdate /top/DUT/adr_i 11 | add wave -noupdate /top/DUT/we_i 12 | add wave -noupdate /top/DUT/dat_i 13 | add wave -noupdate /top/DUT/dat_o 14 | add wave -noupdate /top/DUT/irq 15 | add wave -noupdate -divider {I2C Signals} 16 | add wave -noupdate /top/DUT/scl_i 17 | add wave -noupdate /top/DUT/sda_i 18 | add wave -noupdate /top/DUT/scl_o 19 | add wave -noupdate /top/DUT/sda_o 20 | TreeUpdate [SetDefaultTree] 21 | WaveRestoreCursors {{Cursor 1} {0 ns} 0} 22 | quietly wave cursor active 0 23 | configure wave -namecolwidth 263 24 | configure wave -valuecolwidth 100 25 | configure wave -justifyvalue left 26 | configure wave -signalnamewidth 0 27 | configure wave -snapdistance 10 28 | configure wave -datasetprefix 0 29 | configure wave -rowmargin 4 30 | configure wave -childrowmargin 2 31 | configure wave -gridoffset 0 32 | configure wave -gridperiod 1 33 | configure wave -griddelta 40 34 | configure wave -timeline 0 35 | configure wave -timelineunits ns 36 | update 37 | WaveRestoreZoom {0 ns} {888 ns} 38 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_transaction_rand.svh: -------------------------------------------------------------------------------- 1 | class i2c_transaction_rand extends i2c_transaction; 2 | `ncsu_register_object(i2c_transaction_rand) 3 | 4 | typedef i2c_transaction_rand this_type; 5 | static this_type type_handle = get_type(); 6 | 7 | static function this_type get_type(); 8 | if(type_handle == null) 9 | type_handle = new(); 10 | return type_handle; 11 | endfunction 12 | 13 | virtual function transaction_handler get_type_handle(); 14 | return get_type(); 15 | endfunction 16 | 17 | rand bit[I2C_DATA_WIDTH-1:0] i2c_rand_data[]; 18 | 19 | constraint transfer_size { 0 < i2c_rand_data.size() && i2c_rand_data.size() <= 10; } 20 | 21 | function new(string name = ""); 22 | super.new(name); 23 | endfunction : new 24 | 25 | virtual function string convert2string(); 26 | return {super.convert2string(), $sformatf("read random data: %p", i2c_rand_data)}; 27 | endfunction 28 | 29 | function this_type set_op(i2c_op_t op); 30 | void'(super.set_op(op)); 31 | return this; 32 | endfunction 33 | 34 | virtual function bit [8-1:0] get_data_0(); 35 | return this.i2c_rand_data[0]; 36 | endfunction 37 | 38 | virtual function dynamic_arr_t get_data(); 39 | dynamic_arr_t return_dyn_arr; 40 | return_dyn_arr = i2c_rand_data; 41 | return return_dyn_arr; 42 | endfunction 43 | 44 | endclass 45 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_transaction_rand.svh: -------------------------------------------------------------------------------- 1 | class wb_transaction_rand extends wb_transaction; 2 | `ncsu_register_object(wb_transaction_rand) 3 | 4 | typedef wb_transaction_rand this_type; 5 | static this_type type_handle = get_type(); 6 | 7 | static function this_type get_type(); 8 | if(type_handle == null) 9 | type_handle = new(); 10 | return type_handle; 11 | endfunction 12 | 13 | virtual function transaction_handler get_type_handle(); 14 | return get_type(); 15 | endfunction 16 | 17 | rand bit [WB_DATA_WIDTH-1:0] wb_rand_data; 18 | 19 | function new(string name=""); 20 | super.new(name); 21 | endfunction 22 | 23 | virtual function string convert2string(); 24 | return {super.convert2string(),$sformatf(" random Data:0x%x", wb_rand_data)}; 25 | endfunction 26 | 27 | virtual function this_type set_addr(bit [WB_ADDR_WIDTH-1:0] addr); 28 | void'(super.set_addr(addr)); 29 | return this; 30 | endfunction 31 | 32 | virtual function this_type set_op(wb_op_t OP); 33 | void'(super.set_op(OP)); 34 | return this; 35 | endfunction 36 | 37 | virtual function bit [WB_DATA_WIDTH-1:0] get_data_0(); 38 | return this.wb_rand_data; 39 | endfunction 40 | 41 | virtual function automatic dynamic_arr_t get_data(); 42 | dynamic_arr_t return_dyn_arr; 43 | return_dyn_arr = new[0]; 44 | return_dyn_arr[0] = this.wb_rand_data; 45 | return return_dyn_arr; 46 | endfunction 47 | 48 | 49 | endclass 50 | -------------------------------------------------------------------------------- /project_benches/lab_1/sim/Makefile: -------------------------------------------------------------------------------- 1 | export ECE745_PROJECT_HOME ?= $(PWD)/../../.. 2 | 3 | include $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/wb_pkg/Makefile 4 | 5 | clean: 6 | rm -rf work *.wlf transcript 7 | 8 | comp_I2C_MB: 9 | vcom ../rtl/iicmb_int_pkg.vhd 10 | vcom ../rtl/iicmb_pkg.vhd 11 | vcom ../rtl/mbyte.vhd 12 | vcom ../rtl/mbit.vhd 13 | vcom ../rtl/bus_state.vhd 14 | vcom ../rtl/filter.vhd 15 | vcom ../rtl/conditioner.vhd 16 | vcom ../rtl/conditioner_mux.vhd 17 | vcom ../rtl/iicmb_m.vhd 18 | vcom ../rtl/regblock.vhd 19 | vcom ../rtl/wishbone.vhd 20 | vcom ../rtl/iicmb_m_wb.vhd 21 | 22 | 23 | comp_bench: comp_wb_pkg 24 | vlog ../testbench/top.sv 25 | 26 | optimize: 27 | vopt +acc top -o optimized_debug_top_tb 28 | 29 | compile: comp_I2C_MB comp_bench optimize 30 | 31 | simulate: 32 | vsim -i -classdebug -msgmode both -do "set NoQuitOnFinish 1; do wave.do" optimized_debug_top_tb -pli /mnt/apps/public/COE/synopsys_apps/verdi/S-2021.09-SP1/share/PLI/MODELSIM/LINUX/novas_fli.so 33 | 34 | run: comp_bench optimize 35 | vsim -batch -classdebug -msgmode both -do "set NoQuitOnFinish 1; log -r *; run -all; exit" optimized_debug_top_tb -pli /mnt/apps/public/COE/synopsys_apps/verdi/S-2021.09-SP1/share/PLI/MODELSIM/LINUX/novas_fli.so 36 | 37 | view: 38 | vsim -view vsim.wlf -do wave.do 39 | 40 | debug: clean compile simulate 41 | 42 | #vsim -c TESTBED -pli /mnt/apps/public/COE/synopsys_apps/verdi_vr-2020_12-SP2-1/share/PLI/MODELSIM/LINUX64/novas_fli.so -64 -do "run -all" 43 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_driver.svh: -------------------------------------------------------------------------------- 1 | class i2c_driver extends ncsu_component#(.T(i2c_transaction)); 2 | 3 | function new(string name = "", ncsu_component_base parent = null); 4 | super.new(name, parent); 5 | endfunction : new 6 | 7 | virtual i2c_if #(.I2C_ADDR_WIDTH(I2C_ADDR_WIDTH), .I2C_DATA_WIDTH(I2C_DATA_WIDTH)) i2c_bus; 8 | i2c_configuration i2c_cfg0; 9 | i2c_transaction i2c_trans; 10 | bit transfer_complete; 11 | 12 | function void set_configuration(i2c_configuration cfg); 13 | i2c_cfg0 = cfg; 14 | endfunction 15 | 16 | virtual task bl_put(T trans); 17 | automatic bit [I2C_DATA_WIDTH-1:0] tmp_data []; 18 | 19 | //ncsu_info("i2c_driver::bl_put() ",{ " before ", trans.convert2string()},NCSU_NONE); 20 | if(trans.i2c_op == I2C_WRITE) begin 21 | i2c_bus.wait_for_i2c_transfer(trans.i2c_op, trans.i2c_data ); 22 | end else if(trans.i2c_op == I2C_READ) begin 23 | i2c_bus.wait_for_i2c_transfer(trans.i2c_op, tmp_data ); 24 | i2c_bus.provide_read_data(trans.get_data(), transfer_complete); 25 | end 26 | //ncsu_info("i2c_driver::bl_put() ",{ " after ", trans.convert2string()},NCSU_NONE); 27 | 28 | endtask : bl_put 29 | 30 | task arb_lost_during_restart(); 31 | i2c_bus.arb_lost_during_restart(); 32 | endtask 33 | 34 | task arb_lost_during_write(); 35 | i2c_bus.arb_lost_during_write(); 36 | endtask 37 | task arb_lost_during_read(); 38 | i2c_bus.arb_lost_during_read(); 39 | endtask 40 | task reset(); 41 | i2c_bus.reset(); 42 | endtask 43 | endclass 44 | -------------------------------------------------------------------------------- /project_benches/proj_2/sim/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider I2C_MB 4 | add wave -noupdate -divider {WB Signals} 5 | add wave -noupdate /top/DUT/clk_i 6 | add wave -noupdate /top/DUT/rst_i 7 | add wave -noupdate /top/DUT/cyc_i 8 | add wave -noupdate /top/DUT/stb_i 9 | add wave -noupdate /top/DUT/ack_o 10 | add wave -noupdate /top/DUT/adr_i 11 | add wave -noupdate /top/adr_enum 12 | add wave -noupdate /top/DUT/we_i 13 | add wave -noupdate /top/DUT/dat_i 14 | add wave -noupdate /top/DUT/dat_o 15 | add wave -noupdate /top/dat_o_enum 16 | add wave -noupdate /top/DUT/irq 17 | add wave -noupdate -divider {I2C Signals} 18 | add wave -noupdate /top/DUT/scl_i[5] 19 | add wave -noupdate /top/DUT/sda_i[5] 20 | add wave -noupdate /top/DUT/scl_i 21 | add wave -noupdate /top/DUT/sda_i 22 | add wave -noupdate /top/DUT/scl_o 23 | add wave -noupdate /top/DUT/sda_o 24 | TreeUpdate [SetDefaultTree] 25 | WaveRestoreCursors {{Cursor 1} {0 ns} 0} 26 | quietly wave cursor active 0 27 | configure wave -namecolwidth 263 28 | configure wave -valuecolwidth 100 29 | configure wave -justifyvalue left 30 | configure wave -signalnamewidth 0 31 | configure wave -snapdistance 10 32 | configure wave -datasetprefix 0 33 | configure wave -rowmargin 4 34 | configure wave -childrowmargin 2 35 | configure wave -gridoffset 0 36 | configure wave -gridperiod 1 37 | configure wave -griddelta 40 38 | configure wave -timeline 0 39 | configure wave -timelineunits ns 40 | update 41 | WaveRestoreZoom {0 ns} {888 ns} 42 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider I2C_MB 4 | add wave -noupdate -divider {WB Signals} 5 | add wave -noupdate /top/DUT/clk_i 6 | add wave -noupdate /top/DUT/rst_i 7 | add wave -noupdate /top/DUT/cyc_i 8 | add wave -noupdate /top/DUT/stb_i 9 | add wave -noupdate /top/DUT/ack_o 10 | add wave -noupdate /top/DUT/adr_i 11 | add wave -noupdate /top/adr_enum 12 | add wave -noupdate /top/DUT/we_i 13 | add wave -noupdate /top/DUT/dat_i 14 | add wave -noupdate /top/DUT/dat_o 15 | add wave -noupdate /top/dat_o_enum 16 | add wave -noupdate /top/DUT/irq 17 | add wave -noupdate -divider {I2C Signals} 18 | add wave -noupdate /top/DUT/scl_i[5] 19 | add wave -noupdate /top/DUT/sda_i[5] 20 | add wave -noupdate /top/DUT/scl_i 21 | add wave -noupdate /top/DUT/sda_i 22 | add wave -noupdate /top/DUT/scl_o 23 | add wave -noupdate /top/DUT/sda_o 24 | add wave -noupdate /top/DUT/iicmb_m_inst0/mbit_inst0/state 25 | add wave -noupdate /top/DUT/iicmb_m_inst0/mbit_inst0/mbr 26 | TreeUpdate [SetDefaultTree] 27 | WaveRestoreCursors {{Cursor 1} {0 ns} 0} 28 | quietly wave cursor active 0 29 | configure wave -namecolwidth 263 30 | configure wave -valuecolwidth 100 31 | configure wave -justifyvalue left 32 | configure wave -signalnamewidth 0 33 | configure wave -snapdistance 10 34 | configure wave -datasetprefix 0 35 | configure wave -rowmargin 4 36 | configure wave -childrowmargin 2 37 | configure wave -gridoffset 0 38 | configure wave -gridperiod 1 39 | configure wave -griddelta 40 40 | configure wave -timeline 0 41 | configure wave -timelineunits ns 42 | update 43 | WaveRestoreZoom {0 ns} {888 ns} 44 | -------------------------------------------------------------------------------- /project_benches/proj_4/sim/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate -divider I2C_MB 4 | add wave -noupdate -divider {WB Signals} 5 | add wave -noupdate /top/DUT/clk_i 6 | add wave -noupdate /top/DUT/rst_i 7 | add wave -noupdate /top/DUT/cyc_i 8 | add wave -noupdate /top/DUT/stb_i 9 | add wave -noupdate /top/DUT/ack_o 10 | add wave -noupdate /top/DUT/adr_i 11 | add wave -noupdate /top/adr_enum 12 | add wave -noupdate /top/DUT/we_i 13 | add wave -noupdate /top/DUT/dat_i 14 | add wave -noupdate /top/DUT/dat_o 15 | add wave -noupdate /top/dat_o_enum 16 | add wave -noupdate /top/DUT/irq 17 | add wave -noupdate -divider {I2C Signals} 18 | add wave -noupdate /top/DUT/scl_i[5] 19 | add wave -noupdate /top/DUT/sda_i[5] 20 | add wave -noupdate /top/DUT/scl_i 21 | add wave -noupdate /top/DUT/sda_i 22 | add wave -noupdate /top/DUT/scl_o 23 | add wave -noupdate /top/DUT/sda_o 24 | add wave -noupdate /top/DUT/iicmb_m_inst0/mbit_inst0/state 25 | add wave -noupdate /top/DUT/iicmb_m_inst0/mbit_inst0/mbr 26 | TreeUpdate [SetDefaultTree] 27 | WaveRestoreCursors {{Cursor 1} {0 ns} 0} 28 | quietly wave cursor active 0 29 | configure wave -namecolwidth 263 30 | configure wave -valuecolwidth 100 31 | configure wave -justifyvalue left 32 | configure wave -signalnamewidth 0 33 | configure wave -snapdistance 10 34 | configure wave -datasetprefix 0 35 | configure wave -rowmargin 4 36 | configure wave -childrowmargin 2 37 | configure wave -gridoffset 0 38 | configure wave -gridperiod 1 39 | configure wave -griddelta 40 40 | configure wave -timeline 0 41 | configure wave -timelineunits ns 42 | update 43 | WaveRestoreZoom {0 ns} {888 ns} 44 | -------------------------------------------------------------------------------- /project_benches/proj_3/sim/transcript: -------------------------------------------------------------------------------- 1 | # // Questa Sim 2 | # // Version 2020.4_1 linux Nov 6 2020 3 | # // 4 | # // Copyright 1991-2020 Mentor Graphics Corporation 5 | # // All Rights Reserved. 6 | # // 7 | # // QuestaSim and its associated documentation contain trade 8 | # // secrets and commercial or financial information that are the property of 9 | # // Mentor Graphics Corporation and are privileged, confidential, 10 | # // and exempt from disclosure under the Freedom of Information Act, 11 | # // 5 U.S.C. Section 552. Furthermore, this information 12 | # // is prohibited from disclosure under the Trade Secrets Act, 13 | # // 18 U.S.C. Section 1905. 14 | # // 15 | # do load_ucdbs_and_merge_with_test_plan.do 16 | # Format 'Excel' read from parameter file. 17 | # 40 testplan section(s) added. 18 | # Database './i2cmb_test_plan.ucdb' written. 19 | # Merging file ./i2cmb_generator_register_test.3074353043.ucdb 20 | # Merging file ./i2cmb_generator_fsm_functionality_test.1421797240.ucdb 21 | # Merging file ./i2cmb_generator_control_functionality_test.4148094673.ucdb 22 | # Merging file ./i2cmb_test_plan.ucdb 23 | # Writing merged result to i2cmb_test_plan.ucdb 24 | # 25 | # Applying tag commands ... 26 | # All tags are applied successfully. 27 | coverage open /afs/unity.ncsu.edu/users/z/zli87/ece-745-Projects/ece745_projects/project_benches/proj_3/sim/i2cmb_test_plan.ucdb 28 | # coverage read -dataset i2cmb_test_plan /afs/unity.ncsu.edu/users/z/zli87/ece-745-Projects/ece745_projects/project_benches/proj_3/sim/i2cmb_test_plan.ucdb 29 | # /afs/unity.ncsu.edu/users/z/zli87/ece-745-Projects/ece745_projects/project_benches/proj_3/sim/i2cmb_test_plan.ucdb opened as coverage dataset "i2cmb_test_plan" 30 | -------------------------------------------------------------------------------- /project_benches/proj_1/sim/Makefile: -------------------------------------------------------------------------------- 1 | # if you execute "module load synopsys" then you can uncomment FSDB 2 | OPT = #FSDB 3 | 4 | export ECE745_PROJECT_HOME ?= $(PWD)/../../.. 5 | 6 | include $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/wb_pkg/Makefile 7 | include $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/i2c_pkg/Makefile 8 | 9 | clean: 10 | rm -rf work *.wlf transcript 11 | 12 | comp_I2C_MB: 13 | vcom ../rtl/iicmb_int_pkg.vhd 14 | vcom ../rtl/iicmb_pkg.vhd 15 | vcom ../rtl/mbyte.vhd 16 | vcom ../rtl/mbit.vhd 17 | vcom ../rtl/bus_state.vhd 18 | vcom ../rtl/filter.vhd 19 | vcom ../rtl/conditioner.vhd 20 | vcom ../rtl/conditioner_mux.vhd 21 | vcom ../rtl/iicmb_m.vhd 22 | vcom ../rtl/regblock.vhd 23 | vcom ../rtl/wishbone.vhd 24 | vcom ../rtl/iicmb_m_wb.vhd 25 | 26 | 27 | comp_bench: comp_wb_pkg comp_i2c_pkg 28 | vlog +define+$(OPT) ../testbench/top.sv 29 | #vlog ../testbench/top.sv 30 | 31 | optimize: 32 | vopt +acc top -o optimized_debug_top_tb 33 | 34 | compile: comp_I2C_MB comp_bench optimize 35 | 36 | simulate: 37 | vsim -i -classdebug -msgmode both -l transcript -do "set NoQuitOnFinish 1; do wave.do" optimized_debug_top_tb 38 | 39 | run: clean compile 40 | vsim -batch -classdebug -msgmode both -l transcript -do "set NoQuitOnFinish 1; add wave -r *; log -r *; run -all; exit" optimized_debug_top_tb #-pli /mnt/apps/public/COE/synopsys_apps/verdi/S-2021.09-SP1/share/PLI/MODELSIM/LINUX/novas_fli.so 41 | 42 | view: 43 | vsim -view vsim.wlf -do wave.do 44 | 45 | #nWave: 46 | # nWave -f proj1.fsdb 47 | 48 | debug: clean compile simulate 49 | 50 | #vsim -c TESTBED -pli /mnt/apps/public/COE/synopsys_apps/verdi_vr-2020_12-SP2-1/share/PLI/MODELSIM/LINUX64/novas_fli.so -64 -do "run -all" 51 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_type.svh: -------------------------------------------------------------------------------- 1 | parameter bit [7:0] I2C_BUS_ID = 8'h05; 2 | parameter int NUM_I2C_BUSSES = 13; 3 | 4 | typedef enum bit [3:0] { 5 | S_IDLE = 4'd0, 6 | S_BUS_TAKEN = 4'd1, 7 | S_START_PENDING = 4'd2, 8 | S_START = 4'd3, 9 | S_STOP = 4'd4, 10 | S_WRITE_BYTE = 4'd5, 11 | S_READ_BYTE = 4'd6, 12 | S_WAIT = 4'd7 13 | } BYTE_FSM_STATE; 14 | 15 | typedef enum bit [0:3] { 16 | SS_IDLE = 4'd0, 17 | SS_START_A = 4'd1, 18 | SS_START_B = 4'd2, 19 | SS_START_C = 4'd3, 20 | SS_RW_A = 4'd4, 21 | SS_RW_B = 4'd5, 22 | SS_RW_C = 4'd6, 23 | SS_RW_D = 4'd7, 24 | SS_RW_E = 4'd8, 25 | SS_STOP_A = 4'd9, 26 | SS_STOP_B = 4'd10, 27 | SS_STOP_C = 4'd11, 28 | SS_RSTART_A = 4'd12, 29 | SS_RSTART_B = 4'd13, 30 | SS_RSTART_C = 4'd14 31 | } BIT_FSM_STATE; 32 | 33 | // **************************************************************************** 34 | // Define register structure 35 | 36 | typedef struct{ 37 | bit don; 38 | bit nak; 39 | bit al; 40 | bit err; 41 | bit r; 42 | iicmb_cmdr_t cmd; 43 | } CMDR_REG; 44 | 45 | typedef struct{ 46 | bit e; 47 | bit ie; 48 | bit bb; 49 | bit bc; 50 | bit [3:0] bus_id; 51 | } CSR_REG; 52 | 53 | typedef struct{ 54 | BYTE_FSM_STATE byte_fsm; 55 | bit [3:0] bit_fsm; 56 | } FSMR_REG; 57 | 58 | string map_state_name[ BYTE_FSM_STATE ] = '{ 59 | S_IDLE: "S_IDLE", 60 | S_BUS_TAKEN: "S_BUS_TAKEN" 61 | }; 62 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_component.svh: -------------------------------------------------------------------------------- 1 | typedef ncsu_transaction; 2 | class ncsu_component#(type T=ncsu_transaction) extends ncsu_component_base; 3 | 4 | function new(string name="", ncsu_component_base parent=null); 5 | super.new(name); 6 | this.parent = parent; 7 | endfunction 8 | 9 | virtual function void build(); 10 | super.build(); 11 | ncsu_info("ncsu_component::build()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 12 | endfunction 13 | 14 | virtual task run(); 15 | ncsu_info("ncsu_component::run()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 16 | endtask 17 | 18 | virtual task bl_put(input T trans); 19 | ncsu_info("ncsu_component::bl_put()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 20 | endtask 21 | 22 | virtual function void nb_put(input T trans); 23 | ncsu_info("ncsu_component::nb_put()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 24 | endfunction 25 | 26 | virtual task bl_get(output T trans); 27 | ncsu_info("ncsu_component::bl_get()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 28 | endtask 29 | 30 | virtual function void nb_get(output T trans); 31 | ncsu_info("ncsu_component::nb_get()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 32 | endfunction 33 | 34 | virtual task bl_transport(input T input_trans, output T output_trans); 35 | ncsu_info("ncsu_component::bl_transport()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 36 | endtask 37 | 38 | virtual function void nb_transport(input T input_trans, output T output_trans); 39 | ncsu_info("ncsu_component::nb_transport()", $sformatf(" of %s called",get_full_name()), NCSU_NONE); 40 | endfunction 41 | 42 | endclass 43 | -------------------------------------------------------------------------------- /verification_ip/ncsu_pkg/src/ncsu_object.svh: -------------------------------------------------------------------------------- 1 | class ncsu_object extends ncsu_void; 2 | 3 | string name; 4 | ncsu_verbosity_e verbosity_level=NCSU_MEDIUM; 5 | static ncsu_verbosity_e global_verbosity_level=NCSU_MEDIUM; 6 | static int unsigned ncsu_warnings; 7 | static int unsigned ncsu_errors; 8 | static int unsigned ncsu_fatals; 9 | 10 | function new(string name=""); 11 | super.new(); 12 | this.name = name; 13 | endfunction 14 | 15 | function void set_verbosity(ncsu_verbosity_e new_verbosity); 16 | verbosity_level = new_verbosity; 17 | endfunction 18 | 19 | function void set_global_verbosity(ncsu_verbosity_e new_verbosity); 20 | global_verbosity_level = new_verbosity; 21 | endfunction 22 | 23 | function void ncsu_info(string id, string msg, ncsu_verbosity_e msg_verbosity); 24 | if ((verbosity_level >= msg_verbosity) | (global_verbosity_level >= msg_verbosity)) 25 | $display("NCSU_INFO:Time %t:%s: %s", $time, id, msg); 26 | endfunction 27 | 28 | function void ncsu_warning(string id, string msg); 29 | $display("NCSU_WARNING:Time %t:%s: %s", $time, id, msg); 30 | ncsu_warnings++; 31 | $warning; 32 | endfunction 33 | 34 | function void ncsu_error(string id, string msg); 35 | $display("NCSU_ERROR:Time %t:%s: %s", $time, id, msg); 36 | ncsu_errors++; 37 | $error; 38 | endfunction 39 | 40 | function void ncsu_fatal(string id, string msg); 41 | $display("NCSU_FATAL:Time %t:%s: %s", $time, id, msg); 42 | ncsu_fatals++; 43 | $fatal; 44 | endfunction 45 | 46 | function void ncsu_test_report(); 47 | $display("NCSU_WARNINGS: %d", ncsu_warnings); 48 | $display("NCSU_ERRORS: %d", ncsu_errors); 49 | $display("NCSU_FATALS: %d", ncsu_fatals); 50 | endfunction 51 | 52 | endclass 53 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_irq_transaction.svh: -------------------------------------------------------------------------------- 1 | class wb_irq_transaction extends wb_transaction; 2 | `ncsu_register_object(wb_irq_transaction) 3 | 4 | 5 | typedef wb_irq_transaction this_type; 6 | static this_type type_handle = get_type(); 7 | 8 | static function this_type get_type(); 9 | if(type_handle == null) 10 | type_handle = new(); 11 | return type_handle; 12 | endfunction 13 | 14 | virtual function transaction_handler get_type_handle(); 15 | return get_type(); 16 | endfunction 17 | 18 | // in order to differentiate from original wb_transaction 19 | // in fact, there is no need to read out this bit 20 | // detect instance type can reach the same purpose 21 | static bit irq = 1; 22 | 23 | function new(string name=""); 24 | super.new(name); 25 | endfunction 26 | 27 | virtual function string convert2string(); 28 | return {super.convert2string(),$sformatf("irq bit : %b", irq )}; 29 | endfunction 30 | /* 31 | function bit compare(wb_irq_transaction rhs); 32 | return ((this.addr == rhs.addr ) && 33 | (this.data == rhs.data) && 34 | (this.we == rhs.we)); 35 | endfunction 36 | */ 37 | 38 | virtual function bit [8-1:0] get_addr(); 39 | return 0; 40 | endfunction 41 | 42 | virtual function bit get_op(); 43 | return 0; 44 | endfunction 45 | 46 | virtual function bit [7:0] get_data_0(); 47 | return irq; 48 | endfunction 49 | 50 | virtual function bit compare (transaction_handler rhs); 51 | //return (this.get_addr() == rhs.get_addr()) && (this.get_data() == rhs.get_data()); 52 | return 1'b0; 53 | endfunction 54 | 55 | virtual function automatic dynamic_arr_t get_data(); 56 | dynamic_arr_t return_dyn_arr; 57 | return_dyn_arr = new[0]; 58 | return_dyn_arr[0] = this.irq; 59 | return return_dyn_arr; 60 | endfunction 61 | 62 | 63 | endclass 64 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_agent.svh: -------------------------------------------------------------------------------- 1 | class wb_agent extends ncsu_component #(.T(wb_transaction)); 2 | 3 | wb_configuration wb_cfg0; 4 | wb_driver wb_drv0; 5 | wb_monitor wb_mtr0; 6 | //wb_coverage wb_cov0; 7 | ncsu_component #(T) subscribers[$]; 8 | virtual wb_if#(.ADDR_WIDTH(WB_ADDR_WIDTH), .DATA_WIDTH(WB_DATA_WIDTH)) wb_bus; 9 | 10 | function new(string name= "", ncsu_component_base parent=null); 11 | super.new(name, parent); 12 | if(!(ncsu_config_db#(virtual wb_if#(.ADDR_WIDTH(WB_ADDR_WIDTH), .DATA_WIDTH(WB_DATA_WIDTH)))::get("wb_interface", this.wb_bus))) begin 13 | ncsu_fatal("wb_agent::new()",$sformatf("ncsu_config_db::get() call failed.")); 14 | end 15 | endfunction 16 | 17 | function void set_configuration(wb_configuration cfg); 18 | wb_cfg0 = cfg; 19 | endfunction 20 | 21 | virtual function void connect_subscriber(ncsu_component#(T) subs); 22 | subscribers.push_back(subs); 23 | endfunction 24 | 25 | virtual function void build(); 26 | wb_drv0 = new("wb_driver_0", this); 27 | wb_drv0.set_configuration(wb_cfg0); 28 | wb_drv0.build(); 29 | wb_drv0.wb_bus = this.wb_bus; 30 | 31 | wb_mtr0 = new("wb_monitor_0", this); 32 | wb_mtr0.set_configuration(wb_cfg0); 33 | wb_mtr0.set_agent(this); 34 | wb_mtr0.build(); 35 | wb_mtr0.wb_bus = this.wb_bus; 36 | endfunction 37 | 38 | virtual function void nb_put(T trans); 39 | foreach(subscribers[i]) subscribers[i].nb_put(trans); 40 | endfunction 41 | 42 | virtual task bl_put(T trans); 43 | wb_drv0.bl_put(trans); 44 | endtask 45 | 46 | virtual task bl_put_ref(ref T trans); 47 | wb_drv0.bl_put_ref(trans); 48 | endtask 49 | 50 | virtual task bl_put_No_Wait(T trans); 51 | wb_drv0.bl_put_No_Wait(trans); 52 | endtask 53 | 54 | virtual task wait_for_interrupt(); 55 | wb_drv0.wait_for_interrupt(); 56 | endtask 57 | 58 | virtual task run(); 59 | fork wb_mtr0.run(); join_none 60 | endtask 61 | 62 | endclass 63 | -------------------------------------------------------------------------------- /project_benches/proj_2/sim/Makefile: -------------------------------------------------------------------------------- 1 | # if you execute "module load synopsys" then you can uncomment FSDB 2 | OPT = #FSDB 3 | 4 | export ECE745_PROJECT_HOME ?= $(PWD)/../../.. 5 | 6 | include $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/wb_pkg/Makefile 7 | include $(ECE745_PROJECT_HOME)/verification_ip/interface_packages/i2c_pkg/Makefile 8 | include $(ECE745_PROJECT_HOME)/verification_ip/ncsu_pkg/Makefile 9 | include $(ECE745_PROJECT_HOME)/verification_ip/environment_packages/i2cmb_env_pkg/Makefile 10 | 11 | clean: 12 | rm -rf work *.wlf transcript 13 | 14 | comp_I2C_MB: 15 | vcom ../rtl/iicmb_int_pkg.vhd 16 | vcom ../rtl/iicmb_pkg.vhd 17 | vcom ../rtl/mbyte.vhd 18 | vcom ../rtl/mbit.vhd 19 | vcom ../rtl/bus_state.vhd 20 | vcom ../rtl/filter.vhd 21 | vcom ../rtl/conditioner.vhd 22 | vcom ../rtl/conditioner_mux.vhd 23 | vcom ../rtl/iicmb_m.vhd 24 | vcom ../rtl/regblock.vhd 25 | vcom ../rtl/wishbone.vhd 26 | vcom ../rtl/iicmb_m_wb.vhd 27 | 28 | 29 | comp_bench: comp_ncsu_pkg comp_wb_pkg comp_i2c_pkg comp_i2cmb_env_pkg 30 | vlog +define+$(OPT) ../testbench/top.sv 31 | #vlog ../testbench/top.sv 32 | 33 | optimize: 34 | vopt +acc top -o optimized_debug_top_tb 35 | 36 | compile: comp_I2C_MB comp_bench optimize 37 | 38 | simulate: 39 | vsim -i -classdebug -msgmode both -l transcript -do "set NoQuitOnFinish 1; do wave.do" optimized_debug_top_tb 40 | 41 | run: clean compile 42 | vsim -batch -classdebug -msgmode both -l transcript -do "set NoQuitOnFinish 1; add wave -r *; log -r *; run -all; exit" optimized_debug_top_tb #-pli /mnt/apps/public/COE/synopsys_apps/verdi/S-2021.09-SP1/share/PLI/MODELSIM/LINUX/novas_fli.so 43 | 44 | view: 45 | vsim -view vsim.wlf -do wave.do 46 | 47 | #nWave: 48 | # nWave -f proj1.fsdb 49 | 50 | debug: clean compile simulate 51 | 52 | #vsim -c TESTBED -pli /mnt/apps/public/COE/synopsys_apps/verdi_vr-2020_12-SP2-1/share/PLI/MODELSIM/LINUX64/novas_fli.so -64 -do "run -all" 53 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/handler_pkg/src/transaction_handler.svh: -------------------------------------------------------------------------------- 1 | class transaction_handler extends ncsu_transaction; 2 | `ncsu_register_object(transaction_handler) 3 | 4 | typedef transaction_handler this_type; 5 | static this_type type_handle = get_type(); 6 | 7 | static function this_type get_type(); 8 | if(type_handle == null) 9 | type_handle = new(); 10 | return type_handle; 11 | endfunction 12 | 13 | virtual function transaction_handler get_type_handle(); 14 | return get_type(); 15 | endfunction 16 | 17 | int transaction_id; 18 | static int transaction_count; 19 | time start_time, end_time; 20 | int transaction_view_h; 21 | 22 | function new(string name=""); 23 | super.new(name); 24 | this.name = name; 25 | transaction_id = transaction_count++; 26 | endfunction 27 | 28 | virtual function string convert2string(); 29 | return $sformatf("name: %s transaction_count: %0d ",name,transaction_id); 30 | endfunction 31 | 32 | virtual function void add_to_wave(int transaction_viewing_stream_h); 33 | if ( transaction_view_h == 0) 34 | transaction_view_h = $begin_transaction(transaction_viewing_stream_h,"Transaction",start_time); 35 | $add_attribute( transaction_view_h, transaction_id, "transaction_id" ); 36 | endfunction 37 | 38 | virtual function bit [8-1:0] get_addr(); 39 | return 0; 40 | endfunction 41 | 42 | virtual function bit get_op(); 43 | return 0; 44 | endfunction 45 | 46 | typedef bit [7:0] bit8; 47 | typedef bit8 dynamic_arr_t[]; 48 | 49 | virtual function automatic dynamic_arr_t get_data(); 50 | dynamic_arr_t return_dyn_arr; 51 | return_dyn_arr = new[0]; 52 | return return_dyn_arr; 53 | endfunction 54 | 55 | virtual function bit [8-1:0] get_data_0(); 56 | return 0; 57 | endfunction 58 | 59 | virtual function bit compare(this_type rhs); 60 | return 1'b0; 61 | endfunction 62 | 63 | endclass 64 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_driver.svh: -------------------------------------------------------------------------------- 1 | class wb_driver extends ncsu_component#(.T(wb_transaction)); 2 | 3 | wb_configuration cfg0; 4 | 5 | virtual wb_if#(.ADDR_WIDTH(WB_ADDR_WIDTH), .DATA_WIDTH(WB_DATA_WIDTH)) wb_bus; 6 | 7 | T trans; 8 | 9 | function new(string name="", ncsu_component_base parent=null); 10 | super.new(name, parent); 11 | endfunction 12 | 13 | function void set_configuration(wb_configuration cfg); 14 | cfg0 = cfg; 15 | endfunction 16 | 17 | virtual task bl_put(T trans); 18 | //ncsu_info("wb_driver::bl_put() ",{ " ", trans.convert2string()},NCSU_NONE); 19 | if(trans.wb_op==WB_WRITE) wb_bus.master_write(trans.wb_addr, trans.get_data_0()); 20 | if(trans.wb_op==WB_READ) wb_bus.master_read(trans.wb_addr, trans.wb_data); 21 | if((trans.wb_op==WB_WRITE) && (trans.wb_addr==CMDR)) begin 22 | wb_bus.wait_for_interrupt(); 23 | wb_bus.master_read(CMDR, trans.cmdr_data); 24 | end 25 | 26 | endtask 27 | 28 | virtual task bl_put_ref(ref T trans); 29 | //ncsu_info("wb_driver::bl_put() ",{ " ", trans.convert2string()},NCSU_NONE); 30 | if(trans.wb_op==WB_WRITE) wb_bus.master_write(trans.wb_addr, trans.get_data_0()); 31 | if(trans.wb_op==WB_READ) wb_bus.master_read(trans.wb_addr, trans.wb_data); 32 | if((trans.wb_op==WB_WRITE) && (trans.wb_addr==CMDR) && (trans.wb_data[2:0]!= CMD_NO_USED)) begin 33 | wb_bus.wait_for_interrupt(); 34 | wb_bus.master_read(CMDR, trans.cmdr_data); 35 | end 36 | //ncsu_info("wb_driver::bl_put() ",{ " END ", trans.convert2string()},NCSU_NONE); 37 | endtask 38 | 39 | virtual task bl_put_No_Wait(T trans); 40 | if(trans.wb_op==WB_WRITE) wb_bus.master_write(trans.wb_addr, trans.wb_data); 41 | if(trans.wb_op==WB_READ) wb_bus.master_read(trans.wb_addr, trans.wb_data); 42 | endtask 43 | 44 | virtual task wait_for_interrupt(); 45 | wb_bus.wait_for_interrupt(); 46 | endtask 47 | 48 | endclass 49 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_environment.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_environment extends ncsu_component; 2 | 3 | i2cmb_env_configuration cfg0; 4 | wb_configuration wb_cfg0; 5 | i2c_configuration i2c_cfg0; 6 | 7 | wb_agent wb_agt0; 8 | i2c_agent i2c_agt0; 9 | i2cmb_predictor pred0; 10 | i2cmb_scoreboard sb0; 11 | i2cmb_coverage_wb cov0; 12 | i2cmb_coverage_i2c cov1; 13 | 14 | function new(string name="", ncsu_component_base parent=null); 15 | super.new(name, parent); 16 | endfunction 17 | 18 | function void set_configuration(i2cmb_env_configuration cfg); 19 | cfg0 = cfg; 20 | wb_cfg0 = new(cfg.get_name()); 21 | i2c_cfg0 = new(cfg.get_name()); 22 | endfunction 23 | 24 | 25 | virtual function void build(); 26 | wb_agt0 = new("wb_agent", this); 27 | wb_agt0.set_configuration(wb_cfg0); 28 | wb_agt0.build(); 29 | i2c_agt0 = new("i2c_agent", this); 30 | i2c_agt0.set_configuration(i2c_cfg0); 31 | i2c_agt0.build(); 32 | cov0 = new("wb_coverage", this); 33 | cov0.set_configuration(cfg0); 34 | cov0.build(); 35 | cov1 = new("i2c_coverage", this); 36 | cov1.set_configuration(cfg0); 37 | cov1.build(); 38 | pred0 = new("predictor", this); 39 | pred0.set_configuration(cfg0); 40 | pred0.build(); 41 | sb0 = new("scoreboard", this); 42 | sb0.build(); 43 | i2c_agt0.connect_subscriber(sb0); 44 | i2c_agt0.connect_subscriber(cov1); 45 | // !!! if you want to connect predictor and i2c bus, 46 | // !!! you need to think about how to transfer from i2c agent's type,"ncsu_component#(i2c_transaction)", 47 | // !!! to predictor's type, "ncsu_component#(wb_transaction)". 48 | // i2c_agt0.connect_subscriber(pred0); 49 | wb_agt0.connect_subscriber(cov0); 50 | wb_agt0.connect_subscriber(pred0); 51 | pred0.set_scoreboard(sb0); 52 | endfunction 53 | 54 | function wb_agent get_wb_agent(); 55 | return wb_agt0; 56 | endfunction 57 | 58 | function i2c_agent get_i2c_agent(); 59 | return i2c_agt0; 60 | endfunction 61 | 62 | virtual task run(); 63 | wb_agt0.run(); 64 | i2c_agt0.run(); 65 | fork sb0.run(); join_none 66 | endtask 67 | 68 | endclass 69 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_coverage_i2c.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_coverage_i2c extends ncsu_component #(.T(i2c_transaction)); 2 | 3 | i2cmb_env_configuration cfg0; 4 | 5 | //***************************************************************** 6 | // variable for i2c coverage 7 | 8 | i2c_op_t i2c_op; 9 | bit [I2C_ADDR_WIDTH-1:0] i2c_addr; 10 | bit [I2C_DATA_WIDTH-1:0] i2c_data[]; 11 | int i2c_data_arr_size; 12 | event sample_i2c; 13 | 14 | //***************************************************************** 15 | // covergroups for i2c 16 | 17 | covergroup i2c_coverage @(sample_i2c); 18 | // Create 4 automatic bins, each bins cover 128/4= 32 values 19 | i2c_address: coverpoint i2c_addr { option.auto_bin_max = 4; } 20 | i2c_operation: coverpoint i2c_op; // c1.auto[I2C_WRITE], c1.auto[I2C_READ] 21 | i2c_data_value: coverpoint i2c_data[0] { option.auto_bin_max = 4; } 22 | i2c_transfer_size: coverpoint i2c_data_arr_size { 23 | bins one_transfer = {1}; 24 | bins small_transfer = {[2:10]}; 25 | bins large_transfer = {[11:$]}; 26 | } 27 | i2c_addrXop: cross i2c_address, i2c_operation; 28 | i2c_addrXtransSize: cross i2c_address, i2c_transfer_size; 29 | i2c_opXtransSize: cross i2c_operation, i2c_transfer_size; 30 | 31 | endgroup 32 | 33 | function void set_configuration(i2cmb_env_configuration cfg); 34 | cfg0 = cfg; 35 | endfunction 36 | 37 | function new(string name= "", ncsu_component_base parent = null); 38 | super.new(name, parent); 39 | i2c_coverage = new; 40 | endfunction 41 | 42 | virtual function void nb_put(T trans); 43 | // case(trans.get_type_handle()) 44 | // wb_transaction::get_type(): $display("this is wb_transaction"); 45 | // i2c_transaction::get_type(): $display("this is i2c_transaction"); 46 | // default: $display(" not in handle type"); 47 | // endcase 48 | 49 | $cast(i2c_op ,trans.get_op()); 50 | i2c_addr = trans.get_addr(); 51 | 52 | i2c_data = trans.get_data(); 53 | i2c_data_arr_size = i2c_data.size(); 54 | //$display("ENV COVERAGE/ i2c_addr: %p i2c_data: %p", i2c_addr ,i2c_data); 55 | ->>sample_i2c; 56 | 57 | endfunction 58 | 59 | endclass 60 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_scoreboard.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_scoreboard extends ncsu_component#(.T(i2c_transaction)); 2 | 3 | T expected_trans; 4 | T actual_trans; 5 | event i2c_done; 6 | event wb_done; 7 | 8 | function new(string name="", ncsu_component_base parent=null); 9 | super.new(name,parent); 10 | endfunction 11 | 12 | // call from predictor 13 | virtual function void nb_transport(input T input_trans, output T output_trans); 14 | if( i2c_op_t'(input_trans.get_op()) == I2C_READ)begin 15 | this.actual_trans = input_trans; 16 | ncsu_info("scoreboard::nb_transport()",{"actual transaction ",input_trans.convert2string()},NCSU_NONE); 17 | end 18 | if( i2c_op_t'(input_trans.get_op()) == I2C_WRITE)begin 19 | this.expected_trans = input_trans; 20 | ncsu_info("scoreboard::nb_transport()",{"expected transaction ",input_trans.convert2string()},NCSU_NONE); 21 | end 22 | ->>wb_done; 23 | 24 | endfunction 25 | 26 | // call from i2c_agent 27 | virtual function void nb_put(T trans); 28 | 29 | if( i2c_op_t'(trans.get_op()) == I2C_WRITE)begin 30 | this.actual_trans = trans; 31 | ncsu_info("scoreboard::nb_put()",{"actual transaction ",trans.convert2string()},NCSU_NONE); 32 | end 33 | if( i2c_op_t'(trans.get_op()) == I2C_READ)begin 34 | this.expected_trans = trans; 35 | ncsu_info("scoreboard::nb_put()",{"expected transaction ",trans.convert2string()},NCSU_NONE); 36 | end 37 | ->>i2c_done; 38 | 39 | endfunction 40 | 41 | virtual task run(); 42 | 43 | forever begin 44 | fork 45 | begin @(i2c_done.triggered); @(wb_done.triggered); end 46 | begin @(wb_done.triggered); @(i2c_done.triggered); end 47 | join_any 48 | disable fork; 49 | 50 | if( !this.expected_trans.compare(actual_trans)) begin 51 | ncsu_fatal("scoreboard::run()",$sformatf({get_full_name()," comparison error!"})); 52 | end 53 | if( this.expected_trans.compare(actual_trans)) ncsu_info("scoreboard::run()",{"comparison MATCH! ",$sformatf("actual trans= %p, expected_trans= %p",actual_trans.get_data(),expected_trans.get_data())},NCSU_NONE); 54 | end 55 | 56 | endtask 57 | 58 | endclass 59 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_agent.svh: -------------------------------------------------------------------------------- 1 | class i2c_agent extends ncsu_component#(.T(i2c_transaction)); 2 | 3 | i2c_configuration i2c_cfg0; 4 | i2c_driver i2c_drv0; 5 | i2c_monitor i2c_mtr0; 6 | //i2c_coverage i2c_cov0; 7 | ncsu_component #(T) subscribers[$]; 8 | // ncsu_component #(transaction_handler) pred0; 9 | 10 | virtual i2c_if #(.I2C_ADDR_WIDTH(I2C_ADDR_WIDTH), .I2C_DATA_WIDTH(I2C_DATA_WIDTH)) i2c_bus; 11 | 12 | function new(string name="", ncsu_component_base parent=null); 13 | super.new(name, parent); 14 | if(!(ncsu_config_db#(virtual i2c_if#(.I2C_ADDR_WIDTH(I2C_ADDR_WIDTH), .I2C_DATA_WIDTH(I2C_DATA_WIDTH)))::get("i2c_interface", i2c_bus))) begin 15 | ncsu_fatal("i2c_agent::new()",$sformatf("ncsu_config_db::get() call failed.")); 16 | end 17 | endfunction 18 | 19 | function void set_configuration(i2c_configuration cfg); 20 | i2c_cfg0 = cfg; 21 | endfunction 22 | 23 | virtual function void build(); 24 | i2c_drv0 = new("i2c_drv0", this); 25 | i2c_drv0.set_configuration(i2c_cfg0); 26 | i2c_drv0.build(); 27 | i2c_drv0.i2c_bus = this.i2c_bus; 28 | 29 | //i2c_cov0 = new("i2c_cov0", this); 30 | //i2c_cov0.set_configuration(i2c_cfg0); 31 | //i2c_cov0.build(); 32 | //connect_subscriber(i2c_cov0); 33 | 34 | i2c_mtr0 = new("i2c_mtr0", this); 35 | i2c_mtr0.set_configuration(i2c_cfg0); 36 | i2c_mtr0.build(); 37 | i2c_mtr0.set_agent(this); 38 | i2c_mtr0.i2c_bus = this.i2c_bus; 39 | 40 | endfunction 41 | 42 | virtual function void nb_put(T trans); 43 | foreach(subscribers[i]) subscribers[i].nb_put(trans); 44 | endfunction 45 | 46 | virtual function void connect_subscriber(ncsu_component#(T) subs); 47 | subscribers.push_back(subs); 48 | endfunction 49 | 50 | virtual task bl_put(T trans); 51 | i2c_drv0.bl_put(trans); 52 | endtask 53 | 54 | virtual task bl_get(output T trans); 55 | i2c_drv0.bl_get(trans); 56 | endtask 57 | 58 | virtual task run(); 59 | fork i2c_mtr0.run(); join_none 60 | endtask 61 | 62 | task arb_lost_during_restart(); 63 | i2c_drv0.arb_lost_during_restart(); 64 | endtask 65 | task arb_lost_during_write(); 66 | i2c_drv0.arb_lost_during_write(); 67 | endtask 68 | task arb_lost_during_read(); 69 | i2c_drv0.arb_lost_during_read(); 70 | endtask 71 | 72 | task reset(); 73 | i2c_drv0.reset(); 74 | endtask 75 | 76 | endclass 77 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/i2c_pkg/src/i2c_transaction.svh: -------------------------------------------------------------------------------- 1 | class i2c_transaction extends transaction_handler; 2 | `ncsu_register_object(i2c_transaction) 3 | 4 | typedef i2c_transaction this_type; 5 | static this_type type_handle = get_type(); 6 | 7 | static function this_type get_type(); 8 | if(type_handle == null) 9 | type_handle = new(); 10 | return type_handle; 11 | endfunction 12 | 13 | virtual function transaction_handler get_type_handle(); 14 | return get_type(); 15 | endfunction 16 | 17 | bit [I2C_DATA_WIDTH-1:0] i2c_data []; 18 | //bit [I2C_DATA_WIDTH-1:0] read_data []; 19 | bit [I2C_ADDR_WIDTH-1:0] i2c_addr; 20 | i2c_op_t i2c_op; 21 | bit ack; 22 | // bit [7:0] data []; 23 | // bit [7:0] data_random; 24 | // rand bit [7:0] data_temp; 25 | 26 | 27 | function new(string name = ""); 28 | super.new(name); 29 | endfunction : new 30 | 31 | virtual function string convert2string(); 32 | if(this.i2c_op == I2C_WRITE) 33 | return {super.convert2string(), $sformatf("write data: %p", i2c_data)}; 34 | else 35 | return {super.convert2string(), $sformatf("read data: %p", i2c_data)}; 36 | endfunction 37 | 38 | virtual function bit compare (transaction_handler rhs); 39 | return (this.get_addr() == rhs.get_addr()) && (this.get_data() == rhs.get_data()); 40 | endfunction 41 | 42 | virtual function this_type set_data(bit [I2C_DATA_WIDTH-1:0] data_buffer [$]); 43 | this.i2c_data = new [data_buffer.size()]; 44 | this.i2c_data = {>>{data_buffer}}; 45 | return this; 46 | endfunction 47 | 48 | function this_type set_op(i2c_op_t op); 49 | this.i2c_op = op; 50 | return this; 51 | endfunction 52 | 53 | virtual function bit [8-1:0] get_addr(); 54 | // because addr only has 7 bits, use the 8th unused bit to transfer ackowledgement 55 | return {this.ack, this.i2c_addr}; 56 | endfunction 57 | 58 | virtual function bit get_op(); 59 | return this.i2c_op; 60 | endfunction 61 | 62 | virtual function bit [8-1:0] get_data_0(); 63 | return this.i2c_data[0]; 64 | endfunction 65 | 66 | virtual function dynamic_arr_t get_data(); 67 | dynamic_arr_t return_dyn_arr; 68 | return_dyn_arr = i2c_data; 69 | return return_dyn_arr; 70 | endfunction 71 | 72 | endclass 73 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_transaction.svh: -------------------------------------------------------------------------------- 1 | class wb_transaction extends transaction_handler; 2 | `ncsu_register_object(wb_transaction) 3 | 4 | typedef wb_transaction this_type; 5 | static this_type type_handle = get_type(); 6 | 7 | static function this_type get_type(); 8 | if(type_handle == null) 9 | type_handle = new(); 10 | return type_handle; 11 | endfunction 12 | 13 | virtual function transaction_handler get_type_handle(); 14 | return get_type(); 15 | endfunction 16 | 17 | bit [WB_ADDR_WIDTH-1:0] wb_addr; 18 | bit [WB_DATA_WIDTH-1:0] wb_data, cmdr_data; 19 | wb_op_t wb_op; 20 | 21 | static bit irq = 0; // in order to differentiate from wb_i2c_transaction 22 | 23 | function new(string name=""); 24 | super.new(name); 25 | endfunction 26 | 27 | virtual function string convert2string(); 28 | automatic iicmb_reg_ofst_t tmp_addr = iicmb_reg_ofst_t'(wb_addr); 29 | automatic iicmb_cmdr_t tmp_cmd = iicmb_cmdr_t'(wb_data[2:0]); 30 | if(tmp_addr==CMDR) 31 | return {super.convert2string(),$sformatf("Wishbone Addr:CMDR WE:%s Data:%s",map_we_name[wb_op], map_cmd_name[tmp_cmd] )}; 32 | else 33 | return {super.convert2string(),$sformatf("Wishbone Addr:%x WE:%s Data:0x%x", map_reg_ofst_name[tmp_addr],map_we_name[wb_op], wb_data)}; 34 | endfunction 35 | /* 36 | function bit compare(wb_transaction rhs); 37 | return ((this.addr == rhs.addr ) && 38 | (this.data == rhs.data) && 39 | (this.we == rhs.we)); 40 | endfunction 41 | */ 42 | 43 | virtual function this_type set_data(bit [WB_DATA_WIDTH-1:0] data); 44 | this.wb_data = data; 45 | return this; 46 | endfunction 47 | 48 | virtual function this_type set_addr(bit [WB_ADDR_WIDTH-1:0] addr); 49 | this.wb_addr = addr; 50 | return this; 51 | endfunction 52 | 53 | virtual function this_type set_op(wb_op_t OP); 54 | this.wb_op = OP; 55 | return this; 56 | endfunction 57 | 58 | virtual function bit [8-1:0] get_addr(); 59 | return this.wb_addr; 60 | endfunction 61 | 62 | virtual function bit get_op(); 63 | return this.wb_op; 64 | endfunction 65 | 66 | virtual function bit [WB_DATA_WIDTH-1:0] get_data_0(); 67 | return this.wb_data; 68 | endfunction 69 | 70 | virtual function bit compare (transaction_handler rhs); 71 | return (this.get_addr() == rhs.get_addr()) && (this.get_data() == rhs.get_data()); 72 | //return 1'b0; 73 | endfunction 74 | 75 | virtual function automatic dynamic_arr_t get_data(); 76 | dynamic_arr_t return_dyn_arr; 77 | return_dyn_arr = new[0]; 78 | return_dyn_arr[0] = this.wb_data; 79 | return return_dyn_arr; 80 | endfunction 81 | 82 | 83 | endclass 84 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_type.svh: -------------------------------------------------------------------------------- 1 | // **************************************************************************** 2 | // Define Parameter 3 | parameter int WB_ADDR_WIDTH = 2; 4 | parameter int WB_DATA_WIDTH = 8; 5 | 6 | // **************************************************************************** 7 | // Define enum 8 | 9 | typedef enum bit { 10 | PRINT =1, 11 | NO_PRINT =0 12 | } print_t; 13 | 14 | typedef enum bit { 15 | WB_READ =0, 16 | WB_WRITE =1 17 | } wb_op_t; 18 | 19 | // ***************************************** 20 | // Name Offset Access Description 21 | // CSR 0x00 R/W Control/Status Register 22 | // DPR 0x01 R/W Data/Parameter Register 23 | // CMDR 0x02 R/W Command Register 24 | // FSMR 0x03 RO FSM States Register 25 | // ***************************************** 26 | typedef enum bit [1:0] { 27 | CSR = 2'd0, 28 | DPR = 2'd1, 29 | CMDR = 2'd2, 30 | FSMR = 2'd3 31 | } iicmb_reg_ofst_t; 32 | 33 | typedef enum bit [2:0] { 34 | CMD_SET_BUS = 3'b110, // 6 35 | CMD_START = 3'b100, // 4 36 | CMD_WRITE = 3'b001, // 1 37 | CMD_STOP = 3'b101, // 5 38 | CMD_READ_W_NAK = 3'b011, // 3 39 | CMD_READ_W_AK = 3'b010, // 2 40 | CMD_WAIT = 3'b000, // 0 41 | CMD_NO_USED = 3'b111 // 7 42 | } iicmb_cmdr_t; 43 | 44 | typedef enum bit [7:0] { 45 | CSR_E = 8'b10000000, 46 | CSR_IE = 8'b01000000, 47 | CSR_BB = 8'b00100000, 48 | CSR_BC = 8'b00010000, 49 | CSR_BUS_ID = 8'b00001111 50 | } iicmb_csr_t; 51 | 52 | typedef enum bit [7:0]{ 53 | CMDR_DON_MASK = 8'b10000000, 54 | CMDR_NAK_MASK = 8'b01000000, 55 | CMDR_AL_MASK = 8'b00100000, 56 | CMDR_ERR_MASK = 8'b00010000, 57 | CMDR_CMD_MASK = 8'b00000111 58 | } cmdr_mask_t; 59 | 60 | 61 | 62 | // **************************************************************************** 63 | // Define enum string mapping variable 64 | 65 | string map_reg_ofst_name [ iicmb_reg_ofst_t ] = '{ 66 | CSR : "CSR" , 67 | DPR : "DPR" , 68 | CMDR : "CMDR", 69 | FSMR : "FSMR" 70 | }; 71 | string map_cmd_name [ iicmb_cmdr_t ] = '{ 72 | CMD_SET_BUS : "CMD_SET_BUS", 73 | CMD_START : "CMD_START", 74 | CMD_WRITE : "CMD_WRITE", 75 | CMD_STOP : "CMD_STOP", 76 | CMD_READ_W_NAK : "CMD_READ_W_NAK", 77 | CMD_READ_W_AK : "CMD_READ_W_AK", 78 | CMD_WAIT : "CMD_WAIT" 79 | }; 80 | 81 | string map_we_name [ wb_op_t ] = '{ 82 | WB_READ : "READ", 83 | WB_WRITE : "WRITE" 84 | }; 85 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_checker.sv: -------------------------------------------------------------------------------- 1 | import ncsu_pkg::*; 2 | import wb_pkg::*; 3 | import i2c_pkg::*; 4 | import i2cmb_env_pkg::*; 5 | 6 | interface i2cmb_checker #( 7 | parameter NUM_I2C_BUSSES = 1 8 | )( 9 | // System sigals 10 | input wire clk_i, 11 | input wire rst_i, 12 | input wire irq_i, 13 | // wb master sigals 14 | input wire cyc_o, 15 | input wire stb_o, 16 | input wire ack_i, 17 | input wire [WB_ADDR_WIDTH-1:0] adr_o, 18 | input wire we_o, 19 | // Shared signals 20 | input wire [WB_DATA_WIDTH-1:0] dat_o, 21 | input wire [WB_DATA_WIDTH-1:0] dat_i, 22 | // I2C sigals 23 | input wire [NUM_I2C_BUSSES-1:0] scl_i, 24 | input wire [NUM_I2C_BUSSES-1:0] sda_i 25 | ); 26 | 27 | CMDR_REG cmdr_reg; 28 | CSR_REG csr_reg; 29 | FSMR_REG fsmr_reg = FSMR_REG'(8'd0); 30 | logic DUT_executing_cmd; 31 | logic rd_handshake; 32 | logic wr_handshake; 33 | 34 | assign rd_handshake = cyc_o & stb_o & (we_o==WB_READ) & ack_i; 35 | assign wr_handshake = cyc_o & stb_o & (we_o==WB_WRITE) & ack_i; 36 | assign DUT_finish_cmd = cmdr_reg.don|cmdr_reg.nak|cmdr_reg.al|cmdr_reg.err; 37 | 38 | always @ (*)begin 39 | if(adr_o==CSR && wr_handshake) {csr_reg.e, csr_reg.ie, csr_reg.bb, csr_reg.bc, csr_reg.bus_id} = {dat_o[7:6],6'd0}; 40 | else csr_reg = csr_reg; 41 | end 42 | 43 | property irq_not_set_when_irq_bit_reset; 44 | @(posedge clk_i) !csr_reg.ie |-> !irq_i; 45 | endproperty 46 | 47 | assert property(irq_not_set_when_irq_bit_reset) else $fatal("Interrupt generated when IE bit is reset"); 48 | 49 | always @ (*) begin 50 | if(adr_o==CMDR && rd_handshake) {cmdr_reg.don, cmdr_reg.nak, cmdr_reg.al, cmdr_reg.err, cmdr_reg.r, cmdr_reg.cmd} = dat_o; 51 | else cmdr_reg = cmdr_reg; 52 | end 53 | 54 | property cmdr_reserved_bit_never_assert; 55 | @(posedge clk_i) !cmdr_reg.r; 56 | endproperty 57 | 58 | assert property(cmdr_reserved_bit_never_assert) else $fatal("CMDR register reserved bit should never been asserted. %p",cmdr_reg); 59 | 60 | property dut_never_execute_undefined_cmd; 61 | @(posedge clk_i) !( (!DUT_finish_cmd) && (cmdr_reg.cmd==CMD_NO_USED) ); 62 | endproperty 63 | 64 | assert property(dut_never_execute_undefined_cmd) else $fatal("DUT should never request undefined command! (cmd == 7). %p",cmdr_reg); 65 | 66 | // !TBD 67 | // assertion: fsm should never reach undefined state! 68 | // BYTE_FSM_STATE < 8, BIT_FSM_STATE < 15 69 | 70 | always @ (*)begin 71 | if(adr_o==FSMR && rd_handshake) {fsmr_reg.byte_fsm, fsmr_reg.bit_fsm} = dat_o; 72 | else fsmr_reg = fsmr_reg; 73 | end 74 | 75 | property byte_fsm_never_reach_undefined_state; 76 | @(posedge clk_i) (fsmr_reg.byte_fsm < 4'd8); 77 | endproperty 78 | 79 | assert property(byte_fsm_never_reach_undefined_state) else $fatal("Byte level FSM should never reach undefined command! (cmd >=8 ). %p",fsmr_reg); 80 | 81 | property bit_fsm_never_reach_undefined_state; 82 | @(posedge clk_i) (fsmr_reg.bit_fsm < 4'd15); 83 | endproperty 84 | 85 | assert property(bit_fsm_never_reach_undefined_state) else $fatal("Byte level FSM should never reach undefined command! (cmd >= 15 ). %p",fsmr_reg); 86 | 87 | endinterface // checker 88 | -------------------------------------------------------------------------------- /verification_ip/interface_packages/wb_pkg/src/wb_if.sv: -------------------------------------------------------------------------------- 1 | interface wb_if #( 2 | int ADDR_WIDTH = 32, 3 | int DATA_WIDTH = 16 4 | ) 5 | ( 6 | // System sigals 7 | input wire clk_i, 8 | input wire rst_i, 9 | input wire irq_i, 10 | // Master signals 11 | output reg cyc_o, 12 | output reg stb_o, 13 | input wire ack_i, 14 | output reg [ADDR_WIDTH-1:0] adr_o, 15 | output reg we_o, 16 | // Slave signals 17 | input wire cyc_i, 18 | input wire stb_i, 19 | output reg ack_o, 20 | input wire [ADDR_WIDTH-1:0] adr_i, 21 | input wire we_i, 22 | // Shared signals 23 | output reg [DATA_WIDTH-1:0] dat_o, 24 | input wire [DATA_WIDTH-1:0] dat_i 25 | ); 26 | 27 | import wb_pkg::*; 28 | 29 | initial reset_bus(); 30 | 31 | // **************************************************************************** 32 | task wait_for_reset(); 33 | if (rst_i !== 0) @(negedge rst_i); 34 | endtask 35 | 36 | // **************************************************************************** 37 | task wait_for_num_clocks(int num_clocks); 38 | repeat (num_clocks) @(posedge clk_i); 39 | endtask 40 | 41 | // **************************************************************************** 42 | task wait_for_interrupt(); 43 | @(posedge irq_i); 44 | endtask 45 | 46 | // **************************************************************************** 47 | task reset_bus(); 48 | cyc_o <= 1'b0; 49 | stb_o <= 1'b0; 50 | we_o <= 1'b0; 51 | adr_o <= 'b0; 52 | dat_o <= 'b0; 53 | endtask 54 | 55 | // **************************************************************************** 56 | task master_write( 57 | input bit [ADDR_WIDTH-1:0] addr, 58 | input bit [DATA_WIDTH-1:0] data 59 | ); 60 | 61 | @(posedge clk_i); 62 | adr_o <= addr; 63 | dat_o <= data; 64 | cyc_o <= 1'b1; 65 | stb_o <= 1'b1; 66 | we_o <= 1'b1; 67 | while (!ack_i) @(posedge clk_i); 68 | cyc_o <= 1'b0; 69 | stb_o <= 1'b0; 70 | adr_o <= 'bx; 71 | dat_o <= 'bx; 72 | we_o <= 1'b0; 73 | @(posedge clk_i); 74 | 75 | endtask 76 | 77 | // **************************************************************************** 78 | task master_read( 79 | input bit [ADDR_WIDTH-1:0] addr, 80 | output bit [DATA_WIDTH-1:0] data 81 | ); 82 | 83 | @(posedge clk_i); 84 | adr_o <= addr; 85 | dat_o <= 'bx; 86 | cyc_o <= 1'b1; 87 | stb_o <= 1'b1; 88 | we_o <= 1'b0; 89 | @(posedge clk_i); 90 | while (!ack_i) @(posedge clk_i); 91 | cyc_o <= 1'b0; 92 | stb_o <= 1'b0; 93 | adr_o <= 'bx; 94 | dat_o <= 'bx; 95 | we_o <= 1'b0; 96 | data = dat_i; 97 | 98 | endtask 99 | 100 | // **************************************************************************** 101 | task master_monitor( 102 | output bit [ADDR_WIDTH-1:0] addr, 103 | output bit [DATA_WIDTH-1:0] data, 104 | output wb_op_t we 105 | ); 106 | 107 | while (!cyc_o) @(posedge clk_i); 108 | while (!ack_i) @(posedge clk_i); 109 | addr = adr_o; 110 | we = wb_op_t'(we_o); 111 | if (we_o) begin 112 | data = dat_o; 113 | end else begin 114 | data = dat_i; 115 | end 116 | while (cyc_o) @(posedge clk_i); 117 | endtask 118 | 119 | endinterface 120 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_generator_random_test.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_generator_random_test extends i2cmb_generator; 2 | `ncsu_register_object(i2cmb_generator_random_test) 3 | 4 | integer max_test_round = 10; 5 | int rand_size []; 6 | i2c_transaction_rand i2c_trans_rand; 7 | wb_transaction_rand wb_trans_rand; 8 | 9 | function new(string name="", ncsu_component_base parent=null); 10 | super.new(name, parent); 11 | 12 | $cast(wb_trans_rand, ncsu_object_factory::create("wb_transaction_rand")); 13 | void'(wb_trans_rand.set_op(WB_WRITE)); void'(wb_trans_rand.set_addr(DPR)); // Write Command 14 | $cast(i2c_trans_rand, ncsu_object_factory::create("i2c_transaction_rand")); 15 | void'(i2c_trans_rand.set_op(I2C_READ)); 16 | 17 | endfunction 18 | 19 | virtual task run(); 20 | automatic int k,j,kk,jj; 21 | 22 | $display("--------------------------------------------------------"); 23 | $display(" TEST PLAN: I2CMB RANDOM TESTS START "); 24 | $display("--------------------------------------------------------"); 25 | 26 | rand_size = new [max_test_round]; 27 | for(k=0;kCMD_SET_BUS), (CMD_SET_BUS=>CMD_START), (CMD_SET_BUS=>CMD_STOP), (CMD_SET_BUS=>CMD_WAIT), 51 | (CMD_START=>CMD_START), (CMD_START=>CMD_WRITE), (CMD_START=>CMD_STOP), 52 | (CMD_STOP=>CMD_START), (CMD_STOP=>CMD_SET_BUS), (CMD_STOP=>CMD_WAIT), 53 | (CMD_WRITE=>CMD_WRITE), (CMD_WRITE=>CMD_STOP), (CMD_WRITE=>CMD_START), (CMD_WRITE=>CMD_READ_W_NAK), (CMD_WRITE=>CMD_READ_W_AK), 54 | (CMD_READ_W_AK=>CMD_READ_W_AK), (CMD_READ_W_AK=>CMD_READ_W_NAK), (CMD_READ_W_AK=>CMD_START), (CMD_READ_W_AK=>CMD_STOP), 55 | (CMD_READ_W_NAK=>CMD_START), (CMD_READ_W_NAK=>CMD_STOP), 56 | (CMD_WAIT=>CMD_WAIT), (CMD_WAIT=>CMD_SET_BUS), (CMD_WAIT=>CMD_START), (CMD_WAIT=>CMD_STOP); 57 | } 58 | endgroup 59 | 60 | 61 | function void set_configuration(i2cmb_env_configuration cfg); 62 | cfg0 = cfg; 63 | endfunction 64 | 65 | function new(string name= "", ncsu_component_base parent = null); 66 | super.new(name, parent); 67 | env_coverage = new; 68 | CSR_coverage = new; 69 | DPR_coverage = new; 70 | CMDR_coverage = new; 71 | endfunction 72 | 73 | virtual function void nb_put(T trans); 74 | // wb_irq_transaction should not count to coverage. 75 | if(trans.get_type_handle()==wb_transaction::get_type())begin 76 | $cast( wb_op , trans.get_op()); 77 | $cast( wb_addr, trans.get_addr()); 78 | wb_data = trans.get_data_0(); 79 | 80 | {cmdr_reg.don, cmdr_reg.nak, cmdr_reg.al, cmdr_reg.err, cmdr_reg.r, cmdr_reg.cmd} = wb_data; 81 | {csr_reg.e, csr_reg.ie, csr_reg.bb, csr_reg.bc, csr_reg.bus_id} = wb_data; 82 | if(wb_op == WB_READ && wb_addr==CMDR) assert(cmdr_reg.r == 1'b0) begin end else $fatal("CMDR reserved bit should never be asserted."); 83 | 84 | if(wb_addr==CSR) ->>sample_CSR; 85 | if(wb_addr==DPR) ->>sample_DPR; 86 | if(wb_addr==CMDR) ->>sample_CMDR; 87 | //$display("ENV COVERAGE/ cmdr_reg: %p trans.wb_data: %b", cmdr_reg,wb_data)); 88 | ->>sample_wb; 89 | end 90 | endfunction 91 | 92 | 93 | endclass 94 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ASIC-Verification 2 | ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM. 3 | 4 | # Abstraction 5 | The purpose of this project is functional verificaiton of a Whishbone-to-I2C-Controller IP with SystemVerilog. 6 | First, I created a test plan with four type of verification methods: testing, functional coverage, code coverage, and assertions. Second, I designed an I2C slave Bus Functional Model (BFM) to support all test cases in the test plan. Third, I developed class-based layered testbench architecture including generator, agent, driver, monitor, predictor, scoreboard, coverage. Last, I wrote script and Makefile to generate multiple coverage database and merge them with test plan. 7 | 8 |
**Note**: This project focus on functional verification not unit verification. Thus, the verification environment treat design under test (DUT) as a black box. The verification environment connects with DUT through wishbone interface and i2c interfaceand we can not directly access unit blocks inside DUT. 9 | 10 | # Table of Contents 11 | - [1. **DUT Specification**](#1-dut-specification) 12 | - [2. **Verification Environment**](#2-verification-environment) 13 | - [3. **Verification methods**](#3-verification-methods) 14 | 15 | # 0. **Directory structure** 16 | 17 | ``` 18 | + docs/ 19 | | \--- testplan.xml 20 | + project_benches/ 21 | | |--- proj_1/ 22 | | |--- proj_2/ 23 | | |--- proj_3/ 24 | | \--- proj_4/ 25 | + verification_ip/ 26 | | |--- ncsu_pkg/ 27 | | +--- interface_packages/ 28 | | | |--- i2c_pkg/ 29 | | | \--- wb_pkg/ 30 | | +--- environment_packages/ 31 | | | \--- i2cmb_env_pkg/ 32 | ``` 33 | 34 | Each proj_n directories contains three folders: rtl, sim, testbench. 35 | - rtl folder contains DUT's VHDL files. 36 | - sim folder contains Makefile, scripts, output ucdb files. 37 | - testbench folder contains top.sv 38 | 39 | # 1. DUT Specification 40 | 41 | ![hls](./pic/dut_arch.png) 42 | Figure 1. DUT Specification from IP user's view point 43 | 44 | DUT owns four registers: 1. Control/Status Register (CSR), 2. Data/Parameter Register (DPR), 3. Command Register (CMDR), 4. FSM States Register (FSMR). 45 | These are the only four registers that verification environment can access and manipulate(R/W) directly. 46 | 47 | scl, sda signals are the only two signal that verification environment can access and response. 48 | 49 | For detail explanation of iicmb controller's feature and control command, please refer to **docs/iicmb_spec.pdf** 50 | 51 | # 2. Verification Environment 52 | ![hls](./pic/ver_arch.png) 53 | 54 | # 3. Verification methods 55 | 56 | - functional coverage 57 | 1. wisbone covergroup: 58 | - auto defined bins: 4 types of wb_address, 2 types of wishbone operation(r/w) 59 | - cross bins: wb_addrXop 60 | 2. CSR covergroup: 61 | - user-defined state bins: 5 types of csr feature bits 62 | 3. DPR covergroup: 63 | - user-defined state bins: 3 groups of dpr register value 64 | 4. CMDR covergroup: 65 | - user-defined state bins: 4 types of cmdr feature bits, 6 types of commands 66 | - transition bins: 25 types of command transition 67 | 68 | 5. i2c covergroup 69 | - auto defined bins: 2 types of i2c operations 70 | - user-defined state bins: 4 groups of i2c address, 4 groups of i2c data value, 3 groups of i2c transfer byte numbers(transSize) 71 | - cross bins: i2c_addrXop, i2c_addrXtransSize, i2c_opXtransSize 72 | 73 | - SystemVerilog assertion 74 | 1. irq signal should never be asserted if interrupt is disabled. 75 | 2. cmdr reserved bit should never be asserted. 76 | 3. dut should never execute undefined command. 77 | 4. byte finite state machine state should never be undefined state. 78 | 5. bit finite state machine state should never be undefined state. 79 | 80 | - code coverage 81 | 1. make sure each statement and condition in finite state machine has executed. 82 | 83 | - direct test case 84 | 1. register reset test: ensure system can reset 85 | 2. register default value test: ensure registers' default value is correct after reset. 86 | 3. register aliasing test: ensure R/W to one register doesn't affect other registers. 87 | 4. slave bus busy and capture test: ensure bus state bits works correctly before and after freed. 88 | 5. slave bus ID set up test: ensure invalid bus ID failed, valid bus ID success. 89 | 6. illegal command transition test: ensure FSM state transfer correctly if command transite illegally. 90 | 7. arbitration lost test: ensure DUT can detect slave arbitration lost. 91 | 8. no acknowledge test: ensure DUT can detect slave doesn't acknowledge. 92 | -------------------------------------------------------------------------------- /project_benches/lab_1/rtl/filter.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Digital filter with hysteresis. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity filter is 46 | generic 47 | ( 48 | g_cycles : positive := 10 -- Number of levels to receive before toggling output 49 | ); 50 | port 51 | ( 52 | ------------------------------------- 53 | clk : in std_logic; -- Clock 54 | s_rst : in std_logic; -- Synchronous reset 55 | ------------------------------------- 56 | ------------------------------------- 57 | sig_in : in std_logic; -- Input signal 58 | sig_out : out std_logic -- Output (filtered) signal 59 | ------------------------------------- 60 | ); 61 | end entity filter; 62 | --============================================================================== 63 | 64 | --============================================================================== 65 | architecture rtl of filter is 66 | 67 | signal sig_out_y : std_logic := '1'; 68 | signal cnt : integer range 0 to g_cycles := g_cycles; 69 | 70 | begin 71 | 72 | ------------------------------------------------------------------------------ 73 | sig_out_y_proc: 74 | process(clk) 75 | begin 76 | if rising_edge(clk) then 77 | if (s_rst = '1') then 78 | sig_out_y <= '1'; 79 | cnt <= g_cycles; 80 | else 81 | if (sig_in = '1') then 82 | if (cnt /= g_cycles) then 83 | cnt <= cnt + 1; 84 | end if; 85 | else 86 | if (cnt /= 0) then 87 | cnt <= cnt - 1; 88 | end if; 89 | end if; 90 | 91 | if (sig_out_y = '1') then 92 | if (sig_in = '0')and(cnt = 1) then 93 | sig_out_y <= '0'; 94 | end if; 95 | else 96 | if (sig_in = '1')and(cnt = (g_cycles - 1)) then 97 | sig_out_y <= '1'; 98 | end if; 99 | end if; 100 | end if; 101 | end if; 102 | end process sig_out_y_proc; 103 | ------------------------------------------------------------------------------ 104 | 105 | sig_out <= sig_out_y; 106 | 107 | end rtl; 108 | --============================================================================== 109 | 110 | -------------------------------------------------------------------------------- /project_benches/proj_1/rtl/filter.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Digital filter with hysteresis. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity filter is 46 | generic 47 | ( 48 | g_cycles : positive := 10 -- Number of levels to receive before toggling output 49 | ); 50 | port 51 | ( 52 | ------------------------------------- 53 | clk : in std_logic; -- Clock 54 | s_rst : in std_logic; -- Synchronous reset 55 | ------------------------------------- 56 | ------------------------------------- 57 | sig_in : in std_logic; -- Input signal 58 | sig_out : out std_logic -- Output (filtered) signal 59 | ------------------------------------- 60 | ); 61 | end entity filter; 62 | --============================================================================== 63 | 64 | --============================================================================== 65 | architecture rtl of filter is 66 | 67 | signal sig_out_y : std_logic := '1'; 68 | signal cnt : integer range 0 to g_cycles := g_cycles; 69 | 70 | begin 71 | 72 | ------------------------------------------------------------------------------ 73 | sig_out_y_proc: 74 | process(clk) 75 | begin 76 | if rising_edge(clk) then 77 | if (s_rst = '1') then 78 | sig_out_y <= '1'; 79 | cnt <= g_cycles; 80 | else 81 | if (sig_in = '1') then 82 | if (cnt /= g_cycles) then 83 | cnt <= cnt + 1; 84 | end if; 85 | else 86 | if (cnt /= 0) then 87 | cnt <= cnt - 1; 88 | end if; 89 | end if; 90 | 91 | if (sig_out_y = '1') then 92 | if (sig_in = '0')and(cnt = 1) then 93 | sig_out_y <= '0'; 94 | end if; 95 | else 96 | if (sig_in = '1')and(cnt = (g_cycles - 1)) then 97 | sig_out_y <= '1'; 98 | end if; 99 | end if; 100 | end if; 101 | end if; 102 | end process sig_out_y_proc; 103 | ------------------------------------------------------------------------------ 104 | 105 | sig_out <= sig_out_y; 106 | 107 | end rtl; 108 | --============================================================================== 109 | 110 | -------------------------------------------------------------------------------- /project_benches/proj_2/rtl/filter.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Digital filter with hysteresis. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity filter is 46 | generic 47 | ( 48 | g_cycles : positive := 10 -- Number of levels to receive before toggling output 49 | ); 50 | port 51 | ( 52 | ------------------------------------- 53 | clk : in std_logic; -- Clock 54 | s_rst : in std_logic; -- Synchronous reset 55 | ------------------------------------- 56 | ------------------------------------- 57 | sig_in : in std_logic; -- Input signal 58 | sig_out : out std_logic -- Output (filtered) signal 59 | ------------------------------------- 60 | ); 61 | end entity filter; 62 | --============================================================================== 63 | 64 | --============================================================================== 65 | architecture rtl of filter is 66 | 67 | signal sig_out_y : std_logic := '1'; 68 | signal cnt : integer range 0 to g_cycles := g_cycles; 69 | 70 | begin 71 | 72 | ------------------------------------------------------------------------------ 73 | sig_out_y_proc: 74 | process(clk) 75 | begin 76 | if rising_edge(clk) then 77 | if (s_rst = '1') then 78 | sig_out_y <= '1'; 79 | cnt <= g_cycles; 80 | else 81 | if (sig_in = '1') then 82 | if (cnt /= g_cycles) then 83 | cnt <= cnt + 1; 84 | end if; 85 | else 86 | if (cnt /= 0) then 87 | cnt <= cnt - 1; 88 | end if; 89 | end if; 90 | 91 | if (sig_out_y = '1') then 92 | if (sig_in = '0')and(cnt = 1) then 93 | sig_out_y <= '0'; 94 | end if; 95 | else 96 | if (sig_in = '1')and(cnt = (g_cycles - 1)) then 97 | sig_out_y <= '1'; 98 | end if; 99 | end if; 100 | end if; 101 | end if; 102 | end process sig_out_y_proc; 103 | ------------------------------------------------------------------------------ 104 | 105 | sig_out <= sig_out_y; 106 | 107 | end rtl; 108 | --============================================================================== 109 | 110 | -------------------------------------------------------------------------------- /project_benches/proj_3/rtl/filter.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Digital filter with hysteresis. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity filter is 46 | generic 47 | ( 48 | g_cycles : positive := 10 -- Number of levels to receive before toggling output 49 | ); 50 | port 51 | ( 52 | ------------------------------------- 53 | clk : in std_logic; -- Clock 54 | s_rst : in std_logic; -- Synchronous reset 55 | ------------------------------------- 56 | ------------------------------------- 57 | sig_in : in std_logic; -- Input signal 58 | sig_out : out std_logic -- Output (filtered) signal 59 | ------------------------------------- 60 | ); 61 | end entity filter; 62 | --============================================================================== 63 | 64 | --============================================================================== 65 | architecture rtl of filter is 66 | 67 | signal sig_out_y : std_logic := '1'; 68 | signal cnt : integer range 0 to g_cycles := g_cycles; 69 | 70 | begin 71 | 72 | ------------------------------------------------------------------------------ 73 | sig_out_y_proc: 74 | process(clk) 75 | begin 76 | if rising_edge(clk) then 77 | if (s_rst = '1') then 78 | sig_out_y <= '1'; 79 | cnt <= g_cycles; 80 | else 81 | if (sig_in = '1') then 82 | if (cnt /= g_cycles) then 83 | cnt <= cnt + 1; 84 | end if; 85 | else 86 | if (cnt /= 0) then 87 | cnt <= cnt - 1; 88 | end if; 89 | end if; 90 | 91 | if (sig_out_y = '1') then 92 | if (sig_in = '0')and(cnt = 1) then 93 | sig_out_y <= '0'; 94 | end if; 95 | else 96 | if (sig_in = '1')and(cnt = (g_cycles - 1)) then 97 | sig_out_y <= '1'; 98 | end if; 99 | end if; 100 | end if; 101 | end if; 102 | end process sig_out_y_proc; 103 | ------------------------------------------------------------------------------ 104 | 105 | sig_out <= sig_out_y; 106 | 107 | end rtl; 108 | --============================================================================== 109 | 110 | -------------------------------------------------------------------------------- /project_benches/proj_4/rtl/filter.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Digital filter with hysteresis. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity filter is 46 | generic 47 | ( 48 | g_cycles : positive := 10 -- Number of levels to receive before toggling output 49 | ); 50 | port 51 | ( 52 | ------------------------------------- 53 | clk : in std_logic; -- Clock 54 | s_rst : in std_logic; -- Synchronous reset 55 | ------------------------------------- 56 | ------------------------------------- 57 | sig_in : in std_logic; -- Input signal 58 | sig_out : out std_logic -- Output (filtered) signal 59 | ------------------------------------- 60 | ); 61 | end entity filter; 62 | --============================================================================== 63 | 64 | --============================================================================== 65 | architecture rtl of filter is 66 | 67 | signal sig_out_y : std_logic := '1'; 68 | signal cnt : integer range 0 to g_cycles := g_cycles; 69 | 70 | begin 71 | 72 | ------------------------------------------------------------------------------ 73 | sig_out_y_proc: 74 | process(clk) 75 | begin 76 | if rising_edge(clk) then 77 | if (s_rst = '1') then 78 | sig_out_y <= '1'; 79 | cnt <= g_cycles; 80 | else 81 | if (sig_in = '1') then 82 | if (cnt /= g_cycles) then 83 | cnt <= cnt + 1; 84 | end if; 85 | else 86 | if (cnt /= 0) then 87 | cnt <= cnt - 1; 88 | end if; 89 | end if; 90 | 91 | if (sig_out_y = '1') then 92 | if (sig_in = '0')and(cnt = 1) then 93 | sig_out_y <= '0'; 94 | end if; 95 | else 96 | if (sig_in = '1')and(cnt = (g_cycles - 1)) then 97 | sig_out_y <= '1'; 98 | end if; 99 | end if; 100 | end if; 101 | end if; 102 | end process sig_out_y_proc; 103 | ------------------------------------------------------------------------------ 104 | 105 | sig_out <= sig_out_y; 106 | 107 | end rtl; 108 | --============================================================================== 109 | 110 | -------------------------------------------------------------------------------- /verification_ip/environment_packages/i2cmb_env_pkg/src/i2cmb_generator_control_functionality_test.svh: -------------------------------------------------------------------------------- 1 | class i2cmb_generator_control_functionality_test extends i2cmb_generator; 2 | `ncsu_register_object(i2cmb_generator_control_functionality_test) 3 | 4 | wb_transaction cmd_en_trans; 5 | wb_transaction trans_r[iicmb_reg_ofst_t]; 6 | wb_transaction trans_w[iicmb_reg_ofst_t]; 7 | 8 | i2c_transaction i2c_write_trans, i2c_read_trans; 9 | bit [I2C_DATA_WIDTH-1:0] i2c_data [$]; 10 | time time_start,time_end; 11 | bit [7:0] wait_time; 12 | 13 | function new(string name="", ncsu_component_base parent=null); 14 | super.new(name, parent); 15 | for(int i=3; i>=0; i--) begin 16 | automatic iicmb_reg_ofst_t addr_ofst = iicmb_reg_ofst_t'(i); 17 | //ncsu_info("i2cmb_generator_register_test::run()" ,$sformatf("construct transactions for testing %s register.", map_reg_ofst_name[addr_ofst]),NCSU_NONE); 18 | $cast(trans_r[addr_ofst], ncsu_object_factory::create("wb_transaction")); 19 | $cast(trans_w[addr_ofst], ncsu_object_factory::create("wb_transaction")); 20 | // fixed command 21 | void'(trans_r[addr_ofst].set_addr(addr_ofst)); void'(trans_r[addr_ofst].set_op(WB_READ)); 22 | // half-fixed command, need assign wb_data while using 23 | void'(trans_w[addr_ofst].set_addr(addr_ofst)); void'(trans_w[addr_ofst].set_op(WB_WRITE)); 24 | end 25 | 26 | $cast(cmd_en_trans, ncsu_object_factory::create("wb_transaction")); 27 | void'(cmd_en_trans.set_op(WB_WRITE)); void'(cmd_en_trans.set_addr(CSR)); void'(cmd_en_trans.set_data( CSR_E | CSR_IE)); // Enable Core 28 | $cast(cmd_start_trans, ncsu_object_factory::create("wb_transaction")); 29 | void'(cmd_start_trans.set_op(WB_WRITE)); void'(cmd_start_trans.set_addr(CMDR)); void'(cmd_start_trans.set_data({5'b0,CMD_START})); // Repeated START Command 30 | $cast(cmd_write_trans, ncsu_object_factory::create("wb_transaction")); 31 | void'(cmd_write_trans.set_op(WB_WRITE)); void'(cmd_write_trans.set_addr(CMDR)); void'(cmd_write_trans.set_data({5'b0,CMD_WRITE})); // Write Command 32 | $cast(cmd_stop_trans, ncsu_object_factory::create("wb_transaction")); 33 | void'(cmd_stop_trans.set_op(WB_WRITE)); void'(cmd_stop_trans.set_addr(CMDR)); void'(cmd_stop_trans.set_data(CMD_STOP)); // Stop Command 34 | 35 | 36 | $cast(i2c_write_trans, ncsu_object_factory::create("i2c_transaction")); 37 | $cast(i2c_read_trans, ncsu_object_factory::create("i2c_transaction")); 38 | 39 | i2c_data.push_back( 100 ); 40 | void'(i2c_write_trans.set_op(I2C_WRITE)); 41 | void'(i2c_read_trans.set_op(I2C_READ)); void'(i2c_read_trans.set_data(i2c_data)); 42 | endfunction 43 | 44 | virtual task run(); 45 | 46 | $display("--------------------------------------------------------"); 47 | $display(" TEST PLAN 3: I2CMB CONTROL FUNCTIONALITY TESTS START "); 48 | $display("--------------------------------------------------------"); 49 | 50 | fork begin i2c_agt0.bl_put( i2c_write_trans ); 51 | i2c_agt0.bl_put( i2c_read_trans ); 52 | end 53 | join_none 54 | 55 | wb_agt0.bl_put_ref(cmd_en_trans); 56 | wb_agt0.bl_put_ref(trans_r[CSR]); 57 | assert(!(to_csr_reg(trans_r[CSR].wb_data).bb)) $display("TEST CASE PASSED: BUS BUSY BIT RESET BEFORE ISSUE OF START"); 58 | else $fatal("TEST CASE FAILED: BUS BUSY BIT SET BEFORE ISSUE OF START"); 59 | 60 | assert(!to_csr_reg(trans_r[CSR].wb_data).bc) $display("TEST CASE PASSED: BUS CAPTURE BIT NOT SET BEFORE SET BUS COMMAND"); 61 | else $fatal("TEST CASE FAILED: BUS CAPTURE BIT SET BEFORE SET BUS COMMAND"); 62 | 63 | $display(""); 64 | 65 | void'(trans_w[DPR].set_data( 8'h00 )); 66 | wb_agt0.bl_put(trans_w[DPR]); 67 | 68 | void'(trans_w[CMDR].set_data( {5'b0,CMD_SET_BUS} )); 69 | wb_agt0.bl_put(trans_w[CMDR]); 70 | wb_agt0.bl_put_ref(trans_r[CMDR]); 71 | assert(to_cmdr_reg(trans_r[CMDR].wb_data).don ) $display("TEST CASE PASSED: VALID BUS ID"); 72 | else $fatal("TEST CASE FAILED: VALID BUS ID GENERATED ERROR"); 73 | 74 | wb_agt0.bl_put(cmd_start_trans); 75 | 76 | void'(trans_w[DPR].set_data( {I2C_SLAVE_ADDRESS<<1} | bit'(I2C_WRITE) )); 77 | wb_agt0.bl_put(trans_w[DPR]); 78 | 79 | wb_agt0.bl_put(cmd_write_trans); 80 | 81 | void'(trans_w[DPR].set_data( 8'd200 )); 82 | wb_agt0.bl_put(trans_w[DPR]); 83 | wb_agt0.bl_put_No_Wait(cmd_write_trans); 84 | wb_agt0.bl_put_ref(trans_r[CSR]); 85 | assert(to_csr_reg(trans_r[CSR].wb_data).bc) $display("TEST CASE PASSED: BUS CAPTURE BIT SET DURING EXECUTING COMMAND"); 86 | else $fatal("TEST CASE FAILED: BUS CAPTURE BIT RESET DURING EXECUTING COMMAND"); 87 | 88 | assert(to_csr_reg(trans_r[CSR].wb_data).bb) $display("TEST CASE PASSED: BUS BUSY BIT SET DURING EXECUTING COMMAND"); 89 | else $fatal("TEST CASE FAILED: BUS BUSY BIT RESET DURING EXECUTING COMMAND"); 90 | //$display("cmdr before irq triggered: %p", trans_r[CSR].to_csr_reg()); 91 | 92 | wb_agt0.wait_for_interrupt(); 93 | wb_agt0.bl_put_ref(trans_r[CMDR]); 94 | 95 | wb_agt0.bl_put(cmd_stop_trans); 96 | 97 | wb_agt0.bl_put_ref(trans_r[CSR]); 98 | assert(!to_csr_reg(trans_r[CSR].wb_data).bc) $display("TEST CASE PASSED: BUS CAPTURE BIT RESET AFTER STOP"); 99 | else $fatal("TEST CASE FAILED: BUS CAPTURE BIT SET AFTER STOP"); 100 | 101 | $display("--------------------------------------------------------"); 102 | $display(" TEST PLAN 3: I2CMB CONTROL FUNCTIONALITY TESTS PASSED "); 103 | $display("--------------------------------------------------------"); 104 | 105 | endtask 106 | 107 | endclass 108 | -------------------------------------------------------------------------------- /project_benches/proj_4/rtl/iicmb_int_pkg.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Package for internal declarations. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | package iicmb_int_pkg is 46 | 47 | ------------------------------------------------------------------------------ 48 | -- Bit-level master mode commands: 49 | ------------------------------------------------------------------------------ 50 | type mbc_type is 51 | ( 52 | mbc_start, -- Start --> Done | Arbitration Lost 53 | mbc_stop, -- Stop --> Done 54 | mbc_write_0, -- Write Bit 0 --> Done | Error 55 | mbc_write_1, -- Write Bit 1 --> Done | Arbitration Lost | Error 56 | mbc_read -- Read Bit --> Bit 0 Received | Bit 1 Received | Error 57 | ); 58 | ------------------------------------------------------------------------------ 59 | 60 | ------------------------------------------------------------------------------ 61 | -- Bit-level master mode responses: 62 | ------------------------------------------------------------------------------ 63 | type mbr_type is 64 | ( 65 | mbr_done, -- Done 66 | mbr_arb_lost, -- Arbitration Lost 67 | mbr_bit_0, -- Bit 0 Received 68 | mbr_bit_1, -- Bit 1 Received 69 | mbr_error -- Error 70 | ); 71 | ------------------------------------------------------------------------------ 72 | 73 | ------------------------------------------------------------------------------ 74 | -- Bit-level slave mode commands: 75 | ------------------------------------------------------------------------------ 76 | type sbc_type is 77 | ( 78 | sbc_idle, -- Idle 79 | sbc_hold, -- Clock stretching 80 | sbc_write_0, -- Write Bit 0 81 | sbc_write_1, -- Write Bit 1 82 | sbc_read -- Read Bit 83 | ); 84 | ------------------------------------------------------------------------------ 85 | 86 | ------------------------------------------------------------------------------ 87 | -- Bit-level slave mode responses: 88 | ------------------------------------------------------------------------------ 89 | type sbr_type is 90 | ( 91 | sbr_start, -- Start 92 | sbr_stop, -- Stop 93 | sbr_bit_0, -- Bit 0 received 94 | sbr_bit_1 -- Bit 1 received 95 | ); 96 | ------------------------------------------------------------------------------ 97 | 98 | end package iicmb_int_pkg; 99 | --============================================================================== 100 | 101 | --============================================================================== 102 | package body iicmb_int_pkg is 103 | 104 | 105 | end package body iicmb_int_pkg; 106 | --============================================================================== 107 | -------------------------------------------------------------------------------- /project_benches/lab_1/rtl/iicmb_int_pkg.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Package for internal declarations. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | package iicmb_int_pkg is 46 | 47 | ------------------------------------------------------------------------------ 48 | -- Bit-level master mode commands: 49 | ------------------------------------------------------------------------------ 50 | type mbc_type is 51 | ( 52 | mbc_start, -- Start --> Done | Arbitration Lost 53 | mbc_stop, -- Stop --> Done 54 | mbc_write_0, -- Write Bit 0 --> Done | Error 55 | mbc_write_1, -- Write Bit 1 --> Done | Arbitration Lost | Error 56 | mbc_read -- Read Bit --> Bit 0 Received | Bit 1 Received | Error 57 | ); 58 | ------------------------------------------------------------------------------ 59 | 60 | ------------------------------------------------------------------------------ 61 | -- Bit-level master mode responses: 62 | ------------------------------------------------------------------------------ 63 | type mbr_type is 64 | ( 65 | mbr_done, -- Done 66 | mbr_arb_lost, -- Arbitration Lost 67 | mbr_bit_0, -- Bit 0 Received 68 | mbr_bit_1, -- Bit 1 Received 69 | mbr_error -- Error 70 | ); 71 | ------------------------------------------------------------------------------ 72 | 73 | ------------------------------------------------------------------------------ 74 | -- Bit-level slave mode commands: 75 | ------------------------------------------------------------------------------ 76 | type sbc_type is 77 | ( 78 | sbc_idle, -- Idle 79 | sbc_hold, -- Clock stretching 80 | sbc_write_0, -- Write Bit 0 81 | sbc_write_1, -- Write Bit 1 82 | sbc_read -- Read Bit 83 | ); 84 | ------------------------------------------------------------------------------ 85 | 86 | ------------------------------------------------------------------------------ 87 | -- Bit-level slave mode responses: 88 | ------------------------------------------------------------------------------ 89 | type sbr_type is 90 | ( 91 | sbr_start, -- Start 92 | sbr_stop, -- Stop 93 | sbr_bit_0, -- Bit 0 received 94 | sbr_bit_1 -- Bit 1 received 95 | ); 96 | ------------------------------------------------------------------------------ 97 | 98 | end package iicmb_int_pkg; 99 | --============================================================================== 100 | 101 | --============================================================================== 102 | package body iicmb_int_pkg is 103 | 104 | 105 | end package body iicmb_int_pkg; 106 | --============================================================================== 107 | 108 | -------------------------------------------------------------------------------- /project_benches/lab_1/rtl/avalon_mm.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Avalon-MM adapter. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity avalon_mm is 46 | port 47 | ( 48 | ------------------------------------ 49 | clk : in std_logic; -- Clock input 50 | s_rst : in std_logic; -- Synchronous reset (active high) 51 | ------------------------------------ 52 | ------------------------------------ 53 | -- Avalon-MM slave interface: 54 | waitrequest : out std_logic; -- Wait request 55 | readdata : out std_logic_vector(31 downto 0); -- Data from slave to master 56 | readdatavalid : out std_logic; -- Data validity indication 57 | writedata : in std_logic_vector(31 downto 0); -- Data from master to slave 58 | write : in std_logic; -- Asserted to indicate write transfer 59 | read : in std_logic; -- Asserted to indicate read transfer 60 | byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) 61 | ------------------------------------ 62 | ------------------------------------ 63 | -- Regblock interface: 64 | wr : out std_logic_vector( 3 downto 0); -- Write (active high) 65 | rd : out std_logic_vector( 3 downto 0); -- Read (active high) 66 | idata : out std_logic_vector(31 downto 0); -- Data from System Bus 67 | odata : in std_logic_vector(31 downto 0) -- Data for System Bus 68 | ------------------------------------ 69 | ); 70 | end entity avalon_mm; 71 | --============================================================================== 72 | 73 | --============================================================================== 74 | architecture rtl of avalon_mm is 75 | 76 | begin 77 | 78 | waitrequest <= '0'; 79 | wr <= (3 downto 0 => write) and byteenable; 80 | rd <= (3 downto 0 => read ) and byteenable; 81 | idata <= writedata; 82 | 83 | ------------------------------------------------------------------------------ 84 | readdata_proc: 85 | process(clk) 86 | begin 87 | if rising_edge(clk) then 88 | if (s_rst = '1') then 89 | readdata <= (others => '0'); 90 | readdatavalid <= '0'; 91 | else 92 | readdata <= odata; 93 | readdatavalid <= read; 94 | end if; 95 | end if; 96 | end process readdata_proc; 97 | ------------------------------------------------------------------------------ 98 | 99 | end architecture rtl; 100 | --============================================================================== 101 | 102 | -------------------------------------------------------------------------------- /project_benches/proj_1/rtl/iicmb_int_pkg.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Package for internal declarations. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | package iicmb_int_pkg is 46 | 47 | ------------------------------------------------------------------------------ 48 | -- Bit-level master mode commands: 49 | ------------------------------------------------------------------------------ 50 | type mbc_type is 51 | ( 52 | mbc_start, -- Start --> Done | Arbitration Lost 53 | mbc_stop, -- Stop --> Done 54 | mbc_write_0, -- Write Bit 0 --> Done | Error 55 | mbc_write_1, -- Write Bit 1 --> Done | Arbitration Lost | Error 56 | mbc_read -- Read Bit --> Bit 0 Received | Bit 1 Received | Error 57 | ); 58 | ------------------------------------------------------------------------------ 59 | 60 | ------------------------------------------------------------------------------ 61 | -- Bit-level master mode responses: 62 | ------------------------------------------------------------------------------ 63 | type mbr_type is 64 | ( 65 | mbr_done, -- Done 66 | mbr_arb_lost, -- Arbitration Lost 67 | mbr_bit_0, -- Bit 0 Received 68 | mbr_bit_1, -- Bit 1 Received 69 | mbr_error -- Error 70 | ); 71 | ------------------------------------------------------------------------------ 72 | 73 | ------------------------------------------------------------------------------ 74 | -- Bit-level slave mode commands: 75 | ------------------------------------------------------------------------------ 76 | type sbc_type is 77 | ( 78 | sbc_idle, -- Idle 79 | sbc_hold, -- Clock stretching 80 | sbc_write_0, -- Write Bit 0 81 | sbc_write_1, -- Write Bit 1 82 | sbc_read -- Read Bit 83 | ); 84 | ------------------------------------------------------------------------------ 85 | 86 | ------------------------------------------------------------------------------ 87 | -- Bit-level slave mode responses: 88 | ------------------------------------------------------------------------------ 89 | type sbr_type is 90 | ( 91 | sbr_start, -- Start 92 | sbr_stop, -- Stop 93 | sbr_bit_0, -- Bit 0 received 94 | sbr_bit_1 -- Bit 1 received 95 | ); 96 | ------------------------------------------------------------------------------ 97 | 98 | end package iicmb_int_pkg; 99 | --============================================================================== 100 | 101 | --============================================================================== 102 | package body iicmb_int_pkg is 103 | 104 | 105 | end package body iicmb_int_pkg; 106 | --============================================================================== 107 | 108 | -------------------------------------------------------------------------------- /project_benches/proj_2/rtl/iicmb_int_pkg.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Package for internal declarations. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | package iicmb_int_pkg is 46 | 47 | ------------------------------------------------------------------------------ 48 | -- Bit-level master mode commands: 49 | ------------------------------------------------------------------------------ 50 | type mbc_type is 51 | ( 52 | mbc_start, -- Start --> Done | Arbitration Lost 53 | mbc_stop, -- Stop --> Done 54 | mbc_write_0, -- Write Bit 0 --> Done | Error 55 | mbc_write_1, -- Write Bit 1 --> Done | Arbitration Lost | Error 56 | mbc_read -- Read Bit --> Bit 0 Received | Bit 1 Received | Error 57 | ); 58 | ------------------------------------------------------------------------------ 59 | 60 | ------------------------------------------------------------------------------ 61 | -- Bit-level master mode responses: 62 | ------------------------------------------------------------------------------ 63 | type mbr_type is 64 | ( 65 | mbr_done, -- Done 66 | mbr_arb_lost, -- Arbitration Lost 67 | mbr_bit_0, -- Bit 0 Received 68 | mbr_bit_1, -- Bit 1 Received 69 | mbr_error -- Error 70 | ); 71 | ------------------------------------------------------------------------------ 72 | 73 | ------------------------------------------------------------------------------ 74 | -- Bit-level slave mode commands: 75 | ------------------------------------------------------------------------------ 76 | type sbc_type is 77 | ( 78 | sbc_idle, -- Idle 79 | sbc_hold, -- Clock stretching 80 | sbc_write_0, -- Write Bit 0 81 | sbc_write_1, -- Write Bit 1 82 | sbc_read -- Read Bit 83 | ); 84 | ------------------------------------------------------------------------------ 85 | 86 | ------------------------------------------------------------------------------ 87 | -- Bit-level slave mode responses: 88 | ------------------------------------------------------------------------------ 89 | type sbr_type is 90 | ( 91 | sbr_start, -- Start 92 | sbr_stop, -- Stop 93 | sbr_bit_0, -- Bit 0 received 94 | sbr_bit_1 -- Bit 1 received 95 | ); 96 | ------------------------------------------------------------------------------ 97 | 98 | end package iicmb_int_pkg; 99 | --============================================================================== 100 | 101 | --============================================================================== 102 | package body iicmb_int_pkg is 103 | 104 | 105 | end package body iicmb_int_pkg; 106 | --============================================================================== 107 | 108 | -------------------------------------------------------------------------------- /project_benches/proj_3/rtl/iicmb_int_pkg.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Package for internal declarations. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | package iicmb_int_pkg is 46 | 47 | ------------------------------------------------------------------------------ 48 | -- Bit-level master mode commands: 49 | ------------------------------------------------------------------------------ 50 | type mbc_type is 51 | ( 52 | mbc_start, -- Start --> Done | Arbitration Lost 53 | mbc_stop, -- Stop --> Done 54 | mbc_write_0, -- Write Bit 0 --> Done | Error 55 | mbc_write_1, -- Write Bit 1 --> Done | Arbitration Lost | Error 56 | mbc_read -- Read Bit --> Bit 0 Received | Bit 1 Received | Error 57 | ); 58 | ------------------------------------------------------------------------------ 59 | 60 | ------------------------------------------------------------------------------ 61 | -- Bit-level master mode responses: 62 | ------------------------------------------------------------------------------ 63 | type mbr_type is 64 | ( 65 | mbr_done, -- Done 66 | mbr_arb_lost, -- Arbitration Lost 67 | mbr_bit_0, -- Bit 0 Received 68 | mbr_bit_1, -- Bit 1 Received 69 | mbr_error -- Error 70 | ); 71 | ------------------------------------------------------------------------------ 72 | 73 | ------------------------------------------------------------------------------ 74 | -- Bit-level slave mode commands: 75 | ------------------------------------------------------------------------------ 76 | type sbc_type is 77 | ( 78 | sbc_idle, -- Idle 79 | sbc_hold, -- Clock stretching 80 | sbc_write_0, -- Write Bit 0 81 | sbc_write_1, -- Write Bit 1 82 | sbc_read -- Read Bit 83 | ); 84 | ------------------------------------------------------------------------------ 85 | 86 | ------------------------------------------------------------------------------ 87 | -- Bit-level slave mode responses: 88 | ------------------------------------------------------------------------------ 89 | type sbr_type is 90 | ( 91 | sbr_start, -- Start 92 | sbr_stop, -- Stop 93 | sbr_bit_0, -- Bit 0 received 94 | sbr_bit_1 -- Bit 1 received 95 | ); 96 | ------------------------------------------------------------------------------ 97 | 98 | end package iicmb_int_pkg; 99 | --============================================================================== 100 | 101 | --============================================================================== 102 | package body iicmb_int_pkg is 103 | 104 | 105 | end package body iicmb_int_pkg; 106 | --============================================================================== 107 | 108 | -------------------------------------------------------------------------------- /project_benches/proj_1/rtl/avalon_mm.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Avalon-MM adapter. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity avalon_mm is 46 | port 47 | ( 48 | ------------------------------------ 49 | clk : in std_logic; -- Clock input 50 | s_rst : in std_logic; -- Synchronous reset (active high) 51 | ------------------------------------ 52 | ------------------------------------ 53 | -- Avalon-MM slave interface: 54 | waitrequest : out std_logic; -- Wait request 55 | readdata : out std_logic_vector(31 downto 0); -- Data from slave to master 56 | readdatavalid : out std_logic; -- Data validity indication 57 | writedata : in std_logic_vector(31 downto 0); -- Data from master to slave 58 | write : in std_logic; -- Asserted to indicate write transfer 59 | read : in std_logic; -- Asserted to indicate read transfer 60 | byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) 61 | ------------------------------------ 62 | ------------------------------------ 63 | -- Regblock interface: 64 | wr : out std_logic_vector( 3 downto 0); -- Write (active high) 65 | rd : out std_logic_vector( 3 downto 0); -- Read (active high) 66 | idata : out std_logic_vector(31 downto 0); -- Data from System Bus 67 | odata : in std_logic_vector(31 downto 0) -- Data for System Bus 68 | ------------------------------------ 69 | ); 70 | end entity avalon_mm; 71 | --============================================================================== 72 | 73 | --============================================================================== 74 | architecture rtl of avalon_mm is 75 | 76 | begin 77 | 78 | waitrequest <= '0'; 79 | wr <= (3 downto 0 => write) and byteenable; 80 | rd <= (3 downto 0 => read ) and byteenable; 81 | idata <= writedata; 82 | 83 | ------------------------------------------------------------------------------ 84 | readdata_proc: 85 | process(clk) 86 | begin 87 | if rising_edge(clk) then 88 | if (s_rst = '1') then 89 | readdata <= (others => '0'); 90 | readdatavalid <= '0'; 91 | else 92 | readdata <= odata; 93 | readdatavalid <= read; 94 | end if; 95 | end if; 96 | end process readdata_proc; 97 | ------------------------------------------------------------------------------ 98 | 99 | end architecture rtl; 100 | --============================================================================== 101 | 102 | -------------------------------------------------------------------------------- /project_benches/proj_2/rtl/avalon_mm.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Avalon-MM adapter. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity avalon_mm is 46 | port 47 | ( 48 | ------------------------------------ 49 | clk : in std_logic; -- Clock input 50 | s_rst : in std_logic; -- Synchronous reset (active high) 51 | ------------------------------------ 52 | ------------------------------------ 53 | -- Avalon-MM slave interface: 54 | waitrequest : out std_logic; -- Wait request 55 | readdata : out std_logic_vector(31 downto 0); -- Data from slave to master 56 | readdatavalid : out std_logic; -- Data validity indication 57 | writedata : in std_logic_vector(31 downto 0); -- Data from master to slave 58 | write : in std_logic; -- Asserted to indicate write transfer 59 | read : in std_logic; -- Asserted to indicate read transfer 60 | byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) 61 | ------------------------------------ 62 | ------------------------------------ 63 | -- Regblock interface: 64 | wr : out std_logic_vector( 3 downto 0); -- Write (active high) 65 | rd : out std_logic_vector( 3 downto 0); -- Read (active high) 66 | idata : out std_logic_vector(31 downto 0); -- Data from System Bus 67 | odata : in std_logic_vector(31 downto 0) -- Data for System Bus 68 | ------------------------------------ 69 | ); 70 | end entity avalon_mm; 71 | --============================================================================== 72 | 73 | --============================================================================== 74 | architecture rtl of avalon_mm is 75 | 76 | begin 77 | 78 | waitrequest <= '0'; 79 | wr <= (3 downto 0 => write) and byteenable; 80 | rd <= (3 downto 0 => read ) and byteenable; 81 | idata <= writedata; 82 | 83 | ------------------------------------------------------------------------------ 84 | readdata_proc: 85 | process(clk) 86 | begin 87 | if rising_edge(clk) then 88 | if (s_rst = '1') then 89 | readdata <= (others => '0'); 90 | readdatavalid <= '0'; 91 | else 92 | readdata <= odata; 93 | readdatavalid <= read; 94 | end if; 95 | end if; 96 | end process readdata_proc; 97 | ------------------------------------------------------------------------------ 98 | 99 | end architecture rtl; 100 | --============================================================================== 101 | 102 | -------------------------------------------------------------------------------- /project_benches/proj_3/rtl/avalon_mm.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Avalon-MM adapter. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity avalon_mm is 46 | port 47 | ( 48 | ------------------------------------ 49 | clk : in std_logic; -- Clock input 50 | s_rst : in std_logic; -- Synchronous reset (active high) 51 | ------------------------------------ 52 | ------------------------------------ 53 | -- Avalon-MM slave interface: 54 | waitrequest : out std_logic; -- Wait request 55 | readdata : out std_logic_vector(31 downto 0); -- Data from slave to master 56 | readdatavalid : out std_logic; -- Data validity indication 57 | writedata : in std_logic_vector(31 downto 0); -- Data from master to slave 58 | write : in std_logic; -- Asserted to indicate write transfer 59 | read : in std_logic; -- Asserted to indicate read transfer 60 | byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) 61 | ------------------------------------ 62 | ------------------------------------ 63 | -- Regblock interface: 64 | wr : out std_logic_vector( 3 downto 0); -- Write (active high) 65 | rd : out std_logic_vector( 3 downto 0); -- Read (active high) 66 | idata : out std_logic_vector(31 downto 0); -- Data from System Bus 67 | odata : in std_logic_vector(31 downto 0) -- Data for System Bus 68 | ------------------------------------ 69 | ); 70 | end entity avalon_mm; 71 | --============================================================================== 72 | 73 | --============================================================================== 74 | architecture rtl of avalon_mm is 75 | 76 | begin 77 | 78 | waitrequest <= '0'; 79 | wr <= (3 downto 0 => write) and byteenable; 80 | rd <= (3 downto 0 => read ) and byteenable; 81 | idata <= writedata; 82 | 83 | ------------------------------------------------------------------------------ 84 | readdata_proc: 85 | process(clk) 86 | begin 87 | if rising_edge(clk) then 88 | if (s_rst = '1') then 89 | readdata <= (others => '0'); 90 | readdatavalid <= '0'; 91 | else 92 | readdata <= odata; 93 | readdatavalid <= read; 94 | end if; 95 | end if; 96 | end process readdata_proc; 97 | ------------------------------------------------------------------------------ 98 | 99 | end architecture rtl; 100 | --============================================================================== 101 | 102 | -------------------------------------------------------------------------------- /project_benches/proj_4/rtl/avalon_mm.vhd: -------------------------------------------------------------------------------- 1 | 2 | --============================================================================== 3 | -- | 4 | -- Project: IIC Multiple Bus Controller (IICMB) | 5 | -- | 6 | -- Module: Avalon-MM adapter. | 7 | -- Version: | 8 | -- 1.0, April 29, 2016 | 9 | -- | 10 | -- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | 11 | -- | 12 | --============================================================================== 13 | --============================================================================== 14 | -- Copyright (c) 2016, Sergey Shuvalkin | 15 | -- All rights reserved. | 16 | -- | 17 | -- Redistribution and use in source and binary forms, with or without | 18 | -- modification, are permitted provided that the following conditions are met: | 19 | -- | 20 | -- 1. Redistributions of source code must retain the above copyright notice, | 21 | -- this list of conditions and the following disclaimer. | 22 | -- 2. Redistributions in binary form must reproduce the above copyright | 23 | -- notice, this list of conditions and the following disclaimer in the | 24 | -- documentation and/or other materials provided with the distribution. | 25 | -- | 26 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | 27 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | 28 | -- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | 29 | -- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | 30 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | 31 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | 32 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | 33 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | 34 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 35 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | 36 | -- POSSIBILITY OF SUCH DAMAGE. | 37 | --============================================================================== 38 | 39 | 40 | library ieee; 41 | use ieee.std_logic_1164.all; 42 | 43 | 44 | --============================================================================== 45 | entity avalon_mm is 46 | port 47 | ( 48 | ------------------------------------ 49 | clk : in std_logic; -- Clock input 50 | s_rst : in std_logic; -- Synchronous reset (active high) 51 | ------------------------------------ 52 | ------------------------------------ 53 | -- Avalon-MM slave interface: 54 | waitrequest : out std_logic; -- Wait request 55 | readdata : out std_logic_vector(31 downto 0); -- Data from slave to master 56 | readdatavalid : out std_logic; -- Data validity indication 57 | writedata : in std_logic_vector(31 downto 0); -- Data from master to slave 58 | write : in std_logic; -- Asserted to indicate write transfer 59 | read : in std_logic; -- Asserted to indicate read transfer 60 | byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) 61 | ------------------------------------ 62 | ------------------------------------ 63 | -- Regblock interface: 64 | wr : out std_logic_vector( 3 downto 0); -- Write (active high) 65 | rd : out std_logic_vector( 3 downto 0); -- Read (active high) 66 | idata : out std_logic_vector(31 downto 0); -- Data from System Bus 67 | odata : in std_logic_vector(31 downto 0) -- Data for System Bus 68 | ------------------------------------ 69 | ); 70 | end entity avalon_mm; 71 | --============================================================================== 72 | 73 | --============================================================================== 74 | architecture rtl of avalon_mm is 75 | 76 | begin 77 | 78 | waitrequest <= '0'; 79 | wr <= (3 downto 0 => write) and byteenable; 80 | rd <= (3 downto 0 => read ) and byteenable; 81 | idata <= writedata; 82 | 83 | ------------------------------------------------------------------------------ 84 | readdata_proc: 85 | process(clk) 86 | begin 87 | if rising_edge(clk) then 88 | if (s_rst = '1') then 89 | readdata <= (others => '0'); 90 | readdatavalid <= '0'; 91 | else 92 | readdata <= odata; 93 | readdatavalid <= read; 94 | end if; 95 | end if; 96 | end process readdata_proc; 97 | ------------------------------------------------------------------------------ 98 | 99 | end architecture rtl; 100 | --============================================================================== 101 | 102 | -------------------------------------------------------------------------------- /project_benches/proj_2/testbench/top.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | module top(); 3 | 4 | import ncsu_pkg::*; 5 | import wb_pkg::*; 6 | import i2c_pkg::*; 7 | import i2cmb_env_pkg::*; 8 | 9 | // **************************************************************************** 10 | // define your parameter below 11 | 12 | parameter int CLK_PERIOD = 10; 13 | parameter int RESET_DELAY = 113; 14 | parameter int MAX_SIMULATION_TIME = 100000000; 15 | 16 | parameter int NUM_I2C_BUSSES = 16; 17 | 18 | // **************************************************************************** 19 | // Define variable 20 | 21 | bit clk; 22 | bit rst = 1'b1; 23 | wire cyc; 24 | wire stb; 25 | wire we; 26 | tri ack; 27 | wire [WB_ADDR_WIDTH-1:0] adr; 28 | wire [WB_DATA_WIDTH-1:0] dat_wr_o; 29 | wire [WB_DATA_WIDTH-1:0] dat_rd_i; 30 | wire irq; 31 | tri [NUM_I2C_BUSSES] scl; 32 | tri [NUM_I2C_BUSSES] sda; 33 | 34 | integer i,j,k; 35 | 36 | iicmb_reg_ofst_t adr_enum; 37 | iicmb_cmdr_t dat_o_enum; 38 | 39 | assign adr_enum = iicmb_reg_ofst_t'(adr); 40 | assign dat_o_enum = (adr_enum == CMDR)? iicmb_cmdr_t'(dat_wr_o) : XX ; 41 | 42 | // **************************************************************************** 43 | // Instantiate the I2C slave Bus Functional Model 44 | i2c_if #( 45 | .I2C_ADDR_WIDTH(I2C_ADDR_WIDTH), 46 | .I2C_DATA_WIDTH(I2C_DATA_WIDTH), 47 | .SLAVE_ADDRESS(I2C_SLAVE_ADDRESS) 48 | ) 49 | i2c_bus ( 50 | // Slave signals 51 | .scl_s(scl[ WB_BUS_ID ]), 52 | .sda_s(sda[ WB_BUS_ID ]) 53 | ); 54 | // **************************************************************************** 55 | // Instantiate the Wishbone master Bus Functional Model 56 | wb_if #( 57 | .ADDR_WIDTH(WB_ADDR_WIDTH), 58 | .DATA_WIDTH(WB_DATA_WIDTH) 59 | ) 60 | wb_bus ( 61 | // System sigals 62 | .clk_i(clk), 63 | .rst_i(rst), 64 | .irq_i(irq), 65 | // Master signals 66 | .cyc_o(cyc), 67 | .stb_o(stb), 68 | .ack_i(ack), 69 | .adr_o(adr), 70 | .we_o(we), 71 | // Slave signals 72 | .cyc_i(), 73 | .stb_i(), 74 | .ack_o(), 75 | .adr_i(), 76 | .we_i(), 77 | // Shred signals 78 | .dat_o(dat_wr_o), 79 | .dat_i(dat_rd_i) 80 | ); 81 | 82 | 83 | // **************************************************************************** 84 | // Instantiate the DUT - I2C Multi-Bus Controller 85 | \work.iicmb_m_wb(str) #(.g_bus_num(NUM_I2C_BUSSES)) DUT 86 | ( 87 | // ------------------------------------ 88 | // -- Wishbone signals: 89 | .clk_i(clk), // in std_logic; -- Clock 90 | .rst_i(rst), // in std_logic; -- Synchronous reset (active high) 91 | // ------------- 92 | .cyc_i(cyc), // in std_logic; -- Valid bus cycle indication 93 | .stb_i(stb), // in std_logic; -- Slave selection 94 | .ack_o(ack), // out std_logic; -- Acknowledge output 95 | .adr_i(adr), // in std_logic_vector(1 downto 0); -- Low bits of Wishbone address 96 | .we_i(we), // in std_logic; -- Write enable 97 | .dat_i(dat_wr_o), // in std_logic_vector(7 downto 0); -- Data input 98 | .dat_o(dat_rd_i), // out std_logic_vector(7 downto 0); -- Data output 99 | // ------------------------------------ 100 | // ------------------------------------ 101 | // -- Interrupt request: 102 | .irq(irq), // out std_logic; -- Interrupt request 103 | // ------------------------------------ 104 | // ------------------------------------ 105 | // -- I2C master interfaces: 106 | .scl_i(scl), // in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs 107 | .sda_i(sda), // in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs 108 | .scl_o(scl), // out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs 109 | .sda_o(sda) // out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs 110 | // ------------------------------------ 111 | ); 112 | 113 | // **************************************************************************** 114 | // Dump waveform if you use synopsys verdi 115 | `ifdef FSDB 116 | initial begin : dumpfsdb 117 | // $dumpfile("count.vcd"); // waveforms in this file.. 118 | // $dumpvars; // saves all waveforms 119 | $fsdbDumpfile("proj1.fsdb"); // waveforms in this file.. 120 | $fsdbDumpvars(0,"+mda"); // saves all waveforms 121 | $display("[info] enable output fsdb file"); 122 | end 123 | `endif 124 | 125 | initial $timeformat(-9, 2, " ns", 6); 126 | 127 | // **************************************************************************** 128 | // Clock generator 129 | initial begin : clk_gen 130 | clk = 0; 131 | forever #(CLK_PERIOD/2) clk = ~clk; 132 | end 133 | 134 | // **************************************************************************** 135 | // Reset generator 136 | initial begin : rst_gen 137 | #(RESET_DELAY) rst = 0; 138 | end 139 | 140 | // **************************************************************************** 141 | // 1. Place an instance of i2cmb_test within top.sv 142 | i2cmb_test tst; 143 | 144 | initial begin : test_flow 145 | // 2. Place virtual interface handles into ncsu_config_db 146 | // 3. Construct the test class 147 | // 4. Execute the run task of the test after reset is released 148 | // 5. Execute $finish after test complete 149 | 150 | ncsu_config_db#(virtual wb_if#(.ADDR_WIDTH(WB_ADDR_WIDTH), .DATA_WIDTH(WB_DATA_WIDTH)))::set("wb_interface", wb_bus); 151 | ncsu_config_db#(virtual i2c_if#(.I2C_ADDR_WIDTH(I2C_ADDR_WIDTH), .I2C_DATA_WIDTH(I2C_DATA_WIDTH)))::set("i2c_interface", i2c_bus); 152 | 153 | tst = new("tst", null); 154 | wait( rst==0 ); 155 | tst.run(); 156 | #1000ns $finish; 157 | end 158 | 159 | // **************************************************************************** 160 | initial begin : time_limit 161 | #(MAX_SIMULATION_TIME) $fatal("[%t] run out of time!!!",$time); 162 | $finish; 163 | end 164 | 165 | endmodule 166 | -------------------------------------------------------------------------------- /project_benches/lab_1/testbench/top.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 10ps 2 | 3 | module top(); 4 | 5 | parameter int WB_ADDR_WIDTH = 2; 6 | parameter int WB_DATA_WIDTH = 8; 7 | parameter int NUM_I2C_BUSSES = 16; 8 | // ***************************************** 9 | // Name Offset Access Description 10 | // CSR 0x00 R/W Control/Status Register 11 | // DPR 0x01 R/W Data/Parameter Register 12 | // CMDR 0x02 R/W Command Register 13 | // FSMR 0x03 RO FSM States Register 14 | // ***************************************** 15 | typedef enum logic [1:0] { 16 | CSR = 2'd0, 17 | DPR = 2'd1, 18 | CMDR = 2'd2, 19 | FSMR = 2'd3 20 | } REG_OFST; 21 | 22 | bit clk; 23 | bit rst = 1'b1; 24 | wire cyc; 25 | wire stb; 26 | wire we; 27 | tri1 ack; 28 | wire [WB_ADDR_WIDTH-1:0] adr; 29 | wire [WB_DATA_WIDTH-1:0] dat_wr_o; 30 | wire [WB_DATA_WIDTH-1:0] dat_rd_i; 31 | wire irq; 32 | tri [NUM_I2C_BUSSES] scl; 33 | tri [NUM_I2C_BUSSES] sda; 34 | 35 | // define temp variable 36 | logic [WB_ADDR_WIDTH-1:0] addr_p; 37 | logic [WB_DATA_WIDTH-1:0] data_p; 38 | logic we_p; 39 | 40 | // **************************************************************************** 41 | // Clock generator 42 | initial begin : clk_gen 43 | clk = 0; 44 | forever #5 clk = ~clk; 45 | end 46 | 47 | // **************************************************************************** 48 | // Reset generator 49 | initial begin : rst_gen 50 | #113 rst = 0; 51 | end 52 | 53 | // **************************************************************************** 54 | // Monitor Wishbone bus and display transfers in the transcript 55 | initial begin : wb_monitoring 56 | $timeformat(-9, 2, " ns", 6); 57 | wb_bus.master_monitor(addr_p,data_p,we_p); 58 | $display("============== transaction at %t ns ==============",$time); 59 | $display("addr: %h",addr_p); 60 | $display("data: %h",data_p); 61 | $display("we: %b", we_p); 62 | $display("======================================================"); 63 | end 64 | 65 | // **************************************************************************** 66 | // Define the flow of the simulation 67 | task wait_done(); 68 | wait(irq); 69 | // read CMDR to clear irq bit 70 | wb_bus.master_read(CMDR,data_p); 71 | endtask 72 | 73 | initial begin : test_flow 74 | @(negedge rst); 75 | repeat(3) @(posedge clk); 76 | 77 | // reset core 78 | //wb_bus.master_write(CSR_ADDR_OFST,8'b0xxxxxxx); 79 | 80 | // enable core and interrupt 81 | wb_bus.master_write(CSR,8'b11xxxxxx); 82 | 83 | // store parameter, I2C Bus ID = 5 84 | wb_bus.master_write(DPR,8'h05); 85 | // set Bus command 86 | wb_bus.master_write(CMDR,8'bxxxxx110); 87 | wait_done(); 88 | 89 | // Start command 90 | wb_bus.master_write(CMDR,8'bxxxxx100); 91 | wait_done(); 92 | 93 | // store parameter 94 | wb_bus.master_write(DPR,8'h44); 95 | // Write command 96 | wb_bus.master_write(CMDR,8'bxxxxx001); 97 | wait_done(); 98 | 99 | // store parameter 100 | wb_bus.master_write(DPR,8'h78); 101 | // Write command 102 | wb_bus.master_write(CMDR,8'bxxxxx001); 103 | wait_done(); 104 | 105 | // Stop command 106 | wb_bus.master_write(CMDR,8'bxxxxx001); 107 | wait_done(); 108 | 109 | #100 $finish; 110 | end 111 | 112 | initial begin : end_flow 113 | #200000 $display("run out of time"); 114 | $finish; 115 | end 116 | // **************************************************************************** 117 | // Instantiate the Wishbone master Bus Functional Model 118 | wb_if #( 119 | .ADDR_WIDTH(WB_ADDR_WIDTH), 120 | .DATA_WIDTH(WB_DATA_WIDTH) 121 | ) 122 | wb_bus ( 123 | // System sigals 124 | .clk_i(clk), 125 | .rst_i(rst), 126 | // Master signals 127 | .cyc_o(cyc), 128 | .stb_o(stb), 129 | .ack_i(ack), 130 | .adr_o(adr), 131 | .we_o(we), 132 | // Slave signals 133 | .cyc_i(), 134 | .stb_i(), 135 | .ack_o(), 136 | .adr_i(), 137 | .we_i(), 138 | // Shred signals 139 | .dat_o(dat_wr_o), 140 | .dat_i(dat_rd_i) 141 | ); 142 | 143 | REG_OFST adr_ii; 144 | assign adr_ii = REG_OFST'(adr); 145 | // **************************************************************************** 146 | // Instantiate the DUT - I2C Multi-Bus Controller 147 | \work.iicmb_m_wb(str) #(.g_bus_num(NUM_I2C_BUSSES)) DUT 148 | ( 149 | // ------------------------------------ 150 | // -- Wishbone signals: 151 | .clk_i(clk), // in std_logic; -- Clock 152 | .rst_i(rst), // in std_logic; -- Synchronous reset (active high) 153 | // ------------- 154 | .cyc_i(cyc), // in std_logic; -- Valid bus cycle indication 155 | .stb_i(stb), // in std_logic; -- Slave selection 156 | .ack_o(ack), // out std_logic; -- Acknowledge output 157 | .adr_i(adr), // in std_logic_vector(1 downto 0); -- Low bits of Wishbone address 158 | .we_i(we), // in std_logic; -- Write enable 159 | .dat_i(dat_wr_o), // in std_logic_vector(7 downto 0); -- Data input 160 | .dat_o(dat_rd_i), // out std_logic_vector(7 downto 0); -- Data output 161 | // ------------------------------------ 162 | // ------------------------------------ 163 | // -- Interrupt request: 164 | .irq(irq), // out std_logic; -- Interrupt request 165 | // ------------------------------------ 166 | // ------------------------------------ 167 | // -- I2C interfaces: 168 | .scl_i(scl), // in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs 169 | .sda_i(sda), // in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs 170 | .scl_o(scl), // out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs 171 | .sda_o(sda) // out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs 172 | // ------------------------------------ 173 | ); 174 | 175 | initial begin : dumpfsdb 176 | // $dumpfile("count.vcd"); // waveforms in this file.. 177 | // $dumpvars; // saves all waveforms 178 | $fsdbDumpfile("counter.fsdb"); // waveforms in this file.. 179 | $fsdbDumpvars(0,"+mda"); // saves all waveforms 180 | end 181 | 182 | endmodule 183 | --------------------------------------------------------------------------------