├── CPUtop.v ├── LICENSE ├── Layout.PNG ├── Processor.PNG ├── README.md ├── SIMDadd.v ├── SIMDmultiply.v ├── SIMDshifter.v ├── post_layout_Sim.PNG ├── processor_tb.v └── report.pdf /CPUtop.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module CPUtop( 4 | input clk, 5 | input rst, 6 | input [17:0] instruction_in, 7 | input [15:0] data_in, 8 | output [15:0] data_out, 9 | output [9:0] instruction_address, 10 | output [9:0] data_address, 11 | output data_R, 12 | output data_W, 13 | output done 14 | ); 15 | 16 | wire [5:0] opcode = instruction_in[17:12]; 17 | 18 | parameter [2:0] STATE_IDLE = 0; 19 | parameter [2:0] STATE_IF = 1; 20 | parameter [2:0] STATE_ID = 2; 21 | parameter [2:0] STATE_EX = 3; 22 | parameter [2:0] STATE_MEM = 4; 23 | parameter [2:0] STATE_WB = 5; 24 | parameter [2:0] STATE_HALT = 6; 25 | 26 | reg [2:0] current_state; 27 | reg [9:0] PC,next_PC; 28 | // reg [17:0] current_instruction; 29 | // reg [5:0] current_opcode; 30 | reg [9:0] current_data_address; 31 | reg rdata_en; 32 | reg wdata_en; 33 | reg [15:0] data_out_reg; 34 | 35 | assign data_out = data_out_reg; 36 | assign data_R = rdata_en; 37 | assign data_W = wdata_en; 38 | assign data_address = current_data_address; 39 | 40 | //data register 41 | reg [15:0] H[0:3]; 42 | reg [15:0] Oset[0:2]; 43 | reg [15:0] Qset[0:2]; 44 | reg [9:0] LC; 45 | reg [9:0] im_reg; 46 | 47 | //control register 48 | reg CMD_addition; 49 | reg CMD_multiplication; 50 | reg CMD_substruction; 51 | reg CMD_mul_accumulation; 52 | reg CMD_logic_shift_right; 53 | reg CMD_logic_shift_left; 54 | reg CMD_and; 55 | reg CMD_or; 56 | reg CMD_not; 57 | reg CMD_load; 58 | reg CMD_store; 59 | reg CMD_set; 60 | reg CMD_loopjump; 61 | reg CMD_setloop; 62 | // reg CMD_halt; 63 | 64 | //cmd type 65 | reg Hreg1,Hreg2,Hreg3,Him,Oreg1,Oreg2,Oreg3,Oim,Qreg1,Qreg2,Qreg3,Qim; 66 | 67 | //result register 68 | reg [15:0] result_reg_add; 69 | reg [15:0] result_reg_sub; 70 | reg [15:0] result_reg_mul; 71 | reg [15:0] result_reg_mac; 72 | reg [15:0] result_reg_Lshift; 73 | reg [15:0] result_reg_Rshift; 74 | reg [15:0] result_reg_and; 75 | reg [15:0] result_reg_or; 76 | reg [15:0] result_reg_not; 77 | reg [15:0] result_reg_load; 78 | reg [15:0] result_reg_store; 79 | reg [15:0] result_reg_set; 80 | reg [1:0] R0,R1,R2,R3; 81 | 82 | wire [15:0] comp_input_A = Hreg1?(H[R0]):((Hreg2|Hreg3)?(H[R2]):(Oreg1?(Oset[R0]):((Oreg2|Oreg3)?(Oset[R2]):(Qreg1?(Qset[R0]):((Qset[R2])))))); 83 | wire [15:0] comp_input_B = Hreg1?(im_reg):((Hreg2|Hreg3)?(H[R3]):(Oreg1?({im_reg[7:0],im_reg[7:0]}):((Oreg2|Oreg3)?(Oset[R3]):(Qreg1?({im_reg[3:0],im_reg[3:0],im_reg[3:0],im_reg[3:0]}):((Qset[R3])))))); 84 | 85 | wire [15:0] Add_output_Cout; 86 | wire [15:0] Mul_output_Cout; 87 | wire [15:0] MAC_output_Cout; 88 | 89 | wire [15:0] MAC_input_A = Hreg3?(H[R1]):(Oreg3?(Oset[R1]):(Qset[R1])); 90 | wire [15:0] MAC_input_B = Mul_output_Cout; 91 | 92 | SIMDadd Add( 93 | .A(CMD_mul_accumulation?MAC_input_A:comp_input_A), 94 | .B(CMD_mul_accumulation?MAC_input_B:comp_input_B), 95 | .H(Hreg1|Hreg2|Hreg3), 96 | .O(Oreg1|Oreg2|Oreg3), 97 | .Q(Qreg1|Qreg2|Qreg3), 98 | .sub(CMD_substruction), 99 | .Cout(Add_output_Cout) 100 | ); 101 | 102 | wire [15:0] shiftinput = Hreg1?(H[R3]):(Oreg1?(Oset[R3]):(Qset[R3])); 103 | wire [15:0] shiftoutput; 104 | 105 | SIMDshifter shift( 106 | .shiftinput(shiftinput), 107 | .H(Hreg1), 108 | .O(Oreg1), 109 | .Q(Qreg1), 110 | .left(CMD_logic_shift_left), 111 | .shiftoutput(shiftoutput) 112 | ); 113 | 114 | SIMDmultiply Mul( 115 | .mulinputa(comp_input_A), 116 | .mulinputb(comp_input_B), 117 | .H(Hreg1|Hreg2|Hreg3), 118 | .O(Oreg1|Oreg2|Oreg3), 119 | .Q(Qreg1|Qreg2|Qreg3), 120 | .muloutput(Mul_output_Cout) 121 | ); 122 | 123 | 124 | //some signal 125 | 126 | assign instruction_address = PC; 127 | assign done = current_state == STATE_HALT; 128 | 129 | always @(posedge clk)//state machine 130 | begin 131 | if (rst) 132 | begin 133 | current_state <= STATE_IDLE; 134 | PC <= 0; 135 | end 136 | else 137 | begin 138 | if (opcode == 63) current_state <= STATE_HALT; 139 | else 140 | if (current_state == STATE_IDLE) 141 | begin 142 | current_state <= STATE_IF; 143 | end 144 | else if (current_state == STATE_IF) 145 | begin 146 | $display("======== another instruction ========"); 147 | $display("H00: %b",H[0]); 148 | $display("H01: %b",H[1]); 149 | $display("H10: %b",H[2]); 150 | $display("H11: %b",H[3]); 151 | $display("Oset00: %b",Oset[0]); 152 | $display("Oset01: %b",Oset[1]); 153 | $display("Oset10: %b",Oset[2]); 154 | $display("Qset00: %b",Qset[0]); 155 | $display("Qset01: %b",Qset[1]); 156 | $display("Qset10: %b",Qset[2]); 157 | $display(" -- execute -- "); 158 | current_state <= STATE_ID; 159 | end 160 | else if (current_state == STATE_ID) 161 | begin 162 | current_state <= STATE_EX; 163 | end 164 | else if (current_state == STATE_EX) 165 | begin 166 | current_state <= STATE_MEM; 167 | end 168 | else if (current_state == STATE_MEM) 169 | begin 170 | current_state <= STATE_WB; 171 | end 172 | else if (current_state == STATE_WB) 173 | begin 174 | current_state <= STATE_IF; 175 | PC <= next_PC; 176 | end 177 | end 178 | end 179 | 180 | always @(posedge clk)//STATE_IF 181 | begin 182 | if (rst) 183 | begin 184 | 185 | end 186 | else 187 | begin 188 | 189 | end 190 | end 191 | 192 | 193 | always @(posedge clk)//STATE_ID 194 | begin 195 | if (rst || current_state == STATE_IDLE || current_state == STATE_IF) 196 | begin 197 | CMD_addition <= 0; 198 | CMD_multiplication <= 0; 199 | CMD_substruction <= 0; 200 | CMD_mul_accumulation <= 0; 201 | CMD_logic_shift_right <= 0; 202 | CMD_logic_shift_left <= 0; 203 | CMD_and <= 0; 204 | CMD_or <= 0; 205 | CMD_not <= 0; 206 | CMD_load <= 0; 207 | CMD_store <= 0; 208 | CMD_set <= 0; 209 | CMD_loopjump <= 0; 210 | CMD_setloop <= 0; 211 | // CMD_halt <= 0; 212 | Hreg1<=0; 213 | Hreg2<=0; 214 | Hreg3<=0; 215 | Him<=0; 216 | Oreg1<=0; 217 | Oreg2<=0; 218 | Oreg3<=0; 219 | Oim<=0; 220 | Qreg1<=0; 221 | Qreg2<=0; 222 | Qreg3<=0; 223 | Qim<=0; 224 | im_reg <= 10'b0000000000; 225 | R0 <= 0; 226 | R1 <= 0; 227 | R2 <= 0; 228 | R3 <= 0; 229 | end 230 | else 231 | begin 232 | if (current_state == STATE_ID) 233 | begin 234 | // current_instruction <= instruction_in; 235 | // current_opcode <= opcode; 236 | 237 | //cmd 238 | CMD_addition <= (opcode<=5); 239 | CMD_substruction <= (opcode>=6)&&(opcode<=11); 240 | CMD_multiplication <= (opcode>=12)&&(opcode<=17); 241 | CMD_mul_accumulation <= (opcode>=18)&&(opcode<=20); 242 | CMD_logic_shift_left <= (opcode>=21)&&(opcode<=23); 243 | CMD_logic_shift_right <= (opcode>=24)&&(opcode<=26); 244 | CMD_and <= (opcode>=27)&&(opcode<=29); 245 | CMD_or <= (opcode>=30)&&(opcode<=32); 246 | CMD_not <= (opcode>=33)&&(opcode<=35); 247 | CMD_loopjump <= opcode==36; 248 | CMD_setloop <= opcode==37; 249 | CMD_load <= (opcode>=38)&&(opcode<=40); 250 | CMD_store <= (opcode>=41)&&(opcode<=43); 251 | CMD_set <= (opcode>=44)&&(opcode<=46); 252 | // CMD_halt <= (opcode==63); 253 | 254 | //datatype 255 | Hreg1<=(opcode==3)||(opcode==9)||(opcode==15)||(opcode==21)||(opcode==24)||(opcode==33)||(opcode==38)||(opcode==41)||(opcode==44); 256 | Hreg2<=(opcode==0)||(opcode==6)||(opcode==12)||(opcode==27)||(opcode==30); 257 | Hreg3<=(opcode==18); 258 | Him<=(opcode==3)||(opcode==9)||(opcode==15)||(opcode==38)||(opcode==41)||(opcode==44); 259 | 260 | Oreg1<=(opcode==4)||(opcode==10)||(opcode==16)||(opcode==22)||(opcode==25)||(opcode==34)||(opcode==39)||(opcode==42)||(opcode==45); 261 | Oreg2<=(opcode==1)||(opcode==7)||(opcode==13)||(opcode==28)||(opcode==31); 262 | Oreg3<=(opcode==19); 263 | Oim<=(opcode==4)||(opcode==10)||(opcode==16)||(opcode==39)||(opcode==42)||(opcode==45); 264 | 265 | Qreg1<=(opcode==5)||(opcode==11)||(opcode==17)||(opcode==23)||(opcode==26)||(opcode==35)||(opcode==40)||(opcode==43)||(opcode==46); 266 | Qreg2<=(opcode==2)||(opcode==8)||(opcode==14)||(opcode==29)||(opcode==32); 267 | Qreg3<=(opcode==20); 268 | Qim<=(opcode==5)||(opcode==11)||(opcode==17)||(opcode==40)||(opcode==43)||(opcode==46); 269 | 270 | im_reg <= instruction_in[9:0]; 271 | R0 <= instruction_in[11:10]; 272 | R1 <= instruction_in[5:4]; 273 | R2 <= instruction_in[3:2]; 274 | R3 <= instruction_in[1:0]; 275 | $display("PC: %0d : instruction = %b", PC,instruction_in); 276 | end 277 | end 278 | end 279 | 280 | always @(posedge clk)//STATE_EX 281 | begin 282 | if (rst || current_state == STATE_IDLE || current_state == STATE_IF) 283 | begin 284 | result_reg_add <= 0; 285 | result_reg_sub <= 0; 286 | result_reg_mul <= 0; 287 | result_reg_mac <= 0; 288 | result_reg_Lshift <= 0; 289 | result_reg_Rshift <= 0; 290 | result_reg_and <= 0; 291 | result_reg_or <= 0; 292 | result_reg_not <= 0; 293 | result_reg_set <= 0; 294 | current_data_address <= 0; 295 | rdata_en <= 0; 296 | wdata_en <= 0; 297 | if (rst) 298 | begin 299 | next_PC <= 0; 300 | end 301 | end 302 | 303 | else if (current_state == STATE_EX) 304 | begin 305 | 306 | if (CMD_addition) // do addition 307 | begin 308 | result_reg_add <= Add_output_Cout; 309 | if (Hreg2) 310 | begin 311 | $display("add16bit R%d=%b R%d=%b", R2,H[R2],R3,H[R3]); 312 | end 313 | else if (Oreg2) 314 | begin 315 | $display("add8bit R%d=%b R%d=%b", R2,Oset[R2],R3,Oset[R3]); 316 | end 317 | else if (Qreg2) 318 | begin 319 | $display("add4bit R%d=%b R%d=%b", R2,Qset[R2],R3,Qset[R3]); 320 | end 321 | else if (Him) 322 | begin 323 | $display("add16bit R%d=%b im=%b", R0,H[R0],im_reg); 324 | end 325 | else if (Oim) 326 | begin 327 | $display("add8bit R%d=%b im=%b", R0,Oset[R0],im_reg); 328 | end 329 | else if (Qim) 330 | begin 331 | $display("add4bit R%d=%b im=%b", R0,Qset[R0],im_reg); 332 | end 333 | end 334 | 335 | else if (CMD_substruction) // do substruction 336 | begin 337 | result_reg_sub <= Add_output_Cout; 338 | if (Hreg2) 339 | begin 340 | $display("sub16bit R%d=%b R%d=%b", R2,H[R2],R3,H[R3]); 341 | end 342 | else if (Oreg2) 343 | begin 344 | $display("sub8bit R%d=%b R%d=%b", R2,Oset[R2],R3,Oset[R3]); 345 | end 346 | else if (Qreg2) 347 | begin 348 | $display("sub4bit R%d=%b R%d=%b", R2,Qset[R2],R3,Qset[R3]); 349 | end 350 | else if (Him) 351 | begin 352 | $display("sub16bit R%d=%b im=%b", R0,H[R0],im_reg); 353 | end 354 | else if (Oim) 355 | begin 356 | $display("sub8bit R%d=%b im=%b", R0,Oset[R0],im_reg); 357 | end 358 | else if (Qim) 359 | begin 360 | $display("sub4bit R%d=%b im=%b", R0,Qset[R0],im_reg); 361 | end 362 | end 363 | 364 | else if (CMD_multiplication) // do multiplication 365 | begin 366 | result_reg_mul<=Mul_output_Cout; 367 | if (Hreg2) 368 | begin 369 | $display("mul16bit R%d=%b R%d=%b", R2,H[R2],R3,H[R3]); 370 | end 371 | else if (Oreg2) 372 | begin 373 | $display("mul8bit R%d=%b R%d=%b", R2,Oset[R2],R3,Oset[R3]); 374 | end 375 | else if (Qreg2) 376 | begin 377 | $display("mul4bit R%d=%b R%d=%b", R2,Qset[R2],R3,Qset[R3]); 378 | end 379 | else if (Him) 380 | begin 381 | $display("mul16bit R%d=%b im=%b", R0,H[R0],im_reg); 382 | end 383 | else if (Oim) 384 | begin 385 | $display("mul8bit R%d=%b im=%b", R0,Oset[R0],im_reg); 386 | end 387 | else if (Qim) 388 | begin 389 | $display("mul4bit R%d=%b im=%b", R0,Qset[R0],im_reg); 390 | end 391 | end 392 | 393 | else if (CMD_mul_accumulation) // do mac 394 | begin 395 | result_reg_mac <= Add_output_Cout; 396 | if (Hreg3) 397 | begin 398 | $display("MAC16bit R%d=%b R%d=%b R%d=%b", R1,H[R1],R2,H[R2],R3,H[R3]); 399 | end 400 | else if (Oreg3) 401 | begin 402 | $display("MAC8bit R%d=%b R%d=%b R%d=%b", R1,Oset[R1],R2,Oset[R2],R3,Oset[R3]); 403 | end 404 | else if (Qreg3) 405 | begin 406 | $display("MAC4bit R%d=%b R%d=%b R%d=%b", R1,Qset[R1],R2,Qset[R2],R3,Qset[R3]); 407 | end 408 | end 409 | 410 | else if (CMD_logic_shift_right) // do shift right 411 | begin 412 | result_reg_Rshift <= shiftoutput; 413 | if (Hreg1) 414 | begin 415 | $display("Rshift16bit R%d=%b", R3,H[R3]); 416 | end 417 | else if (Oreg1) 418 | begin 419 | $display("Rshift8bit R%d=%b", R3,Oset[R3]); 420 | end 421 | else if (Qreg1) 422 | begin 423 | $display("Rshift4bit R%d=%b", R3,Qset[R3]); 424 | end 425 | end 426 | 427 | else if (CMD_logic_shift_left) // do shift left 428 | begin 429 | result_reg_Lshift <= shiftoutput; 430 | if (Hreg1) 431 | begin 432 | $display("Lshift16bit R%d=%b", R3,H[R3]); 433 | end 434 | else if (Oreg1) 435 | begin 436 | $display("Lshift8bit R%d=%b", R3,Oset[R3]); 437 | end 438 | else if (Qreg1) 439 | begin 440 | $display("Lshift4bit R%d=%b", R3,Qset[R3]); 441 | end 442 | end 443 | 444 | else if (CMD_and) // do and 445 | begin 446 | if (Hreg2) 447 | begin 448 | result_reg_and <= H[R2] & H[R3]; 449 | $display("and16bit R%d=%b R%d=%b", R2,H[R2],R3,H[R3]); 450 | end 451 | else if (Oreg2) 452 | begin 453 | result_reg_and <= Oset[R2] & Oset[R3]; 454 | $display("and8bit R%d=%b R%d=%b", R2,Oset[R2],R3,Oset[R3]); 455 | end 456 | else if (Qreg2) 457 | begin 458 | result_reg_and <= Qset[R2] & Qset[R3]; 459 | $display("and4bit R%d=%b R%d=%b", R2,Qset[R2],R3,Qset[R3]); 460 | end 461 | end 462 | 463 | else if (CMD_or) // do or 464 | begin 465 | if (Hreg2) 466 | begin 467 | result_reg_or <= H[R2] | H[R3]; 468 | $display("or16bit R%d=%b R%d=%b", R2,H[R2],R3,H[R3]); 469 | end 470 | else if (Oreg2) 471 | begin 472 | result_reg_or <= Oset[R2] | Oset[R3]; 473 | $display("or8bit R%d=%b R%d=%b", R2,Oset[R2],R3,Oset[R3]); 474 | end 475 | else if (Qreg2) 476 | begin 477 | result_reg_or <= Qset[R2] | Qset[R3]; 478 | $display("or4bit R%d=%b R%d=%b", R2,Qset[R2],R3,Qset[R3]); 479 | end 480 | end 481 | 482 | 483 | else if (CMD_not) // do not 484 | begin 485 | if (Hreg1) 486 | begin 487 | result_reg_not <= ~H[R3]; 488 | $display("not16bit R%d=%b", R3,H[R3]); 489 | end 490 | else if (Oreg1) 491 | begin 492 | result_reg_not <= ~Oset[R3]; 493 | $display("not8bit R%d=%b", R3,Oset[R3]); 494 | end 495 | else if (Qreg1) 496 | begin 497 | result_reg_not <= ~Qset[R3]; 498 | $display("not4bit R%d=%b", R3,Qset[R3]); 499 | end 500 | end 501 | 502 | else if (CMD_set) // do set 503 | begin 504 | if (Hreg1) 505 | begin 506 | result_reg_set <= im_reg; 507 | $display("set16bit R%d im=%b", R0,im_reg); 508 | end 509 | else if (Oreg1) 510 | begin 511 | result_reg_set[7:0] <= im_reg; 512 | result_reg_set[15:8] <= im_reg; 513 | $display("set8bit R%d im=%b", R0,im_reg); 514 | end 515 | else if (Qreg1) 516 | begin 517 | result_reg_set[3:0] <= im_reg; 518 | result_reg_set[7:4] <= im_reg; 519 | result_reg_set[11:8] <= im_reg; 520 | result_reg_set[15:12] <= im_reg; 521 | $display("set4bit R%d im=%b", R0,im_reg); 522 | end 523 | end 524 | 525 | else if (CMD_load) // do load 526 | begin 527 | rdata_en <= 1; 528 | current_data_address <= im_reg; 529 | if (Hreg1) 530 | begin 531 | $display("load16bit R%d im=%b", R0,im_reg); 532 | end 533 | else if (Oreg1) 534 | begin 535 | $display("load8bit R%d im=%b", R0,im_reg); 536 | end 537 | else if (Qreg1) 538 | begin 539 | $display("load4bit R%d im=%b", R0,im_reg); 540 | end 541 | 542 | end 543 | 544 | else if (CMD_store) // do store 545 | begin 546 | wdata_en <= 1; 547 | rdata_en <= 1; 548 | current_data_address <= im_reg; 549 | 550 | if (Hreg1) 551 | begin 552 | data_out_reg <= H[R0]; 553 | $display("store16bit R%d=%b im=%b", R0,H[R0],im_reg); 554 | end 555 | else if (Oreg1) 556 | begin 557 | data_out_reg <= Oset[R0]; 558 | $display("store8bit R%d=%b im=%b", R0,Oset[R0],im_reg); 559 | end 560 | else if (Qreg1) 561 | begin 562 | data_out_reg <= Qset[R0]; 563 | $display("store4bit R%d=%b im=%b", R0,Qset[R0],im_reg); 564 | end 565 | end 566 | 567 | if (CMD_loopjump) 568 | begin 569 | $display("loopjump LC=%d im=%d", LC,im_reg); 570 | if (LC != 0) 571 | begin 572 | next_PC <= im_reg; 573 | LC <= LC - 1; 574 | end 575 | else 576 | begin 577 | next_PC <= next_PC + 1; 578 | end 579 | end 580 | else 581 | next_PC <= next_PC + 1; 582 | 583 | if (CMD_setloop) 584 | begin 585 | $display("setloop im=%d", im_reg); 586 | LC <= im_reg; 587 | end 588 | end 589 | end 590 | 591 | 592 | always @(posedge clk)//STATE_MEM 593 | begin 594 | if (rst || current_state == STATE_IDLE || current_state == STATE_IF) 595 | begin 596 | end 597 | else 598 | begin 599 | if (current_state == STATE_MEM) 600 | begin 601 | 602 | end 603 | end 604 | end 605 | 606 | always @(posedge clk)//STATE_WB 607 | begin 608 | if (rst || current_state == STATE_IDLE || current_state == STATE_IF) 609 | begin 610 | end 611 | 612 | else if (current_state == STATE_WB) 613 | begin 614 | 615 | if (CMD_addition) // do addition 616 | begin 617 | if (Hreg2) 618 | begin 619 | H[R2] <= result_reg_add; 620 | end 621 | else if (Oreg2) 622 | begin 623 | Oset[R2] <= result_reg_add; 624 | end 625 | else if (Qreg2) 626 | begin 627 | Qset[R2] <= result_reg_add; 628 | end 629 | else if (Him) 630 | begin 631 | H[R0] <= result_reg_add; 632 | end 633 | else if (Oim) 634 | begin 635 | Oset[R0] <= result_reg_add; 636 | end 637 | else if (Qim) 638 | begin 639 | Qset[R0] <= result_reg_add; 640 | end 641 | end 642 | 643 | else if (CMD_substruction) // do substruction 644 | begin 645 | if (Hreg2) 646 | begin 647 | H[R2] <= result_reg_sub; 648 | end 649 | else if (Oreg2) 650 | begin 651 | Oset[R2] <= result_reg_sub; 652 | end 653 | else if (Qreg2) 654 | begin 655 | Qset[R2] <= result_reg_sub; 656 | end 657 | else if (Him) 658 | begin 659 | H[R0] <= result_reg_sub; 660 | end 661 | else if (Oim) 662 | begin 663 | Oset[R0] <= result_reg_sub; 664 | end 665 | else if (Qim) 666 | begin 667 | Qset[R0] <= result_reg_sub; 668 | end 669 | end 670 | end 671 | 672 | else if (CMD_multiplication) // do multiplication 673 | begin 674 | if (Hreg2) 675 | begin 676 | H[R2] <= result_reg_mul; 677 | end 678 | else if (Oreg2) 679 | begin 680 | Oset[R2] <= result_reg_mul; 681 | end 682 | else if (Qreg2) 683 | begin 684 | Qset[R2] <= result_reg_mul; 685 | end 686 | else if (Him) 687 | begin 688 | H[R0] <= result_reg_mul; 689 | end 690 | else if (Oim) 691 | begin 692 | Oset[R0] <= result_reg_mul; 693 | end 694 | else if (Qim) 695 | begin 696 | Qset[R0] <= result_reg_mul; 697 | end 698 | end 699 | 700 | else if (CMD_mul_accumulation) // do mac 701 | begin 702 | if (Hreg3) 703 | begin 704 | H[R1] <= result_reg_mac; 705 | end 706 | else if (Oreg3) 707 | begin 708 | Oset[R1] <= result_reg_mac; 709 | end 710 | else if (Qreg3) 711 | begin 712 | Qset[R1] <= result_reg_mac; 713 | end 714 | end 715 | 716 | else if (CMD_logic_shift_right) // do shift right 717 | begin 718 | if (Hreg1) 719 | begin 720 | H[R3] <= result_reg_Rshift; 721 | end 722 | else if (Oreg1) 723 | begin 724 | Oset[R3] <= result_reg_Rshift; 725 | end 726 | else if (Qreg1) 727 | begin 728 | Qset[R3] <= result_reg_Rshift; 729 | end 730 | end 731 | 732 | else if (CMD_logic_shift_left) // do shift left 733 | begin 734 | if (Hreg1) 735 | begin 736 | H[R3] <= result_reg_Lshift; 737 | end 738 | else if (Oreg1) 739 | begin 740 | Oset[R3] <= result_reg_Lshift; 741 | end 742 | else if (Qreg1) 743 | begin 744 | Qset[R3] <= result_reg_Lshift; 745 | end 746 | end 747 | 748 | else if (CMD_and) // do and 749 | begin 750 | if (Hreg2) 751 | begin 752 | H[R2] <= result_reg_and; 753 | end 754 | else if (Oreg2) 755 | begin 756 | Oset[R2] <= result_reg_and; 757 | end 758 | else if (Qreg2) 759 | begin 760 | Qset[R2] <= result_reg_and; 761 | end 762 | end 763 | 764 | else if (CMD_or) // do or 765 | begin 766 | if (Hreg2) 767 | begin 768 | H[R2] <= result_reg_or; 769 | end 770 | else if (Oreg2) 771 | begin 772 | Oset[R2] <= result_reg_or; 773 | end 774 | else if (Qreg2) 775 | begin 776 | Qset[R2] <= result_reg_or; 777 | end 778 | end 779 | 780 | 781 | else if (CMD_not) // do not 782 | begin 783 | if (Hreg1) 784 | begin 785 | H[R3] <= result_reg_not; 786 | end 787 | else if (Oreg1) 788 | begin 789 | Oset[R3] <= result_reg_not; 790 | end 791 | else if (Qreg1) 792 | begin 793 | Qset[R3] <= result_reg_not; 794 | end 795 | end 796 | 797 | else if (CMD_set) // do set 798 | begin 799 | if (Hreg1) 800 | begin 801 | H[R0] <= result_reg_set; 802 | end 803 | else if (Oreg1) 804 | begin 805 | Oset[R0] <= result_reg_set; 806 | end 807 | else if (Qreg1) 808 | begin 809 | Qset[R0] <= result_reg_set; 810 | end 811 | end 812 | else if (CMD_load) 813 | begin 814 | if (Hreg1) 815 | begin 816 | H[R0] <= data_in; 817 | end 818 | else if (Oreg1) 819 | begin 820 | Oset[R0] <= data_in; 821 | end 822 | else if (Qreg1) 823 | begin 824 | Qset[R0] <= data_in; 825 | end 826 | end 827 | 828 | end 829 | 830 | endmodule 831 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. 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It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /Layout.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial/44952cdcde3ea135950ccea62d1dab64787b9871/Layout.PNG -------------------------------------------------------------------------------- /Processor.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial/44952cdcde3ea135950ccea62d1dab64787b9871/Processor.PNG -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Basic-SIMD-Processor-Verilog-Tutorial 2 | Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit. 3 | 4 | 5 | 6 | The ALU will be embedded into a simple processor based on 5-stage, delay of each stage will 7 | be 1 cycle, meeting the delay of ALU, as shown in the figure below. The 5 typical stages are IF, ID, 8 | EX, MEM and WB, without pipeline. In the stage IF, a 10-bit address will be sent to an instruction 9 | Block-RAM (BRAM) to fetch 18-bit instruction. In the stage ID, the instruction will be decoded 10 | and some of control registers will be set to control the following stage. In the stage EX, ALU will 11 | process data in registers or implement some control commands, e.g. jump. In the stage MEM, if the 12 | instruction is “store” or “load”, data would be read from/ written to data BRAM, based on instruction 13 | and address. Finally, in the stage WB, data will be written back to register. The pins of clock, reset, 14 | address, data and BRAM enable will be exposed on the interface of processor. The architecture of 15 | processor is shown in the figure above. 16 | 17 | The experiment based on Cadence are shown below and more details can be found in the **[report](https://github.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial/blob/master/report.pdf)**. The source code is well-commented and user can easily understanding how it work. This work was implemented as the final project of Digital VLSI System Design and Design Automation, HKUST. Thanks Prof. Tsui and TA Zhu a lot for their patience and time! 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /SIMDadd.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SIMDadd( 4 | input [15:0] A, 5 | input [15:0] B, 6 | input H, 7 | input O, 8 | input Q, 9 | input sub, 10 | output [15:0] Cout 11 | ); 12 | wire [15:0] B_real = sub?(~B):B; 13 | wire [4:0] C0 = A[3:0] + B_real[3:0] + sub; 14 | wire [4:0] C1 = A[7:4] + B_real[7:4] + (C0[4]&(O|H)) + (Q&sub); 15 | wire [4:0] C2 = A[11:8] + B_real[11:8] + (C1[4]&H) + ((Q|O)&sub); 16 | wire [4:0] C3 = A[15:12] + B_real[15:12] + (C2[4]&(O|H)) + (Q&sub); 17 | 18 | assign Cout = {C3[3:0],C2[3:0],C1[3:0],C0[3:0]}; 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /SIMDmultiply.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 15.05.2018 16:15:26 7 | // Design Name: 8 | // Module Name: Multiply 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SIMDmultiply( 24 | input [15:0] mulinputa, 25 | input [15:0] mulinputb, 26 | input H, 27 | input O, 28 | input Q, 29 | output [15:0] muloutput 30 | ); 31 | 32 | 33 | wire [15:0] sel0 = H?16'hFFFF:(O?16'h00FF:16'h000F); 34 | wire [15:0] sel1 = H?16'hFFFF:(O?16'h00FF:16'h00F0); 35 | wire [15:0] sel2 = H?16'hFFFF:(O?16'hFF00:16'h0F00); 36 | wire [15:0] sel3 = H?16'hFFFF:(O?16'hFF00:16'hF000); 37 | 38 | wire [15:0] a0 = (mulinputb[0]?mulinputa:16'h0000)&sel0; 39 | wire [15:0] a1 = (mulinputb[1]?mulinputa:16'h0000)&sel0; 40 | wire [15:0] a2 = (mulinputb[2]?mulinputa:16'h0000)&sel0; 41 | wire [15:0] a3 = (mulinputb[3]?mulinputa:16'h0000)&sel0; 42 | wire [15:0] a4 = (mulinputb[4]?mulinputa:16'h0000)&sel1; 43 | wire [15:0] a5 = (mulinputb[5]?mulinputa:16'h0000)&sel1; 44 | wire [15:0] a6 = (mulinputb[6]?mulinputa:16'h0000)&sel1; 45 | wire [15:0] a7 = (mulinputb[7]?mulinputa:16'h0000)&sel1; 46 | wire [15:0] a8 = (mulinputb[8]?mulinputa:16'h0000)&sel2; 47 | wire [15:0] a9 = (mulinputb[9]?mulinputa:16'h0000)&sel2; 48 | wire [15:0] a10 = (mulinputb[10]?mulinputa:16'h0000)&sel2; 49 | wire [15:0] a11 = (mulinputb[11]?mulinputa:16'h0000)&sel2; 50 | wire [15:0] a12 = (mulinputb[12]?mulinputa:16'h0000)&sel3; 51 | wire [15:0] a13 = (mulinputb[13]?mulinputa:16'h0000)&sel3; 52 | wire [15:0] a14 = (mulinputb[14]?mulinputa:16'h0000)&sel3; 53 | wire [15:0] a15 = (mulinputb[15]?mulinputa:16'h0000)&sel3; 54 | 55 | wire [15:0] tmp0,tmp1,tmp2,tmp3; 56 | wire [15:0] tmp00,tmp11; 57 | wire [15:0] tmp000; 58 | 59 | assign tmp0 = a0 + (a1<<1) + (a2<<2) + (a3<<3); 60 | assign tmp1 = a4 + (a5<<1) + (a6<<2) + (a7<<3); 61 | assign tmp2 = a8 + (a9<<1) + (a10<<2) + (a11<<3); 62 | assign tmp3 = a12 + (a13<<1) + (a14<<2) + (a15<<3); 63 | 64 | assign tmp00 = tmp0 + (tmp1<<4); 65 | assign tmp11 = tmp2 + (tmp3<<4); 66 | 67 | assign tmp000 = tmp00 + (tmp11<<8); 68 | 69 | wire [3:0] tmp1h,tmp1o,tmp1q; 70 | wire [3:0] tmp2h,tmp2o,tmp2q; 71 | wire [3:0] tmp3h,tmp3o,tmp3q; 72 | 73 | assign muloutput[3:0] = tmp0[3:0]; 74 | 75 | assign tmp1h = tmp000[7:4]; 76 | assign tmp2h = tmp000[11:8]; 77 | assign tmp3h = tmp000[15:12]; 78 | 79 | assign tmp1o = tmp00[7:4]; 80 | assign tmp2o = tmp11[11:8]; 81 | assign tmp3o = tmp11[15:12]; 82 | 83 | assign tmp1q = tmp1[7:4]; 84 | assign tmp2q = tmp2[11:8]; 85 | assign tmp3q = tmp3[15:12]; 86 | 87 | assign muloutput[7:4] = H?tmp1h:(O?tmp1o:tmp1q); 88 | assign muloutput[11:8] = H?tmp2h:(O?tmp2o:tmp2q); 89 | assign muloutput[15:12] = H?tmp3h:(O?tmp3o:tmp3q); 90 | 91 | 92 | endmodule 93 | 94 | -------------------------------------------------------------------------------- /SIMDshifter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SIMDshifter( 4 | input [15:0] shiftinput, 5 | input H, 6 | input O, 7 | input Q, 8 | input left, 9 | output [15:0] shiftoutput 10 | ); 11 | 12 | wire [14:0] left_shift = shiftinput[14:0]; 13 | wire [14:0] right_shift = shiftinput[15:1]; 14 | wire [15:0] shiftoutput_tmp = left?{left_shift,1'b0}:{1'b0,right_shift}; 15 | assign shiftoutput[3:0] = {(left|H|O)&shiftoutput_tmp[3], shiftoutput_tmp[2:0]}; 16 | assign shiftoutput[7:4] = {(left|H)&shiftoutput_tmp[7], shiftoutput_tmp[6:5], (!left|H|O)&shiftoutput_tmp[4]}; 17 | assign shiftoutput[11:8] = {(left|H|O)&shiftoutput_tmp[11], shiftoutput_tmp[10:9], (!left|H)&shiftoutput_tmp[8]}; 18 | assign shiftoutput[15:12] = {(left|H)&shiftoutput_tmp[15], shiftoutput_tmp[14:13], (!left|H|O)&shiftoutput_tmp[12]}; 19 | 20 | 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /post_layout_Sim.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial/44952cdcde3ea135950ccea62d1dab64787b9871/post_layout_Sim.PNG -------------------------------------------------------------------------------- /processor_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ps 2 | 3 | module processor_tb; 4 | 5 | // ---------------------------------- 6 | // Local parameter declaration 7 | // ---------------------------------- 8 | localparam CLK_PERIOD = 20.0; // clock period: 5ns 9 | 10 | // ---------------------------------- 11 | // Interface of the CPUtop module 12 | // ---------------------------------- 13 | reg clk, rst; 14 | reg [17:0] INST_MEM[1023:0]; 15 | reg [15:0] DATA_MEM[1023:0]; 16 | wire done; 17 | reg [17:0] instruction_in; 18 | reg [15:0] data_in; 19 | wire [15:0] data_out; 20 | wire [9:0] instruction_address; 21 | wire [9:0] data_address; 22 | wire data_R; 23 | wire data_W; 24 | // ---------------------------------- 25 | // Instantiate the CPUtop 26 | // ---------------------------------- 27 | CPUtop uut ( 28 | .clk (clk), // system clock 29 | .rst (rst), // system reset (active high) 30 | .instruction_in (instruction_in), 31 | .data_in(data_in), 32 | .data_out(data_out), 33 | .instruction_address(instruction_address), 34 | .data_address(data_address), 35 | .data_R(data_R), 36 | .data_W(data_W), 37 | .done(done) 38 | ); 39 | 40 | initial begin 41 | $sdf_annotate("CPUtop.mapped.sdf", uut); 42 | end 43 | 44 | //instructions and memory initialization 45 | initial begin 46 | INST_MEM[0] = 18'b100110_00_0000000000; // load MEM0 into H0 load16bit R0 im=0000000000 47 | INST_MEM[1] = 18'b100110_01_0000000001; // load MEM1 into H1 load16bit R1 im=0000000001 48 | INST_MEM[2] = 18'b100110_10_0000000010; // load MEM2 into H2 load16bit R2 im=0000000010 49 | INST_MEM[3] = 18'b000000_00000000_00_01; // add H1 to H0 add16bit R0=0000000000000101 R1=0000000000001111 50 | INST_MEM[4] = 18'b000000_00000000_10_00; // add H0 to H2 add16bit R2=0000000000000100 R0=0000000000010100 51 | INST_MEM[5] = 18'b101001_00_0000000000; // store H0 back into MEM0 store16bit R0=0000000000010100 im=0000000000 52 | INST_MEM[6] = 18'b101100_01_0100100010; // set H1 to 0100100010 set16bit R1 im=0100100010 53 | INST_MEM[7] = 18'b000000_00000000_01_10; // add H2 to H1 add16bit R1=0000000100100010 R2=0000000000011000 54 | INST_MEM[8] = 18'b101001_01_0000000011; // store H1 back into MEM3 store16bit R1=0000000100111010 im=0000000011 55 | INST_MEM[9] = 18'b101001_10_0000000100; // store H2 back into MEM4 store16bit R2=0000000000011000 im=0000000100 56 | INST_MEM[10] = 18'b101001_00_0000000101; // store H0 back into MEM5 store16bit R0=0000000000010100 im=0000000101 57 | 58 | INST_MEM[11] = 18'b100111_01_0000000010; // load MEM2 into O1 load8bit R1 im=0000000010 59 | INST_MEM[12] = 18'b100111_10_0000000011; // load MEM3 into O2 load8bit R2 im=0000000011 60 | INST_MEM[13] = 18'b100111_00_0000000100; // load MEM4 into O0 load8bit R0 im=0000000100 61 | INST_MEM[14] = 18'b101101_01_0001011010; // set each register in O1 set8bit R1 im=0001011010 62 | 63 | INST_MEM[15] = 18'b100101_00_0000000010; // setloop = 2 setloop im= 2 64 | 65 | INST_MEM[16] = 18'b000001_00000000_00_01; // add O0 to O1 add8bit R0=0000000000011000 R1=0101101001011010 66 | INST_MEM[17] = 18'b000001_00000000_10_00; // add O2 to O0 add8bit R2=0000000100111010 R0=0101101001110010 67 | INST_MEM[18] = 18'b000111_00000000_10_01; // sub O1 from O2 sub8bit R2=0101101110101100 R1=0101101001011010 68 | INST_MEM[19] = 18'b001101_00000000_10_01; // mul O2 with O1 mul8bit R2=0000000101010010 R1=0101101001011010 69 | INST_MEM[20] = 18'b101010_01_0000000101; // store O1 MEM5 into store8bit R1=0101101001011010 im=0000000101 70 | INST_MEM[21] = 18'b101010_10_0000000110; // store O2 MEM6 into O2 store8bit R2=0101101011010100 im=0000000110 71 | INST_MEM[22] = 18'b101010_00_0000000111; // store O0 MEM7 into O0 store8bit R0=0101101001110010 im=0000000111 72 | 73 | INST_MEM[23] = 18'b100110_01_0000000101; // load MEM5 into H1 load16bit R1 im=0000000101 74 | INST_MEM[24] = 18'b100110_10_0000000111; // load MEM7 into H2 load16bit R2 im=0000000111 75 | INST_MEM[25] = 18'b001100_00000000_10_01; // mul H2 with H1 mul16bit R2=0101101001110010 R1=0101101001011010 76 | INST_MEM[26] = 18'b000110_00000000_10_01; // sub H1 from H2 sub16bit R2=1110000000010100 R1=0101101001011010 77 | INST_MEM[27] = 18'b011000_0000000000_01; // shift right H1 Rshift16bit R1=0101101001011010 78 | INST_MEM[28] = 18'b010101_0000000000_10; // shift left H2 Lshift16bit R2=1000010110111010 79 | INST_MEM[29] = 18'b000011_10_0000001110; // add im_number into H2 add16bit R2=0000101101110100 im=0000001110 80 | INST_MEM[30] = 18'b001001_10_0000001110; // sub im_number from H2 sub16bit R2=0000101110000010 im=0000001110 81 | INST_MEM[31] = 18'b100001_0000000000_10; // not H2 not16bit R2=0000101101110100 82 | INST_MEM[32] = 18'b011011_00000000_01_00; // H1 and H0 and16bit R1=0010110100101101 R0=0000000000010100 83 | INST_MEM[33] = 18'b011110_00000000_10_01; // H2 or H1 or16bit R2=1111010010001011 R1=0000000000000100 84 | INST_MEM[34] = 18'b101100_00_0000001111; // set H0 to 0000001111 set16bit R0 im=0000001111 85 | INST_MEM[35] = 18'b101100_01_0000000100; // set H1 to 0000000100 set16bit R1 im=0000000100 86 | INST_MEM[36] = 18'b101100_10_0000000010; // set H2 to 0000000010 set16bit R2 im=0000000010 87 | INST_MEM[37] = 18'b010010_000000_00_01_10; // H0+H1*H2 MAC16bit R0=0000000000001111 R1=0000000000000100 R2=0000000000000010 88 | INST_MEM[38] = 18'b001001_00_0000001000; // sub im_number from H0 sub16bit R0=0000000000010111 im=0000001000 89 | INST_MEM[39] = 18'b001111_01_0000001101; // mul H1 with im_number mul16bit R1=0000000000000100 im=0000001101 90 | INST_MEM[40] = 18'b101001_01_0000000111; // store H1 back into MEM7 store16bit R1=0000000000110100 im=0000000111 91 | INST_MEM[41] = 18'b101001_10_0000000100; // store H2 back into MEM4 store16bit R2=0000000000000010 im=0000000100 92 | INST_MEM[42] = 18'b101001_00_0000001000; // store H0 back into MEM8 store16bit R0=0000000000001111 im=0000001000 93 | 94 | INST_MEM[43] = 18'b100111_01_0000000110; // load MEM6 into O1 load8bit R1 im=0000000110 95 | INST_MEM[44] = 18'b100111_10_0000000111; // load MEM7 into O2 load8bit R2 im=0000000111 96 | INST_MEM[45] = 18'b100111_00_0000001000; // load MEM8 into O0 load8bit R0 im=0000001000 97 | INST_MEM[46] = 18'b011001_0000000000_01; // shift right O1 Rshift8bit R1=0101101011010100 98 | INST_MEM[47] = 18'b010110_0000000000_10; // shift left O2 Lshift8bit R2=0000000000110100 99 | INST_MEM[48] = 18'b000100_10_0000001110; // add im_number into O2 add8bit R2=0000000001101000 im=0000001110 100 | INST_MEM[49] = 18'b001010_10_0000001110; // sub im_number from O2 sub8bit R2=0000111001110110 im=0000001110 101 | INST_MEM[50] = 18'b100010_0000000000_10; // not O2 not8bit R2=0000000001101000 102 | INST_MEM[51] = 18'b011100_00000000_01_00; // O1 and O0 and8bit R1=0010110101101010 R0=0000000000001111 103 | INST_MEM[52] = 18'b011111_00000000_10_01; // O2 or O1 or8bit R2=1111111110010111 R1=0000000000001010 104 | INST_MEM[53] = 18'b101101_00_0000001111; // set O0 to 0000001111 set8bit R0 im=0000001111 105 | INST_MEM[54] = 18'b101101_01_0000000100; // set O1 to 0000000100 set8bit R1 im=0000000100 106 | INST_MEM[55] = 18'b101101_10_0000000010; // set O2 to 0000000010 set8bit R2 im=0000000010 107 | INST_MEM[56] = 18'b010011_000000_00_01_10; // O0+O1*O2 MAC8bit R0=0000111100001111 R1=0000010000000100 R2=0000001000000010 108 | INST_MEM[57] = 18'b001010_00_0000001000; // sub im_number from O0 sub8bit R0=0001011100010111 im=0000001000 109 | INST_MEM[58] = 18'b010000_01_0000001101; // mul O1 with im_number mul8bit R1=0000010000000100 im=0000001101 110 | INST_MEM[59] = 18'b101010_01_0000001001; // store O1 into MEM9 store8bit R1=0011010000110100 im=0000001001 111 | INST_MEM[60] = 18'b101010_10_0000000110; // store O2 into MEM6 store8bit R2=0000001000000010 im=0000000110 112 | INST_MEM[61] = 18'b101010_00_0000000111; // store O0 into MEM7 store8bit R0=0000111100001111 im=0000000111 113 | 114 | 115 | INST_MEM[62] = 18'b101000_01_0000001001; // load MEM9 into Q1 load4bit R1 im=0000001001 116 | INST_MEM[63] = 18'b101000_10_0000000110; // load MEM6 into Q2 load4bit R2 im=0000000110 117 | INST_MEM[64] = 18'b101000_00_0000000111; // load MEM7 into Q0 load4bit R0 im=0000000111 118 | INST_MEM[65] = 18'b101110_10_0001011010; // set each register in Q2 set4bit R2 im=0001011010 119 | INST_MEM[66] = 18'b011010_0000000000_01; // shift right Q1 Rshift4bit R1=0011010000110100 120 | INST_MEM[67] = 18'b010111_0000000000_10; // shift left Q2 Lshift4bit R2=1010101010101010 121 | INST_MEM[68] = 18'b000101_10_0000001110; // add im_number into Q2 add4bit R2=0100010001000100 im=0000001110 122 | INST_MEM[69] = 18'b001011_10_0000001110; // sub im_number from Q2 sub4bit R2=0010001000100010 im=0000001110 123 | INST_MEM[70] = 18'b100011_0000000000_10; // not Q2 not4bit R2=0100010001000100 124 | INST_MEM[71] = 18'b011101_00000000_01_00; // Q1 and Q0 and4bit R1=0001001000010010 R0=0000111100001111 125 | INST_MEM[72] = 18'b100000_00000000_10_01; // Q2 or Q1 or4bit R2=1011101110111011 R1=0000001000000010 126 | INST_MEM[73] = 18'b101110_00_0000001111; // set Q0 to 0000001111 set4bit R0 im=0000001111 127 | INST_MEM[74] = 18'b101110_01_0000000100; // set Q1 to 0000000100 set4bit R1 im=0000000100 128 | INST_MEM[75] = 18'b101110_10_0000000010; // set Q2 to 0000000010 set4bit R2 im=0000000010 129 | INST_MEM[76] = 18'b010100_000000_00_01_10; // Q0+Q1*Q2 MAC4bit R0=1111111111111111 R1=0100010001000100 R2=0010001000100010 130 | INST_MEM[77] = 18'b001011_00_0000001000; // sub im_number from Q0 sub4bit R0=0111011101110111 im=0000001000 131 | INST_MEM[78] = 18'b010001_01_0000000101; // mul Q1 with im_number mul4bit R1=0100010001000100 im=0000000101 132 | INST_MEM[79] = 18'b101110_01_0001011010; // set each register in Q1 set4bit R1 im=0001011010 133 | INST_MEM[80] = 18'b000010_00000000_00_01; // add Q0 to O1 add4bit R0=1111111111111111 R1=1010101010101010 134 | INST_MEM[81] = 18'b000010_00000000_10_00; // add Q2 to Q0 add4bit R2=0010001000100010 R0=1001100110011001 135 | INST_MEM[82] = 18'b001000_00000000_10_01; // sub Q1 from Q2 sub4bit R2=1011101110111011 R1=1010101010101010 136 | INST_MEM[83] = 18'b001110_00000000_10_01; // mul Q2 with Q1 mul4bit R2=0001000100010001 R1=1010101010101010 137 | INST_MEM[84] = 18'b101011_01_0000001001; // store Q1 into MEM9 store4bit R1=1010101010101010 im=0000001001 138 | INST_MEM[85] = 18'b101011_10_0000000110; // store Q2 into MEM6 store4bit R2=1010101010101010 im=0000000110 139 | INST_MEM[86] = 18'b101011_00_0000000111; // store Q0 into MEM7 store4bit R0=1001100110011001 im=0000000111 140 | 141 | INST_MEM[87] = 18'b100100_00_0000010000; // jump to 16 loopjump LC= x im= 16 142 | 143 | INST_MEM[88] = 18'b111111_000000000000; // halt 144 | 145 | DATA_MEM[0] = 5; 146 | DATA_MEM[1] = 15; 147 | DATA_MEM[2] = 4; 148 | end 149 | 150 | 151 | // ---------------------------------- 152 | // Clock generation 153 | // ---------------------------------- 154 | initial begin 155 | clk = 1'b0; 156 | forever #(CLK_PERIOD/2.0) clk = ~clk; 157 | end 158 | 159 | 160 | // ---------------------------------- 161 | // Memory(BRAM/low latency Cache) Simulation 162 | // ---------------------------------- 163 | always @(negedge clk) 164 | begin 165 | if (data_R) 166 | begin 167 | if (data_W) 168 | begin 169 | DATA_MEM[data_address] <= data_out; 170 | $display("write mem %d: %b",data_address,data_out); 171 | end 172 | else 173 | data_in <= DATA_MEM[data_address]; 174 | end 175 | end 176 | 177 | always @(negedge clk) 178 | begin 179 | instruction_in <= INST_MEM[instruction_address]; 180 | $display("inst_addr %d: %b",instruction_address,INST_MEM[instruction_address]); 181 | end 182 | 183 | // ---------------------------------- 184 | // Input stimulus 185 | // Generate the ad-hoc stimulus 186 | // ---------------------------------- 187 | initial 188 | begin 189 | // Reset 190 | rst = 1'b1; 191 | #(2*CLK_PERIOD) rst = 1'b0; 192 | end 193 | 194 | // ---------------------------------- 195 | // Output monitor 196 | // ---------------------------------- 197 | always @(posedge clk) 198 | begin 199 | if (done) begin 200 | $finish; 201 | end 202 | end 203 | 204 | endmodule 205 | -------------------------------------------------------------------------------- /report.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial/44952cdcde3ea135950ccea62d1dab64787b9871/report.pdf --------------------------------------------------------------------------------